drivers/video/tegra/dc/hdmi.c

   1 /*
   2  * drivers/video/tegra/dc/hdmi.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Erik Gilling <konkers@android.com>
   6  *
   7  * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/fb.h>
  24 #include <linux/gpio.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/kernel.h>
  27 #include <linux/slab.h>
  28 #include <linux/mutex.h>
  29 #ifdef CONFIG_SWITCH
  30 #include <linux/switch.h>
  31 #endif
  32 #include <linux/debugfs.h>
  33 #include <linux/seq_file.h>
  34 #include <linux/device.h>
  35 #include <linux/export.h>
  36 #include <linux/clk/tegra.h>
  37
  38 #include <mach/dc.h>
  39 #include <mach/fb.h>
  40 #include <linux/nvhost.h>
  41 #include <mach/hdmi-audio.h>
  42
  43 #include <video/tegrafb.h>
  44
  45 #include "dc_reg.h"
  46 #include "dc_priv.h"
  47 #include "hdmi_reg.h"
  48 #include "hdmi.h"
  49 #include "hdmi_state_machine.h"
  50 #include "edid.h"
  51 #include "nvhdcp.h"
  52 #include <linux/of.h>
  53 #include <linux/of_address.h>
  54
  55 /* datasheet claims this will always be 216MHz */
  56 #define HDMI_AUDIOCLK_FREQ              216000000
  57
  58 #define HDMI_REKEY_DEFAULT              56
  59
  60 /* According to HDMI EDID specs for Short Audio
  61  * Descriptor, format type LPCM is 1 (this is required
  62  * by HAL before EDL is copied to hda codec driver
  63  */
  64 #define AUDIO_CODING_TYPE_LPCM          1
  65 #define AUDIO_SAD_BYTE_SIZE             3
  66
  67 #define HDMI_ELD_VER_INDEX                      0
  68 #define HDMI_ELD_RESERVED1_INDEX                1
  69 #define HDMI_ELD_BASELINE_LEN_INDEX             2
  70 #define HDMI_ELD_RESERVED2_INDEX                3
  71 #define HDMI_ELD_CEA_VER_MNL_INDEX              4
  72 #define HDMI_ELD_SAD_CNT_CON_TYP_SAI_HDCP_INDEX         5
  73 #define HDMI_ELD_AUD_SYNC_DELAY_INDEX           6
  74 #define HDMI_ELD_SPK_ALLOC_INDEX                7
  75 #define HDMI_ELD_PORT_ID_INDEX                  8  /*  8 to 15  */
  76 #define HDMI_ELD_MANF_NAME_INDEX                16 /* 16 to 17 */
  77 #define HDMI_ELD_PRODUCT_CODE_INDEX             18 /* 18 to 19 */
  78 #define HDMI_ELD_MONITOR_NAME_INDEX             20 /* 20 to 20 + MNL - 1 */
  79 #define HDMI_ELD_BUF_SIZE                       96
  80
  81 /* According to HDA ELD spec, the maxmimum baseline
  82  * eld size for tye 2 ELD_Ver encoding (which is
  83  * what this code supports) is 80 bytes.
  84  */
  85 #define MAX_BASELINE_ELD_SIZE                   80
  86
  87 /* These two values need to be cross checked in case of
  88      addition/removal from tegra_dc_hdmi_aspect_ratios[] */
  89 #define TEGRA_DC_HDMI_MIN_ASPECT_RATIO_PERCENT  80
  90 #define TEGRA_DC_HDMI_MAX_ASPECT_RATIO_PERCENT  320
  91
  92 struct tegra_dc_hdmi_data *dc_hdmi;
  93
  94 static ssize_t hdmi_audio_get_max_channel(struct kobject *kobj,
  95         struct kobj_attribute *attr, char *buf);
  96
  97 static struct kobj_attribute hdmi_audio_channel_config =
  98         __ATTR(config, 0640, hdmi_audio_get_max_channel, NULL);
  99
 100 static struct kobject *hdmi_audio;
 101
 102 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
 103 const struct tmds_config tmds_config[] = {
 104         { /* 480p modes */
 105         .pclk = 27000000,
 106         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 107                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0) |
 108                 SOR_PLL_TX_REG_LOAD(0),
 109         .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 110         .pe_current = 0x00000000,
 111         .drive_current = 0x0a0a0a0a,
 112         },
 113         { /* 720p modes */
 114         .pclk = 74250000,
 115         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 116                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(1) |
 117                 SOR_PLL_TX_REG_LOAD(0),
 118         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 119         .pe_current = 0x0a0a0a0a,
 120         .drive_current = 0x0a0a0a0a,
 121         },
 122         { /* 1080p modes */
 123         .pclk = INT_MAX,
 124         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 125                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(3) |
 126                 SOR_PLL_TX_REG_LOAD(0),
 127         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 128         .pe_current = 0x0a0a0a0a,
 129         .drive_current = 0x0a0a0a0a,
 130         },
 131 };
 132 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
 133 const struct tmds_config tmds_config[] = {
 134         { /* 480p modes */
 135         .pclk = 27000000,
 136         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 137                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0) |
 138                 SOR_PLL_TX_REG_LOAD(3),
 139         .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 140         .pe_current = 0x00000000,
 141         .drive_current = 0x0f0f0f0f,
 142         },
 143         { /* 720p modes */
 144         .pclk = 74250000,
 145         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 146                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(1) |
 147                 SOR_PLL_TX_REG_LOAD(3),
 148         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 149         .pe_current = 0x0c0c0c0c,
 150         .drive_current = 0x0f0f0f0f,
 151         },
 152         { /* 1080p modes */
 153         .pclk = INT_MAX,
 154         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 155                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(1) |
 156                 SOR_PLL_TX_REG_LOAD(3),
 157         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 158         .pe_current = 0x0c0c0c0c,
 159         .drive_current = 0x0f0f0f0f,
 160         },
 161 };
 162 #elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
 163 const struct tmds_config tmds_config[] = {
 164         { /* 480p/576p / 25.2MHz/27MHz modes */
 165         .pclk = 27000000,
 166         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 167                 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL_EXT,
 168         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 169         .pe_current = 0x00000000,
 170         .drive_current = 0x1a1a1a1a,
 171         .peak_current = 0x00000000,
 172         },
 173         { /* 720p / 74.25MHz modes */
 174         .pclk = 74250000,
 175         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 176                 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL_EXT,
 177         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 178         .pe_current = 0x0f0f0f0f,
 179         .drive_current = 0x1a1a1a1a,
 180         .peak_current = 0x00000000,
 181         },
 182         { /* 1080p / 148.5MHz modes */
 183         .pclk = 148500000,
 184         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 185                 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL_EXT,
 186         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 187         .pe_current = 0x0a0a0a0a,
 188         .drive_current = 0x1f1f1f1f,
 189         .peak_current = 0x00000000,
 190         },
 191         { /* 225/297MHz modes */
 192         .pclk = INT_MAX,
 193         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 194                 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL_EXT,
 195         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 196                 | SOR_PLL_TMDS_TERM_ENABLE,
 197         .pe_current = 0x00000000,
 198         .drive_current = 0x303f3f3f, /* lane3 needs a slightly lower current */
 199         .peak_current = 0x040f0f0f,
 200         /* Alternative settings:
 201         .drive_current = 0x2c333333,
 202         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(6)
 203                 | SOR_PLL_TMDS_TERM_ENABLE,
 204         */
 205         },
 206 };
 207 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
 208 const struct tmds_config tmds_config[] = {
 209         { /* 480p/576p / 25.2MHz/27MHz modes */
 210         .version = MKDEV(1, 0),
 211         .pclk = 27000000,
 212         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 213                 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL_EXT,
 214         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 215         .pe_current = 0x00000000,
 216         .drive_current = 0x1a1a1a1a,
 217         .peak_current = 0x00000000,
 218         .pad_ctls0_mask    = 0xfffff0ff,
 219         .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */
 220         },
 221         { /* 720p / 74.25MHz modes */
 222         .version = MKDEV(1, 0),
 223         .pclk = 74250000,
 224         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 225                 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL_EXT,
 226         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 227         .pe_current = 0x0f0f0f0f,
 228         .drive_current = 0x1a1a1a1a,
 229         .peak_current = 0x00000000,
 230         .pad_ctls0_mask    = 0xfffff0ff,
 231         .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */
 232         },
 233         { /* 1080p / 148.5MHz modes */
 234         .version = MKDEV(1, 0),
 235         .pclk = 148500000,
 236         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 237                 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL_EXT,
 238         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 239         .pe_current = 0x0a0a0a0a,
 240         .drive_current = 0x1f1f1f1f,
 241         .peak_current = 0x00000000,
 242         .pad_ctls0_mask    = 0xfffff0ff,
 243         .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */
 244         },
 245         { /* 225/297MHz modes */
 246         .version = MKDEV(1, 0),
 247         .pclk = INT_MAX,
 248         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 249                 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL_EXT,
 250         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 251                 | SOR_PLL_TMDS_TERM_ENABLE,
 252         .pe_current = 0x00000000,
 253         .drive_current = 0x303f3f3f, /* lane3 needs a slightly lower current */
 254         .peak_current = 0x040f0f0f,
 255         .pad_ctls0_mask    = 0xfffff0ff,
 256         .pad_ctls0_setting = 0x00000600, /* BG_VREF_LEVEL */
 257         },
 258 };
 259 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
 260 const struct tmds_config tmds_config[] = {
 261         { /* 480p modes */
 262         .pclk = 27000000,
 263         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 264                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0x0) |
 265                 SOR_PLL_TX_REG_LOAD(0),
 266         .pll1 = SOR_PLL_TMDS_TERM_ENABLE |
 267                 SOR_PLL_TMDS_TERMADJ(0xD) | SOR_PLL_LOADADJ(3),
 268         .pe_current = 0x0,
 269         .drive_current = 0x1f1f1f1f,
 270         .peak_current = 0x0,
 271         },
 272         { /* 720p modes */
 273         .pclk = 74250000,
 274         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 275                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0x1) |
 276                 SOR_PLL_TX_REG_LOAD(0),
 277         .pll1 = SOR_PLL_TMDS_TERM_ENABLE |
 278                 SOR_PLL_TMDS_TERMADJ(0xD) | SOR_PLL_LOADADJ(3),
 279         .pe_current = 0x0,
 280         .drive_current = 0x20202020,
 281         .peak_current = 0x0,
 282         },
 283         { /* 1080p modes */
 284         .pclk = INT_MAX,
 285         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 286                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0x3) |
 287                 SOR_PLL_TX_REG_LOAD(0),
 288         .pll1 = SOR_PLL_TMDS_TERM_ENABLE |
 289                 SOR_PLL_TMDS_TERMADJ(0xD) | SOR_PLL_LOADADJ(3),
 290         .pe_current = 0x0,
 291         .drive_current = 0x22222222,
 292         .peak_current = 0x04040404,
 293         },
 294 };
 295 #else
 296 #warning tmds_config needs to be defined for your arch
 297 #endif
 298
 299 struct tegra_hdmi_audio_config {
 300         unsigned pix_clock;
 301         unsigned n;
 302         unsigned cts;
 303         unsigned aval;
 304 };
 305
 306
 307 const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
 308         {25200000,      4096,   25200,  24000},
 309         {27000000,      4096,   27000,  24000},
 310         {74250000,      4096,   74250,  24000},
 311         {148500000,     4096,   148500, 24000},
 312         {241500000,     4096,   241500, 24000},
 313         {297000000,     3072,   222750, 24000},
 314         {0,             0,      0},
 315 };
 316
 317 const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
 318         {25200000,      5880,   26250,  25000},
 319         {27000000,      5880,   28125,  25000},
 320         {74250000,      4704,   61875,  20000},
 321         {148500000,     4704,   123750, 20000},
 322         {241500000,     4704,   201250, 20000},
 323         {297000000,     4704,   247500, 20000},
 324         {0,             0,      0},
 325 };
 326
 327 const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
 328         {25200000,      6144,   25200,  24000},
 329         {27000000,      6144,   27000,  24000},
 330         {74250000,      6144,   74250,  24000},
 331         {148500000,     6144,   148500, 24000},
 332         {241500000,     5632,   221375, 22000},
 333         {297000000,     5120,   247500, 24000},
 334         {0,             0,      0},
 335 };
 336
 337 const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
 338         {25200000,      11760,  26250,  25000},
 339         {27000000,      11760,  28125,  25000},
 340         {74250000,      9408,   61875,  20000},
 341         {148500000,     9408,   123750, 20000},
 342         {241500000,     9408,   201250, 20000},
 343         {297000000,     9408,   247500, 20000},
 344         {0,             0,      0},
 345 };
 346
 347 const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
 348         {25200000,      12288,  25200,  24000},
 349         {27000000,      12288,  27000,  24000},
 350         {74250000,      12288,  74250,  24000},
 351         {148500000,     12288,  148500, 24000},
 352         {241500000,     11264,  221375, 22000},
 353         {297000000,     10240,  247500, 24000},
 354         {0,             0,      0},
 355 };
 356
 357 const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
 358         {25200000,      23520,  26250,  25000},
 359         {27000000,      23520,  28125,  25000},
 360         {74250000,      18816,  61875,  20000},
 361         {148500000,     18816,  123750, 20000},
 362         {241500000,     18816,  201250, 20000},
 363         {297000000,     18816,  247500, 20000},
 364         {0,             0,      0},
 365 };
 366
 367 const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
 368         {25200000,      24576,  25200,  24000},
 369         {27000000,      24576,  27000,  24000},
 370         {74250000,      24576,  74250,  24000},
 371         {148500000,     24576,  148500, 24000},
 372         {241500000,     22528,  221375, 22000},
 373         {297000000,     20480,  247500, 24000},
 374         {0,             0,      0},
 375 };
 376
 377 static const struct tegra_hdmi_audio_config
 378 *tegra_hdmi_get_audio_config(unsigned audio_freq, unsigned pix_clock)
 379 {
 380         const struct tegra_hdmi_audio_config *table;
 381
 382         switch (audio_freq) {
 383         case AUDIO_FREQ_32K:
 384                 table = tegra_hdmi_audio_32k;
 385                 break;
 386         case AUDIO_FREQ_44_1K:
 387                 table = tegra_hdmi_audio_44_1k;
 388                 break;
 389         case AUDIO_FREQ_48K:
 390                 table = tegra_hdmi_audio_48k;
 391                 break;
 392         case AUDIO_FREQ_88_2K:
 393                 table = tegra_hdmi_audio_88_2k;
 394                 break;
 395         case AUDIO_FREQ_96K:
 396                 table = tegra_hdmi_audio_96k;
 397                 break;
 398         case AUDIO_FREQ_176_4K:
 399                 table = tegra_hdmi_audio_176_4k;
 400                 break;
 401         case AUDIO_FREQ_192K:
 402                 table = tegra_hdmi_audio_192k;
 403                 break;
 404         default:
 405                 return NULL;
 406         }
 407
 408         while (table->pix_clock) {
 409                 if (table->pix_clock > (pix_clock/100*99) &&
 410                 table->pix_clock < (pix_clock/100*101) &&
 411                 table->pix_clock >= 1000)
 412                         return table;
 413                 table++;
 414         }
 415
 416         return NULL;
 417 }
 418
 419
 420 unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
 421                                              unsigned long reg)
 422 {
 423         unsigned long ret;
 424
 425         if (WARN(!tegra_is_clk_enabled(hdmi->dc->clk), "DC is clock-gated.\n") ||
 426                 WARN(!tegra_powergate_is_powered(hdmi->dc->powergate_id),
 427                         "DC is power-gated.\n"))
 428                 return 0;
 429
 430         ret = readl(hdmi->base + reg * 4);
 431         trace_display_readl(hdmi->dc, ret, hdmi->base + reg * 4);
 432         return ret;
 433 }
 434
 435 void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
 436                                      unsigned long val, unsigned long reg)
 437 {
 438         if (WARN(!tegra_is_clk_enabled(hdmi->dc->clk), "DC is clock-gated.\n") ||
 439                 WARN(!tegra_powergate_is_powered(hdmi->dc->powergate_id),
 440                         "DC is power-gated.\n"))
 441                 return;
 442
 443         trace_display_writel(hdmi->dc, val, hdmi->base + reg * 4);
 444         writel(val, hdmi->base + reg * 4);
 445 }
 446
 447 static inline int tegra_hdmi_writel_eld_buf(struct tegra_dc_hdmi_data *hdmi,
 448                                             const u8 *buf,
 449                                             size_t buf_entries, size_t index,
 450                                             void __iomem *eld_buf_addr)
 451 {
 452         size_t end_index = index + buf_entries;
 453         do {
 454                 unsigned long val = (index << 8) | *buf;
 455
 456                 trace_display_writel(hdmi->dc, val, eld_buf_addr);
 457                 writel(val, eld_buf_addr);
 458                 index++;
 459                 buf++;
 460         } while (index < end_index);
 461         /* outer for loop that uses this will increment index by 1 */
 462         return index - 1;
 463 }
 464
 465 static inline void tegra_hdmi_clrsetbits(struct tegra_dc_hdmi_data *hdmi,
 466                                          unsigned long reg, unsigned long clr,
 467                                          unsigned long set)
 468 {
 469         unsigned long val = tegra_hdmi_readl(hdmi, reg);
 470         val &= ~clr;
 471         val |= set;
 472         tegra_hdmi_writel(hdmi, val, reg);
 473 }
 474
 475 #ifdef CONFIG_DEBUG_FS
 476 static int dbg_hdmi_show(struct seq_file *m, void *unused)
 477 {
 478         struct tegra_dc_hdmi_data *hdmi = m->private;
 479
 480         /* If gated quitely return */
 481         if (!tegra_dc_is_powered(hdmi->dc))
 482                 return 0;
 483
 484 #define DUMP_REG(a) do {                                                \
 485                 seq_printf(m, "%-32s\t%03x\t%08lx\n",                   \
 486                        #a, a, tegra_hdmi_readl(hdmi, a));               \
 487         } while (0)
 488
 489         tegra_dc_io_start(hdmi->dc);
 490         clk_prepare_enable(hdmi->clk);
 491
 492         DUMP_REG(HDMI_CTXSW);
 493         DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
 494         DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
 495         DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
 496         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
 497         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
 498         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
 499         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
 500         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
 501         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
 502         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
 503         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
 504         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
 505         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
 506         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
 507         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
 508         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
 509         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
 510         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
 511         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
 512         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
 513         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
 514         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
 515         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
 516         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
 517         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
 518         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
 519         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
 520         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
 521         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
 522         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 523         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
 524         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
 525         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
 526         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
 527         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 528         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
 529         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
 530         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
 531         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
 532         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
 533         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
 534         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 535         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
 536         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
 537         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
 538         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
 539         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
 540         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
 541         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
 542         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
 543         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
 544         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
 545         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
 546         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
 547         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
 548         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 549         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 550         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
 551         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
 552         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
 553         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
 554         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
 555         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
 556         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
 557         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
 558         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
 559         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
 560         DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
 561         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
 562         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 563         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
 564         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
 565         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
 566         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
 567         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
 568         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
 569         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
 570         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
 571         DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
 572         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
 573         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
 574         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_CTRL);
 575         DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
 576         DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
 577         DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
 578         DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
 579         DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
 580         DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
 581         DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
 582         DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
 583         DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
 584         DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
 585         DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
 586         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
 587         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST0);
 588         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST1);
 589         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST2);
 590         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST3);
 591         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST4);
 592         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST5);
 593         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST6);
 594         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST7);
 595         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST8);
 596         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST9);
 597         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTA);
 598         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTB);
 599         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTC);
 600         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTD);
 601         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTE);
 602         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTF);
 603         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
 604         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
 605         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
 606         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
 607         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
 608         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
 609         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
 610         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
 611         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
 612         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
 613         DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
 614         DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
 615         DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 616         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
 617         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
 618         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
 619         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
 620         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
 621         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
 622         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
 623         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
 624         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
 625         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
 626         DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
 627         DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
 628         DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
 629         DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
 630         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
 631         DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
 632         DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
 633         DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
 634         DUMP_REG(HDMI_NV_PDISP_SCRATCH);
 635         DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
 636         DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
 637         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
 638         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
 639         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
 640         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
 641         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
 642         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
 643         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
 644         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
 645         DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
 646 #if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
 647         DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
 648 #endif
 649 #if !defined(CONFIG_ARCH_TEGRA_3x_SOC) && !defined(CONFIG_ARCH_TEGRA_11x_SOC)
 650         DUMP_REG(HDMI_NV_PDISP_SOR_PAD_CTLS0);
 651         DUMP_REG(HDMI_NV_PDISP_SOR_PAD_CTLS1);
 652         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_CTRL);
 653         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_STATUS);
 654         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_HEADER);
 655         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_LOW);
 656         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH);
 657         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_LOW);
 658         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH);
 659         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_LOW);
 660         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH);
 661         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_LOW);
 662         DUMP_REG(HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH);
 663 #endif
 664
 665 #undef DUMP_REG
 666
 667         clk_disable_unprepare(hdmi->clk);
 668         tegra_dc_io_end(hdmi->dc);
 669
 670         return 0;
 671 }
 672
 673 static int dbg_hdmi_show_open(struct inode *inode, struct file *file)
 674 {
 675         return single_open(file, dbg_hdmi_show, inode->i_private);
 676 }
 677
 678 static const struct file_operations dbg_hdmi_show_fops = {
 679         .open           = dbg_hdmi_show_open,
 680         .read           = seq_read,
 681         .llseek         = seq_lseek,
 682         .release        = single_release,
 683 };
 684
 685 static int dbg_hotplug_show(struct seq_file *m, void *unused)
 686 {
 687         struct tegra_dc_hdmi_data *hdmi = m->private;
 688         struct tegra_dc *dc = hdmi->dc;
 689
 690         if (WARN_ON(!hdmi || !dc || !dc->out))
 691                 return -EINVAL;
 692
 693         seq_put_decimal_ll(m, '\0', dc->out->hotplug_state);
 694         seq_putc(m, '\n');
 695         return 0;
 696 }
 697
 698 static int dbg_hotplug_open(struct inode *inode, struct file *file)
 699 {
 700         return single_open(file, dbg_hotplug_show, inode->i_private);
 701 }
 702
 703 static ssize_t dbg_hotplug_write(struct file *file, const char __user *addr,
 704         size_t len, loff_t *pos)
 705 {
 706         struct seq_file *m = file->private_data; /* single_open() initialized */
 707         struct tegra_dc_hdmi_data *hdmi = m->private;
 708         struct tegra_dc *dc = hdmi->dc;
 709         int ret;
 710         long new_state;
 711
 712         if (WARN_ON(!hdmi || !dc || !dc->out))
 713                 return -EINVAL;
 714
 715         ret = kstrtol_from_user(addr, len, 10, &new_state);
 716         if (ret < 0)
 717                 return ret;
 718
 719         if (dc->out->hotplug_state == 0 && new_state != 0
 720                         && tegra_dc_hotplug_supported(dc)) {
 721                 /* was 0, now -1 or 1.
 722                  * we are overriding the hpd GPIO, so ignore the interrupt. */
 723                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
 724
 725                 disable_irq(gpio_irq);
 726         } else if (dc->out->hotplug_state != 0 && new_state == 0
 727                         && tegra_dc_hotplug_supported(dc)) {
 728                 /* was -1 or 1, and now 0
 729                  * restore the interrupt for hpd GPIO. */
 730                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
 731
 732                 enable_irq(gpio_irq);
 733         }
 734
 735         dc->out->hotplug_state = new_state;
 736
 737         hdmi_state_machine_set_pending_hpd();
 738
 739         return len;
 740 }
 741
 742 static const struct file_operations dbg_hotplug_fops = {
 743         .open           = dbg_hotplug_open,
 744         .read           = seq_read,
 745         .write          = dbg_hotplug_write,
 746         .llseek         = seq_lseek,
 747         .release        = single_release,
 748 };
 749
 750 static struct dentry *hdmidir;
 751
 752 static void tegra_dc_hdmi_debug_create(struct tegra_dc_hdmi_data *hdmi)
 753 {
 754         struct dentry *retval;
 755
 756         hdmidir = debugfs_create_dir("tegra_hdmi", NULL);
 757         if (!hdmidir)
 758                 return;
 759         retval = debugfs_create_file("regs", S_IRUGO, hdmidir, hdmi,
 760                 &dbg_hdmi_show_fops);
 761         if (!retval)
 762                 goto free_out;
 763         retval = debugfs_create_file("hotplug", S_IRUGO, hdmidir, hdmi,
 764                 &dbg_hotplug_fops);
 765         if (!retval)
 766                 goto free_out;
 767         return;
 768 free_out:
 769         debugfs_remove_recursive(hdmidir);
 770         hdmidir = NULL;
 771         return;
 772 }
 773 #else
 774 static inline void tegra_dc_hdmi_debug_create(struct tegra_dc_hdmi_data *hdmi)
 775 { }
 776 #endif
 777
 778 #define PIXCLOCK_TOLERANCE      200
 779
 780 static int tegra_dc_calc_clock_per_frame(const struct fb_videomode *mode)
 781 {
 782         return (mode->left_margin + mode->xres +
 783                 mode->right_margin + mode->hsync_len) *
 784                (mode->upper_margin + mode->yres +
 785                 mode->lower_margin + mode->vsync_len);
 786 }
 787
 788 static bool tegra_dc_hdmi_valid_pixclock(const struct tegra_dc *dc,
 789                                         const struct fb_videomode *mode)
 790 {
 791         unsigned max_pixclock = tegra_dc_get_out_max_pixclock(dc);
 792         if (max_pixclock) {
 793                 /* this might look counter-intuitive,
 794                  * but pixclock's unit is picos(not Khz)
 795                  */
 796                 return mode->pixclock >= max_pixclock;
 797         } else {
 798                 return true;
 799         }
 800 }
 801
 802 static bool tegra_dc_check_constraint(const struct fb_videomode *mode)
 803 {
 804         return mode->hsync_len >= 1 && mode->vsync_len >= 1 &&
 805                 mode->lower_margin + mode->vsync_len + mode->upper_margin > 1 &&
 806                 mode->xres >= 16 && mode->yres >= 16;
 807 }
 808
 809 /* adjusts pixclock to fit audio table */
 810 static bool tegra_dc_hdmi_adjust_pixclock(const struct tegra_dc *dc,
 811                                         struct fb_videomode *mode)
 812 {
 813         const struct tegra_hdmi_audio_config *cfg = tegra_hdmi_audio_44_1k;
 814         unsigned pclk;
 815
 816         if (!mode->pixclock)
 817                 return false;
 818
 819         pclk = PICOS2KHZ(mode->pixclock) * 1000;
 820
 821         /* look on 44.1k audio table, if mode's pixel clock is within 1%, then
 822          * use the pixel clock from the audio table.*/
 823         while (cfg->pix_clock) {
 824                 if (cfg->pix_clock > (pclk / 100 * 99) &&
 825                         cfg->pix_clock < (pclk / 100 * 101) &&
 826                         cfg->pix_clock >= 1000) {
 827                         mode->pixclock = KHZ2PICOS(cfg->pix_clock / 1000);
 828                         return true;
 829                 }
 830                 cfg++;
 831         }
 832         return false;
 833 }
 834
 835 bool tegra_dc_hdmi_mode_filter(const struct tegra_dc *dc,
 836                                         struct fb_videomode *mode)
 837 {
 838         long total_clocks;
 839
 840 #ifndef CONFIG_ARCH_TEGRA_12x_SOC
 841         if (mode->vmode & FB_VMODE_INTERLACED)
 842                 return false;
 843 #endif
 844
 845         /* Ignore modes with a 0 pixel clock */
 846         if (!mode->pixclock)
 847                 return false;
 848
 849 #ifdef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
 850                 if (PICOS2KHZ(mode->pixclock) > 74250)
 851                         return false;
 852 #endif
 853
 854 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
 855         /* Display B max is 4096 */
 856         if (mode->xres > 4096)
 857                 return false;
 858 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
 859         if (mode->xres > 2560)
 860                 return false;
 861 #else
 862         /* don't filter any modes due to width - probably not what you want */
 863 #endif
 864
 865         tegra_dc_hdmi_adjust_pixclock(dc, mode);
 866
 867         /* Check if the mode's pixel clock is more than the max rate*/
 868         if (!tegra_dc_hdmi_valid_pixclock(dc, mode))
 869                 return false;
 870
 871         /* Work around for modes that fail the constrait:
 872          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1 */
 873         if (mode->lower_margin == 1) {
 874                 mode->lower_margin++;
 875                 mode->upper_margin--;
 876         }
 877
 878         /* even after fix-ups the mode still isn't supported */
 879         if (!tegra_dc_check_constraint(mode))
 880                 return false;
 881
 882         mode->flag |= FB_MODE_IS_DETAILED;
 883         total_clocks = tegra_dc_calc_clock_per_frame(mode);
 884         mode->refresh = total_clocks ?
 885                 (PICOS2KHZ(mode->pixclock) * 1000) / total_clocks : 0;
 886
 887         return true;
 888 }
 889
 890 /* used by tegra_dc_probe() to detect hpd/hdmi status at boot */
 891 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
 892 {
 893         /* trigger an edid read by the hdmi state machine */
 894         hdmi_state_machine_set_pending_hpd();
 895
 896         return tegra_dc_hpd(dc);
 897 }
 898
 899 static irqreturn_t tegra_dc_hdmi_irq(int irq, void *ptr)
 900 {
 901         struct tegra_dc *dc = ptr;
 902         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 903
 904         pr_info("%s: start\n", __func__);
 905         rt_mutex_lock(&hdmi->suspend_lock);
 906         if (!hdmi->suspended)
 907                 hdmi_state_machine_set_pending_hpd();
 908         rt_mutex_unlock(&hdmi->suspend_lock);
 909         pr_info("%s: end\n", __func__);
 910         return IRQ_HANDLED;
 911 }
 912
 913 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
 914 {
 915         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 916
 917         tegra_nvhdcp_suspend(hdmi->nvhdcp);
 918
 919         if (hdmi->info.hdmi2fpd_bridge_enable)
 920                 hdmi2fpd_suspend(hdmi);
 921
 922         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0) {
 923                 int wake_irq = gpio_to_irq(dc->out->hotplug_gpio);
 924                 int ret;
 925
 926                 ret = enable_irq_wake(wake_irq);
 927                 if (ret < 0) {
 928                         dev_err(&dc->ndev->dev,
 929                         "%s: Couldn't enable HDMI wakeup, irq=%d, error=%d\n",
 930                         __func__, wake_irq, ret);
 931                 }
 932         }
 933
 934         rt_mutex_lock(&hdmi->suspend_lock);
 935         hdmi->suspended = true;
 936         rt_mutex_unlock(&hdmi->suspend_lock);
 937
 938 }
 939
 940 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
 941 {
 942         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 943
 944         rt_mutex_lock(&hdmi->suspend_lock);
 945         hdmi->suspended = false;
 946         hdmi_state_machine_set_pending_hpd();
 947         rt_mutex_unlock(&hdmi->suspend_lock);
 948
 949         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
 950                 disable_irq_wake(gpio_to_irq(dc->out->hotplug_gpio));
 951
 952         if (hdmi->info.hdmi2fpd_bridge_enable)
 953                 hdmi2fpd_resume(hdmi);
 954
 955         tegra_nvhdcp_resume(hdmi->nvhdcp);
 956 }
 957
 958 #ifdef CONFIG_SWITCH
 959 static ssize_t underscan_show(struct device *dev,
 960                                 struct device_attribute *attr, char *buf)
 961 {
 962         struct tegra_dc_hdmi_data *hdmi =
 963                         container_of(dev_get_drvdata(dev), struct tegra_dc_hdmi_data, hpd_switch);
 964
 965         if (hdmi->edid)
 966                 return sprintf(buf, "%d\n", tegra_edid_underscan_supported(hdmi->edid));
 967         else
 968                 return 0;
 969 }
 970
 971 static DEVICE_ATTR(underscan, S_IRUGO, underscan_show, NULL);
 972
 973 static ssize_t hdmi_audio_show(struct device *dev,
 974                                 struct device_attribute *attr, char *buf)
 975 {
 976         struct tegra_dc_hdmi_data *hdmi =
 977                         container_of(dev_get_drvdata(dev),
 978                                    struct tegra_dc_hdmi_data, audio_switch);
 979
 980         if (hdmi->edid)
 981                 return sprintf(buf, "%d\n",
 982                                    tegra_edid_audio_supported(hdmi->edid));
 983         else
 984                 return 0;
 985 }
 986
 987 static DEVICE_ATTR(hdmi_audio, S_IRUGO, hdmi_audio_show, NULL);
 988 #endif
 989
 990
 991 static int tegra_dc_hdmi_i2c_xfer(struct tegra_dc *dc, struct i2c_msg *msgs,
 992         int num)
 993 {
 994         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 995
 996         return i2c_transfer(hdmi->i2c_info.client->adapter, msgs, num);
 997 }
 998
 999 /* This is needed to obtain audio channel info before HAL
1000  * opens pcm stream and copies edid audio data */
1001 static int tegra_hdmi_get_max_channels(void)
1002 {
1003         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1004         u8 sad_channels;
1005         u8 sad_format;
1006         u8 max_channels = 0;
1007         int i;
1008
1009         if (!hdmi)
1010                 return 0;
1011
1012         if (!hdmi->eld_retrieved)
1013                 return 0;
1014
1015         if (!hdmi->dc->enabled)
1016                 return 0;
1017
1018         for (i = 0; i < hdmi->eld.sad_count; i++) {
1019                 sad_channels = max(((hdmi->eld.sad[AUDIO_SAD_BYTE_SIZE*i]
1020                         & 0x7) + 1), 2);
1021                 sad_format = ((hdmi->eld.sad[AUDIO_SAD_BYTE_SIZE*i]
1022                         & 0x78) >> 3);
1023                 if (sad_format == AUDIO_CODING_TYPE_LPCM)
1024                         max_channels =  max_channels > sad_channels ?
1025                                 max_channels : sad_channels;
1026         }
1027         return max_channels;
1028 }
1029
1030 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
1031 {
1032         struct tegra_dc_hdmi_data *hdmi;
1033         struct resource *res;
1034         struct resource hdmi_res;
1035         struct resource *base_res;
1036         int ret;
1037         void __iomem *base;
1038         struct clk *clk = NULL;
1039         struct clk *disp1_clk = NULL;
1040         struct clk *disp2_clk = NULL;
1041         struct tegra_hdmi_out *hdmi_out = NULL;
1042         struct i2c_adapter *adapter = NULL;
1043         int err;
1044         struct device_node *np = dc->ndev->dev.of_node;
1045 #ifdef CONFIG_OF
1046         struct device_node *np_hdmi =
1047                 of_find_node_by_path(HDMI_NODE);
1048 #else
1049         struct device_node *np_hdmi = NULL;
1050 #endif
1051         struct device_node *np_panel = NULL;
1052
1053         bool virtual_edid = false;
1054         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1055         if (!hdmi) {
1056                 of_node_put(np_hdmi);
1057                 return -ENOMEM;
1058         }
1059         if (np) {
1060                 if (np_hdmi && of_device_is_available(np_hdmi)) {
1061                         of_address_to_resource(np_hdmi, 0, &hdmi_res);
1062                         res = &hdmi_res;
1063                         np_panel = tegra_get_panel_node_out_type_check(dc,
1064                                 TEGRA_DC_OUT_HDMI);
1065                         if (np_panel && of_device_is_available(np_panel)) {
1066                                 virtual_edid = of_property_read_bool(np_panel,
1067                                         "nvidia,edid");
1068                                 of_node_put(np_panel);
1069                         }
1070                 } else {
1071                         err = -EINVAL;
1072                         of_node_put(np_panel);
1073                         goto err_free_hdmi;
1074                 }
1075         } else {
1076                 res = platform_get_resource_byname(dc->ndev,
1077                         IORESOURCE_MEM, "hdmi_regs");
1078         }
1079         if (!res) {
1080                 dev_err(&dc->ndev->dev, "hdmi: no mem resource\n");
1081                 err = -ENOENT;
1082                 goto err_free_hdmi;
1083         }
1084
1085         base_res = request_mem_region(res->start,
1086                 resource_size(res), dc->ndev->name);
1087         if (!base_res) {
1088                 dev_err(&dc->ndev->dev, "hdmi: request_mem_region failed\n");
1089                 err = -EBUSY;
1090                 goto err_free_hdmi;
1091         }
1092
1093         base = ioremap(res->start, resource_size(res));
1094         if (!base) {
1095                 dev_err(&dc->ndev->dev, "hdmi: registers can't be mapped\n");
1096                 err = -EBUSY;
1097                 goto err_release_resource_reg;
1098         }
1099
1100         clk = clk_get(&dc->ndev->dev, "hdmi");
1101         if (IS_ERR_OR_NULL(clk)) {
1102                 dev_err(&dc->ndev->dev, "hdmi: can't get clock\n");
1103                 err = -ENOENT;
1104                 goto err_iounmap_reg;
1105         }
1106
1107         disp1_clk = clk_get_sys("tegradc.0", NULL);
1108         if (IS_ERR_OR_NULL(disp1_clk)) {
1109                 dev_err(&dc->ndev->dev, "hdmi: can't disp1 clock\n");
1110                 err = -ENOENT;
1111                 goto err_put_clock;
1112         }
1113
1114         disp2_clk = clk_get_sys("tegradc.1", NULL);
1115         if (IS_ERR_OR_NULL(disp2_clk)) {
1116                 dev_err(&dc->ndev->dev, "hdmi: can't disp2 clock\n");
1117                 err = -ENOENT;
1118                 goto err_put_clock;
1119         }
1120
1121 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1122         hdmi->hda_clk = clk_get_sys("tegra30-hda", "hda");
1123         if (IS_ERR_OR_NULL(hdmi->hda_clk)) {
1124                 dev_err(&dc->ndev->dev, "hdmi: can't get hda clock\n");
1125                 err = -ENOENT;
1126                 goto err_put_clock;
1127         }
1128
1129         hdmi->hda2codec_clk = clk_get_sys("tegra30-hda", "hda2codec");
1130         if (IS_ERR_OR_NULL(hdmi->hda2codec_clk)) {
1131                 dev_err(&dc->ndev->dev, "hdmi: can't get hda2codec clock\n");
1132                 err = -ENOENT;
1133                 goto err_put_clock;
1134         }
1135
1136         hdmi->hda2hdmi_clk = clk_get_sys("tegra30-hda", "hda2hdmi");
1137         if (IS_ERR_OR_NULL(hdmi->hda2hdmi_clk)) {
1138                 dev_err(&dc->ndev->dev, "hdmi: can't get hda2hdmi clock\n");
1139                 err = -ENOENT;
1140                 goto err_put_clock;
1141         }
1142 #endif
1143
1144         /* Get the pointer of board file settings */
1145         hdmi_out = dc->pdata->default_out->hdmi_out;
1146         if (hdmi_out)
1147                 memcpy(&hdmi->info, hdmi_out, sizeof(hdmi->info));
1148
1149         if (virtual_edid)
1150                 hdmi->edid = tegra_edid_create(dc, tegra_dc_edid_blob);
1151         else
1152                 hdmi->edid = tegra_edid_create(dc, tegra_dc_hdmi_i2c_xfer);
1153
1154         if (IS_ERR_OR_NULL(hdmi->edid)) {
1155                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
1156                 err = PTR_ERR(hdmi->edid);
1157                 goto err_put_clock;
1158         }
1159         tegra_dc_set_edid(dc, hdmi->edid);
1160
1161         adapter = i2c_get_adapter(dc->out->dcc_bus);
1162         if (!adapter) {
1163                 pr_err("can't get adpater for bus %d\n", dc->out->dcc_bus);
1164                 err = -EBUSY;
1165                 goto err_put_clock;
1166         }
1167
1168         hdmi->i2c_info.board.addr = 0x50;
1169         hdmi->i2c_info.board.platform_data = hdmi;
1170         strlcpy(hdmi->i2c_info.board.type, "tegra_hdmi",
1171                 sizeof(hdmi->i2c_info.board.type));
1172
1173         hdmi->i2c_info.client = i2c_new_device(adapter, &hdmi->i2c_info.board);
1174         i2c_put_adapter(adapter);
1175
1176         if (!hdmi->i2c_info.client) {
1177                 pr_err("can't create new device\n");
1178                 err = -EBUSY;
1179                 goto err_put_clock;
1180         }
1181
1182 #ifdef CONFIG_TEGRA_NVHDCP
1183         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, tegra_dc_which_sor(dc),
1184                         dc->out->ddc_bus);
1185         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
1186                 dev_err(&dc->ndev->dev, "hdmi: can't create nvhdcp\n");
1187                 err = PTR_ERR(hdmi->nvhdcp);
1188                 goto err_edid_destroy;
1189         }
1190 #else
1191         hdmi->nvhdcp = NULL;
1192 #endif
1193         hdmi_state_machine_init(hdmi);
1194
1195         hdmi->dc = dc;
1196         hdmi->base = base;
1197         hdmi->base_res = base_res;
1198         hdmi->clk = clk;
1199         hdmi->disp1_clk = disp1_clk;
1200         hdmi->disp2_clk = disp2_clk;
1201         hdmi->suspended = false;
1202         hdmi->eld_retrieved = false;
1203         hdmi->clk_enabled = false;
1204         hdmi->audio_freq = 44100;
1205         hdmi->audio_source = AUTO;
1206         rt_mutex_init(&hdmi->suspend_lock);
1207
1208 #ifdef CONFIG_SWITCH
1209         hdmi->hpd_switch.name = "hdmi";
1210         ret = switch_dev_register(&hdmi->hpd_switch);
1211
1212         if (!ret)
1213                 ret = device_create_file(hdmi->hpd_switch.dev,
1214                         &dev_attr_underscan);
1215         BUG_ON(ret != 0);
1216
1217         hdmi->audio_switch.name = "hdmi_audio";
1218         ret = switch_dev_register(&hdmi->audio_switch);
1219
1220         if (!ret)
1221                 ret = device_create_file(hdmi->audio_switch.dev,
1222                         &dev_attr_hdmi_audio);
1223         BUG_ON(ret != 0);
1224 #endif
1225
1226         dc->out->depth = 24;
1227
1228         tegra_dc_set_outdata(dc, hdmi);
1229
1230         dc_hdmi = hdmi;
1231         /* boards can select default content protection policy */
1232         if (dc->out->flags & TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND)
1233                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
1234                         TEGRA_NVHDCP_POLICY_ON_DEMAND);
1235         else
1236                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
1237                         TEGRA_NVHDCP_POLICY_ALWAYS_ON);
1238
1239         tegra_dc_hdmi_debug_create(hdmi);
1240
1241         if (tegra_dc_hotplug_supported(dc)) {
1242                 err = gpio_request(dc->out->hotplug_gpio, "hdmi_hpd");
1243                 if (err < 0) {
1244                         dev_err(&dc->ndev->dev, "hdmi: hpd gpio_request failed\n");
1245                         goto err_nvhdcp_destroy;
1246                 }
1247
1248                 gpio_direction_input(dc->out->hotplug_gpio);
1249
1250                 /* TODO: support non-hotplug */
1251                 ret = request_threaded_irq(gpio_to_irq(dc->out->hotplug_gpio),
1252                                 NULL, tegra_dc_hdmi_irq,
1253                                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1254                                 | IRQF_ONESHOT,
1255                                 dev_name(&dc->ndev->dev), dc);
1256
1257                 if (ret) {
1258                         dev_err(&dc->ndev->dev,
1259                                         "hdmi: request_irq %d failed - %d\n",
1260                                         gpio_to_irq(dc->out->hotplug_gpio),
1261                                         ret);
1262                         err = -EBUSY;
1263                         goto err_gpio_free;
1264                 }
1265         }
1266         if (hdmi->info.hdmi2fpd_bridge_enable)
1267                 hdmi2fpd_init(hdmi);
1268
1269         /* NOTE: Below code is applicable to L4T or embedded systems and is
1270          * protected accordingly. This section early enables DC with first mode
1271          * from the monitor specs.
1272          * In case there is no hotplug we are falling back
1273          * to default VGA mode.
1274          */
1275         if ((config_enabled(CONFIG_FRAMEBUFFER_CONSOLE) ||
1276                         ((dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) &&
1277                          (dc->pdata->flags & TEGRA_DC_FLAG_SET_EARLY_MODE))) &&
1278                         dc->out && (dc->out->type == TEGRA_DC_OUT_HDMI)) {
1279                 struct fb_monspecs specs;
1280                 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
1281                         if (!tegra_edid_get_monspecs(hdmi->edid, &specs))
1282                                 tegra_dc_set_fb_mode(dc, specs.modedb, false);
1283                         kfree(specs.modedb);
1284                 } else
1285                         tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, false);
1286         }
1287
1288         /*Add sysfs node to query hdmi audio channels on startup*/
1289         hdmi_audio = kobject_create_and_add("hdmi_audio_channels", kernel_kobj);
1290         if (!hdmi_audio) {
1291                 pr_warn("kobject create_and_add hdmi_audio_channels failed\n");
1292                 of_node_put(np_hdmi);
1293                 return 0;
1294         }
1295         ret = sysfs_create_file(hdmi_audio, &hdmi_audio_channel_config.attr);
1296         if (ret) {
1297                 pr_warn("sysfs create file hdmi_audio_channels failed\n");
1298                 of_node_put(np_hdmi);
1299                 return 0;
1300         }
1301         of_node_put(np_hdmi);
1302         return 0;
1303
1304 err_gpio_free:
1305         if (tegra_dc_hotplug_supported(dc))
1306                 gpio_free(dc->out->hotplug_gpio);
1307 err_nvhdcp_destroy:
1308         if (hdmi->nvhdcp)
1309                 tegra_nvhdcp_destroy(hdmi->nvhdcp);
1310 #ifdef CONFIG_TEGRA_NVHDCP
1311 err_edid_destroy:
1312 #endif
1313         tegra_edid_destroy(hdmi->edid);
1314 err_put_clock:
1315 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1316         if (!IS_ERR_OR_NULL(hdmi->hda2hdmi_clk))
1317                 clk_put(hdmi->hda2hdmi_clk);
1318         if (!IS_ERR_OR_NULL(hdmi->hda2codec_clk))
1319                 clk_put(hdmi->hda2codec_clk);
1320         if (!IS_ERR_OR_NULL(hdmi->hda_clk))
1321                 clk_put(hdmi->hda_clk);
1322 #endif
1323         if (!IS_ERR_OR_NULL(disp2_clk))
1324                 clk_put(disp2_clk);
1325         if (!IS_ERR_OR_NULL(disp1_clk))
1326                 clk_put(disp1_clk);
1327         if (!IS_ERR_OR_NULL(clk))
1328                 clk_put(clk);
1329 err_iounmap_reg:
1330         iounmap(base);
1331 err_release_resource_reg:
1332         release_resource(base_res);
1333 err_free_hdmi:
1334         kfree(hdmi);
1335         of_node_put(np_hdmi);
1336         return err;
1337 }
1338
1339 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
1340 {
1341         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1342
1343         if (tegra_dc_hotplug_supported(dc))
1344                 free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
1345         hdmi_state_machine_shutdown();
1346
1347         if (hdmi->info.hdmi2fpd_bridge_enable)
1348                 hdmi2fpd_destroy(hdmi);
1349
1350         i2c_release_client(hdmi->i2c_info.client);
1351 #ifdef CONFIG_SWITCH
1352         switch_dev_unregister(&hdmi->hpd_switch);
1353         switch_dev_unregister(&hdmi->audio_switch);
1354 #endif
1355         iounmap(hdmi->base);
1356         release_resource(hdmi->base_res);
1357 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1358         clk_put(hdmi->hda2hdmi_clk);
1359         clk_put(hdmi->hda2codec_clk);
1360         clk_put(hdmi->hda_clk);
1361 #endif
1362         clk_put(hdmi->clk);
1363         clk_put(hdmi->disp1_clk);
1364         clk_put(hdmi->disp2_clk);
1365         tegra_edid_destroy(hdmi->edid);
1366         tegra_nvhdcp_destroy(hdmi->nvhdcp);
1367
1368         kfree(hdmi);
1369
1370 }
1371
1372 static void tegra_dc_hdmi_setup_audio_fs_tables(struct tegra_dc *dc)
1373 {
1374         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1375         int i;
1376         unsigned freqs[] = {
1377                 32000,
1378                 44100,
1379                 48000,
1380                 88200,
1381                 96000,
1382                 176400,
1383                 192000,
1384         };
1385
1386         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
1387                 unsigned f = freqs[i];
1388                 unsigned eight_half;
1389                 unsigned delta;;
1390
1391                 if (f > 96000)
1392                         delta = 2;
1393                 else if (f > 48000)
1394                         delta = 6;
1395                 else
1396                         delta = 9;
1397
1398                 if (!f)
1399                         eight_half = 0;
1400                 else
1401                         eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
1402                 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
1403                                   AUDIO_FS_HIGH(eight_half + delta),
1404                                   HDMI_NV_PDISP_AUDIO_FS(i));
1405         }
1406 }
1407
1408 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1409 static void tegra_dc_hdmi_setup_eld_buff(struct tegra_dc *dc)
1410 {
1411         size_t i;
1412         u8 tmp;
1413         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1414         void __iomem *eld_buf_addr;
1415         int baseline_eld_len = (HDMI_ELD_MONITOR_NAME_INDEX -
1416                                 HDMI_ELD_CEA_VER_MNL_INDEX +
1417                                 hdmi->eld.mnl +
1418                                 (3 * hdmi->eld.sad_count));
1419         u8 baseline_eld_len_val;
1420
1421         eld_buf_addr = hdmi->base + HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0 * 4;
1422
1423         /* the baseline_eld_len needs to be written as a
1424          * multiple of DWORDS (4 bytes).
1425          */
1426         BUG_ON(baseline_eld_len > MAX_BASELINE_ELD_SIZE);
1427         baseline_eld_len_val = DIV_ROUND_UP(baseline_eld_len, 4);
1428
1429         /* program ELD stuff.  we must write all bytes of the
1430          * ELD buffer.  when hda_eld.c tries to read it back,
1431          * it's query of the size returns not how many valid
1432          * were written, but the entire size, and will try to
1433          * read all the bytes in the buffer.  it will fail
1434          * if any invalid bytes are read back, so we have to
1435          * fill the entire buffer with something, even if it's
1436          * just zeroes.
1437          */
1438         for (i = 0; i < HDMI_ELD_BUF_SIZE; i++) {
1439                 switch (i) {
1440                 case HDMI_ELD_VER_INDEX:
1441                         tmp = (hdmi->eld.eld_ver << 3);
1442                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1443                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1444                         break;
1445                 case HDMI_ELD_RESERVED1_INDEX:
1446                 case HDMI_ELD_RESERVED2_INDEX:
1447                         /* must write a dummy byte or else hda_eld.c
1448                          * will get an error when it tries to read a
1449                          * complete eld buffer
1450                          */
1451                         tegra_hdmi_writel(hdmi, (i << 8),
1452                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1453                         break;
1454                 case HDMI_ELD_BASELINE_LEN_INDEX:
1455                         tegra_hdmi_writel(hdmi, (i << 8) | baseline_eld_len_val,
1456                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1457                         break;
1458                 case HDMI_ELD_CEA_VER_MNL_INDEX:
1459                         tmp = (hdmi->eld.cea_edid_ver << 5);
1460                         tmp |= (hdmi->eld.mnl & 0x1f);
1461                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1462                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1463                         break;
1464                 case HDMI_ELD_SAD_CNT_CON_TYP_SAI_HDCP_INDEX:
1465                         tmp = (hdmi->eld.sad_count << 4);
1466                         tmp |= (hdmi->eld.conn_type & 0xC);
1467                         tmp |= (hdmi->eld.support_ai & 0x2);
1468                         tmp |= (hdmi->eld.support_hdcp & 0x1);
1469                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1470                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1471                         break;
1472                 case HDMI_ELD_AUD_SYNC_DELAY_INDEX:
1473                         tegra_hdmi_writel(hdmi, (i << 8) | (hdmi->eld.aud_synch_delay),
1474                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1475                         break;
1476                 case HDMI_ELD_SPK_ALLOC_INDEX:
1477                         tegra_hdmi_writel(hdmi, (i << 8) | (hdmi->eld.spk_alloc),
1478                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1479                         break;
1480                 case HDMI_ELD_PORT_ID_INDEX:
1481                         i = tegra_hdmi_writel_eld_buf(hdmi, hdmi->eld.port_id,
1482                                                       8, i, eld_buf_addr);
1483                         break;
1484                 case HDMI_ELD_MANF_NAME_INDEX:
1485                         i = tegra_hdmi_writel_eld_buf(hdmi,
1486                                                       hdmi->eld.manufacture_id,
1487                                                       2, i, eld_buf_addr);
1488                         break;
1489                 case HDMI_ELD_PRODUCT_CODE_INDEX:
1490                         i = tegra_hdmi_writel_eld_buf(hdmi,
1491                                                       hdmi->eld.product_id,
1492                                                       2, i, eld_buf_addr);
1493                         break;
1494                 case HDMI_ELD_MONITOR_NAME_INDEX:
1495                         /* write the eld.mnl bytes of the monitor name,
1496                          * followed immediately the short audio descriptor bytes
1497                          */
1498                         i = tegra_hdmi_writel_eld_buf(hdmi,
1499                                                       hdmi->eld.monitor_name,
1500                                                       hdmi->eld.mnl, i,
1501                                                       eld_buf_addr) + 1;
1502                         i = tegra_hdmi_writel_eld_buf(hdmi, hdmi->eld.sad,
1503                                                       hdmi->eld.sad_count * 3,
1504                                                       i, eld_buf_addr);
1505                         break;
1506                 default:
1507                         tegra_hdmi_writel(hdmi, (i << 8),
1508                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1509                 }
1510         }
1511
1512         /* set presence and valid bit  */
1513         tegra_hdmi_writel(hdmi, 3, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
1514 }
1515 #endif
1516
1517 static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc, unsigned audio_freq,
1518                                         unsigned audio_source)
1519 {
1520         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1521         const struct tegra_hdmi_audio_config *config;
1522         unsigned long audio_n;
1523 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1524         unsigned long reg_addr = 0;
1525 #endif
1526         unsigned a_source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
1527
1528         if (HDA == audio_source)
1529                 a_source = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
1530         else if (SPDIF == audio_source)
1531                 a_source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
1532
1533 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1534         if (hdmi->audio_inject_null)
1535                 a_source |= AUDIO_CNTRL0_INJECT_NULLSMPL;
1536
1537         tegra_hdmi_writel(hdmi,a_source,
1538                           HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1539         tegra_hdmi_writel(hdmi,
1540                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
1541                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0),
1542                           HDMI_NV_PDISP_AUDIO_CNTRL0);
1543 #if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1544         tegra_hdmi_writel(hdmi, (1 << HDMI_AUDIO_HBR_ENABLE_SHIFT) |
1545            tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0),
1546            HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0);
1547 #endif
1548 #else
1549         tegra_hdmi_writel(hdmi,
1550                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
1551                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
1552                           a_source,
1553                           HDMI_NV_PDISP_AUDIO_CNTRL0);
1554 #endif
1555         config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk);
1556         if (!config) {
1557                 dev_err(&dc->ndev->dev,
1558                         "hdmi: can't set audio to %d at %d pix_clock",
1559                         audio_freq, dc->mode.pclk);
1560                 return -EINVAL;
1561         }
1562
1563         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
1564
1565         audio_n = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNALTE |
1566                 AUDIO_N_VALUE(config->n - 1);
1567         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
1568
1569         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
1570                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1571
1572         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
1573                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1574
1575         tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
1576                           SPARE_CTS_RESET_VAL(1),
1577                           HDMI_NV_PDISP_HDMI_SPARE);
1578
1579         audio_n &= ~AUDIO_N_RESETF;
1580         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
1581
1582 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1583         switch (audio_freq) {
1584         case AUDIO_FREQ_32K:
1585                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_0;
1586                 break;
1587         case AUDIO_FREQ_44_1K:
1588                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441_0;
1589                 break;
1590         case AUDIO_FREQ_48K:
1591                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_0;
1592                 break;
1593         case AUDIO_FREQ_88_2K:
1594                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882_0;
1595                 break;
1596         case AUDIO_FREQ_96K:
1597                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960_0;
1598                 break;
1599         case AUDIO_FREQ_176_4K:
1600                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764_0;
1601                 break;
1602         case AUDIO_FREQ_192K:
1603                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920_0;
1604                 break;
1605         }
1606
1607         tegra_hdmi_writel(hdmi, config->aval, reg_addr);
1608 #endif
1609         tegra_dc_hdmi_setup_audio_fs_tables(dc);
1610
1611         return 0;
1612 }
1613
1614 int tegra_hdmi_setup_audio_freq_source(unsigned audio_freq, unsigned audio_source)
1615 {
1616         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1617
1618         if (!hdmi)
1619                 return -EAGAIN;
1620
1621         /* check for know freq */
1622         if (AUDIO_FREQ_32K == audio_freq ||
1623                 AUDIO_FREQ_44_1K== audio_freq ||
1624                 AUDIO_FREQ_48K== audio_freq ||
1625                 AUDIO_FREQ_88_2K== audio_freq ||
1626                 AUDIO_FREQ_96K== audio_freq ||
1627                 AUDIO_FREQ_176_4K== audio_freq ||
1628                 AUDIO_FREQ_192K== audio_freq) {
1629                 /* If we can program HDMI, then proceed */
1630                 if (hdmi->clk_enabled) {
1631                         tegra_dc_io_start(hdmi->dc);
1632                         tegra_dc_hdmi_setup_audio(hdmi->dc, audio_freq,audio_source);
1633                         tegra_dc_io_end(hdmi->dc);
1634                 }
1635
1636                 /* Store it for using it in enable */
1637                 hdmi->audio_freq = audio_freq;
1638                 hdmi->audio_source = audio_source;
1639         }
1640         else
1641                 return -EINVAL;
1642
1643         return 0;
1644 }
1645 EXPORT_SYMBOL(tegra_hdmi_setup_audio_freq_source);
1646
1647 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1648 int tegra_hdmi_audio_null_sample_inject(bool on)
1649 {
1650         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1651         unsigned int val = 0;
1652
1653         if (!hdmi)
1654                 return -EAGAIN;
1655
1656         if (hdmi->audio_inject_null != on) {
1657                 hdmi->audio_inject_null = on;
1658                 if (hdmi->clk_enabled) {
1659                         val = tegra_hdmi_readl(hdmi,
1660                                 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1661                         val &= ~AUDIO_CNTRL0_INJECT_NULLSMPL;
1662                         if (on)
1663                                 val |= AUDIO_CNTRL0_INJECT_NULLSMPL;
1664                         tegra_hdmi_writel(hdmi,val,
1665                                 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1666                 }
1667         }
1668
1669         return 0;
1670 }
1671 EXPORT_SYMBOL(tegra_hdmi_audio_null_sample_inject);
1672
1673 int tegra_hdmi_setup_hda_presence()
1674 {
1675         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1676
1677         if (!hdmi)
1678                 return -EAGAIN;
1679
1680         if (hdmi->clk_enabled && hdmi->eld_retrieved) {
1681                 /* If HDA_PRESENCE is already set reset it */
1682                 tegra_dc_unpowergate_locked(hdmi->dc);
1683                 if (tegra_hdmi_readl(hdmi,
1684                                      HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0))
1685                         tegra_hdmi_writel(hdmi, 0,
1686                                      HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
1687
1688                 tegra_dc_hdmi_setup_eld_buff(hdmi->dc);
1689                 tegra_dc_powergate_locked(hdmi->dc);
1690                 return 0;
1691         }
1692         return -ENODEV;
1693
1694 }
1695 EXPORT_SYMBOL(tegra_hdmi_setup_hda_presence);
1696 #endif
1697
1698 static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
1699                                          u8 type, u8 version, void *data, int len)
1700 {
1701         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1702         u32 subpack[2];  /* extra byte for zero padding of subpack */
1703         int i;
1704         u8 csum;
1705
1706         /* first byte of data is the checksum */
1707         csum = type + version + len - 1;
1708         for (i = 1; i < len; i++)
1709                 csum +=((u8 *)data)[i];
1710         ((u8 *)data)[0] = 0x100 - csum;
1711
1712         tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
1713                           INFOFRAME_HEADER_VERSION(version) |
1714                           INFOFRAME_HEADER_LEN(len - 1),
1715                           header_reg);
1716
1717         /* The audio inforame only has one set of subpack registers.  The hdmi
1718          * block pads the rest of the data as per the spec so we have to fixup
1719          * the length before filling in the subpacks.
1720          */
1721         if (header_reg == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
1722                 len = 6;
1723
1724         /* each subpack 7 bytes devided into:
1725          *   subpack_low - bytes 0 - 3
1726          *   subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
1727          */
1728         for (i = 0; i < len; i++) {
1729                 int subpack_idx = i % 7;
1730
1731                 if (subpack_idx == 0)
1732                         memset(subpack, 0x0, sizeof(subpack));
1733
1734                 ((u8 *)subpack)[subpack_idx] = ((u8 *)data)[i];
1735
1736                 if (subpack_idx == 6 || (i + 1 == len)) {
1737                         int reg = header_reg + 1 + (i / 7) * 2;
1738
1739                         tegra_hdmi_writel(hdmi, subpack[0], reg);
1740                         tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
1741                 }
1742         }
1743 }
1744
1745 static int tegra_dc_find_cea_vic(const struct tegra_dc_mode *mode)
1746 {
1747         struct fb_videomode m;
1748         unsigned i;
1749         unsigned best = 0;
1750
1751         tegra_dc_to_fb_videomode(&m, mode);
1752
1753         m.vmode &= ~FB_VMODE_STEREO_MASK; /* stereo modes have the same VICs */
1754
1755         for (i = 1; i < CEA_861_D_MODEDB_SIZE; i++) {
1756                 const struct fb_videomode *curr = &cea_modes[i];
1757
1758                 if (!fb_mode_is_equal(&m, curr))
1759                         continue;
1760
1761                 if (!best)
1762                         best = i;
1763                 /* if either flag is set, then match is required */
1764                 if (curr->flag & (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9)) {
1765                         if (m.flag & curr->flag & FB_FLAG_RATIO_4_3)
1766                                 best = i;
1767                         else if (m.flag & curr->flag & FB_FLAG_RATIO_16_9)
1768                                 best = i;
1769                 } else {
1770                         best = i;
1771                 }
1772         }
1773         return best;
1774 }
1775
1776 static int tegra_dc_find_hdmi_vic(const struct tegra_dc_mode *mode)
1777 {
1778         struct fb_videomode m;
1779         unsigned i;
1780
1781         tegra_dc_to_fb_videomode(&m, mode);
1782
1783         for (i = 1; i < HDMI_EXT_MODEDB_SIZE; i++) {
1784                 const struct fb_videomode *curr = &hdmi_ext_modes[i];
1785
1786                 if (fb_mode_is_equal(&m, curr))
1787                         return i;
1788         }
1789         return 0;
1790 }
1791
1792 static void tegra_dc_hdmi_disable_generic_infoframe(struct tegra_dc *dc)
1793 {
1794         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1795         u32 val;
1796
1797         val  = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1798         val &= ~GENERIC_CTRL_ENABLE;
1799         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1800 }
1801
1802 /* return 1 if generic infoframe is used, 0 if not used */
1803 static int tegra_dc_hdmi_setup_hdmi_vic_infoframe(struct tegra_dc *dc, bool dvi)
1804 {
1805         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1806         struct hdmi_extres_infoframe extres;
1807         int hdmi_vic;
1808         u32 val;
1809
1810         if (dvi)
1811                 return 0;
1812         hdmi_vic = tegra_dc_find_hdmi_vic(&dc->mode);
1813         if (hdmi_vic <= 0)
1814                 return 0;
1815
1816         memset(&extres, 0x0, sizeof(extres));
1817
1818         extres.csum = 0;
1819         extres.regid0 = 0x03;
1820         extres.regid1 = 0x0c;
1821         extres.regid2 = 0x00;
1822         extres.hdmi_video_format = 1; /* Extended Resolution Format */
1823         extres.hdmi_vic = hdmi_vic;
1824
1825         tegra_dc_hdmi_write_infopack(dc,
1826                 HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
1827                 HDMI_INFOFRAME_TYPE_VENDOR, HDMI_VENDOR_VERSION,
1828                 &extres, 6);
1829         val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1830         val |= GENERIC_CTRL_ENABLE;
1831         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1832         return 1;
1833 }
1834
1835 static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
1836 {
1837         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1838         struct hdmi_avi_infoframe avi;
1839         unsigned int blender_reg;
1840
1841         if (dvi) {
1842                 tegra_hdmi_writel(hdmi, 0x0,
1843                                   HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1844                 return;
1845         }
1846
1847         memset(&avi, 0x0, sizeof(avi));
1848
1849         /* Indicate active format info is valid. */
1850         avi.a = 1;
1851         avi.r = HDMI_AVI_R_SAME;
1852
1853 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
1854         blender_reg = DC_DISP_BORDER_COLOR;
1855 #else
1856         blender_reg = DC_DISP_BLEND_BACKGROUND_COLOR;
1857 #endif
1858
1859         if ((dc->mode.h_active == 720) && ((dc->mode.v_active == 480) || (dc->mode.v_active == 576)))
1860                 tegra_dc_writel(dc, 0x00101010, blender_reg);
1861         else
1862                 tegra_dc_writel(dc, 0x00000000, blender_reg);
1863
1864         avi.vic = tegra_dc_find_cea_vic(&dc->mode);
1865         avi.m = dc->mode.avi_m;
1866         /*Enable YUV format for 4k support*/
1867         if (dc->mode.vmode & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
1868                 avi.y = 3;
1869         else if (dc->mode.vmode & FB_VMODE_Y422)
1870                 avi.y = 1;
1871         else
1872                 avi.y = 0;
1873
1874         if (tegra_edid_underscan_supported(hdmi->edid))
1875                 avi.s = HDMI_AVI_S_UNDERSCAN;
1876         dev_dbg(&dc->ndev->dev, "HDMI AVI vic=%d m=%d\n", avi.vic, avi.m);
1877         avi.s = HDMI_AVI_S_UNDERSCAN;
1878
1879         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
1880                                      HDMI_INFOFRAME_TYPE_AVI,
1881                                      HDMI_AVI_VERSION,
1882                                      &avi, sizeof(avi));
1883
1884         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
1885                           HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1886 }
1887
1888 static void tegra_dc_hdmi_setup_stereo_infoframe(struct tegra_dc *dc)
1889 {
1890         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1891         struct hdmi_stereo_infoframe stereo;
1892         u32 val;
1893
1894         WARN(!dc->mode.stereo_mode,
1895                 "function assumes 3D/stereo mode is disabled\n");
1896
1897         memset(&stereo, 0x0, sizeof(stereo));
1898
1899         stereo.regid0 = 0x03;
1900         stereo.regid1 = 0x0c;
1901         stereo.regid2 = 0x00;
1902         stereo.hdmi_video_format = 2; /* 3D_Structure present */
1903 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1904         stereo._3d_structure = 0; /* frame packing */
1905 #else
1906         stereo._3d_structure = 8; /* side-by-side (half) */
1907         stereo._3d_ext_data = 0; /* something which fits into 00XX bit req */
1908 #endif
1909
1910         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
1911                                         HDMI_INFOFRAME_TYPE_VENDOR,
1912                                         HDMI_VENDOR_VERSION,
1913                                         &stereo, 6);
1914
1915         val  = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1916         val |= GENERIC_CTRL_ENABLE;
1917
1918         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1919 }
1920
1921 static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
1922 {
1923         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1924         struct hdmi_audio_infoframe audio;
1925
1926         if (dvi) {
1927                 tegra_hdmi_writel(hdmi, 0x0,
1928                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1929                 return;
1930         }
1931
1932         memset(&audio, 0x0, sizeof(audio));
1933
1934         audio.cc = HDMI_AUDIO_CC_2;
1935         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
1936                                      HDMI_INFOFRAME_TYPE_AUDIO,
1937                                      HDMI_AUDIO_VERSION,
1938                                      &audio, sizeof(audio));
1939
1940         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
1941                           HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1942 }
1943
1944 static void tegra_dc_hdmi_setup_tmds(struct tegra_dc_hdmi_data *hdmi,
1945                 const struct tmds_config *tc)
1946 {
1947 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1948         u32 val;
1949 #endif
1950
1951         tegra_hdmi_writel(hdmi, tc->pll0, HDMI_NV_PDISP_SOR_PLL0);
1952         tegra_hdmi_writel(hdmi, tc->pll1, HDMI_NV_PDISP_SOR_PLL1);
1953
1954         tegra_hdmi_writel(hdmi, tc->pe_current, HDMI_NV_PDISP_PE_CURRENT);
1955
1956 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1957         tegra_hdmi_writel(hdmi, tc->drive_current,
1958                 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1959         val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PAD_CTLS0);
1960         val |= DRIVE_CURRENT_FUSE_OVERRIDE_T11x;
1961         if (MAJOR(tc->version) >= 1) {
1962                 val &= tc->pad_ctls0_mask;
1963                 val |= tc->pad_ctls0_setting;
1964         }
1965         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_PAD_CTLS0);
1966
1967         tegra_hdmi_writel(hdmi, tc->peak_current,
1968                 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1969 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
1970         tegra_hdmi_writel(hdmi, tc->drive_current,
1971                 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1972         tegra_hdmi_writel(hdmi, 0x800034bb, HDMI_NV_PDISP_SOR_PAD_CTLS0);
1973
1974         tegra_hdmi_writel(hdmi, tc->peak_current,
1975                 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1976 #else
1977         tegra_hdmi_writel(hdmi, tc->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE,
1978                 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1979 #endif
1980 }
1981
1982 void tegra_dc_hdmi_setup_audio_and_infoframes(struct tegra_dc *dc)
1983 {
1984         int rekey;
1985         int err;
1986         u32 val;
1987         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1988
1989         if (!hdmi->dvi) {
1990                 err = tegra_dc_hdmi_setup_audio(dc, hdmi->audio_freq,
1991                         hdmi->audio_source);
1992
1993                 if (err < 0)
1994                         hdmi->dvi = true;
1995         }
1996
1997 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1998         tegra_dc_hdmi_setup_eld_buff(dc);
1999 #endif
2000
2001         rekey = HDMI_REKEY_DEFAULT;
2002         val = HDMI_CTRL_REKEY(rekey);
2003         val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width +
2004                                         dc->mode.h_back_porch +
2005                                         dc->mode.h_front_porch -
2006                                         rekey - 18) / 32);
2007         if (!hdmi->dvi)
2008                 val |= HDMI_CTRL_ENABLE;
2009         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
2010
2011         if (hdmi->dvi)
2012                 tegra_hdmi_writel(hdmi, 0x0,
2013                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2014         else
2015                 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
2016                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
2017
2018         tegra_dc_hdmi_setup_avi_infoframe(dc, hdmi->dvi);
2019
2020         if (dc->mode.stereo_mode)
2021                 tegra_dc_hdmi_setup_stereo_infoframe(dc);
2022         else if (!tegra_dc_hdmi_setup_hdmi_vic_infoframe(dc, hdmi->dvi))
2023                 tegra_dc_hdmi_disable_generic_infoframe(dc);
2024
2025         tegra_dc_hdmi_setup_audio_infoframe(dc, hdmi->dvi);
2026 }
2027
2028 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
2029 {
2030         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2031         int pulse_start;
2032         int dispclk_div_8_2;
2033         int retries;
2034         unsigned long val;
2035         unsigned i;
2036         const struct tmds_config *tmds_ptr;
2037         size_t tmds_len;
2038         bool edid_read;
2039
2040         /* enable power, clocks, resets, etc. */
2041
2042         /* The upstream DC needs to be clocked for accesses to HDMI to not
2043          * hard lock the system.  Because we don't know if HDMI is connected
2044          * to disp1 or disp2 we need to enable both until we set the DC mux.
2045          */
2046         clk_prepare_enable(hdmi->disp1_clk);
2047         clk_prepare_enable(hdmi->disp2_clk);
2048
2049 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2050         /* Enabling HDA clocks before asserting HDA PD and ELDV bits */
2051         clk_prepare_enable(hdmi->hda_clk);
2052         clk_prepare_enable(hdmi->hda2codec_clk);
2053         clk_prepare_enable(hdmi->hda2hdmi_clk);
2054 #endif
2055
2056         /* Reseting HDMI clock would cause visible display reset during boot
2057          * if bootloader set an image already. Skip such operation if HDMI
2058          * is already running on desired clock rate.
2059          */
2060         if (clk_get_rate(hdmi->clk) == dc->mode.pclk) {
2061                 pr_info("%s: HDMI clock already configured to "
2062                         "target frequency, skipping clk setup.\n", __func__);
2063                 clk_prepare_enable(hdmi->clk);
2064         } else {
2065                 tegra_dc_setup_clk(dc, hdmi->clk);
2066                 clk_set_rate(hdmi->clk, dc->mode.pclk);
2067
2068                 clk_prepare_enable(hdmi->clk);
2069                 tegra_periph_reset_assert(hdmi->clk);
2070                 mdelay(1);
2071                 tegra_periph_reset_deassert(hdmi->clk);
2072         }
2073
2074         /* TODO: copy HDCP keys from KFUSE to HDMI */
2075
2076         /* Program display timing registers: handled by dc */
2077
2078         /* program HDMI registers and SOR sequencer */
2079
2080         tegra_dc_io_start(dc);
2081         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
2082
2083         dc->out->depth = 24;
2084         dc->out->dither = TEGRA_DC_DISABLE_DITHER;
2085         tegra_dc_set_color_control(dc);
2086
2087         /* video_preamble uses h_pulse2 */
2088         pulse_start = dc->mode.h_ref_to_sync + dc->mode.h_sync_width +
2089                 dc->mode.h_back_porch - 10;
2090         tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
2091         tegra_dc_writel(dc,
2092                         PULSE_MODE_NORMAL |
2093                         PULSE_POLARITY_HIGH |
2094                         PULSE_QUAL_VACTIVE |
2095                         PULSE_LAST_END_A,
2096                         DC_DISP_H_PULSE2_CONTROL);
2097         tegra_dc_writel(dc, PULSE_START(pulse_start) | PULSE_END(pulse_start + 8),
2098                   DC_DISP_H_PULSE2_POSITION_A);
2099
2100         tegra_hdmi_writel(hdmi,
2101                           VSYNC_WINDOW_END(0x210) |
2102                           VSYNC_WINDOW_START(0x200) |
2103                           VSYNC_WINDOW_ENABLE,
2104                           HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
2105
2106         if ((dc->mode.h_active == 720) && ((dc->mode.v_active == 480) || (dc->mode.v_active == 576)))
2107                 tegra_hdmi_writel(hdmi,
2108                                   (dc->ctrl_num ? HDMI_SRC_DISPLAYB :
2109                                    HDMI_SRC_DISPLAYA) |
2110                                   ARM_VIDEO_RANGE_FULL,
2111                                   HDMI_NV_PDISP_INPUT_CONTROL);
2112         else
2113                 tegra_hdmi_writel(hdmi,
2114                                   (dc->ctrl_num ? HDMI_SRC_DISPLAYB :
2115                                    HDMI_SRC_DISPLAYA) |
2116                                   ARM_VIDEO_RANGE_LIMITED,
2117                                   HDMI_NV_PDISP_INPUT_CONTROL);
2118
2119         clk_disable_unprepare(hdmi->disp1_clk);
2120         clk_disable_unprepare(hdmi->disp2_clk);
2121
2122         dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4;
2123         tegra_hdmi_writel(hdmi,
2124                           SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
2125                           SOR_REFCLK_DIV_FRAC(dispclk_div_8_2),
2126                           HDMI_NV_PDISP_SOR_REFCLK);
2127
2128         hdmi->clk_enabled = true;
2129
2130         edid_read = hdmi->eld_retrieved;
2131         /* on first boot, we haven't read EDID yet so
2132          * we don't know what to setup yet.  we'll
2133          * call audio and infoframes setup in hdmi worker
2134          * after EDID has been read.
2135          */
2136         if (edid_read) {
2137                 /* after boot, this is called by hwc via ioctl
2138                  * blank/unblank, which is done after EDID has
2139                  * been read.
2140                  */
2141                 tegra_dc_hdmi_setup_audio_and_infoframes(dc);
2142         }
2143
2144         /* Set tmds config. Set it to custom values provided in board file;
2145          * otherwise, set it to default values. */
2146         if (hdmi->info.tmds_config && hdmi->info.n_tmds_config) {
2147                 tmds_ptr = hdmi->info.tmds_config;
2148                 tmds_len = hdmi->info.n_tmds_config;
2149         } else {
2150                 tmds_ptr = tmds_config;
2151                 tmds_len = ARRAY_SIZE(tmds_config);
2152         }
2153
2154         for (i = 0; i < tmds_len && tmds_ptr[i].pclk < dc->mode.pclk; i++)
2155                 ;
2156         if (i < tmds_len) {
2157                 tegra_dc_hdmi_setup_tmds(hdmi, &tmds_ptr[i]);
2158         } else {
2159                 dev_warn(&dc->ndev->dev,
2160                         "pixel clock %u not present on TMDS table.\n",
2161                         dc->mode.pclk);
2162                 tegra_dc_hdmi_setup_tmds(hdmi, &tmds_ptr[tmds_len - 1]);
2163         }
2164
2165         /* enable SOR */
2166         tegra_hdmi_writel(hdmi,
2167                           SOR_SEQ_CTL_PU_PC(0) |
2168                           SOR_SEQ_PU_PC_ALT(0) |
2169                           SOR_SEQ_PD_PC(8) |
2170                           SOR_SEQ_PD_PC_ALT(8),
2171                           HDMI_NV_PDISP_SOR_SEQ_CTL);
2172
2173         val = SOR_SEQ_INST_WAIT_TIME(1) |
2174                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
2175                 SOR_SEQ_INST_HALT |
2176                 SOR_SEQ_INST_PIN_A_LOW |
2177                 SOR_SEQ_INST_PIN_B_LOW |
2178                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
2179
2180         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
2181         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
2182
2183         val = 0x1c800;
2184         val &= ~SOR_CSTM_ROTCLK(~0);
2185         val |= SOR_CSTM_ROTCLK(2);
2186         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
2187
2188         /* Putting display into STOP MODE will reset display which is undesired
2189          * if bootloader has already initialized display with image.
2190          */
2191         if (!hdmi->dc->initialized) {
2192                 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP,
2193                                 DC_CMD_DISPLAY_COMMAND);
2194                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2195                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2196         } else {
2197                 pr_info("%s: DC already initialized, skip putting HDMI "
2198                         "to STOP mode.\n", __func__);
2199         }
2200
2201         /* start SOR */
2202         tegra_hdmi_writel(hdmi,
2203                           SOR_PWR_NORMAL_STATE_PU |
2204                           SOR_PWR_NORMAL_START_NORMAL |
2205                           SOR_PWR_SAFE_STATE_PD |
2206                           SOR_PWR_SETTING_NEW_TRIGGER,
2207                           HDMI_NV_PDISP_SOR_PWR);
2208         tegra_hdmi_writel(hdmi,
2209                           SOR_PWR_NORMAL_STATE_PU |
2210                           SOR_PWR_NORMAL_START_NORMAL |
2211                           SOR_PWR_SAFE_STATE_PD |
2212                           SOR_PWR_SETTING_NEW_DONE,
2213                           HDMI_NV_PDISP_SOR_PWR);
2214
2215         retries = 1000;
2216         do {
2217                 BUG_ON(--retries < 0);
2218                 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
2219         } while (val & SOR_PWR_SETTING_NEW_PENDING);
2220
2221         val = SOR_STATE_ASY_CRCMODE_COMPLETE |
2222                 SOR_STATE_ASY_OWNER_HEAD0 |
2223                 SOR_STATE_ASY_SUBOWNER_BOTH |
2224                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
2225                 SOR_STATE_ASY_DEPOL_POS;
2226
2227         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
2228                 val |= SOR_STATE_ASY_HSYNCPOL_NEG;
2229         else
2230                 val |= SOR_STATE_ASY_HSYNCPOL_POS;
2231
2232         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
2233                 val |= SOR_STATE_ASY_VSYNCPOL_NEG;
2234         else
2235                 val |= SOR_STATE_ASY_VSYNCPOL_POS;
2236
2237         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE2);
2238
2239         val = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
2240         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
2241
2242         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
2243         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
2244         tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
2245                           HDMI_NV_PDISP_SOR_STATE1);
2246         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
2247
2248         tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
2249
2250         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2251                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
2252                         DC_CMD_DISPLAY_POWER_CONTROL);
2253
2254         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
2255         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2256         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2257
2258         /* we are called at boot when the actual connection state
2259          * isn't known, and other times (like fb_blank, which
2260          * does a disable followed by an enable) when it is.
2261          * don't just assume a connection but check hpd.
2262          */
2263         if (hdmi->info.hdmi2fpd_bridge_enable)
2264                 hdmi2fpd_enable(hdmi);
2265
2266         tegra_nvhdcp_set_plug(hdmi->nvhdcp, tegra_dc_hpd(dc));
2267         tegra_dc_io_end(dc);
2268 }
2269
2270 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
2271 {
2272         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2273
2274         if (hdmi->info.hdmi2fpd_bridge_enable)
2275                 hdmi2fpd_disable(hdmi);
2276
2277         /*
2278          * set DC to STOP mode
2279          */
2280         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2281         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2282         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2283
2284         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
2285
2286 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2287         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
2288         /* sleep 1ms before disabling clocks to ensure HDA gets the interrupt */
2289         msleep(1);
2290         clk_disable_unprepare(hdmi->hda2hdmi_clk);
2291         clk_disable_unprepare(hdmi->hda2codec_clk);
2292         clk_disable_unprepare(hdmi->hda_clk);
2293 #endif
2294         tegra_periph_reset_assert(hdmi->clk);
2295         hdmi->clk_enabled = false;
2296         clk_disable_unprepare(hdmi->clk);
2297         tegra_dvfs_set_rate(hdmi->clk, 0);
2298 }
2299
2300
2301 /* To determine the best parent clock rate for a nominal HDMI pixel clock
2302  * rate for T124 host1x display controller
2303  * o inputs:
2304  *  - dc: pointer to the display controller
2305  *  - parent_clk: pointer to the parent clock
2306  *  - pclk: rate of nominal HDMI pixel clock in Hz
2307  * o outputs:
2308  *  - return: best parent clock rate in Hz
2309  */
2310 static unsigned long  tegra12x_hdmi_determine_parent(
2311         struct tegra_dc *dc, struct clk *parent_clk, int pclk)
2312 {
2313         /* T124 hdmi pclk:
2314          *   parentClk = pclk * m  (m=1,1.5,2,2.5,...,128.5)
2315          *   refclk * n = pclk * m  (n=1,1.5,2,2.5,...,128.5)
2316          *   (prevent m==1.5 due to too much uneven out clock duty cycle)
2317          *   refclk * (N / 2) = pclk * (M / 2)  (M&N=2,3,4,...,257)
2318          *   M = (refclk * N) / pclk  (prevent the use of M==3)
2319          *   (look for N to make M whole number)
2320          */
2321         int  n, m;  /* N & M */
2322         int  b, fr, f;
2323
2324         /* following parameters should come from parent clock */
2325         const int  ref  = 12000000;   /* reference clock to parent */
2326         const int  pmax = 600000000;  /* max freq of parent clock */
2327         const int  pmin = 200000000;  /* min freq of parent clock */
2328
2329         b = 0;
2330         fr = 1000;
2331         for (n = 4; (ref / 2 * n) <= pmax; n++) {
2332                 if ((ref / 2 * n) < pmin)  /* too low */
2333                         continue;
2334                 m = (ref * n) / (pclk / 1000);
2335                 if (3 == (((m - 1) / 1000) + 1))  /* omit M==3 aft rnd-up */
2336                         continue;
2337                 f = m % 1000;  /* fractional parts */
2338                 f = (0 == f) ? f : (1000 - f);  /* round-up */
2339                 if (0 == f) {  /* exact match */
2340                         b = n;
2341                         fr = f;
2342                         break;
2343                 } else if (f < fr) {
2344                         b = n;
2345                         fr = f;
2346                 }
2347         }
2348
2349         /* parent clk: ref * b / 2
2350          * divider value: (m + 2000 - 1) / 2000 (if m saved; round-up)
2351          * expected pclk: ref * b / 2 / divider
2352          */
2353         return (unsigned long)(ref / 2 * b);
2354 }
2355
2356
2357 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk)
2358 {
2359         unsigned long rate;
2360         struct clk *parent_clk = clk_get_sys(NULL,
2361                 dc->out->parent_clk ? : "pll_d_out0");
2362 #if !defined(CONFIG_ARCH_TEGRA_12x_SOC)
2363         struct clk *base_clk = clk_get_parent(parent_clk);
2364 #endif
2365         if (clk != dc->clk) {
2366 #if !defined(CONFIG_ARCH_TEGRA_12x_SOC)
2367                 clk_set_rate(base_clk, dc->mode.pclk);
2368
2369                 if (clk_get_parent(clk) != parent_clk)
2370                         clk_set_parent(clk, parent_clk);
2371
2372                 clk_set_rate(clk, dc->mode.pclk / 4);
2373 #else
2374                 rate = 100000000;
2375                 clk_set_rate(parent_clk, rate);
2376                 if (clk_get_parent(clk) != parent_clk)
2377                         clk_set_parent(clk, parent_clk);
2378                 clk_set_rate(clk,  rate / 4);
2379 #endif
2380         }
2381
2382         /*
2383          * Providing dynamic frequency rate setting for T20/T30 HDMI.
2384          * The required rate needs to be setup at 4x multiplier,
2385          * as out0 is 1/2 of the actual PLL output.
2386          */
2387 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2388         rate = tegra12x_hdmi_determine_parent(dc, parent_clk, dc->mode.pclk);
2389 #else
2390         rate = dc->mode.pclk * 2;
2391         while (rate < 500000000)
2392                 rate *= 2;
2393 #endif
2394 #if !defined(CONFIG_ARCH_TEGRA_12x_SOC)
2395         if (rate != clk_get_rate(base_clk))
2396                 clk_set_rate(base_clk, rate);
2397 #else
2398         if (rate != clk_get_rate(parent_clk))
2399                 clk_set_rate(parent_clk, rate);
2400 #endif
2401         if (clk_get_parent(clk) != parent_clk)
2402                 clk_set_parent(clk, parent_clk);
2403
2404         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2405 }
2406
2407 static bool tegra_dc_hdmi_hpd_state(struct tegra_dc *dc)
2408 {
2409         int sense;
2410         int level;
2411         bool hpd;
2412
2413         if (WARN_ON(!dc || !dc->out))
2414                 return false;
2415
2416         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
2417
2418         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
2419
2420         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
2421                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
2422
2423         return hpd;
2424 }
2425
2426 struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
2427         .init = tegra_dc_hdmi_init,
2428         .destroy = tegra_dc_hdmi_destroy,
2429         .enable = tegra_dc_hdmi_enable,
2430         .disable = tegra_dc_hdmi_disable,
2431         .detect = tegra_dc_hdmi_detect,
2432         .suspend = tegra_dc_hdmi_suspend,
2433         .resume = tegra_dc_hdmi_resume,
2434         .mode_filter = tegra_dc_hdmi_mode_filter,
2435         .setup_clk = tegra_dc_hdmi_setup_clk,
2436         .hpd_state = tegra_dc_hdmi_hpd_state,
2437 };
2438
2439 struct tegra_dc *tegra_dc_hdmi_get_dc(struct tegra_dc_hdmi_data *hdmi)
2440 {
2441         return hdmi ? hdmi->dc : NULL;
2442 }
2443
2444 static ssize_t hdmi_audio_get_max_channel(struct kobject *kobj,
2445         struct kobj_attribute *attr, char *buf)
2446 {
2447         return sprintf(buf, "%d\n", tegra_hdmi_get_max_channels());
2448 }