drivers/video/tegra/dc/dsi.c

   1 /*
   2  * drivers/video/tegra/dc/dsi.c
   3  *
   4  * Copyright (c) 2011-2016, NVIDIA CORPORATION, All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/fb.h>
  22 #include <linux/gpio.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/export.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/nvhost.h>
  32 #include <linux/lcm.h>
  33 #include <linux/gcd.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/clk/tegra.h>
  37 #include <linux/tegra-soc.h>
  38 #include <linux/nvhost.h>
  39 #include <linux/of_address.h>
  40
  41 #include <mach/dc.h>
  42 #include <mach/fb.h>
  43 #include <mach/csi.h>
  44 #include <mach/io_dpd.h>
  45
  46 #include "dc_reg.h"
  47 #include "dc_priv.h"
  48 #include "dev.h"
  49 #include "dsi_regs.h"
  50 #include "dsi.h"
  51 #include "mipi_cal.h"
  52
  53 /* HACK! This needs to come from DT */
  54 #include "../../../../arch/arm/mach-tegra/iomap.h"
  55
  56 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
  57 #define DSIB_MODE_ENABLE                0x2
  58
  59 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
  60         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
  61         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
  62         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
  63 #define DSI_USE_SYNC_POINTS 1
  64 #else
  65 #define DSI_USE_SYNC_POINTS 0
  66 #endif
  67
  68 #define S_TO_MS(x)                      (1000 * (x))
  69 #define MS_TO_US(x)                     (1000 * (x))
  70
  71 #define DSI_MODULE_NOT_INIT             0x0
  72 #define DSI_MODULE_INIT                 0x1
  73
  74 #define DSI_LPHS_NOT_INIT               0x0
  75 #define DSI_LPHS_IN_LP_MODE             0x1
  76 #define DSI_LPHS_IN_HS_MODE             0x2
  77
  78 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
  79 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
  80 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
  81
  82 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
  83 #define DSI_DRIVEN_MODE_DC              0x1
  84 #define DSI_DRIVEN_MODE_HOST            0x2
  85
  86 #define DSI_PHYCLK_OUT_DIS              0x0
  87 #define DSI_PHYCLK_OUT_EN               0x1
  88
  89 #define DSI_PHYCLK_NOT_INIT             0x0
  90 #define DSI_PHYCLK_CONTINUOUS           0x1
  91 #define DSI_PHYCLK_TX_ONLY              0x2
  92
  93 #define DSI_CLK_BURST_NOT_INIT          0x0
  94 #define DSI_CLK_BURST_NONE_BURST        0x1
  95 #define DSI_CLK_BURST_BURST_MODE        0x2
  96
  97 #define DSI_DC_STREAM_DISABLE           0x0
  98 #define DSI_DC_STREAM_ENABLE            0x1
  99
 100 #define DSI_LP_OP_NOT_INIT              0x0
 101 #define DSI_LP_OP_WRITE                 0x1
 102 #define DSI_LP_OP_READ                  0x2
 103
 104 #define DSI_HOST_IDLE_PERIOD            1000
 105 static atomic_t dsi_syncpt_rst = ATOMIC_INIT(0);
 106
 107 static bool enable_read_debug;
 108 module_param(enable_read_debug, bool, 0644);
 109 MODULE_PARM_DESC(enable_read_debug,
 110                 "Enable to print read fifo and return packet type");
 111
 112 static struct tegra_io_dpd dsi_io = {
 113         .name                   = "DSI",
 114         .io_dpd_reg_index       = 0,
 115         .io_dpd_bit             = 2,
 116 };
 117 static struct tegra_io_dpd dsib_io = {
 118         .name                   = "DSIB",
 119         .io_dpd_reg_index       = 1,
 120         .io_dpd_bit             = 7,
 121 };
 122 static struct tegra_io_dpd dsic_io = {
 123         .name                   = "DSIC",
 124         .io_dpd_reg_index       = 1,
 125         .io_dpd_bit             = 8,
 126 };
 127 static struct tegra_io_dpd dsid_io = {
 128         .name                   = "DSID",
 129         .io_dpd_reg_index       = 1,
 130         .io_dpd_bit             = 9,
 131 };
 132
 133 bool tegra_dsi_enable_read_debug(struct tegra_dc_dsi_data *dsi)
 134 {
 135         enable_read_debug = true;
 136         return enable_read_debug;
 137 }
 138
 139 bool tegra_dsi_disable_read_debug(struct tegra_dc_dsi_data *dsi)
 140 {
 141         enable_read_debug = false;
 142         return enable_read_debug;
 143 }
 144
 145 /* source of video data */
 146 enum {
 147         TEGRA_DSI_DRIVEN_BY_DC,
 148         TEGRA_DSI_DRIVEN_BY_HOST,
 149 };
 150
 151 static const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
 152         DSI_PKT_SEQ_0_LO,
 153         DSI_PKT_SEQ_0_HI,
 154         DSI_PKT_SEQ_1_LO,
 155         DSI_PKT_SEQ_1_HI,
 156         DSI_PKT_SEQ_2_LO,
 157         DSI_PKT_SEQ_2_HI,
 158         DSI_PKT_SEQ_3_LO,
 159         DSI_PKT_SEQ_3_HI,
 160         DSI_PKT_SEQ_4_LO,
 161         DSI_PKT_SEQ_4_HI,
 162         DSI_PKT_SEQ_5_LO,
 163         DSI_PKT_SEQ_5_HI,
 164 };
 165
 166 static const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
 167         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 168         0,
 169         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 170         0,
 171         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 172         0,
 173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
 174         PKT_ID2(CMD_HE) | PKT_LEN2(0),
 175         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
 176         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
 177         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 178         0,
 179         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
 180         PKT_ID2(CMD_HE) | PKT_LEN2(0),
 181         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
 182         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
 183 };
 184
 185 static const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
 186         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 187         0,
 188         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 189         0,
 190         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 191         0,
 192         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 193         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 194         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 195         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 196         0,
 197         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 198         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 199         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 200 };
 201
 202 static const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
 203         PKT_ID0(CMD_VS) | PKT_LEN0(0),
 204         0,
 205         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 206         0,
 207         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 208         0,
 209         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
 210         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
 211         0,
 212         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 213         0,
 214         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
 215         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
 216         0,
 217 };
 218
 219 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
 220         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 221         0,
 222         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 223         0,
 224         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 225         0,
 226         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 227         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 228         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
 229         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 230         0,
 231         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 232         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 233         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
 234 };
 235
 236 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
 237         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
 238         0,
 239         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 240         0,
 241         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 242         0,
 243         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 244         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 245         0,
 246         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 247         0,
 248         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 249         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 250         0,
 251 };
 252
 253 static const u32 dsi_pkt_seq_video_non_burst_no_eot[NUMOF_PKT_SEQ] = {
 254         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
 255         0,
 256         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 257         0,
 258         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 259         0,
 260         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 261                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 262         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 263         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 264         0,
 265         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 266                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 267         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 268 };
 269
 270 static const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
 271         0,
 272         0,
 273         0,
 274         0,
 275         0,
 276         0,
 277         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) |
 278                 PKT_LEN1(7) | PKT_LP,
 279         0,
 280         0,
 281         0,
 282         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) |
 283                 PKT_LEN1(7) | PKT_LP,
 284         0,
 285 };
 286
 287 static const u32 init_reg[] = {
 288         DSI_INT_ENABLE,
 289         DSI_INT_STATUS,
 290         DSI_INT_MASK,
 291         DSI_INIT_SEQ_DATA_0,
 292         DSI_INIT_SEQ_DATA_1,
 293         DSI_INIT_SEQ_DATA_2,
 294         DSI_INIT_SEQ_DATA_3,
 295         DSI_INIT_SEQ_DATA_4,
 296         DSI_INIT_SEQ_DATA_5,
 297         DSI_INIT_SEQ_DATA_6,
 298         DSI_INIT_SEQ_DATA_7,
 299         DSI_INIT_SEQ_DATA_15,
 300         DSI_DCS_CMDS,
 301         DSI_PKT_SEQ_0_LO,
 302         DSI_PKT_SEQ_1_LO,
 303         DSI_PKT_SEQ_2_LO,
 304         DSI_PKT_SEQ_3_LO,
 305         DSI_PKT_SEQ_4_LO,
 306         DSI_PKT_SEQ_5_LO,
 307         DSI_PKT_SEQ_0_HI,
 308         DSI_PKT_SEQ_1_HI,
 309         DSI_PKT_SEQ_2_HI,
 310         DSI_PKT_SEQ_3_HI,
 311         DSI_PKT_SEQ_4_HI,
 312         DSI_PKT_SEQ_5_HI,
 313         DSI_CONTROL,
 314         DSI_HOST_DSI_CONTROL,
 315         DSI_PAD_CONTROL,
 316         DSI_PAD_CONTROL_CD,
 317         DSI_SOL_DELAY,
 318         DSI_MAX_THRESHOLD,
 319         DSI_TRIGGER,
 320         DSI_TX_CRC,
 321         DSI_INIT_SEQ_CONTROL,
 322         DSI_PKT_LEN_0_1,
 323         DSI_PKT_LEN_2_3,
 324         DSI_PKT_LEN_4_5,
 325         DSI_PKT_LEN_6_7,
 326 };
 327
 328 static const u32 init_reg_vs1_ext[] = {
 329         DSI_PAD_CONTROL_0_VS1,
 330         DSI_PAD_CONTROL_CD_VS1,
 331         DSI_PAD_CD_STATUS_VS1,
 332         DSI_PAD_CONTROL_1_VS1,
 333         DSI_PAD_CONTROL_2_VS1,
 334         DSI_PAD_CONTROL_3_VS1,
 335         DSI_PAD_CONTROL_4_VS1,
 336         DSI_GANGED_MODE_CONTROL,
 337         DSI_GANGED_MODE_START,
 338         DSI_GANGED_MODE_SIZE,
 339 };
 340
 341 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
 342 static int tegra_dsi_host_resume(struct tegra_dc *dc);
 343 static void tegra_dc_dsi_idle_work(struct work_struct *work);
 344 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
 345                                      struct tegra_dc_dsi_data *dsi,
 346                                      int no_of_frames);
 347
 348 unsigned long tegra_dsi_controller_readl(struct tegra_dc_dsi_data *dsi,
 349                                                         u32 reg, int index)
 350 {
 351         unsigned long ret;
 352
 353         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 354         if (likely(tegra_platform_is_silicon())) {
 355                 if (WARN(!tegra_is_clk_enabled(dsi->dsi_clk[index]),
 356                 "DSI is clock gated!"))
 357                         return 0;
 358         }
 359         ret = readl(dsi->base[index] + reg * 4);
 360         trace_display_readl(dsi->dc, ret, dsi->base[index] + reg * 4);
 361         return ret;
 362 }
 363 EXPORT_SYMBOL(tegra_dsi_controller_readl);
 364
 365 void tegra_dsi_controller_writel(struct tegra_dc_dsi_data *dsi,
 366                                                 u32 val, u32 reg, int index)
 367 {
 368         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 369         if (likely(tegra_platform_is_silicon())) {
 370                 if (WARN(!tegra_is_clk_enabled(dsi->dsi_clk[index]),
 371                 "DSI is clock gated!"))
 372                         return;
 373         }
 374         trace_display_writel(dsi->dc, val, dsi->base[index] + reg * 4);
 375         writel(val, dsi->base[index] + reg * 4);
 376 }
 377 EXPORT_SYMBOL(tegra_dsi_controller_writel);
 378
 379 unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
 380 {
 381         unsigned long ret;
 382         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 383         ret = readl(dsi->base[DSI_INSTANCE_0] + reg * 4);
 384         trace_display_readl(dsi->dc, ret, dsi->base[DSI_INSTANCE_0] + reg * 4);
 385         return ret;
 386 }
 387 EXPORT_SYMBOL(tegra_dsi_readl);
 388
 389 void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
 390 {
 391         int  i = 0;
 392         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 393         for (i = 0; i < dsi->max_instances; i++) {
 394                 trace_display_writel(dsi->dc, val, dsi->base[i] + reg * 4);
 395                 writel(val, dsi->base[i] + reg * 4);
 396         }
 397 }
 398 EXPORT_SYMBOL(tegra_dsi_writel);
 399
 400 inline void tegra_dsi_reset_deassert(struct tegra_dc_dsi_data *dsi)
 401 {
 402         int i = 0;
 403         for (i = 0; i < dsi->max_instances; i++)
 404                 tegra_periph_reset_deassert(dsi->dsi_clk[i]);
 405 }
 406
 407 inline void tegra_dsi_reset_assert(struct tegra_dc_dsi_data *dsi)
 408 {
 409         int i = 0;
 410         for (i = 0; i < dsi->max_instances; i++)
 411                 tegra_periph_reset_assert(dsi->dsi_clk[i]);
 412 }
 413
 414 static inline void tegra_dsi_lp_clk_enable(struct tegra_dc_dsi_data *dsi);
 415 static inline void tegra_dsi_lp_clk_disable(struct tegra_dc_dsi_data *dsi);
 416
 417 void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
 418 {
 419         int i = 0;
 420         for (i = 0; i < dsi->max_instances; i++) {
 421                 tegra_disp_clk_prepare_enable(dsi->dsi_clk[i]);
 422                 udelay(800);
 423         }
 424 }
 425
 426 void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
 427 {
 428         int i = 0;
 429         for (i = 0; i < dsi->max_instances; i++) {
 430                 tegra_disp_clk_disable_unprepare(dsi->dsi_clk[i]);
 431                 udelay(800);
 432         }
 433 }
 434
 435 static inline void tegra_dsi_lp_clk_enable(struct tegra_dc_dsi_data *dsi)
 436 {
 437         int i = 0;
 438         for (i = 0; i < dsi->max_instances; i++) {
 439                 tegra_disp_clk_prepare_enable(dsi->dsi_lp_clk[i]);
 440                 udelay(800);
 441         }
 442 }
 443
 444 static inline void tegra_dsi_lp_clk_disable(struct tegra_dc_dsi_data *dsi)
 445 {
 446         int i = 0;
 447         for (i = 0; i < dsi->max_instances; i++) {
 448                 tegra_disp_clk_disable_unprepare(dsi->dsi_lp_clk[i]);
 449                 udelay(800);
 450         }
 451 }
 452
 453 static void tegra_dsi_setup_clk(struct tegra_dc *dc,
 454         struct tegra_dc_dsi_data *dsi)
 455 {
 456         int i = 0;
 457
 458         for (i = 0; i < dsi->max_instances; i++) {
 459                 tegra_dc_setup_clk(dc, dsi->dsi_clk[i]);
 460                 mdelay(3);
 461         }
 462 }
 463
 464 static void __maybe_unused tegra_dsi_syncpt_reset(
 465                                 struct tegra_dc_dsi_data *dsi)
 466 {
 467         tegra_dsi_writel(dsi, 0x1, DSI_INCR_SYNCPT_CNTRL);
 468         /* stabilization delay */
 469         udelay(300);
 470         tegra_dsi_writel(dsi, 0x0, DSI_INCR_SYNCPT_CNTRL);
 471         /* stabilization delay */
 472         udelay(300);
 473 }
 474
 475 static int __maybe_unused tegra_dsi_syncpt
 476         (struct tegra_dc_dsi_data *dsi, u8 link_id)
 477 {
 478         u32 val;
 479         int ret = 0;
 480
 481         if (!nvhost_syncpt_read_ext_check(dsi->dc->ndev, dsi->syncpt_id, &val))
 482                 dsi->syncpt_val = val;
 483
 484         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
 485                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
 486         if (dsi->info.ganged_type && dsi->info.ganged_write_to_all_links)
 487                 tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
 488         else
 489                 tegra_dsi_controller_writel(dsi, val, DSI_INCR_SYNCPT, link_id);
 490
 491         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
 492                 dsi->syncpt_val + 1, msecs_to_jiffies(500), NULL, NULL);
 493         if (ret < 0) {
 494                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
 495                 goto fail;
 496         }
 497
 498         (dsi->syncpt_val)++;
 499         return 0;
 500 fail:
 501         return ret;
 502 }
 503
 504 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
 505 {
 506         u32 dsi_clock_rate_khz;
 507
 508         switch (dsi->info.video_burst_mode) {
 509         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
 510         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
 511         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
 512         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
 513                 /* Calculate DSI HS clock rate for DSI burst mode */
 514                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
 515                                         dsi->shift_clk_div.mul /
 516                                         dsi->shift_clk_div.div;
 517                 break;
 518         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
 519         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
 520         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
 521         default:
 522                 /* Clock rate is default DSI clock rate for non-burst mode */
 523                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
 524                 break;
 525         }
 526
 527         return dsi_clock_rate_khz;
 528 }
 529
 530 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
 531 {
 532         u32 dsi_clock_rate_khz;
 533
 534         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
 535                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
 536                         dsi_clock_rate_khz =
 537                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
 538                 else
 539                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
 540         else
 541                 if (lp_op == DSI_LP_OP_READ)
 542                         dsi_clock_rate_khz =
 543                                 dsi->info.lp_read_cmd_mode_freq_khz;
 544                 else
 545                         dsi_clock_rate_khz =
 546                                 dsi->info.lp_cmd_mode_freq_khz;
 547
 548         return dsi_clock_rate_khz;
 549 }
 550
 551 static struct tegra_dc_shift_clk_div tegra_dsi_get_shift_clk_div(
 552                                                 struct tegra_dc_dsi_data *dsi)
 553 {
 554         struct tegra_dc_shift_clk_div shift_clk_div;
 555         struct tegra_dc_shift_clk_div max_shift_clk_div;
 556         struct tegra_dc_shift_clk_div delta_shift_clk_div;
 557         u32 temp_lcm;
 558         u32 burst_width;
 559         u32 burst_width_max;
 560         u32 temp_gcd;
 561         u32 default_hs_clk_mhz =
 562                 DIV_ROUND_CLOSEST(dsi->default_hs_clk_khz, 1000);
 563         u32 max_panel_freq_mhz =
 564                 DIV_ROUND_CLOSEST(dsi->info.max_panel_freq_khz, 1000);
 565
 566         /* Get the real value of default shift_clk_div. default_shift_clk_div
 567          * holds the real value of shift_clk_div.
 568          */
 569         shift_clk_div = dsi->default_shift_clk_div;
 570
 571         /* Calculate shift_clk_div which can match the video_burst_mode. */
 572         if (dsi->info.video_burst_mode >=
 573                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
 574                 if (max_panel_freq_mhz >= default_hs_clk_mhz) {
 575                         /* formula:
 576                          * dsi->info.max_panel_freq_khz * shift_clk_div /
 577                          * dsi->default_hs_clk_khz
 578                          */
 579                         max_shift_clk_div.mul = max_panel_freq_mhz *
 580                                                 shift_clk_div.mul;
 581                         max_shift_clk_div.div = default_hs_clk_mhz *
 582                                                 shift_clk_div.div;
 583                 } else {
 584                         max_shift_clk_div = shift_clk_div;
 585                 }
 586
 587                 burst_width = dsi->info.video_burst_mode
 588                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
 589                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
 590                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
 591
 592                 /* formula:
 593                  * (max_shift_clk_div - shift_clk_div) *
 594                  * burst_width / burst_width_max
 595                  */
 596                 temp_lcm = lcm(max_shift_clk_div.div, shift_clk_div.div);
 597                 delta_shift_clk_div.mul = (temp_lcm / max_shift_clk_div.div *
 598                                         max_shift_clk_div.mul -
 599                                         temp_lcm / shift_clk_div.div *
 600                                         shift_clk_div.mul) *
 601                                         burst_width;
 602                 delta_shift_clk_div.div = temp_lcm * burst_width_max;
 603
 604                 /* formula:
 605                  * shift_clk_div + delta_shift_clk_div
 606                  */
 607                 temp_lcm = lcm(shift_clk_div.div, delta_shift_clk_div.div);
 608                 shift_clk_div.mul = temp_lcm / shift_clk_div.div *
 609                                 shift_clk_div.mul +
 610                                 temp_lcm / delta_shift_clk_div.div *
 611                                 delta_shift_clk_div.mul;
 612                 shift_clk_div.div = temp_lcm;
 613
 614                 /* crunch shift clk numerator and denominator */
 615                 temp_gcd = gcd(shift_clk_div.mul, shift_clk_div.div);
 616                 shift_clk_div.mul /= temp_gcd;
 617                 shift_clk_div.div /= temp_gcd;
 618         }
 619
 620         return shift_clk_div;
 621 }
 622
 623 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
 624                                         struct tegra_dc_dsi_data *dsi)
 625 {
 626         u32 h_width_pixels;
 627         u32 h_act_corr = 0;
 628         u32 hfp_corr = 0;
 629         u32 temp = 0;
 630
 631         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
 632                         dc->mode.h_sync_width + dc->mode.h_active;
 633
 634         if (WARN(!dsi->info.n_data_lanes, "dsi n_data_lanes is 0\n"))
 635                 return;
 636
 637         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
 638                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
 639                 if (temp) {
 640                         h_act_corr = dsi->info.n_data_lanes - temp;
 641                         h_width_pixels += h_act_corr;
 642                 }
 643         }
 644
 645         temp = h_width_pixels % dsi->info.n_data_lanes;
 646         if (temp) {
 647                 hfp_corr = dsi->info.n_data_lanes - temp;
 648                 h_width_pixels += hfp_corr;
 649         }
 650
 651         while (1) {
 652                 if (WARN(!dsi->pixel_scaler_div, "dsi pixel_scaler_div is 0"))
 653                         temp = 0;
 654                 else
 655                         temp = (h_width_pixels * dsi->pixel_scaler_mul /
 656                                 dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
 657                 if (temp) {
 658                         hfp_corr += dsi->info.n_data_lanes;
 659                         h_width_pixels += dsi->info.n_data_lanes;
 660                 } else
 661                         break;
 662         }
 663
 664         dc->mode.h_front_porch += hfp_corr;
 665         dc->mode.h_active += h_act_corr;
 666 }
 667
 668 void tegra_dsi_init_clock_param(struct tegra_dc *dc)
 669 {
 670         u32 h_width_pixels;
 671         u32 v_width_lines;
 672         u32 pixel_clk_hz;
 673         u32 byte_clk_hz;
 674         u32 plld_clk_mhz;
 675         u8 n_data_lanes;
 676
 677         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
 678
 679         switch (dsi->info.pixel_format) {
 680         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
 681                 /* 2 bytes per pixel */
 682                 dsi->pixel_scaler_mul = 2;
 683                 dsi->pixel_scaler_div = 1;
 684                 break;
 685         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
 686                 /* 2.25 bytes per pixel */
 687                 dsi->pixel_scaler_mul = 9;
 688                 dsi->pixel_scaler_div = 4;
 689                 break;
 690         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
 691         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
 692                 /* 3 bytes per pixel */
 693                 dsi->pixel_scaler_mul = 3;
 694                 dsi->pixel_scaler_div = 1;
 695                 break;
 696         default:
 697                 break;
 698         }
 699
 700         n_data_lanes = dsi->info.n_data_lanes;
 701         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
 702                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD ||
 703                 dsi->info.ganged_type ==
 704                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP)
 705                 n_data_lanes /= 2;
 706
 707         dsi->dsi_control_val =
 708                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
 709                         DSI_CONTROL_NUM_DATA_LANES(n_data_lanes - 1) |
 710                         DSI_CONTROL_VID_SOURCE(dc->ctrl_num) |
 711                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
 712
 713         if (dsi->info.ganged_type)
 714                 tegra_dsi_pix_correction(dc, dsi);
 715
 716         /* Below we are going to calculate dsi and dc clock rate.
 717          * Calcuate the horizontal and vertical width.
 718          */
 719         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
 720                         dc->mode.h_sync_width + dc->mode.h_active;
 721
 722         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
 723                         dc->mode.v_sync_width + dc->mode.v_active;
 724
 725         /* Calculate minimum required pixel rate. */
 726         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
 727         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
 728                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
 729                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
 730                                 "should be larger than rated refresh rate.\n");
 731                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
 732                                                 dsi->info.rated_refresh_rate;
 733         }
 734
 735         /* Calculate minimum byte rate on DSI interface. */
 736         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
 737                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
 738
 739         /* Round up to multiple of mega hz. */
 740         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
 741                                                                 1000000);
 742
 743         /* Calculate default real shift_clk_div. */
 744         dsi->default_shift_clk_div.mul = NUMOF_BIT_PER_BYTE *
 745                                         dsi->pixel_scaler_mul;
 746         dsi->default_shift_clk_div.div = 2 * dsi->pixel_scaler_div *
 747                                         dsi->info.n_data_lanes;
 748
 749
 750         /* Calculate default DSI hs clock. DSI interface is double data rate.
 751          * Data is transferred on both rising and falling edge of clk, div by 2
 752          * to get the actual clock rate.
 753          */
 754         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
 755
 756         dsi->default_pixel_clk_khz = (plld_clk_mhz * 1000 *
 757                                         dsi->default_shift_clk_div.div) /
 758                                         (2 * dsi->default_shift_clk_div.mul);
 759
 760         /* Get the actual shift_clk_div and clock rates. */
 761         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
 762         dsi->target_lp_clk_khz =
 763                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
 764         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
 765
 766         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
 767                                         dsi->target_hs_clk_khz);
 768
 769         /*
 770          * Force video clock to be continuous mode if
 771          * enable_hs_clock_on_lp_cmd_mode is set
 772          */
 773         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
 774                 if (dsi->info.video_clock_mode !=
 775                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
 776                         dev_warn(&dc->ndev->dev,
 777                                 "Force clock continuous mode\n");
 778
 779                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
 780         }
 781 }
 782
 783 static void tegra_dsi_init_sw(struct tegra_dc *dc,
 784                         struct tegra_dc_dsi_data *dsi)
 785 {
 786         dsi->ulpm = false;
 787         dsi->enabled = false;
 788         dsi->clk_ref = false;
 789
 790 #if DSI_USE_SYNC_POINTS
 791         dsi->syncpt_id = nvhost_get_syncpt_client_managed(dc->ndev, "dsi");
 792 #endif
 793
 794         tegra_dsi_init_clock_param(dc);
 795
 796         atomic_set(&dsi->host_ref, 0);
 797         dsi->host_suspended = false;
 798         mutex_init(&dsi->host_lock);
 799         init_completion(&dc->out->user_vblank_comp);
 800         INIT_DELAYED_WORK(&dsi->idle_work, tegra_dc_dsi_idle_work);
 801         dsi->idle_delay = msecs_to_jiffies(DSI_HOST_IDLE_PERIOD);
 802 }
 803
 804 #define SELECT_T_PHY(platform_t_phy_ps, default_phy, clk_ps, hw_inc) ( \
 805 (platform_t_phy_ps) ? ( \
 806 ((DSI_CONVERT_T_PHY_PS_TO_T_PHY(platform_t_phy_ps, clk_ps, hw_inc)) < 0 ? 0 : \
 807 (DSI_CONVERT_T_PHY_PS_TO_T_PHY(platform_t_phy_ps, clk_ps, hw_inc)))) : \
 808 ((default_phy) < 0 ? 0 : (default_phy)))
 809
 810 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
 811                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 812 {
 813         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 814                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 815                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 816
 817         phy_timing_clk->t_clktrail = SELECT_T_PHY(
 818                 dsi->info.phy_timing.t_clktrail_ns * 1000,
 819                 T_CLKTRAIL_DEFAULT(clk_ps), clk_ps, T_CLKTRAIL_HW_INC);
 820
 821         phy_timing_clk->t_clkpost = SELECT_T_PHY(
 822                 dsi->info.phy_timing.t_clkpost_ns * 1000,
 823                 T_CLKPOST_DEFAULT(clk_ps), clk_ps, T_CLKPOST_HW_INC);
 824
 825         phy_timing_clk->t_clkzero = SELECT_T_PHY(
 826                 dsi->info.phy_timing.t_clkzero_ns * 1000,
 827                 T_CLKZERO_DEFAULT(clk_ps), clk_ps, T_CLKZERO_HW_INC);
 828
 829         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
 830                 dsi->info.phy_timing.t_clkprepare_ns * 1000,
 831                 T_CLKPREPARE_DEFAULT(clk_ps), clk_ps, T_CLKPREPARE_HW_INC);
 832
 833         phy_timing_clk->t_clkpre = SELECT_T_PHY(
 834                 dsi->info.phy_timing.t_clkpre_ns * 1000,
 835                 T_CLKPRE_DEFAULT, clk_ps, T_CLKPRE_HW_INC);
 836 }
 837
 838 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
 839                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 840 {
 841         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 842                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 843                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 844
 845         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
 846                 dsi->info.phy_timing.t_hsdexit_ns * 1000,
 847                 T_HSEXIT_DEFAULT(clk_ps), clk_ps, T_HSEXIT_HW_INC);
 848
 849         phy_timing_clk->t_hstrail = SELECT_T_PHY(
 850                 dsi->info.phy_timing.t_hstrail_ns * 1000,
 851                 T_HSTRAIL_DEFAULT(clk_ps), clk_ps, T_HSTRAIL_HW_INC);
 852
 853         phy_timing_clk->t_datzero = SELECT_T_PHY(
 854                 dsi->info.phy_timing.t_datzero_ns * 1000,
 855                 T_DATZERO_DEFAULT(clk_ps), clk_ps, T_DATZERO_HW_INC);
 856
 857         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
 858                 dsi->info.phy_timing.t_hsprepare_ns * 1000,
 859                 T_HSPREPARE_DEFAULT(clk_ps), clk_ps, T_HSPREPARE_HW_INC);
 860 }
 861
 862 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
 863                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 864 {
 865         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 866                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 867                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 868 }
 869
 870 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
 871                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 872 {
 873         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 874                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 875                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 876
 877         phy_timing_clk->t_taget = SELECT_T_PHY(
 878                 dsi->info.phy_timing.t_taget_ns * 1000,
 879                 T_TAGET_DEFAULT(clk_ps), clk_ps, T_TAGET_HW_INC);
 880
 881         phy_timing_clk->t_tasure = SELECT_T_PHY(
 882                 dsi->info.phy_timing.t_tasure_ns * 1000,
 883                 T_TASURE_DEFAULT(clk_ps), clk_ps, T_TASURE_HW_INC);
 884
 885         phy_timing_clk->t_tago = SELECT_T_PHY(
 886                 dsi->info.phy_timing.t_tago_ns * 1000,
 887                 T_TAGO_DEFAULT(clk_ps), clk_ps, T_TAGO_HW_INC);
 888 }
 889
 890 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
 891                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 892 {
 893         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 894                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 895                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 896
 897         phy_timing_clk->t_wakeup = SELECT_T_PHY(
 898                 dsi->info.phy_timing.t_wakeup_ns * 1000,
 899                 T_WAKEUP_DEFAULT, clk_ps, T_WAKEUP_HW_INC);
 900 }
 901
 902 #undef SELECT_T_PHY
 903
 904 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
 905                                 struct dsi_phy_timing_inclk *phy_timing_clk,
 906                                 u32 clk_ps, u8 lphs)
 907 {
 908         if (tegra_platform_is_fpga()) {
 909                 clk_ps = (1000 * 1000 * 1000) / (dsi->info.fpga_freq_khz ?
 910                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
 911         }
 912
 913         if (lphs == DSI_LPHS_IN_HS_MODE) {
 914                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ps);
 915                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ps);
 916         } else {
 917                 /* default is LP mode */
 918                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ps);
 919                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ps);
 920                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ps);
 921                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
 922                         tegra_dsi_get_clk_phy_timing(dsi,
 923                                         phy_timing_clk, clk_ps);
 924         }
 925 }
 926
 927 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
 928                                 struct dsi_phy_timing_inclk *phy_timing,
 929                                 u32 clk_ps, u8 lphs)
 930 {
 931         int err = 0;
 932
 933 #define CHECK_RANGE(val, min, max) ( \
 934                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
 935                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
 936
 937         if (tegra_platform_is_fpga())
 938                 clk_ps = dsi->info.fpga_freq_khz ?
 939                         ((1000 * 1000 * 1000) / dsi->info.fpga_freq_khz) :
 940                         DEFAULT_FPGA_FREQ_KHZ;
 941
 942         err = CHECK_RANGE(
 943         DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 944                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC),
 945                         MIPI_T_TLPX_PS_MIN, MIPI_T_TLPX_PS_MAX);
 946         if (err < 0) {
 947                 dev_warn(&dsi->dc->ndev->dev,
 948                         "dsi: Tlpx mipi range violated\n");
 949                 goto fail;
 950         }
 951
 952         if (lphs == DSI_LPHS_IN_HS_MODE) {
 953                 err = CHECK_RANGE(
 954                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 955                         phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC),
 956                         MIPI_T_HSEXIT_PS_MIN, MIPI_T_HSEXIT_PS_MAX);
 957                 if (err < 0) {
 958                         dev_warn(&dsi->dc->ndev->dev,
 959                                 "dsi: HsExit mipi range violated\n");
 960                         goto fail;
 961                 }
 962
 963                 err = CHECK_RANGE(
 964                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 965                         phy_timing->t_hstrail, clk_ps, T_HSTRAIL_HW_INC),
 966                         MIPI_T_HSTRAIL_PS_MIN(clk_ps), MIPI_T_HSTRAIL_PS_MAX);
 967                 if (err < 0) {
 968                         dev_warn(&dsi->dc->ndev->dev,
 969                                 "dsi: HsTrail mipi range violated\n");
 970                         goto fail;
 971                 }
 972
 973                 err = CHECK_RANGE(
 974                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 975                         phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC),
 976                         MIPI_T_HSZERO_PS_MIN, MIPI_T_HSZERO_PS_MAX);
 977                 if (err < 0) {
 978                         dev_warn(&dsi->dc->ndev->dev,
 979                                 "dsi: HsZero mipi range violated\n");
 980                         goto fail;
 981                 }
 982
 983                 err = CHECK_RANGE(
 984                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 985                         phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC),
 986                         MIPI_T_HSPREPARE_PS_MIN(clk_ps),
 987                         MIPI_T_HSPREPARE_PS_MAX(clk_ps));
 988                 if (err < 0) {
 989                         dev_warn(&dsi->dc->ndev->dev,
 990                                 "dsi: HsPrepare mipi range violated\n");
 991                         goto fail;
 992                 }
 993
 994                 err = CHECK_RANGE(
 995                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 996                         phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC) +
 997                         DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 998                         phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC),
 999                         MIPI_T_HSPREPARE_ADD_HSZERO_PS_MIN(clk_ps),
1000                         MIPI_T_HSPREPARE_ADD_HSZERO_PS_MAX);
1001                 if (err < 0) {
1002                         dev_warn(&dsi->dc->ndev->dev,
1003                         "dsi: HsPrepare + HsZero mipi range violated\n");
1004                         goto fail;
1005                 }
1006         } else {
1007                 /* default is LP mode */
1008                 err = CHECK_RANGE(
1009                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1010                         phy_timing->t_wakeup, clk_ps, T_WAKEUP_HW_INC),
1011                         MIPI_T_WAKEUP_PS_MIN, MIPI_T_WAKEUP_PS_MAX);
1012                 if (err < 0) {
1013                         dev_warn(&dsi->dc->ndev->dev,
1014                                 "dsi: WakeUp mipi range violated\n");
1015                         goto fail;
1016                 }
1017
1018                 err = CHECK_RANGE(
1019                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1020                         phy_timing->t_tasure, clk_ps, T_TASURE_HW_INC),
1021                         MIPI_T_TASURE_PS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1022                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC)),
1023                         MIPI_T_TASURE_PS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1024                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC)));
1025                 if (err < 0) {
1026                         dev_warn(&dsi->dc->ndev->dev,
1027                                 "dsi: TaSure mipi range violated\n");
1028                         goto fail;
1029                 }
1030         }
1031
1032         if (lphs == DSI_LPHS_IN_HS_MODE ||
1033                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
1034                 err = CHECK_RANGE(
1035                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1036                         phy_timing->t_clktrail, clk_ps, T_CLKTRAIL_HW_INC),
1037                         MIPI_T_CLKTRAIL_PS_MIN, MIPI_T_CLKTRAIL_PS_MAX);
1038                 if (err < 0) {
1039                         dev_warn(&dsi->dc->ndev->dev,
1040                                 "dsi: ClkTrail mipi range violated\n");
1041                         goto fail;
1042                 }
1043
1044                 err = CHECK_RANGE(
1045                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1046                         phy_timing->t_clkpost, clk_ps, T_CLKPOST_HW_INC),
1047                         MIPI_T_CLKPOST_PS_MIN(clk_ps), MIPI_T_CLKPOST_PS_MAX);
1048                 if (err < 0) {
1049                         dev_warn(&dsi->dc->ndev->dev,
1050                                 "dsi: ClkPost mipi range violated\n");
1051                         goto fail;
1052                 }
1053
1054                 err = CHECK_RANGE(
1055                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1056                         phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC),
1057                         MIPI_T_CLKZERO_PS_MIN, MIPI_T_CLKZERO_PS_MAX);
1058                 if (err < 0) {
1059                         dev_warn(&dsi->dc->ndev->dev,
1060                                 "dsi: ClkZero mipi range violated\n");
1061                         goto fail;
1062                 }
1063
1064                 err = CHECK_RANGE(
1065                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1066                         phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC),
1067                         MIPI_T_CLKPREPARE_PS_MIN, MIPI_T_CLKPREPARE_PS_MAX);
1068                 if (err < 0) {
1069                         dev_warn(&dsi->dc->ndev->dev,
1070                                 "dsi: ClkPrepare mipi range violated\n");
1071                         goto fail;
1072                 }
1073
1074                 err = CHECK_RANGE(
1075                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1076                         phy_timing->t_clkpre, clk_ps, T_CLKPRE_HW_INC),
1077                         MIPI_T_CLKPRE_PS_MIN, MIPI_T_CLKPRE_PS_MAX);
1078                 if (err < 0) {
1079                         dev_warn(&dsi->dc->ndev->dev,
1080                                 "dsi: ClkPre mipi range violated\n");
1081                         goto fail;
1082                 }
1083
1084                 err = CHECK_RANGE(
1085                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1086                 phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC) +
1087                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1088                         phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC),
1089                         MIPI_T_CLKPREPARE_ADD_CLKZERO_PS_MIN,
1090                         MIPI_T_CLKPREPARE_ADD_CLKZERO_PS_MAX);
1091                 if (err < 0) {
1092                         dev_warn(&dsi->dc->ndev->dev,
1093                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
1094                         goto fail;
1095                 }
1096         }
1097 fail:
1098 #undef CHECK_RANGE
1099         return err;
1100 }
1101
1102 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
1103                                 struct dsi_phy_timing_inclk *phy_timing,
1104                                 u32 clk_ps, u8 lphs)
1105 {
1106         u32 hs_t_phy_ps = 0;
1107         u32 clk_t_phy_ps = 0;
1108         u32 t_phy_ps;
1109         u32 h_blank_ps;
1110         struct tegra_dc_mode *modes;
1111         u32 t_pix_ps;
1112         int err = 0;
1113
1114         if (!(lphs == DSI_LPHS_IN_HS_MODE))
1115                 goto fail;
1116
1117         if (dsi->info.video_data_type ==
1118                 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE &&
1119                 dsi->info.video_burst_mode <=
1120                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1121                 goto fail;
1122
1123         modes = dsi->dc->out->modes;
1124         t_pix_ps = clk_ps * BITS_PER_BYTE *
1125                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1126
1127         hs_t_phy_ps =
1128                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1129                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1130                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1131                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1132                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1133                 phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC) +
1134                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1135                 phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC) +
1136                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1137                 phy_timing->t_hstrail, clk_ps, T_HSTRAIL_HW_INC) +
1138                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1139                 phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC);
1140
1141         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_TX_ONLY) {
1142                 clk_t_phy_ps =
1143                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1144                 phy_timing->t_clkpost, clk_ps, T_CLKPOST_HW_INC) +
1145                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1146                 phy_timing->t_clktrail, clk_ps, T_CLKTRAIL_HW_INC) +
1147                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1148                 phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC) +
1149                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1150                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1151                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1152                 phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC) +
1153                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1154                 phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC) +
1155                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1156                 phy_timing->t_clkpre, clk_ps, T_CLKPRE_HW_INC);
1157
1158                 /* clk_pre overlaps LP-11 hs mode start sequence */
1159                 hs_t_phy_ps -= DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1160                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC);
1161         }
1162
1163         h_blank_ps = t_pix_ps * (modes->h_sync_width + modes->h_back_porch +
1164                                                 modes->h_front_porch);
1165
1166         /* Extra tlpx and byte cycle required by dsi HW */
1167         t_phy_ps = dsi->info.n_data_lanes * (hs_t_phy_ps + clk_t_phy_ps +
1168                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1169                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1170                 clk_ps * BITS_PER_BYTE);
1171
1172         if (h_blank_ps < t_phy_ps) {
1173                 err = -EINVAL;
1174                 dev_WARN(&dsi->dc->ndev->dev,
1175                         "dsi: Hblank is smaller than HS phy timing: %u pix\n",
1176                                         (t_phy_ps - h_blank_ps) / t_pix_ps);
1177                 goto fail;
1178         }
1179
1180         return 0;
1181 fail:
1182         return err;
1183 }
1184
1185 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1186                                 struct dsi_phy_timing_inclk *phy_timing,
1187                                 u32 clk_ps, u8 lphs)
1188 {
1189         int err = 0;
1190
1191         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ps, lphs);
1192         if (err < 0) {
1193                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1194                 goto fail;
1195         }
1196
1197         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ps, lphs);
1198         if (err < 0) {
1199                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1200                 goto fail;
1201         }
1202
1203         /* TODO: add more contraints */
1204 fail:
1205         return err;
1206 }
1207
1208 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1209 {
1210         u32 val;
1211         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1212
1213         tegra_dsi_get_phy_timing
1214                 (dsi, &phy_timing, dsi->current_bit_clk_ps, lphs);
1215
1216         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1217                                         dsi->current_bit_clk_ps, lphs);
1218
1219         if (tegra_platform_is_fpga() && dsi->info.ganged_type) {
1220                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1221                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1222                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1223                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1224
1225                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1226                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1227                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1228                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1229
1230                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1231                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1232                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1233
1234                 phy_timing.t_taget += T_TAGET_HW_INC;
1235                 phy_timing.t_tasure += T_TASURE_HW_INC;
1236                 phy_timing.t_tago += T_TAGO_HW_INC;
1237         }
1238         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1239                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1240                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1241                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1242         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1243
1244         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1245                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1246                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1247                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1248         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1249
1250         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1251                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1252                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1253         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1254
1255         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1256                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1257                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1258         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1259
1260         dsi->phy_timing = phy_timing;
1261 }
1262
1263 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1264                                 struct tegra_dc_dsi_data *dsi)
1265 {
1266         u32 dsi_to_pixel_clk_ratio;
1267         u32 temp;
1268         u32 temp1;
1269         u32 mipi_clk_adj_kHz = 0;
1270         u32 sol_delay;
1271         struct tegra_dc_mode *dc_modes = &dc->mode;
1272
1273         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1274         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1275                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1276
1277         /* Convert Fdsi to byte format */
1278         dsi_to_pixel_clk_ratio *= 1000/8;
1279
1280         /* Multiplying by 1000 so that we don't loose the fraction part */
1281         temp = dc_modes->h_active * 1000;
1282         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1283                         dc_modes->h_sync_width;
1284
1285         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1286                         temp * dsi->pixel_scaler_mul /
1287                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1288
1289         /* Do rounding on sol delay */
1290         sol_delay = (sol_delay + 1000 - 1)/1000;
1291
1292         /* TODO:
1293          * 1. find out the correct sol fifo depth to use
1294          * 2. verify with hw about the clamping function
1295          */
1296         if (sol_delay > (480 * 4)) {
1297                 sol_delay = (480 * 4);
1298                 mipi_clk_adj_kHz = sol_delay +
1299                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1300                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1301
1302                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1303
1304                 mipi_clk_adj_kHz *= 4;
1305         }
1306
1307         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1308
1309         return sol_delay;
1310 }
1311
1312 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1313                                 struct tegra_dc_dsi_data *dsi)
1314 {
1315         u32 sol_delay;
1316         u32 internal_delay;
1317         u32 h_width_byte_clk;
1318         u32 h_width_pixels;
1319         u32 h_width_ganged_byte_clk;
1320         u8 n_data_lanes_this_cont = 0;
1321         u8 n_data_lanes_ganged = 0;
1322
1323         if (!(dsi->info.ganged_type)) {
1324                 if (dsi->info.video_burst_mode ==
1325                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1326                         dsi->info.video_burst_mode ==
1327                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1328 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1329                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1330                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1331 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1332                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1333                 } else {
1334                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1335                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1336                 }
1337         } else {
1338 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1339 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1340 #define FIFO_WR_PIX_CLK_DELAY 2
1341 #define FIFO_RD_BYTE_CLK_DELAY 6
1342 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1343                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1344                                 FIFO_WR_PIX_CLK_DELAY)
1345
1346                 internal_delay = DIV_ROUND_UP(
1347                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1348                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1349                                 + FIFO_RD_BYTE_CLK_DELAY;
1350
1351                 h_width_pixels = dc->mode.h_sync_width +
1352                                         dc->mode.h_back_porch +
1353                                         dc->mode.h_active +
1354                                         dc->mode.h_front_porch;
1355
1356                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1357                                         dsi->pixel_scaler_mul,
1358                                         dsi->pixel_scaler_div *
1359                                         dsi->info.n_data_lanes);
1360
1361                 if (dsi->info.ganged_type ==
1362                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1363                         dsi->info.ganged_type ==
1364                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD ||
1365                         dsi->info.ganged_type ==
1366                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP) {
1367                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1368                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1369                 }
1370
1371                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1372                                         n_data_lanes_this_cont *
1373                                         h_width_byte_clk,
1374                                         n_data_lanes_ganged);
1375
1376                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1377                                                         internal_delay;
1378                 sol_delay = (dsi->info.video_data_type ==
1379                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1380                                 sol_delay + 20 : sol_delay;
1381
1382 #undef SOL_TO_VALID_PIX_CLK_DELAY
1383 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1384 #undef FIFO_WR_PIX_CLK_DELAY
1385 #undef FIFO_RD_BYTE_CLK_DELAY
1386 #undef TOT_INTERNAL_PIX_DELAY
1387         }
1388
1389         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1390                                                 DSI_SOL_DELAY);
1391 }
1392
1393 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1394 {
1395         u32 val;
1396         u32 bytes_per_frame;
1397         u32 timeout = 0;
1398
1399         /* TODO: verify the following equation */
1400         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1401                                                 (dsi->info.refresh_rate * 8);
1402         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1403         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1404
1405         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1406                         DSI_TIMEOUT_0_HTX_TO(timeout);
1407         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1408
1409         if (dsi->info.panel_reset_timeout_msec)
1410                 timeout = (dsi->info.panel_reset_timeout_msec * 1000 * 1000 *
1411                                          1000) / dsi->current_bit_clk_ps;
1412         else
1413                 timeout = DSI_PR_TO_VALUE;
1414
1415         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1416                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1417         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1418
1419         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1420                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1421                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1422                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1423         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1424 }
1425
1426 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1427                                                 struct tegra_dc_dsi_data *dsi)
1428 {
1429         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1430         u32 hact_pkt_len_pix = 0;
1431         u32 hact_pkt_len_bytes = 0;
1432         u32 hfp_pkt_len_bytes = 0;
1433         u32 pix_per_line_orig = 0;
1434         u32 pix_per_line = 0;
1435         u32 val = 0;
1436         int i = 0;
1437
1438 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1439 #define HEADER_OVERHEAD 16
1440
1441         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1442                         dc->mode.h_active + dc->mode.h_front_porch;
1443
1444         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1445                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1446         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1447
1448         switch (dsi->info.ganged_type) {
1449         case TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT: /* fall through */
1450         case TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD: /* fall through */
1451                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1452                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1453                 break;
1454         case TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP:
1455                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2) +
1456                         dsi->info.ganged_overlap;
1457                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1458                 break;
1459         default:
1460                 dev_err(&dc->ndev->dev, "dsi: invalid ganged type\n");
1461         }
1462
1463         for (i = 0; i < dsi->max_instances; i++) {
1464                 hact_pkt_len_bytes = hact_pkt_len_pix *
1465                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1466                 hfp_pkt_len_bytes = pix_per_line *
1467                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1468                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1469
1470                 val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1471                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1472                 tegra_dsi_controller_writel(dsi, val, DSI_PKT_LEN_2_3, i);
1473
1474                 val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1475                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1476                 tegra_dsi_controller_writel(dsi, val, DSI_PKT_LEN_4_5, i);
1477
1478                 if (dsi->info.ganged_type !=
1479                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP) {
1480                         hact_pkt_len_pix =
1481                                 hact_pkt_len_pix_orig - hact_pkt_len_pix;
1482                         pix_per_line = pix_per_line_orig - pix_per_line;
1483                 }
1484         }
1485
1486         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1487                 DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1488         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1489
1490 #undef HEADER_OVERHEAD
1491 }
1492
1493 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1494                                                 struct tegra_dc_dsi_data *dsi)
1495 {
1496         u32 val;
1497         u32 hact_pkt_len;
1498         u32 hsa_pkt_len;
1499         u32 hbp_pkt_len;
1500         u32 hfp_pkt_len;
1501
1502         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1503                                                         dsi->pixel_scaler_div;
1504         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1505                                                         dsi->pixel_scaler_div;
1506         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1507                                                         dsi->pixel_scaler_div;
1508         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1509                                                         dsi->pixel_scaler_div;
1510
1511         if (dsi->info.video_burst_mode !=
1512                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1513                 hbp_pkt_len += hsa_pkt_len;
1514
1515         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1516         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1517         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1518
1519         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1520                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1521         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1522
1523         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1524                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1525         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1526
1527         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1528                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1529         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1530
1531         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1532         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1533 }
1534
1535 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1536                                                 struct tegra_dc_dsi_data *dsi)
1537 {
1538         unsigned long   val;
1539         unsigned long   act_bytes;
1540
1541         if (dsi->info.ganged_type) {
1542                 act_bytes = DIV_ROUND_UP(dc->mode.h_active, 2);
1543                 act_bytes = (act_bytes) * dsi->pixel_scaler_mul /
1544                                 dsi->pixel_scaler_div + 1;
1545         } else {
1546                 act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1547                                 dsi->pixel_scaler_div + 1;
1548         }
1549         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1550         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1551
1552         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1553         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1554
1555         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1556         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1557
1558         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1559         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1560 }
1561
1562 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1563                                 struct tegra_dc_dsi_data *dsi)
1564 {
1565         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1566                 return;
1567
1568         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1569                 if (dsi->info.ganged_type)
1570                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1571                 else
1572                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1573         } else {
1574                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1575         }
1576 }
1577
1578 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1579                                 struct tegra_dc_dsi_data *dsi)
1580 {
1581         const u32 *pkt_seq;
1582         u32 rgb_info;
1583         u32 pkt_seq_3_5_rgb_lo;
1584         u32 pkt_seq_3_5_rgb_hi;
1585         u32     val;
1586         u32 reg;
1587         u8  i;
1588
1589         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1590                 return;
1591
1592         switch (dsi->info.pixel_format) {
1593         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1594                 rgb_info = CMD_RGB_16BPP;
1595                 break;
1596         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1597                 rgb_info = CMD_RGB_18BPP;
1598                 break;
1599         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1600                 rgb_info = CMD_RGB_18BPPNP;
1601                 break;
1602         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1603         default:
1604                 rgb_info = CMD_RGB_24BPP;
1605                 break;
1606         }
1607
1608         pkt_seq_3_5_rgb_lo = 0;
1609         pkt_seq_3_5_rgb_hi = 0;
1610         if (dsi->info.pkt_seq)
1611                 pkt_seq = dsi->info.pkt_seq;
1612         else if (dsi->info.video_data_type ==
1613                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1614                         pkt_seq = dsi_pkt_seq_cmd_mode;
1615         } else {
1616                 switch (dsi->info.video_burst_mode) {
1617                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1618                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1619                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1620                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1621                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1622                         pkt_seq_3_5_rgb_lo =
1623                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1624                         if (!dsi->info.no_pkt_seq_eot)
1625                                 pkt_seq = dsi_pkt_seq_video_burst;
1626                         else
1627                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1628                         break;
1629                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1630                         pkt_seq_3_5_rgb_hi =
1631                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1632                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1633                         break;
1634                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1635                 default:
1636                         if (dsi->info.ganged_type) {
1637                                 pkt_seq_3_5_rgb_lo =
1638                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1639                                 pkt_seq =
1640                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1641                         } else {
1642                                 pkt_seq_3_5_rgb_lo =
1643                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1644                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1645                         }
1646
1647                         /* Simulator does not support EOT packet yet */
1648                         if (tegra_cpu_is_asim())
1649                                 pkt_seq = dsi_pkt_seq_video_non_burst_no_eot;
1650                         break;
1651                 }
1652         }
1653
1654         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1655                 val = pkt_seq[i];
1656                 reg = dsi_pkt_seq_reg[i];
1657                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1658                         val |= pkt_seq_3_5_rgb_lo;
1659                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1660                         val |= pkt_seq_3_5_rgb_hi;
1661                 tegra_dsi_writel(dsi, val, reg);
1662         }
1663 }
1664
1665 static void tegra_dsi_reset_underflow_overflow
1666                                 (struct tegra_dc_dsi_data *dsi)
1667 {
1668         u32 val;
1669
1670         val = tegra_dsi_readl(dsi, DSI_STATUS);
1671         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1672         if (val) {
1673                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1674                         dev_warn(&dsi->dc->ndev->dev,
1675                                 "dsi: video fifo overflow. Resetting flag\n");
1676                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1677                         dev_warn(&dsi->dc->ndev->dev,
1678                                 "dsi: video fifo underflow. Resetting flag\n");
1679                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1680                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1681                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1682                 udelay(5);
1683         }
1684 }
1685
1686 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1687 {
1688         u32 trigger;
1689         u32 val;
1690         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1691         struct tegra_dc_mode mode = dsi->dc->mode;
1692         u32 tot_lines = mode.v_sync_width + mode.v_back_porch +
1693                                 mode.v_active + mode.v_front_porch;
1694         u32 line_period = DIV_ROUND_UP(MS_TO_US(frame_period), tot_lines);
1695         u32 timeout_cnt = 0;
1696
1697 /* wait for 1 frame duration + few extra cycles for dsi to go idle */
1698 #define DSI_IDLE_TIMEOUT        (tot_lines + 5)
1699
1700         val = tegra_dsi_readl(dsi, DSI_STATUS);
1701         while (!(val & DSI_STATUS_IDLE(0x1))) {
1702                 cpu_relax();
1703                 udelay(line_period);
1704                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1705                 if (timeout_cnt++ > DSI_IDLE_TIMEOUT) {
1706                         dev_warn(&dsi->dc->ndev->dev, "dsi not idle when soft reset\n");
1707                         break;
1708                 }
1709         }
1710
1711         tegra_dsi_writel(dsi,
1712                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1713                 DSI_POWER_CONTROL);
1714         /* stabilization delay */
1715         udelay(300);
1716
1717         tegra_dsi_writel(dsi,
1718                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1719                 DSI_POWER_CONTROL);
1720         /* stabilization delay */
1721         udelay(300);
1722
1723         /* dsi HW does not clear host trigger bit automatically
1724          * on dsi interface disable if host fifo is empty or in mid
1725          * of host transmission
1726          */
1727         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1728         if (trigger)
1729                 tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER);
1730
1731 #undef DSI_IDLE_TIMEOUT
1732 }
1733
1734 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1735                                         struct tegra_dc_dsi_data *dsi)
1736 {
1737         tegra_dc_get(dc);
1738
1739         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1740         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1741         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1742
1743         /* stabilization delay */
1744         udelay(500);
1745
1746         tegra_dc_put(dc);
1747
1748         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1749 }
1750
1751 /* wait for frame end interrupt or (timeout_n_frames * 1 frame duration)
1752  * whichever happens to occur first
1753  */
1754 static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1755                                 struct tegra_dc_dsi_data *dsi,
1756                                 u32 timeout_n_frames)
1757 {
1758         long timeout;
1759         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1760         struct tegra_dc_mode mode = dc->mode;
1761         u32 line_period = DIV_ROUND_UP(
1762                                 MS_TO_US(frame_period),
1763                                 mode.v_sync_width + mode.v_back_porch +
1764                                 mode.v_active + mode.v_front_porch);
1765
1766         if (timeout_n_frames < 2)
1767                 dev_WARN(&dc->ndev->dev,
1768                 "dsi: to stop at next frame give at least 2 frame delay\n");
1769
1770         timeout = _tegra_dc_wait_for_frame_end(dc, timeout_n_frames *
1771                 frame_period);
1772
1773         /* wait for v_ref_to_sync no. of lines after frame end interrupt */
1774         udelay(mode.v_ref_to_sync * line_period);
1775
1776         return timeout;
1777 }
1778
1779 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1780                                                 struct tegra_dc_dsi_data *dsi,
1781                                                 u32 timeout_n_frames)
1782 {
1783         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1784
1785         tegra_dsi_stop_dc_stream(dc, dsi);
1786
1787         if (tegra_dc_poll_register(dc, DC_CMD_STATE_CONTROL,
1788                 GENERAL_ACT_REQ, 0, 100,
1789                 timeout_n_frames * frame_period))
1790                 dev_err(&dsi->dc->ndev->dev,
1791                         "dc timeout waiting for DC to stop\n");
1792
1793         tegra_dsi_soft_reset(dsi);
1794
1795         tegra_dsi_reset_underflow_overflow(dsi);
1796 }
1797
1798 static void tegra_dc_gpio_to_spio(struct tegra_dc_dsi_data *dsi, unsigned gpio)
1799 {
1800         int err;
1801
1802         /* convert to spio */
1803         err = gpio_request(gpio, "temp_request");
1804         if (err < 0) {
1805                 dev_err(&dsi->dc->ndev->dev,
1806                         "dsi: %s: gpio request failed %d\n", __func__, err);
1807                 return;
1808         }
1809         gpio_free(gpio);
1810 }
1811
1812 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1813                                         struct tegra_dc_dsi_data *dsi)
1814 {
1815         u32 val;
1816
1817         tegra_dc_get(dc);
1818         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
1819
1820         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1821
1822         /* TODO: clean up */
1823         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1824                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1825                         DC_CMD_DISPLAY_POWER_CONTROL);
1826
1827         /* Configure one-shot mode or continuous mode */
1828         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1829                 /* disable LSPI/LCD_DE output */
1830                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1831                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1832
1833                 /* enable MSF & set MSF polarity */
1834                 val = MSF_ENABLE | MSF_LSPI;
1835                 if (!dsi->info.te_polarity_low)
1836                         val |= MSF_POLARITY_HIGH;
1837                 else
1838                         val |= MSF_POLARITY_LOW;
1839                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1840
1841                 /* set non-continuous mode */
1842                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1843                                                 DC_CMD_DISPLAY_COMMAND);
1844
1845                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1846
1847                 if (dsi->info.te_gpio)
1848                         tegra_dc_gpio_to_spio(dsi, dsi->info.te_gpio);
1849         } else {
1850                 /* set continuous mode */
1851                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1852                                                 DC_CMD_DISPLAY_COMMAND);
1853                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1854         }
1855
1856         tegra_dc_put(dc);
1857
1858         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1859 }
1860
1861 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1862                                 struct tegra_dc_dsi_data *dsi)
1863 {
1864         u32 shift_clk_div_register;
1865         u32 val;
1866
1867         /* formula: (dsi->shift_clk_div - 1) * 2 */
1868         shift_clk_div_register = DIV_ROUND_CLOSEST(
1869                                 ((dsi->shift_clk_div.mul -
1870                                 dsi->shift_clk_div.div) * 2),
1871                                 dsi->shift_clk_div.div);
1872
1873         if (tegra_platform_is_fpga()) {
1874                 shift_clk_div_register = 1;
1875                 if (dsi->info.ganged_type)
1876                         shift_clk_div_register = 0;
1877         }
1878
1879         tegra_dc_get(dc);
1880
1881         val = PIXEL_CLK_DIVIDER_PCD1 |
1882                 SHIFT_CLK_DIVIDER(shift_clk_div_register + 2);
1883
1884         /* SW WAR for bug 1045373. To make the shift clk dividor effect under
1885          * all circumstances, write N+2 to SHIFT_CLK_DIVIDER and activate it.
1886          * After 2us delay, write the target values to it. */
1887 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_11x_SOC)
1888         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1889         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1890
1891         udelay(2);
1892 #endif
1893
1894         /* TODO: find out if PCD3 option is required */
1895         val = PIXEL_CLK_DIVIDER_PCD1 |
1896                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1897
1898         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1899
1900         tegra_dc_put(dc);
1901 }
1902
1903 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1904                         struct tegra_dc_dsi_data *dsi, u32 clk)
1905 {
1906         u32 rm;
1907         u32 pclk_khz;
1908
1909         /* Round up to MHz */
1910         rm = clk % 1000;
1911         if (rm != 0)
1912                 clk -= rm;
1913
1914         /* Set up pixel clock */
1915         pclk_khz = (clk * dsi->shift_clk_div.div) /
1916                                 dsi->shift_clk_div.mul;
1917
1918         dc->mode.pclk = pclk_khz * 1000;
1919
1920         dc->shift_clk_div.mul = dsi->shift_clk_div.mul;
1921         dc->shift_clk_div.div = dsi->shift_clk_div.div;
1922
1923         /* TODO: Define one shot work delay in board file. */
1924         /* Since for one-shot mode, refresh rate is usually set larger than
1925          * expected refresh rate, it needs at least 3 frame period. Less
1926          * delay one shot work is, more powering saving we have. */
1927         dc->one_shot_delay_ms = 4 *
1928                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1929
1930         tegra_dsi_setup_clk(dc, dsi);
1931         tegra_dsi_reset_deassert(dsi);
1932
1933         dsi->current_dsi_clk_khz =
1934                         clk_get_rate(dsi->dsi_clk[0]) / 1000;
1935         dsi->current_bit_clk_ps =  DIV_ROUND_CLOSEST((1000 * 1000 * 1000),
1936                                         (dsi->current_dsi_clk_khz * 2));
1937 }
1938
1939 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1940 {
1941         u32 val;
1942
1943         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1944         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1945
1946         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1947                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1948                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1949         } else {
1950                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1951                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1952         }
1953         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1954
1955         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1956         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1957         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1958         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1959
1960         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1961 }
1962
1963 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1964 {
1965         u32 val;
1966         tegra_dsi_hs_clk_out_enable(dsi);
1967
1968         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1969         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1970         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1971         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1972 }
1973
1974 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1975                                                 struct tegra_dc_dsi_data *dsi)
1976 {
1977         u32 val;
1978
1979         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1980                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
1981
1982         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1983         /* stabilization delay */
1984         udelay(300);
1985
1986         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1987         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1988         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1989         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1990
1991         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1992         /* stabilization delay */
1993         udelay(300);
1994
1995         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1996         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1997 }
1998
1999 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
2000 {
2001         u32 dsi_control;
2002         u32 host_dsi_control;
2003         u32 max_threshold;
2004
2005         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
2006         host_dsi_control = HOST_DSI_CTRL_COMMON |
2007                         HOST_DSI_CTRL_HOST_DRIVEN |
2008                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
2009         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
2010
2011         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
2012         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
2013         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
2014
2015         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
2016         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2017         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2018 }
2019
2020 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
2021                                                 u8 driven_mode)
2022 {
2023         u32 dsi_control;
2024         u32 host_dsi_control;
2025         u32 max_threshold;
2026         u32 dcs_cmd;
2027
2028         dsi_control = dsi->dsi_control_val;
2029         host_dsi_control = HOST_DSI_CTRL_COMMON;
2030         max_threshold = 0;
2031         dcs_cmd = 0;
2032
2033         if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
2034                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
2035                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
2036                 max_threshold =
2037                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
2038                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
2039         } else {
2040                 dsi_control |= DSI_CTRL_DC_DRIVEN;
2041                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
2042                 max_threshold =
2043                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
2044                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
2045
2046                 if (dsi->info.video_data_type ==
2047                         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
2048                         dsi_control |= DSI_CTRL_CMD_MODE;
2049                         dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(
2050                                 DSI_WRITE_MEMORY_START)|
2051                                 DSI_DCS_CMDS_LT3_DCS_CMD(
2052                                 DSI_WRITE_MEMORY_CONTINUE);
2053                         dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
2054                 } else {
2055                         dsi_control |= DSI_CTRL_VIDEO_MODE;
2056                         dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
2057                 }
2058         }
2059
2060         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
2061         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
2062         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
2063         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
2064 }
2065
2066 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
2067 {
2068         u32 val;
2069
2070         if (dsi->info.controller_vs == DSI_VS_1) {
2071                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
2072                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2073                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
2074                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2075                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2076                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2077                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
2078                                                 (TEGRA_DSI_PAD_DISABLE) |
2079                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2080                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
2081                                                 (TEGRA_DSI_PAD_DISABLE);
2082                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2083         } else {
2084                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2085                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2086                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2087                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2088                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2089                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
2090                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
2091                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2092         }
2093 }
2094
2095 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
2096 {
2097         u32 val;
2098
2099         if (dsi->info.controller_vs == DSI_VS_1) {
2100                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
2101                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2102                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
2103                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2104                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2105                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2106                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
2107                                                 TEGRA_DSI_PAD_ENABLE) |
2108                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
2109                                                 TEGRA_DSI_PAD_ENABLE) |
2110                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
2111                                                 TEGRA_DSI_PAD_ENABLE);
2112                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2113         } else {
2114                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2115                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2116                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2117                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2118                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2119                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
2120                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
2121                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2122         }
2123 }
2124
2125 static void __maybe_unused
2126 tegra_dsi_mipi_calibration_status(struct tegra_dc_dsi_data *dsi)
2127 {
2128         u32 val = 0;
2129         u32 timeout = 0;
2130         /* Start calibration */
2131         val = tegra_mipi_cal_read(dsi->mipi_cal,
2132                 MIPI_CAL_MIPI_CAL_CTRL_0);
2133         val |= (MIPI_CAL_STARTCAL(0x1));
2134         tegra_mipi_cal_write(dsi->mipi_cal, val,
2135                 MIPI_CAL_MIPI_CAL_CTRL_0);
2136
2137         for (timeout = MIPI_DSI_AUTOCAL_TIMEOUT_USEC;
2138                         timeout; timeout -= 100) {
2139                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2140                 MIPI_CAL_CIL_MIPI_CAL_STATUS_0);
2141                 if (!(val & MIPI_CAL_ACTIVE(0x1)) &&
2142                         (val & MIPI_AUTO_CAL_DONE(0x1))) {
2143                                 dev_info(&dsi->dc->ndev->dev, "DSI pad calibration done\n");
2144                                 break;
2145                 }
2146                 usleep_range(10, 100);
2147         }
2148         if (timeout <= 0)
2149                 dev_info(&dsi->dc->ndev->dev, "DSI calibration timed out\n");
2150 }
2151
2152 #if defined(CONFIG_ARCH_TEGRA_13x_SOC)
2153 void tegra_dsi_mipi_calibration_13x(struct tegra_dc_dsi_data *dsi)
2154 {
2155         u32 val, reg;
2156         struct clk *clk72mhz = NULL;
2157
2158         clk72mhz = clk_get_sys("clk72mhz", NULL);
2159         if (IS_ERR_OR_NULL(clk72mhz)) {
2160                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2161                 return;
2162         }
2163         tegra_disp_clk_prepare_enable(clk72mhz);
2164
2165         /* Calibration settings begin */
2166         val = tegra_mipi_cal_read(dsi->mipi_cal,
2167                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2168         val &= ~(PAD_DRIV_UP_REF(0x7) | PAD_DRIV_DN_REF(0x7));
2169         val |= (PAD_DRIV_UP_REF(0x3) | PAD_DRIV_DN_REF(0x0));
2170         tegra_mipi_cal_write(dsi->mipi_cal, val,
2171                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2172
2173         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2174                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2175                 DSI_PAD_OUTADJCLK(0x0));
2176         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2177
2178         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
2179         val |= (DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
2180                    DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2181         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2182
2183         /* Deselect shared clk lane with DSI pads */
2184         for (reg = MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0;
2185                 reg <= MIPI_CAL_CSIE_MIPI_CAL_CONFIG_2_0;
2186                 reg += 4) {
2187                 val = tegra_mipi_cal_read(dsi->mipi_cal, reg);
2188                 val &= ~(MIPI_CAL_SELA(0x1));
2189                 tegra_mipi_cal_write(dsi->mipi_cal, val, reg);
2190         }
2191
2192         /* Calibrate DSI 0 */
2193         if (dsi->info.ganged_type ||
2194                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2195                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2196                         MIPI_CAL_SELDSIA(0x1) |
2197                         MIPI_CAL_HSPDOSDSIA(0x0) |
2198                         MIPI_CAL_HSPUOSDSIA(0x0) |
2199                         MIPI_CAL_TERMOSDSIA(0x0);
2200                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2201                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2202                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2203                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2204
2205                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2206                                 MIPI_CAL_HSCLKPDOSDSIA(0x3) |
2207                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2208                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2209                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2210                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2211                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2212
2213                 /* Deselect PAD C */
2214                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2215                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2216                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2217                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2218                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2219
2220                 /* Deselect PAD D */
2221                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2222                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2223                 val &= ~(MIPI_CAL_SELDSID(0x1));
2224                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2225                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2226
2227                 val = MIPI_CAL_NOISE_FLT(0xa) |
2228                           MIPI_CAL_PRESCALE(0x2) |
2229                           MIPI_CAL_CLKEN_OVR(0x1) |
2230                           MIPI_CAL_AUTOCAL_EN(0x0);
2231                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2232                         MIPI_CAL_MIPI_CAL_CTRL_0);
2233
2234                 tegra_dsi_mipi_calibration_status(dsi);
2235         }
2236         /* Calibrate DSI 1 */
2237         if (dsi->info.ganged_type ||
2238                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2239                 val = MIPI_CAL_OVERIDEC(0x0) |
2240                         MIPI_CAL_SELC(0x1) |
2241                         MIPI_CAL_HSPDOSC(0x0) |
2242                         MIPI_CAL_HSPUOSC(0x0) |
2243                         MIPI_CAL_TERMOSC(0x0);
2244                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2245                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_0);
2246                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2247                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_0);
2248
2249                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2250                                 MIPI_CAL_HSCLKPDOSDSIA(0x3) |
2251                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2252                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2253                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2254                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2255                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2256
2257                 /* Deselect PAD A */
2258                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2259                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2260                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2261                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2262                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2263
2264                 /* Deselect PAD B */
2265                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2266                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2267                 val &= ~(MIPI_CAL_SELDSID(0x1));
2268                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2269                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2270
2271                 val = MIPI_CAL_NOISE_FLT(0xa) |
2272                           MIPI_CAL_PRESCALE(0x2) |
2273                           MIPI_CAL_CLKEN_OVR(0x1) |
2274                           MIPI_CAL_AUTOCAL_EN(0x0);
2275                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2276                         MIPI_CAL_MIPI_CAL_CTRL_0);
2277
2278                 tegra_dsi_mipi_calibration_status(dsi);
2279         }
2280
2281         tegra_disp_clk_disable_unprepare(clk72mhz);
2282 }
2283 #endif
2284
2285 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
2286 static void tegra_dsi_mipi_calibration_21x(struct tegra_dc_dsi_data *dsi)
2287 {
2288         u32 val = 0;
2289         struct clk *clk72mhz = NULL;
2290         clk72mhz = clk_get_sys("clk72mhz", NULL);
2291         if (IS_ERR_OR_NULL(clk72mhz)) {
2292                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2293                 return;
2294         }
2295         tegra_disp_clk_prepare_enable(clk72mhz);
2296
2297         /* Calibration settings begin */
2298         val = tegra_mipi_cal_read(dsi->mipi_cal,
2299                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2300         val &= ~(PAD_VCLAMP_LEVEL(0x7) | PAD_VAUXP_LEVEL(0x7));
2301         val |= (PAD_VCLAMP_LEVEL(0x1) | PAD_VAUXP_LEVEL(0x1));
2302         tegra_mipi_cal_write(dsi->mipi_cal, val,
2303                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2304
2305         val = tegra_mipi_cal_read(dsi->mipi_cal,
2306                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2307         val &= ~(PAD_DRIV_UP_REF(0x7) | PAD_DRIV_DN_REF(0x7));
2308         val |= (PAD_DRIV_UP_REF(0x3) | PAD_DRIV_DN_REF(0x0));
2309         tegra_mipi_cal_write(dsi->mipi_cal, val,
2310                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2311
2312         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1_VS1);
2313         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2_VS1);
2314
2315         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
2316         val |= (DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
2317                    DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2318         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2319
2320         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4_VS1);
2321
2322         /* Calibrate DSI 0 */
2323         if (dsi->info.ganged_type ||
2324                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2325                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2326                         MIPI_CAL_SELDSIA(0x1) |
2327                         MIPI_CAL_HSPDOSDSIA(0x0) |
2328                         MIPI_CAL_HSPUOSDSIA(0x2) |
2329                         MIPI_CAL_TERMOSDSIA(0x0);
2330                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2331                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2332                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2333                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2334
2335                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2336                                 MIPI_CAL_HSCLKPDOSDSIA(0x0) |
2337                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2338                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2339                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2340                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2341                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2342
2343                 val = MIPI_CAL_NOISE_FLT(0xa) |
2344                           MIPI_CAL_PRESCALE(0x2) |
2345                           MIPI_CAL_CLKEN_OVR(0x0) |
2346                           MIPI_CAL_AUTOCAL_EN(0x0);
2347                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2348                         MIPI_CAL_MIPI_CAL_CTRL_0);
2349
2350                 tegra_dsi_mipi_calibration_status(dsi);
2351         }
2352         /* Calibrate DSI 1 */
2353         if (dsi->info.ganged_type ||
2354                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2355                 val = MIPI_CAL_OVERIDEDSIC(0x0) |
2356                         MIPI_CAL_SELDSIC(0x1) |
2357                         MIPI_CAL_HSPDOSDSIC(0x0) |
2358                         MIPI_CAL_HSPUOSDSIC(0x2) |
2359                         MIPI_CAL_TERMOSDSIC(0x0);
2360                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2361                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2362                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2363                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2364
2365                 val = (MIPI_CAL_CLKSELDSIC(0x1) |
2366                                 MIPI_CAL_HSCLKPDOSDSIC(0x0) |
2367                                 MIPI_CAL_HSCLKPUOSDSIC(0x2));
2368                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2369                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2_0);
2370                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2371                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_2_0);
2372
2373                 val = MIPI_CAL_NOISE_FLT(0xa) |
2374                           MIPI_CAL_PRESCALE(0x2) |
2375                           MIPI_CAL_CLKEN_OVR(0x0) |
2376                           MIPI_CAL_AUTOCAL_EN(0x0);
2377                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2378                         MIPI_CAL_MIPI_CAL_CTRL_0);
2379
2380                 tegra_dsi_mipi_calibration_status(dsi);
2381         }
2382
2383         tegra_disp_clk_disable_unprepare(clk72mhz);
2384 }
2385 #endif
2386
2387 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
2388 static void __maybe_unused
2389 tegra_dsi_mipi_calibration_12x(struct tegra_dc_dsi_data *dsi)
2390 {
2391         u32 val, reg;
2392         struct clk *clk72mhz = NULL;
2393
2394         clk72mhz = clk_get_sys("clk72mhz", NULL);
2395         if (IS_ERR_OR_NULL(clk72mhz)) {
2396                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2397                 return;
2398         }
2399         tegra_disp_clk_prepare_enable(clk72mhz);
2400
2401         /* Calibration settings begin */
2402         val = tegra_mipi_cal_read(dsi->mipi_cal,
2403                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2404         val &= ~PAD_DRIV_UP_REF(0x7);
2405         val |= PAD_DRIV_UP_REF(0x3);
2406         tegra_mipi_cal_write(dsi->mipi_cal, val,
2407                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2408         /*Bug 1445912: override tap delay for panel-a-1200-1920-7-0 */
2409         if (dsi->info.boardinfo.platform_boardid == BOARD_P1761 &&
2410                 dsi->info.boardinfo.display_boardversion == 1) {
2411                 val = (DSI_PAD_OUTADJ3(0x4) | DSI_PAD_OUTADJ2(0x4) |
2412                    DSI_PAD_OUTADJ1(0x4) | DSI_PAD_OUTADJ0(0x4));
2413                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_1_VS1);
2414         }
2415
2416         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2417                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2418                 DSI_PAD_OUTADJCLK(0x0));
2419         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2420
2421         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
2422         val |= (DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
2423                    DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2424         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2425
2426         /* Deselect shared clk lane with DSI pads */
2427         for (reg = MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0;
2428                 reg <= MIPI_CAL_CSIE_MIPI_CAL_CONFIG_2_0;
2429                 reg += 4) {
2430                 val = tegra_mipi_cal_read(dsi->mipi_cal, reg);
2431                 val &= ~(MIPI_CAL_SELA(0x1));
2432                 tegra_mipi_cal_write(dsi->mipi_cal, val, reg);
2433         }
2434
2435         /* Calibrate DSI 0 */
2436         if (dsi->info.ganged_type ||
2437                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2438                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2439                         MIPI_CAL_SELDSIA(0x1) |
2440                         MIPI_CAL_HSPDOSDSIA(0x0) |
2441                         MIPI_CAL_HSPUOSDSIA(0x0) |
2442                         MIPI_CAL_TERMOSDSIA(0x0);
2443                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2444                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2445                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2446                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2447
2448                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2449                                 MIPI_CAL_HSCLKPDOSDSIA(0x1) |
2450                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2451                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2452                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2453                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2454                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2455
2456                 /* Deselect PAD C */
2457                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2458                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2459                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2460                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2461                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2462
2463                 /* Deselect PAD D */
2464                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2465                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2466                 val &= ~(MIPI_CAL_SELDSID(0x1));
2467                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2468                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2469
2470                 val = MIPI_CAL_NOISE_FLT(0xa) |
2471                           MIPI_CAL_PRESCALE(0x2) |
2472                           MIPI_CAL_CLKEN_OVR(0x1) |
2473                           MIPI_CAL_AUTOCAL_EN(0x0);
2474                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2475                         MIPI_CAL_MIPI_CAL_CTRL_0);
2476
2477                 tegra_dsi_mipi_calibration_status(dsi);
2478         }
2479         /* Calibrate DSI 1 */
2480         if (dsi->info.ganged_type ||
2481                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2482                 val = MIPI_CAL_OVERIDEC(0x0) |
2483                         MIPI_CAL_SELC(0x1) |
2484                         MIPI_CAL_HSPDOSC(0x0) |
2485                         MIPI_CAL_HSPUOSC(0x0) |
2486                         MIPI_CAL_TERMOSC(0x0);
2487                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2488                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_0);
2489                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2490                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_0);
2491
2492                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2493                                 MIPI_CAL_HSCLKPDOSDSIA(0x1) |
2494                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2495                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2496                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2497                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2498                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2499
2500                 /* Deselect PAD A */
2501                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2502                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2503                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2504                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2505                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2506
2507                 /* Deselect PAD B */
2508                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2509                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2510                 val &= ~(MIPI_CAL_SELDSID(0x1));
2511                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2512                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2513
2514                 val = MIPI_CAL_NOISE_FLT(0xa) |
2515                           MIPI_CAL_PRESCALE(0x2) |
2516                           MIPI_CAL_CLKEN_OVR(0x1) |
2517                           MIPI_CAL_AUTOCAL_EN(0x0);
2518                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2519                         MIPI_CAL_MIPI_CAL_CTRL_0);
2520
2521                 tegra_dsi_mipi_calibration_status(dsi);
2522         }
2523
2524         tegra_disp_clk_disable_unprepare(clk72mhz);
2525 }
2526 #endif
2527
2528 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2529 void tegra_dsi_mipi_calibration_14x(struct tegra_dc_dsi_data *dsi)
2530 {
2531         u32 val;
2532         struct clk *clk72mhz = NULL;
2533
2534         clk72mhz = clk_get_sys("clk72mhz", NULL);
2535         if (IS_ERR_OR_NULL(clk72mhz)) {
2536                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2537                 return;
2538         }
2539         tegra_disp_clk_prepare_enable(clk72mhz);
2540
2541         tegra_mipi_cal_write(dsi->mipi_cal,
2542                         PAD_DRIV_DN_REF(0x2),
2543                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2544
2545         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2546                      DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1));
2547         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2548
2549         val = (DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2550         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2551
2552         val = MIPI_CAL_HSCLKPDOSDSIA(0x2) |
2553                 MIPI_CAL_HSCLKPUOSDSIA(0x2);
2554         tegra_mipi_cal_write(dsi->mipi_cal, val,
2555                 MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2556         tegra_mipi_cal_write(dsi->mipi_cal, val,
2557                 MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2558
2559         val = MIPI_CAL_OVERIDEDSIA(0x0) |
2560                 MIPI_CAL_SELDSIA(0x1) |
2561                 MIPI_CAL_HSPDOSDSIA(0x0) |
2562                 MIPI_CAL_HSPUOSDSIA(0x0) |
2563                 MIPI_CAL_TERMOSDSIA(0x0);
2564         tegra_mipi_cal_write(dsi->mipi_cal, val,
2565                 MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2566         tegra_mipi_cal_write(dsi->mipi_cal, val,
2567                 MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2568
2569         val = MIPI_CAL_NOISE_FLT(0xa) |
2570                   MIPI_CAL_PRESCALE(0x2) |
2571                   MIPI_CAL_CLKEN_OVR(0x1) |
2572                   MIPI_CAL_AUTOCAL_EN(0x0);
2573         tegra_mipi_cal_write(dsi->mipi_cal, val,
2574                 MIPI_CAL_MIPI_CAL_CTRL_0);
2575
2576         tegra_dsi_mipi_calibration_status(dsi);
2577
2578         tegra_disp_clk_disable_unprepare(clk72mhz);
2579 }
2580 #endif
2581
2582 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2583 static void tegra_dsi_mipi_calibration_11x(struct tegra_dc_dsi_data *dsi)
2584 {
2585         u32 val;
2586         /* Calibration settings begin */
2587         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2588                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2589                 DSI_PAD_OUTADJCLK(0x0));
2590         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2591
2592         /* Calibrate DSI 0 */
2593         if (dsi->info.ganged_type ||
2594                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2595                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2596                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2597                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2598                         MIPI_CAL_SELDSIA(0x1) |
2599                         MIPI_CAL_HSPDOSDSIA(0x0) |
2600                         MIPI_CAL_HSPUOSDSIA(0x4) |
2601                         MIPI_CAL_TERMOSDSIA(0x5);
2602                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2603                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2604                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2605                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2606
2607                 /* Deselect PAD C */
2608                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2609                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2610                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2611                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2612                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2613
2614                 /* Deselect PAD D */
2615                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2616                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2617                 val &= ~(MIPI_CAL_SELDSID(0x1));
2618                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2619                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2620
2621                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2622                         MIPI_CAL_MIPI_CAL_CTRL_0);
2623                 val = MIPI_CAL_NOISE_FLT(0xa) |
2624                           MIPI_CAL_PRESCALE(0x2) |
2625                           MIPI_CAL_CLKEN_OVR(0x1) |
2626                           MIPI_CAL_AUTOCAL_EN(0x0);
2627                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2628                         MIPI_CAL_MIPI_CAL_CTRL_0);
2629
2630                 tegra_dsi_mipi_calibration_status(dsi);
2631         }
2632
2633         /* Calibrate DSI 1 */
2634         if (dsi->info.ganged_type ||
2635                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2636                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2637                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2638                 val = MIPI_CAL_OVERIDEDSIC(0x0) |
2639                         MIPI_CAL_SELDSIC(0x1) |
2640                         MIPI_CAL_HSPDOSDSIC(0x0) |
2641                         MIPI_CAL_HSPUOSDSIC(0x4) |
2642                         MIPI_CAL_TERMOSDSIC(0x5);
2643                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2644                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2645                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2646                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2647
2648                 /* Deselect PAD A */
2649                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2650                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2651                 val &= ~(MIPI_CAL_SELDSIA(0x1));
2652                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2653                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2654
2655                 /* Deselect PAD B */
2656                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2657                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2658                 val &= ~(MIPI_CAL_SELDSIB(0x1));
2659                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2660                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2661
2662                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2663                         MIPI_CAL_MIPI_CAL_CTRL_0);
2664                 val = MIPI_CAL_NOISE_FLT(0xa) |
2665                           MIPI_CAL_PRESCALE(0x2) |
2666                           MIPI_CAL_CLKEN_OVR(0x1) |
2667                           MIPI_CAL_AUTOCAL_EN(0x0);
2668                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2669                         MIPI_CAL_MIPI_CAL_CTRL_0);
2670
2671                 tegra_dsi_mipi_calibration_status(dsi);
2672         }
2673 }
2674 #endif
2675 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
2676 {
2677         u32 val = 0, reg;
2678
2679         if (!dsi->ulpm)
2680                 tegra_dsi_pad_enable(dsi);
2681         else
2682                 tegra_dsi_pad_disable(dsi);
2683
2684         if (dsi->info.controller_vs == DSI_VS_1) {
2685
2686                 tegra_mipi_cal_init_hw(dsi->mipi_cal);
2687
2688                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
2689
2690                 /* Deselect CSI pads */
2691                 for (reg = MIPI_CAL_CILA_MIPI_CAL_CONFIG_0;
2692                         reg <= MIPI_CAL_CILF_MIPI_CAL_CONFIG_0;
2693                         reg += 4) {
2694                         val = tegra_mipi_cal_read(dsi->mipi_cal, reg);
2695                         val &= ~(MIPI_CAL_SELA(0x1));
2696                         tegra_mipi_cal_write(dsi->mipi_cal, val, reg);
2697                 }
2698
2699                 /* enable mipi bias pad */
2700                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2701                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2702                 val &= ~MIPI_BIAS_PAD_PDVCLAMP(0x1);
2703                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2704                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2705
2706 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || \
2707         defined(CONFIG_ARCH_TEGRA_14x_SOC) || \
2708         defined(CONFIG_ARCH_TEGRA_12x_SOC)
2709                 tegra_mipi_cal_write(dsi->mipi_cal,
2710                         MIPI_BIAS_PAD_E_VCLAMP_REF(0x1),
2711                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2712 #else
2713                 tegra_mipi_cal_write(dsi->mipi_cal,
2714                         MIPI_BIAS_PAD_E_VCLAMP_REF(0x0),
2715                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2716 #endif
2717                 tegra_mipi_cal_write(dsi->mipi_cal,
2718                         PAD_PDVREG(0x0) | PAD_VCLAMP_LEVEL(0x0),
2719                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2720 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
2721                 tegra_dsi_mipi_calibration_11x(dsi);
2722 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
2723                 tegra_dsi_mipi_calibration_14x(dsi);
2724 #elif defined(CONFIG_ARCH_TEGRA_13x_SOC)
2725                 tegra_dsi_mipi_calibration_13x(dsi);
2726 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
2727                 tegra_dsi_mipi_calibration_12x(dsi);
2728 #elif defined(CONFIG_ARCH_TEGRA_21x_SOC)
2729                 tegra_dsi_mipi_calibration_21x(dsi);
2730 #endif
2731                 /* disable mipi bias pad */
2732                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2733                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2734                 val |= MIPI_BIAS_PAD_PDVCLAMP(0x1);
2735                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2736                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2737
2738                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
2739         } else {
2740 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2741                 u32 val = 0;
2742
2743                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2744                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
2745                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
2746                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2747                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
2748                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
2749
2750                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
2751                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
2752                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2753                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
2754                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
2755
2756                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2757
2758                 val = MIPI_CAL_TERMOSA(0x4);
2759                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
2760
2761                 val = MIPI_CAL_TERMOSB(0x4);
2762                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
2763
2764                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
2765                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
2766
2767                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
2768                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
2769
2770                 val = PAD_CIL_PDVREG(0x0);
2771                 tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
2772 #endif
2773         }
2774 }
2775
2776 static void tegra_dsi_panelB_enable(void)
2777 {
2778         unsigned int val;
2779
2780         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
2781         val |= DSIB_MODE_ENABLE;
2782         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
2783 }
2784
2785 static int tegra_dsi_init_hw(struct tegra_dc *dc,
2786                                 struct tegra_dc_dsi_data *dsi)
2787 {
2788         u32 i;
2789         int err = 0;
2790
2791         if (dsi->avdd_dsi_csi)
2792                 err = regulator_enable(dsi->avdd_dsi_csi);
2793         if (WARN(err, "unable to enable regulator"))
2794                 return err;
2795         /* stablization delay */
2796         mdelay(50);
2797         /* Enable DSI clocks */
2798         tegra_dsi_clk_enable(dsi);
2799         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2800
2801         /* Stop DC stream before configuring DSI registers
2802          * to avoid visible glitches on panel during transition
2803          * from bootloader to kernel driver
2804          */
2805         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2806
2807         tegra_dsi_writel(dsi,
2808                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
2809                 DSI_POWER_CONTROL);
2810         /* stabilization delay */
2811         udelay(300);
2812
2813         if (dsi->info.dsi_instance || dsi->info.ganged_type)
2814                 tegra_dsi_panelB_enable();
2815
2816         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2817
2818         /* Initialize DSI registers */
2819         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
2820                 tegra_dsi_writel(dsi, 0, init_reg[i]);
2821         if (dsi->info.controller_vs == DSI_VS_1) {
2822                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
2823                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
2824         }
2825
2826 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2827         if (tegra_platform_is_fpga()) {
2828                 if (dsi->info.video_data_type ==
2829                                 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
2830                         /* HW fpga WAR: dsi byte clk to dsi pixel clk ratio */
2831                         tegra_dsi_writel(dsi, 0x8, DSI_INIT_SEQ_DATA_15);
2832                 }
2833         }
2834 #endif
2835
2836         tegra_dsi_pad_calibration(dsi);
2837
2838         tegra_dsi_writel(dsi,
2839                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
2840                 DSI_POWER_CONTROL);
2841         /* stabilization delay */
2842         udelay(300);
2843
2844         dsi->status.init = DSI_MODULE_INIT;
2845         dsi->status.lphs = DSI_LPHS_NOT_INIT;
2846         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2847         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
2848         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
2849         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
2850         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2851         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
2852         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2853
2854         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
2855                 tegra_dsi_syncpt_reset(dsi);
2856
2857         return 0;
2858 }
2859
2860 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
2861                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
2862 {
2863         int err;
2864
2865         if (dsi->status.init != DSI_MODULE_INIT) {
2866                 err = -EPERM;
2867                 goto fail;
2868         }
2869
2870         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2871                         dsi->status.lp_op == lp_op)
2872                 goto success;
2873
2874         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2875                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2876
2877         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
2878         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2879                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2880                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2881
2882         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
2883         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
2884                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2885                 tegra_dsi_set_timeout(dsi);
2886         }
2887
2888         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2889
2890         tegra_dsi_set_control_reg_lp(dsi);
2891
2892         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
2893                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
2894                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
2895
2896         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
2897         dsi->status.lp_op = lp_op;
2898         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2899 success:
2900         err = 0;
2901 fail:
2902         return err;
2903 }
2904
2905 static void tegra_dsi_ganged(struct tegra_dc *dc,
2906                                 struct tegra_dc_dsi_data *dsi)
2907 {
2908         u32 low_width = 0;
2909         u32 high_width = 0;
2910         u32 h_active = dc->out->modes->h_active;
2911         u32 val = 0;
2912         int dsi_instances[2];
2913         u16 ganged_pointer = DIV_ROUND_UP(h_active, 2);
2914
2915         if (dsi->info.controller_vs < DSI_VS_1) {
2916                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2917                 "supported with current controller version\n");
2918                 return;
2919         }
2920
2921         if (dsi->info.ganged_swap_links) {
2922                 dsi_instances[0] = DSI_INSTANCE_1;
2923                 dsi_instances[1] = DSI_INSTANCE_0;
2924         } else {
2925                 dsi_instances[0] = DSI_INSTANCE_0;
2926                 dsi_instances[1] = DSI_INSTANCE_1;
2927         }
2928
2929         if (dsi->info.ganged_type ==
2930                 TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP &&
2931                 dsi->info.ganged_overlap)
2932                 ganged_pointer -= dsi->info.ganged_overlap;
2933
2934         if (dsi->info.ganged_type ==
2935                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
2936                 dsi->info.ganged_type ==
2937                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP) {
2938                 /* DSI 0 */
2939                 tegra_dsi_controller_writel(dsi,
2940                         DSI_GANGED_MODE_START_POINTER(0),
2941                         DSI_GANGED_MODE_START, dsi_instances[0]);
2942                 /* DSI 1 */
2943                 tegra_dsi_controller_writel(dsi,
2944                         DSI_GANGED_MODE_START_POINTER(ganged_pointer),
2945                         DSI_GANGED_MODE_START, dsi_instances[1]);
2946
2947                 low_width = ganged_pointer;
2948                 high_width = h_active - low_width;
2949                 val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2950                         DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2951
2952         } else if (dsi->info.ganged_type ==
2953                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2954                 /* DSI 0 */
2955                 tegra_dsi_controller_writel(dsi,
2956                         DSI_GANGED_MODE_START_POINTER(0),
2957                         DSI_GANGED_MODE_START, dsi_instances[0]);
2958                 /* DSI 1 */
2959                 tegra_dsi_controller_writel(dsi,
2960                         DSI_GANGED_MODE_START_POINTER(
2961                                 dsi->info.even_odd_split_width),
2962                         DSI_GANGED_MODE_START, dsi_instances[1]);
2963
2964                 low_width = dsi->info.even_odd_split_width;
2965                 high_width = dsi->info.even_odd_split_width;
2966                 val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2967                         DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2968         }
2969
2970         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2971
2972         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2973                                                 DSI_GANGED_MODE_CONTROL);
2974 }
2975
2976 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2977                                         struct tegra_dc_dsi_data *dsi,
2978                                         u8 driven_mode)
2979 {
2980         int err;
2981
2982         if (dsi->status.init != DSI_MODULE_INIT) {
2983                 err = -EPERM;
2984                 goto fail;
2985         }
2986
2987         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE &&
2988                 dsi->driven_mode == driven_mode)
2989                 goto success;
2990
2991         dsi->driven_mode = driven_mode;
2992
2993         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2994                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2995
2996         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2997                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2998                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2999
3000         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
3001                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
3002                 tegra_dsi_set_timeout(dsi);
3003         }
3004
3005         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
3006
3007         if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
3008                 tegra_dsi_set_pkt_seq(dc, dsi);
3009                 tegra_dsi_set_pkt_length(dc, dsi);
3010                 tegra_dsi_set_sol_delay(dc, dsi);
3011                 tegra_dsi_set_dc_clk(dc, dsi);
3012         }
3013
3014         tegra_dsi_set_control_reg_hs(dsi, driven_mode);
3015
3016         if (dsi->info.ganged_type)
3017                 tegra_dsi_ganged(dc, dsi);
3018
3019         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
3020                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
3021                 tegra_dsi_hs_clk_out_enable(dsi);
3022
3023         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
3024 success:
3025         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
3026         err = 0;
3027 fail:
3028         return err;
3029 }
3030
3031 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
3032 {
3033         u32 timeout = 0;
3034         bool retVal = true;
3035
3036         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
3037                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
3038                         tegra_dsi_controller_readl(dsi,
3039                                         DSI_TRIGGER, link_id))) {
3040                         retVal = false;
3041                         break;
3042                 }
3043                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
3044                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
3045         }
3046
3047         return retVal;
3048 }
3049
3050 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
3051 {
3052         u32 timeout = 0;
3053         bool retVal = true;
3054
3055         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
3056                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
3057                         tegra_dsi_controller_readl(dsi,
3058                                         DSI_HOST_DSI_CONTROL, link_id))) {
3059                         retVal = false;
3060                         break;
3061                 }
3062                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
3063                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
3064         }
3065
3066         return retVal;
3067 }
3068
3069 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
3070 {
3071         int err = 0;
3072
3073         if (tegra_dsi_write_busy(dsi, link_id)) {
3074                 err = -EBUSY;
3075                 dev_err(&dsi->dc->ndev->dev,
3076                         "DSI trigger bit already set\n");
3077                 goto fail;
3078         }
3079
3080         if (tegra_dsi_read_busy(dsi, link_id)) {
3081                 err = -EBUSY;
3082                 dev_err(&dsi->dc->ndev->dev,
3083                         "DSI immediate bta bit already set\n");
3084                 goto fail;
3085         }
3086 fail:
3087         return (err < 0 ? true : false);
3088 }
3089
3090 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
3091 {
3092         u32 val;
3093
3094         val = tegra_dsi_readl(dsi, DSI_STATUS);
3095         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
3096         if (val) {
3097                 dev_warn(&dsi->dc->ndev->dev,
3098                         "DSI read count not zero, resetting\n");
3099                 tegra_dsi_soft_reset(dsi);
3100         }
3101 }
3102
3103 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
3104                                                 struct tegra_dc_dsi_data *dsi,
3105                                                 struct tegra_dc *dc,
3106                                                 u8 lp_op)
3107 {
3108         struct dsi_status *init_status = NULL;
3109         int err;
3110
3111         if (dsi->status.init != DSI_MODULE_INIT ||
3112                 dsi->status.lphs == DSI_LPHS_NOT_INIT) {
3113                 err = -EPERM;
3114                 goto fail;
3115         }
3116
3117         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
3118         if (!init_status)
3119                 return ERR_PTR(-ENOMEM);
3120
3121         *init_status = dsi->status;
3122
3123         if (dsi->info.hs_cmd_mode_supported) {
3124                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3125                                 TEGRA_DSI_DRIVEN_BY_HOST);
3126                 if (err < 0) {
3127                         dev_err(&dc->ndev->dev,
3128                         "Switch to HS host mode failed\n");
3129                         goto fail;
3130                 }
3131
3132                 goto success;
3133         }
3134
3135         if (dsi->status.lp_op != lp_op) {
3136                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3137                 if (err < 0) {
3138                         dev_err(&dc->ndev->dev,
3139                         "DSI failed to go to LP mode\n");
3140                         goto fail;
3141                 }
3142         }
3143 success:
3144         return init_status;
3145 fail:
3146         kfree(init_status);
3147         return ERR_PTR(err);
3148 }
3149
3150 static struct dsi_status *tegra_dsi_prepare_host_transmission(
3151                                 struct tegra_dc *dc,
3152                                 struct tegra_dc_dsi_data *dsi,
3153                                 u8 lp_op)
3154 {
3155         int i = 0;
3156         int err = 0;
3157         struct dsi_status *init_status;
3158         bool restart_dc_stream = false;
3159
3160         if (dsi->status.init != DSI_MODULE_INIT ||
3161                 dsi->ulpm) {
3162                 err = -EPERM;
3163                 goto fail;
3164         }
3165
3166         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
3167                 restart_dc_stream = true;
3168                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3169         }
3170
3171         for (i = 0; i < dsi->max_instances; i++) {
3172                 if (tegra_dsi_host_busy(dsi, i)) {
3173                         tegra_dsi_soft_reset(dsi);
3174                         if (tegra_dsi_host_busy(dsi, i)) {
3175                                 err = -EBUSY;
3176                                 dev_err(&dc->ndev->dev, "DSI host busy\n");
3177                                 goto fail;
3178                         }
3179                 }
3180         }
3181
3182         if (lp_op == DSI_LP_OP_READ)
3183                 tegra_dsi_reset_read_count(dsi);
3184
3185         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
3186                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3187                 if (err < 0) {
3188                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
3189                         goto fail;
3190                 }
3191         }
3192
3193         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
3194                                         (dsi, dc, lp_op);
3195         if (IS_ERR_OR_NULL(init_status)) {
3196                 err = PTR_ERR(init_status);
3197                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
3198                 goto fail;
3199         }
3200
3201         if (restart_dc_stream)
3202                 init_status->dc_stream = DSI_DC_STREAM_ENABLE;
3203
3204         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3205                 if (atomic_read(&dsi_syncpt_rst))
3206                         tegra_dsi_syncpt_reset(dsi);
3207
3208         return init_status;
3209 fail:
3210         return ERR_PTR(err);
3211 }
3212
3213 static int tegra_dsi_restore_state(struct tegra_dc *dc,
3214                                 struct tegra_dc_dsi_data *dsi,
3215                                 struct dsi_status *init_status)
3216 {
3217         int err = 0;
3218
3219         if (init_status->lphs == DSI_LPHS_IN_LP_MODE) {
3220                 err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
3221                 if (err < 0) {
3222                         dev_err(&dc->ndev->dev,
3223                                 "Failed to config LP mode\n");
3224                         goto fail;
3225                 }
3226                 goto success;
3227         }
3228
3229         if (init_status->lphs == DSI_LPHS_IN_HS_MODE) {
3230                 u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ?
3231                         TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST;
3232                 err = tegra_dsi_set_to_hs_mode(dc, dsi, driven);
3233                 if (err < 0) {
3234                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
3235                         goto fail;
3236                 }
3237         }
3238
3239         if (init_status->dc_stream == DSI_DC_STREAM_ENABLE)
3240                 tegra_dsi_start_dc_stream(dc, dsi);
3241 success:
3242 fail:
3243         kfree(init_status);
3244         return err;
3245 }
3246
3247 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi, u8 link_id)
3248 {
3249         int status = 0;
3250
3251         if (tegra_dsi_controller_readl(dsi, DSI_TRIGGER, link_id)) {
3252                 status = -EBUSY;
3253                 goto fail;
3254         }
3255
3256         tegra_dsi_controller_writel(dsi,
3257                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE),
3258                                 DSI_TRIGGER, link_id);
3259
3260         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3261                 status = tegra_dsi_syncpt(dsi, link_id);
3262                 if (status < 0) {
3263                         dev_err(&dsi->dc->ndev->dev,
3264                                 "DSI syncpt for host trigger failed\n");
3265                         goto fail;
3266                 }
3267         } else {
3268                 if (tegra_dsi_write_busy(dsi, link_id)) {
3269                         status = -EBUSY;
3270                         dev_err(&dsi->dc->ndev->dev,
3271                                 "Timeout waiting on write completion\n");
3272                 }
3273         }
3274
3275 fail:
3276         return status;
3277 }
3278
3279 static int _tegra_dsi_controller_write_data(struct tegra_dc_dsi_data *dsi,
3280                                         struct tegra_dsi_cmd *cmd, int link_id)
3281 {
3282         u8 virtual_channel;
3283         u32 val;
3284         int err;
3285         u8 *pdata = cmd->pdata;
3286         u8 data_id = cmd->data_id;
3287         u16 data_len = cmd->sp_len_dly.data_len;
3288
3289         err = 0;
3290
3291         if (!dsi->info.ganged_type && link_id == TEGRA_DSI_LINK1) {
3292                 dev_err(&dsi->dc->ndev->dev, "DSI invalid command\n");
3293                 return -EINVAL;
3294         }
3295
3296         virtual_channel = dsi->info.virtual_channel <<
3297                                                 DSI_VIR_CHANNEL_BIT_POSITION;
3298
3299         /* always use hw for ecc */
3300         val = (virtual_channel | data_id) << 0 |
3301                         data_len << 8;
3302         tegra_dsi_controller_writel(dsi, val, DSI_WR_DATA, link_id);
3303
3304         /* if pdata != NULL, pkt type is long pkt */
3305         if (pdata != NULL) {
3306                 while (data_len) {
3307                         if (data_len >= 4) {
3308                                 val = ((u32 *) pdata)[0];
3309                                 data_len -= 4;
3310                                 pdata += 4;
3311                         } else {
3312                                 val = 0;
3313                                 memcpy(&val, pdata, data_len);
3314                                 pdata += data_len;
3315                                 data_len = 0;
3316                         }
3317                         tegra_dsi_controller_writel(dsi, val,
3318                                 DSI_WR_DATA, link_id);
3319                 }
3320         }
3321
3322         if (cmd->cmd_type != TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD) {
3323                 err = tegra_dsi_host_trigger(dsi, link_id);
3324                 if (err < 0)
3325                         dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
3326         }
3327
3328         return err;
3329 }
3330
3331 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
3332                                         struct tegra_dsi_cmd *cmd)
3333 {
3334         int i, err = 0;
3335
3336         if (dsi->info.ganged_type && dsi->info.ganged_write_to_all_links)
3337                 for (i = 0; i < dsi->max_instances; i++) {
3338                         err = _tegra_dsi_controller_write_data(dsi, cmd, i);
3339                         if (err)
3340                                 break;
3341                 }
3342         else
3343                 err = _tegra_dsi_controller_write_data(dsi, cmd, cmd->link_id);
3344
3345         return err;
3346 }
3347
3348 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
3349 {
3350         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3351
3352         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
3353                 atomic_inc(&dsi->host_ref);
3354                 tegra_dsi_host_resume(dc);
3355         }
3356 }
3357
3358 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
3359 {
3360         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3361
3362         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
3363                 atomic_dec(&dsi->host_ref);
3364
3365                 if (!atomic_read(&dsi->host_ref) &&
3366                     (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE))
3367                         schedule_delayed_work(&dsi->idle_work, dsi->idle_delay);
3368         }
3369 }
3370
3371 static void tegra_dc_dsi_idle_work(struct work_struct *work)
3372 {
3373         struct tegra_dc_dsi_data *dsi = container_of(
3374                 to_delayed_work(work), struct tegra_dc_dsi_data, idle_work);
3375
3376         if (dsi->dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
3377                 tegra_dsi_host_suspend(dsi->dc);
3378 }
3379
3380 static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
3381                         struct tegra_dc_dsi_data *dsi,
3382                         struct tegra_dsi_cmd *cmd, u8 delay_ms)
3383 {
3384         int err = 0;
3385         int restore_err = 0;
3386         struct dsi_status *init_status;
3387
3388         init_status = tegra_dsi_prepare_host_transmission(
3389                                 dc, dsi, DSI_LP_OP_WRITE);
3390         if (IS_ERR_OR_NULL(init_status)) {
3391                 err = PTR_ERR(init_status);
3392                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3393                 goto fail;
3394         }
3395
3396         err = _tegra_dsi_write_data(dsi, cmd);
3397         if (err < 0) {
3398                 dev_err(&dc->ndev->dev, "Failed DSI write\n");
3399                 restore_err = tegra_dsi_restore_state(dc, dsi, init_status);
3400                 if (restore_err < 0)
3401                         dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3402                 goto fail;
3403         }
3404
3405         mdelay(delay_ms);
3406
3407         err = tegra_dsi_restore_state(dc, dsi, init_status);
3408         if (err < 0)
3409                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3410
3411 fail:
3412         return err;
3413 }
3414
3415 int tegra_dsi_write_data(struct tegra_dc *dc,
3416                         struct tegra_dc_dsi_data *dsi,
3417                         struct tegra_dsi_cmd *cmd, u8 delay_ms)
3418 {
3419         int err;
3420
3421         tegra_dc_io_start(dc);
3422         tegra_dc_dsi_hold_host(dc);
3423
3424         err = tegra_dsi_write_data_nosync(dc, dsi, cmd, delay_ms);
3425
3426         tegra_dc_dsi_release_host(dc);
3427         tegra_dc_io_end(dc);
3428
3429         return err;
3430 }
3431
3432 EXPORT_SYMBOL(tegra_dsi_write_data);
3433
3434 int tegra_dsi_start_host_cmd_v_blank_video(struct tegra_dc_dsi_data *dsi,
3435                                 struct tegra_dsi_cmd *cmd, u8 clubbed_cmd_no)
3436 {
3437         struct tegra_dc *dc = dsi->dc;
3438         int err = 0;
3439         u32 val;
3440         u8 i;
3441
3442         if (!dsi->enabled) {
3443                 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n");
3444                 return -EINVAL;
3445         }
3446
3447         tegra_dc_io_start(dc);
3448         tegra_dc_dsi_hold_host(dc);
3449
3450         val = (DSI_CMD_PKT_VID_ENABLE(1) | DSI_LINE_TYPE(4));
3451         tegra_dsi_writel(dsi, val, DSI_VID_MODE_CONTROL);
3452         if (clubbed_cmd_no)
3453                 for (i = 0; i < clubbed_cmd_no; i++)
3454                         _tegra_dsi_write_data(dsi, &cmd[i]);
3455         else
3456                 _tegra_dsi_write_data(dsi, &cmd[0]);
3457
3458         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3459                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3460                                 TEGRA_DSI_DRIVEN_BY_DC);
3461                 if (err < 0) {
3462                         dev_err(&dc->ndev->dev,
3463                                 "dsi: not able to set to hs mode\n");
3464                         goto fail;
3465                 }
3466         }
3467
3468         tegra_dsi_start_dc_stream(dc, dsi);
3469         tegra_dsi_wait_frame_end(dc, dsi, 2);
3470 fail:
3471         tegra_dc_dsi_release_host(dc);
3472         tegra_dc_io_end(dc);
3473
3474         return err;
3475 }
3476 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_video);
3477
3478 int tegra_dsi_end_host_cmd_v_blank_video(struct tegra_dc *dc,
3479                                         struct tegra_dc_dsi_data *dsi)
3480 {
3481         if (!dsi->enabled) {
3482                 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n");
3483                 return -EINVAL;
3484         }
3485
3486         tegra_dc_io_start(dc);
3487         tegra_dsi_writel(dsi, 0, DSI_VID_MODE_CONTROL);
3488         tegra_dc_io_end(dc);
3489
3490         return 0;
3491 }
3492 EXPORT_SYMBOL(tegra_dsi_end_host_cmd_v_blank_video);
3493
3494 int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
3495                                         struct tegra_dc_dsi_data *dsi,
3496                                         struct tegra_dsi_cmd *cmd,
3497                                         u32 n_cmd)
3498 {
3499 #define DEFAULT_DELAY_MS 1
3500         u32 i;
3501         int err;
3502         u8 delay_ms;
3503         int retry_count;
3504
3505         err = 0;
3506         for (i = 0; i < n_cmd; i++) {
3507                 struct tegra_dsi_cmd *cur_cmd;
3508                 cur_cmd = &cmd[i];
3509
3510                 if (cur_cmd->cmd_type == TEGRA_DSI_GPIO_SET) {
3511                         gpio_set_value(cur_cmd->sp_len_dly.gpio,
3512                                        cur_cmd->data_id);
3513                 } else if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS) {
3514                         usleep_range(cur_cmd->sp_len_dly.delay_ms * 1000,
3515                                 (cur_cmd->sp_len_dly.delay_ms * 1000) + 500);
3516                 } else if (cur_cmd->cmd_type == TEGRA_DSI_SEND_FRAME) {
3517                                 tegra_dsi_send_dc_frames(dc,
3518                                                 dsi,
3519                                                 cur_cmd->sp_len_dly.frame_cnt);
3520                 } else if (cur_cmd->cmd_type ==
3521                                         TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD) {
3522                         u32 j;
3523                         for (j = i; j < n_cmd; j++) {
3524                                 if (!IS_DSI_SHORT_PKT(cmd[j]))
3525                                         break;
3526                                 if (cmd[j].club_cmd != CMD_CLUBBED)
3527                                         break;
3528                                 if (j - i + 1 > DSI_HOST_FIFO_DEPTH)
3529                                         break;
3530                         }
3531                         /* i..j-1: clubbable streak */
3532                         tegra_dsi_start_host_cmd_v_blank_video(dsi, cur_cmd,
3533                                                                         j - i);
3534                         tegra_dsi_end_host_cmd_v_blank_video(dc, dsi);
3535                         if (j != i)
3536                                 i = j - 1;
3537                 } else {
3538                         delay_ms = DEFAULT_DELAY_MS;
3539                         if ((i + 1 < n_cmd) &&
3540                                 (cmd[i + 1].cmd_type == TEGRA_DSI_DELAY_MS)) {
3541                                 delay_ms = cmd[i + 1].sp_len_dly.delay_ms;
3542                                 i++;
3543                         }
3544                         retry_count = DSI_WRITE_DATA_RETRY_ATTEMPTS;
3545                         do {
3546                                 err = tegra_dsi_write_data_nosync(dc, dsi,
3547                                                         cur_cmd, delay_ms);
3548                                 if (err < 0) {
3549                                         retry_count--;
3550                                         dev_err(&dsi->dc->ndev->dev,
3551                                                 "dsi: %s failed, retrying...\n",__func__);
3552                                 } else {
3553                                         retry_count = 0;
3554                                 }
3555                         } while (retry_count);
3556                 }
3557         }
3558         return err;
3559 #undef DEFAULT_DELAY_MS
3560 }
3561
3562 static u8 tegra_dsi_ecc(u32 header)
3563 {
3564         char ecc_parity[24] = {
3565                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
3566                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
3567                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
3568         };
3569         u8 ecc_byte;
3570         int i;
3571
3572         ecc_byte = 0;
3573         for (i = 0; i < 24; i++)
3574                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
3575
3576         return ecc_byte;
3577 }
3578
3579 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
3580 {
3581         u16 byte_cnt;
3582         u8 bit_cnt;
3583         char curr_byte;
3584         u16 crc = 0xFFFF;
3585         u16 poly = 0x8408;
3586
3587         if (data_len > 0) {
3588                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
3589                         curr_byte = pdata[byte_cnt];
3590                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
3591                                 if (((crc & 0x0001) ^
3592                                         (curr_byte & 0x0001)) > 0)
3593                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
3594                                 else
3595                                         crc = (crc >> 1) & 0x7FFF;
3596
3597                                 curr_byte = (curr_byte >> 1) & 0x7F;
3598                         }
3599                 }
3600         }
3601         return crc;
3602 }
3603
3604 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
3605                                                 struct tegra_dsi_cmd *cmd)
3606 {
3607         u8 virtual_channel;
3608         u32 val;
3609         u16 data_len = cmd->sp_len_dly.data_len;
3610         u8 seq_ctrl_reg = 0;
3611
3612         virtual_channel = dsi->info.virtual_channel <<
3613                                 DSI_VIR_CHANNEL_BIT_POSITION;
3614
3615         val = (virtual_channel | cmd->data_id) << 0 |
3616                 data_len << 8;
3617
3618         val |= tegra_dsi_ecc(val) << 24;
3619
3620         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
3621
3622         /* if pdata != NULL, pkt type is long pkt */
3623         if (cmd->pdata != NULL) {
3624                 u8 *pdata;
3625                 u8 *pdata_mem;
3626                 /* allocate memory for pdata + 2 bytes checksum */
3627                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
3628                 if (!pdata_mem) {
3629                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
3630                         tegra_dsi_soft_reset(dsi);
3631                         return -ENOMEM;
3632                 }
3633
3634                 memcpy(pdata_mem, cmd->pdata, data_len);
3635                 pdata = pdata_mem;
3636                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
3637
3638                 /* data_len = length of pdata + 2 byte checksum */
3639                 data_len += 2;
3640
3641                 while (data_len) {
3642                         if (data_len >= 4) {
3643                                 val = ((u32 *) pdata)[0];
3644                                 data_len -= 4;
3645                                 pdata += 4;
3646                         } else {
3647                                 val = 0;
3648                                 memcpy(&val, pdata, data_len);
3649                                 pdata += data_len;
3650                                 data_len = 0;
3651                         }
3652                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
3653                                                         seq_ctrl_reg++);
3654                 }
3655                 kfree(pdata_mem);
3656         }
3657
3658         return 0;
3659 }
3660
3661 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi,
3662                                                 struct tegra_dsi_cmd *cmd)
3663 {
3664 #define PKT_HEADER_LEN_BYTE     4
3665 #define CHECKSUM_LEN_BYTE       2
3666
3667         int err = 0;
3668         u32 val;
3669         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
3670         struct tegra_dc *dc = dsi->dc;
3671
3672         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
3673                 return -EINVAL;
3674
3675         mutex_lock(&dsi->lock);
3676         tegra_dc_io_start(dc);
3677         tegra_dc_dsi_hold_host(dc);
3678
3679 #if DSI_USE_SYNC_POINTS
3680         atomic_set(&dsi_syncpt_rst, 1);
3681 #endif
3682
3683         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
3684         if (err < 0) {
3685                 dev_err(&dsi->dc->ndev->dev,
3686                         "dsi: dcs pkt seq ctrl init failed\n");
3687                 goto fail;
3688         }
3689
3690         if (cmd->pdata) {
3691                 u16 data_len = cmd->sp_len_dly.data_len;
3692                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
3693         }
3694
3695         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
3696                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
3697                                                 TEGRA_DSI_ENABLE);
3698         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
3699
3700 fail:
3701         tegra_dc_dsi_release_host(dc);
3702         tegra_dc_io_end(dc);
3703         mutex_unlock(&dsi->lock);
3704         return err;
3705
3706 #undef PKT_HEADER_LEN_BYTE
3707 #undef CHECKSUM_LEN_BYTE
3708 }
3709 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
3710
3711 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi)
3712 {
3713         struct tegra_dc *dc = dsi->dc;
3714         u32 cnt;
3715
3716         mutex_lock(&dsi->lock);
3717         tegra_dc_io_start(dc);
3718         tegra_dc_dsi_hold_host(dc);
3719
3720         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3721                 if (atomic_read(&dsi_syncpt_rst)) {
3722                         tegra_dsi_wait_frame_end(dc, dsi, 2);
3723                         tegra_dsi_syncpt_reset(dsi);
3724                         atomic_set(&dsi_syncpt_rst, 0);
3725                 }
3726
3727         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
3728
3729         /* clear seq data registers */
3730         for (cnt = 0; cnt < 8; cnt++)
3731                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
3732
3733         tegra_dc_dsi_release_host(dc);
3734         tegra_dc_io_end(dc);
3735
3736         mutex_unlock(&dsi->lock);
3737 }
3738 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
3739
3740 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
3741 {
3742         u32 val;
3743         int err = 0;
3744
3745         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3746         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
3747
3748         if (dsi->info.ganged_type && dsi->info.ganged_write_to_all_links)
3749                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3750         else
3751                 tegra_dsi_controller_writel(dsi, val,
3752                                 DSI_HOST_DSI_CONTROL, TEGRA_DSI_LINK0);
3753
3754         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3755                 err = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
3756                 if (err < 0) {
3757                         dev_err(&dsi->dc->ndev->dev,
3758                                 "DSI syncpt for bta failed\n");
3759                 }
3760         } else {
3761                 if (tegra_dsi_read_busy(dsi, TEGRA_DSI_LINK0)) {
3762                         err = -EBUSY;
3763                         dev_err(&dsi->dc->ndev->dev,
3764                                 "Timeout wating on read completion\n");
3765                 }
3766         }
3767
3768         return err;
3769 }
3770
3771 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
3772                                         u32 rd_fifo_cnt, u8 *read_fifo)
3773 {
3774         int err;
3775         u32 payload_size;
3776
3777         payload_size = 0;
3778         err = 0;
3779
3780         switch (read_fifo[0]) {
3781         case DSI_ESCAPE_CMD:
3782                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
3783                 break;
3784         case DSI_ACK_NO_ERR:
3785                 dev_info(&dc->ndev->dev,
3786                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
3787                 return err;
3788         default:
3789                 dev_info(&dc->ndev->dev, "Invalid read response\n");
3790                 break;
3791         }
3792
3793         switch (read_fifo[4] & 0xff) {
3794         case GEN_LONG_RD_RES:
3795                 /* Fall through */
3796         case DCS_LONG_RD_RES:
3797                 payload_size = (read_fifo[5] |
3798                                 (read_fifo[6] << 8)) & 0xFFFF;
3799                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
3800                                 "payload_size[0x%x]\n", payload_size);
3801                 break;
3802         case GEN_1_BYTE_SHORT_RD_RES:
3803                 /* Fall through */
3804         case DCS_1_BYTE_SHORT_RD_RES:
3805                 payload_size = 1;
3806                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3807                         "payload_size[0x%x]\n", payload_size);
3808                 break;
3809         case GEN_2_BYTE_SHORT_RD_RES:
3810                 /* Fall through */
3811         case DCS_2_BYTE_SHORT_RD_RES:
3812                 payload_size = 2;
3813                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3814                         "payload_size[0x%x]\n", payload_size);
3815                 break;
3816         case ACK_ERR_RES:
3817                 payload_size = 2;
3818                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
3819                         "Packet payload_size[0x%x]\n", payload_size);
3820                 break;
3821         default:
3822                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
3823                 err = -EINVAL;
3824                 break;
3825         }
3826         return err;
3827 }
3828
3829 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
3830                         struct tegra_dc_dsi_data *dsi,
3831                         u8 *read_fifo)
3832 {
3833         u32 val;
3834         u32 i;
3835         u32 poll_time = 0;
3836         u32 rd_fifo_cnt;
3837         int err = 0;
3838         u8 *read_fifo_cp = read_fifo;
3839
3840         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
3841                 mdelay(1);
3842                 val = tegra_dsi_readl(dsi, DSI_STATUS);
3843                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
3844                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH) {
3845                         dev_err(&dc->ndev->dev,
3846                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
3847                         break;
3848                 }
3849                 poll_time++;
3850         }
3851
3852         if (rd_fifo_cnt == 0) {
3853                 dev_info(&dc->ndev->dev,
3854                         "DSI RD_FIFO_CNT is zero\n");
3855                 err = -EINVAL;
3856                 goto fail;
3857         }
3858
3859         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
3860                 DSI_STATUS_LB_OVERFLOW(0x1))) {
3861                 dev_warn(&dc->ndev->dev,
3862                         "DSI overflow/underflow error\n");
3863         }
3864
3865         /* Read data from FIFO */
3866         for (i = 0; i < rd_fifo_cnt; i++) {
3867                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
3868                 if (enable_read_debug)
3869                         dev_info(&dc->ndev->dev,
3870                         "Read data[%d]: 0x%x\n", i, val);
3871                 memcpy(read_fifo, &val, 4);
3872                 read_fifo += 4;
3873         }
3874
3875         /* Make sure all the data is read from the FIFO */
3876         val = tegra_dsi_readl(dsi, DSI_STATUS);
3877         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
3878         if (val)
3879                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
3880                 " even after reading FIFO_RD_CNT words from read fifo\n");
3881
3882         if (enable_read_debug) {
3883                 err =
3884                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
3885                 if (err < 0)
3886                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
3887         }
3888 fail:
3889         return err;
3890 }
3891
3892 int tegra_dsi_read_data(struct tegra_dc *dc,
3893                                 struct tegra_dc_dsi_data *dsi,
3894                                 u16 max_ret_payload_size,
3895                                 u8 panel_reg_addr, u8 *read_data)
3896 {
3897         int err = 0;
3898         struct dsi_status *init_status;
3899         static struct tegra_dsi_cmd temp_cmd;
3900
3901         if (!dsi->enabled) {
3902                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
3903                 return -EINVAL;
3904         }
3905         tegra_dc_dsi_hold_host(dc);
3906         mutex_lock(&dsi->lock);
3907         tegra_dc_io_start(dc);
3908         tegra_disp_clk_prepare_enable(dsi->dsi_fixed_clk);
3909         tegra_dsi_lp_clk_enable(dsi);
3910         init_status = tegra_dsi_prepare_host_transmission(
3911                                 dc, dsi, DSI_LP_OP_WRITE);
3912         if (IS_ERR_OR_NULL(init_status)) {
3913                 err = PTR_ERR(init_status);
3914                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3915                 goto fail;
3916         }
3917
3918         /* Set max return payload size in words */
3919         temp_cmd.data_id = dsi_command_max_return_pkt_size;
3920         temp_cmd.sp_len_dly.data_len = max_ret_payload_size;
3921         err = _tegra_dsi_write_data(dsi, &temp_cmd);
3922         if (err < 0) {
3923                 dev_err(&dc->ndev->dev,
3924                                 "DSI write failed\n");
3925                 goto fail;
3926         }
3927
3928         /* DCS to read given panel register */
3929         temp_cmd.data_id = dsi_command_dcs_read_with_no_params;
3930         temp_cmd.sp_len_dly.sp.data0 = panel_reg_addr;
3931         temp_cmd.sp_len_dly.sp.data1 = 0;
3932         err = _tegra_dsi_write_data(dsi, &temp_cmd);
3933         if (err < 0) {
3934                 dev_err(&dc->ndev->dev,
3935                                 "DSI write failed\n");
3936                 goto fail;
3937         }
3938
3939         tegra_dsi_reset_read_count(dsi);
3940
3941         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3942                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3943                 if (err < 0) {
3944                         dev_err(&dc->ndev->dev,
3945                         "DSI failed to go to LP read mode\n");
3946                         goto fail;
3947                 }
3948         }
3949
3950         err = tegra_dsi_bta(dsi);
3951         if (err < 0) {
3952                 dev_err(&dc->ndev->dev,
3953                         "DSI IMM BTA timeout\n");
3954                 goto fail;
3955         }
3956
3957         err = tegra_dsi_read_fifo(dc, dsi, read_data);
3958         if (err < 0) {
3959                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3960                 goto fail;
3961         }
3962 fail:
3963         err = tegra_dsi_restore_state(dc, dsi, init_status);
3964         if (err < 0)
3965                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3966         tegra_dsi_lp_clk_disable(dsi);
3967         tegra_disp_clk_disable_unprepare(dsi->dsi_fixed_clk);
3968         tegra_dc_io_end(dc);
3969         mutex_unlock(&dsi->lock);
3970         tegra_dc_dsi_release_host(dc);
3971         return err;
3972 }
3973 EXPORT_SYMBOL(tegra_dsi_read_data);
3974
3975 static const char * const error_sanity[] = {
3976                 "SoT Error",
3977                 "SoT Sync Error",
3978                 "EoT Sync Error",
3979                 "Escape Mode Entry Comand Error",
3980                 "Low-Power Transmit Sync Error",
3981                 "HS Receive Timeout Error",
3982                 "False Control Error",
3983                 "Reserved",
3984                 "ECC Error,Single Bit",
3985                 "ECC Error, Multi Bit",
3986                 "Checksum Error",
3987                 "DSI Data Type Not recognized",
3988                 "DSI VC ID Invalid",
3989                 "DSI Protocol Violation",
3990                 "Reserved",
3991                 "Reserved",
3992 };
3993
3994 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
3995                                 struct tegra_dc_dsi_data *dsi,
3996                                 struct sanity_status *san)
3997 {
3998         int err = 0;
3999         u32 flagset[16];
4000         u8 read_fifo[DSI_READ_FIFO_DEPTH];
4001         struct dsi_status *init_status;
4002         static struct tegra_dsi_cmd dsi_nop_cmd =
4003                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
4004
4005         if (!dsi->enabled) {
4006                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
4007                 return -EINVAL;
4008         }
4009         tegra_dc_dsi_hold_host(dc);
4010         tegra_dc_io_start(dc);
4011         tegra_disp_clk_prepare_enable(dsi->dsi_fixed_clk);
4012         tegra_dsi_lp_clk_enable(dsi);
4013         memset(flagset, 0, sizeof(flagset));
4014         init_status = tegra_dsi_prepare_host_transmission(
4015                                 dc, dsi, DSI_LP_OP_WRITE);
4016         if (IS_ERR_OR_NULL(init_status)) {
4017                 err = PTR_ERR(init_status);
4018                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
4019                 goto fail;
4020         }
4021
4022         err = _tegra_dsi_write_data(dsi, &dsi_nop_cmd);
4023         if (err < 0) {
4024                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
4025                 goto fail;
4026         }
4027
4028         tegra_dsi_reset_read_count(dsi);
4029
4030         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
4031                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
4032                 if (err < 0) {
4033                         dev_err(&dc->ndev->dev,
4034                         "DSI failed to go to LP read mode\n");
4035                         goto fail;
4036                 }
4037         }
4038
4039         err = tegra_dsi_bta(dsi);
4040         if (err < 0) {
4041                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
4042                 goto fail;
4043         }
4044
4045         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
4046         if (err < 0) {
4047                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
4048                 goto fail;
4049         }
4050
4051         if (read_fifo[0] != DSI_ACK_NO_ERR) {
4052                 if (read_fifo[4] == ACK_ERR_RES) {
4053                         u16 payload = read_fifo[5] | (read_fifo[6] << 8);
4054                         int i = 0;
4055                         for (; payload; payload >>= 1, i++) {
4056                                 if (payload & 1) {
4057                                         flagset[i] = 0x01;
4058                                         if (enable_read_debug)
4059                                                 dev_info(&dc->ndev->dev,
4060                                                         " %s => error flag number %d\n",
4061                                                         error_sanity[i], i);
4062                                 }
4063                         }
4064                         if (san != NULL) {
4065                                 san->sot_error = flagset[0];
4066                                 san->sot_sync_error = flagset[1];
4067                                 san->eot_sync_error = flagset[2];
4068                                 san->escape_mode_entry_comand_error =
4069                                                 flagset[3];
4070                                 san->low_power_transmit_sync_error = flagset[4];
4071                                 san->hs_receive_timeout_error = flagset[5];
4072                                 san->false_control_error = flagset[6];
4073                                 san->reserved1 = flagset[7];
4074                                 san->ecc_error_single_bit = flagset[8];
4075                                 san->ecc_error_multi_bit = flagset[9];
4076                                 san->checksum_error = flagset[10];
4077                                 san->dsi_data_type_not_recognized = flagset[11];
4078                                 san->dsi_vc_id_invalid = flagset[12];
4079                                 san->dsi_protocol_violation = flagset[13];
4080                                 san->reserved2 = flagset[14];
4081                                 san->reserved3 = flagset[15];
4082                         }
4083                 }
4084                 dev_warn(&dc->ndev->dev,
4085                         "Ack no error trigger message not received\n");
4086                 err = -EAGAIN;
4087         }
4088
4089 fail:
4090         err = tegra_dsi_restore_state(dc, dsi, init_status);
4091         if (err < 0)
4092                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
4093         tegra_dsi_lp_clk_disable(dsi);
4094         tegra_disp_clk_disable_unprepare(dsi->dsi_fixed_clk);
4095         tegra_dc_io_end(dc);
4096         tegra_dc_dsi_release_host(dc);
4097         return err;
4098 }
4099 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
4100
4101 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
4102 {
4103         u32 val;
4104         int ret = 0;
4105
4106         if (dsi->info.ulpm_not_supported)
4107                 return 0;
4108
4109         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
4110                 if (atomic_read(&dsi_syncpt_rst))
4111                         tegra_dsi_syncpt_reset(dsi);
4112
4113         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
4114         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
4115         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
4116         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
4117
4118         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
4119                 ret = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
4120                 if (ret < 0) {
4121                         dev_err(&dsi->dc->ndev->dev,
4122                                 "DSI syncpt for ulpm enter failed\n");
4123                         return ret;
4124                 }
4125         } else {
4126                 /* TODO: Find exact delay required */
4127                 mdelay(10);
4128         }
4129         dsi->ulpm = true;
4130
4131         return ret;
4132 }
4133
4134 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
4135 {
4136         u32 val;
4137         int ret = 0;
4138
4139         if (dsi->info.ulpm_not_supported)
4140                 return 0;
4141
4142         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
4143                 if (atomic_read(&dsi_syncpt_rst))
4144                         tegra_dsi_syncpt_reset(dsi);
4145
4146         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
4147         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
4148         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
4149         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
4150
4151         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
4152                 ret = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
4153                 if (ret < 0) {
4154                         dev_err(&dsi->dc->ndev->dev,
4155                                 "DSI syncpt for ulpm exit failed\n");
4156                         return ret;
4157                 }
4158         } else {
4159                 /* TODO: Find exact delay required */
4160                 mdelay(10);
4161         }
4162         dsi->ulpm = false;
4163
4164         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
4165         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
4166         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
4167         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
4168
4169         return ret;
4170 }
4171
4172 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
4173                                      struct tegra_dc_dsi_data *dsi,
4174                                      int no_of_frames)
4175 {
4176         int err;
4177         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
4178         u8 lp_op = dsi->status.lp_op;
4179         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
4180
4181         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
4182                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
4183                                 TEGRA_DSI_DRIVEN_BY_DC);
4184                 if (err < 0) {
4185                         dev_err(&dc->ndev->dev,
4186                                 "Switch to HS host mode failed\n");
4187                         return;
4188                 }
4189         }
4190
4191         /*
4192          * Some panels need DC frames be sent under certain
4193          * conditions. We are working on the right fix for this
4194          * requirement, while using this current fix.
4195          */
4196         tegra_dsi_start_dc_stream(dc, dsi);
4197
4198         /*
4199          * Send frames in Continuous or One-shot mode.
4200          */
4201         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
4202                 /* FIX ME: tegra_dc_blank() implicitly takes lock */
4203                 int flag = mutex_is_locked(&dc->lock);
4204                 if (flag)
4205                         mutex_unlock(&dc->lock);
4206                 while (no_of_frames--)
4207                         tegra_dc_blank(dc, BLANK_ALL);
4208                 if (flag)
4209                         mutex_lock(&dc->lock);
4210         } else
4211                 mdelay(no_of_frames * frame_period);
4212
4213         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4214
4215         if (switch_to_lp) {
4216                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
4217                 if (err < 0)
4218                         dev_err(&dc->ndev->dev,
4219                                 "DSI failed to go to LP mode\n");
4220         }
4221 }
4222
4223 static void tegra_dsi_setup_initialized_panel(struct tegra_dc_dsi_data *dsi)
4224 {
4225         int err = 0;
4226
4227         if (dsi->avdd_dsi_csi)
4228                 err = regulator_enable(dsi->avdd_dsi_csi);
4229         WARN(err, "unable to enable regulator");
4230
4231         dsi->status.init = DSI_MODULE_INIT;
4232         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
4233         dsi->status.driven = DSI_DRIVEN_MODE_DC;
4234         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
4235         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
4236         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
4237         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
4238
4239         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
4240                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
4241         else
4242                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
4243
4244         if (!(dsi->info.ganged_type)) {
4245                 if (dsi->info.video_burst_mode ==
4246                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
4247                         dsi->info.video_burst_mode ==
4248                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
4249                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
4250                 else
4251                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
4252         }
4253
4254         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
4255                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
4256         else
4257                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
4258
4259         tegra_dsi_clk_enable(dsi);
4260
4261         dsi->enabled = true;
4262 }
4263
4264 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
4265 {
4266         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4267         int err = 0;
4268
4269         sysedp_set_state(dsi->sysedpc, 1);
4270         mutex_lock(&dsi->lock);
4271         tegra_dc_io_start(dc);
4272
4273         /*
4274          * Do not program this panel as the bootloader as has already
4275          * initialized it. This avoids periods of blanking during boot.
4276          */
4277         if (dc->initialized) {
4278                 tegra_dsi_setup_initialized_panel(dsi);
4279                 goto fail;
4280         }
4281
4282         /* Stop DC stream before configuring DSI registers
4283          * to avoid visible glitches on panel during transition
4284          * from bootloader to kernel driver
4285          */
4286         tegra_dsi_stop_dc_stream(dc, dsi);
4287
4288         if (dsi->enabled) {
4289                 if (dsi->ulpm) {
4290                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4291                                 dev_err(&dc->ndev->dev,
4292                                         "DSI failed to exit ulpm\n");
4293                                 goto fail;
4294                         }
4295                 }
4296
4297                 if (dsi->info.panel_reset) {
4298                         /*
4299                          * Certain panels need dc frames be sent before
4300                          * waking panel.
4301                          */
4302                         if (dsi->info.panel_send_dc_frames)
4303                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
4304
4305                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4306                                                         dsi->info.dsi_init_cmd,
4307                                                         dsi->info.n_init_cmd);
4308                         if (err < 0) {
4309                                 dev_err(&dc->ndev->dev,
4310                                 "dsi: error sending dsi init cmd\n");
4311                                 goto fail;
4312                         }
4313                 } else if (dsi->info.dsi_late_resume_cmd) {
4314                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4315                                                 dsi->info.dsi_late_resume_cmd,
4316                                                 dsi->info.n_late_resume_cmd);
4317                         if (err < 0) {
4318                                 dev_err(&dc->ndev->dev,
4319                                 "dsi: error sending late resume cmd\n");
4320                                 goto fail;
4321                         }
4322                 }
4323         } else {
4324                 err = tegra_dsi_init_hw(dc, dsi);
4325                 if (err < 0) {
4326                         dev_err(&dc->ndev->dev,
4327                                 "dsi: not able to init dsi hardware\n");
4328                         goto fail;
4329                 }
4330
4331                 if (dsi->ulpm) {
4332                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
4333                                 dev_err(&dc->ndev->dev,
4334                                         "DSI failed to enter ulpm\n");
4335                                 goto fail;
4336                         }
4337
4338                         tegra_dsi_pad_enable(dsi);
4339
4340                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4341                                 dev_err(&dc->ndev->dev,
4342                                         "DSI failed to exit ulpm\n");
4343                                 goto fail;
4344                         }
4345                 }
4346
4347                 /*
4348                  * Certain panels need dc frames be sent before
4349                  * waking panel.
4350                  */
4351                 if (dsi->info.panel_send_dc_frames)
4352                         tegra_dsi_send_dc_frames(dc, dsi, 2);
4353
4354                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
4355                 if (err < 0) {
4356                         dev_err(&dc->ndev->dev,
4357                                 "dsi: not able to set to lp mode\n");
4358                         goto fail;
4359                 }
4360
4361                 if (dsi->info.lp00_pre_panel_wakeup)
4362                         tegra_dsi_pad_disable(dsi);
4363
4364                 dsi->enabled = true;
4365         }
4366
4367         if (dsi->out_ops && dsi->out_ops->enable)
4368                 dsi->out_ops->enable(dsi);
4369 fail:
4370         tegra_dc_io_end(dc);
4371         mutex_unlock(&dsi->lock);
4372 }
4373
4374 static void tegra_dc_dsi_postpoweron(struct tegra_dc *dc)
4375 {
4376         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4377         int err = 0;
4378
4379         /*
4380          * Do not configure. Use bootloader configuration.
4381          * This avoids periods of blanking during boot.
4382          */
4383         if (dc->initialized)
4384                 return;
4385
4386         mutex_lock(&dsi->lock);
4387         tegra_dc_io_start(dc);
4388
4389         if (dsi->enabled) {
4390                 if (dsi->info.lp00_pre_panel_wakeup)
4391                         tegra_dsi_pad_enable(dsi);
4392
4393                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
4394                                                         dsi->info.n_init_cmd);
4395                 if (err < 0) {
4396                         dev_err(&dc->ndev->dev,
4397                                 "dsi: error while sending dsi init cmd\n");
4398                         goto fail;
4399                 }
4400
4401                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
4402                                 TEGRA_DSI_DRIVEN_BY_DC);
4403                 if (err < 0) {
4404                         dev_err(&dc->ndev->dev,
4405                                 "dsi: not able to set to hs mode\n");
4406                         goto fail;
4407                 }
4408
4409                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
4410                         tegra_dsi_start_dc_stream(dc, dsi);
4411
4412                 dsi->host_suspended = false;
4413         }
4414 fail:
4415         tegra_dc_io_end(dc);
4416         mutex_unlock(&dsi->lock);
4417 }
4418
4419 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
4420 {
4421         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4422
4423 #ifdef CONFIG_DEBUG_FS
4424         tegra_dc_dsi_debug_create(dsi);
4425 #endif
4426
4427         if (dsi->info.dsi2lvds_bridge_enable)
4428                 dsi->out_ops = &tegra_dsi2lvds_ops;
4429         else if (dsi->info.dsi2edp_bridge_enable)
4430                 dsi->out_ops = &tegra_dsi2edp_ops;
4431         else
4432                 dsi->out_ops = NULL;
4433
4434         if (dsi->out_ops && dsi->out_ops->init)
4435                 dsi->out_ops->init(dsi);
4436
4437         tegra_dsi_init_sw(dc, dsi);
4438 }
4439
4440 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
4441                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
4442 {
4443         u16 i;
4444         u16 len;
4445
4446         memcpy(dst, src, sizeof(*dst) * n_cmd);
4447
4448         for (i = 0; i < n_cmd; i++)
4449                 if (src[i].pdata) {
4450                         len = sizeof(*src[i].pdata) *
4451                                         src[i].sp_len_dly.data_len;
4452                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
4453                         if (!dst[i].pdata)
4454                                 goto free_cmd_pdata;
4455                         memcpy(dst[i].pdata, src[i].pdata, len);
4456                 }
4457
4458         return 0;
4459
4460 free_cmd_pdata:
4461         while (i--)
4462                 if (dst[i].pdata)
4463                         kfree(dst[i].pdata);
4464         return -ENOMEM;
4465 }
4466
4467 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
4468                                                 struct tegra_dsi_out *p_dsi)
4469 {
4470         struct tegra_dsi_cmd *p_init_cmd;
4471         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
4472         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
4473         struct tegra_dsi_cmd *p_suspend_cmd;
4474         int err = 0;
4475
4476         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
4477                 return -EINVAL;
4478
4479         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
4480                                 p_dsi->n_init_cmd, GFP_KERNEL);
4481         if (!p_init_cmd)
4482                 return -ENOMEM;
4483
4484         if (p_dsi->dsi_early_suspend_cmd) {
4485                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
4486                                         p_dsi->n_early_suspend_cmd,
4487                                         GFP_KERNEL);
4488                 if (!p_early_suspend_cmd) {
4489                         err = -ENOMEM;
4490                         goto err_free_init_cmd;
4491                 }
4492         }
4493
4494         if (p_dsi->dsi_late_resume_cmd) {
4495                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
4496                                         p_dsi->n_late_resume_cmd,
4497                                         GFP_KERNEL);
4498                 if (!p_late_resume_cmd) {
4499                         err = -ENOMEM;
4500                         goto err_free_p_early_suspend_cmd;
4501                 }
4502         }
4503
4504         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
4505                                 GFP_KERNEL);
4506         if (!p_suspend_cmd) {
4507                 err = -ENOMEM;
4508                 goto err_free_p_late_resume_cmd;
4509         }
4510
4511         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
4512
4513         /* Copy panel init cmd */
4514         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
4515                                                 p_init_cmd, p_dsi->n_init_cmd);
4516         if (err < 0)
4517                 goto err_free;
4518         dsi->info.dsi_init_cmd = p_init_cmd;
4519
4520         /* Copy panel early suspend cmd */
4521         if (p_dsi->dsi_early_suspend_cmd) {
4522                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
4523                                         p_early_suspend_cmd,
4524                                         p_dsi->n_early_suspend_cmd);
4525                 if (err < 0)
4526                         goto err_free;
4527                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
4528         }
4529
4530         /* Copy panel late resume cmd */
4531         if (p_dsi->dsi_late_resume_cmd) {
4532                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
4533                                                 p_late_resume_cmd,
4534                                                 p_dsi->n_late_resume_cmd);
4535                 if (err < 0)
4536                         goto err_free;
4537                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
4538         }
4539
4540         /* Copy panel suspend cmd */
4541         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
4542                                         p_dsi->n_suspend_cmd);
4543         if (err < 0)
4544                 goto err_free;
4545         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
4546
4547         if (!dsi->info.panel_reset_timeout_msec)
4548                 dsi->info.panel_reset_timeout_msec =
4549                                                 DEFAULT_PANEL_RESET_TIMEOUT;
4550         if (!dsi->info.panel_buffer_size_byte)
4551                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
4552
4553         if (!dsi->info.max_panel_freq_khz) {
4554                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
4555
4556                 if (dsi->info.video_burst_mode >
4557                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
4558                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
4559                                         "is not set for DSI burst mode.\n");
4560                         dsi->info.video_burst_mode =
4561                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
4562                 }
4563         }
4564
4565         if (!dsi->info.lp_cmd_mode_freq_khz)
4566                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
4567
4568         if (!dsi->info.lp_read_cmd_mode_freq_khz)
4569                 dsi->info.lp_read_cmd_mode_freq_khz =
4570                         dsi->info.lp_cmd_mode_freq_khz;
4571
4572         /* host mode is for testing only */
4573         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
4574         return 0;
4575
4576 err_free:
4577         kfree(p_suspend_cmd);
4578 err_free_p_late_resume_cmd:
4579         kfree(p_late_resume_cmd);
4580 err_free_p_early_suspend_cmd:
4581         kfree(p_early_suspend_cmd);
4582 err_free_init_cmd:
4583         kfree(p_init_cmd);
4584         return err;
4585 }
4586
4587 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
4588 {
4589         struct tegra_dc_dsi_data *dsi;
4590         struct resource *res;
4591         struct resource *base_res;
4592         struct resource dsi_res;
4593         void __iomem *base;
4594         struct clk *dc_clk = NULL;
4595         struct clk *dsi_clk;
4596         struct clk *dsi_fixed_clk = NULL;
4597         struct clk *dsi_lp_clk = NULL;
4598         struct tegra_dsi_out *dsi_pdata = NULL;
4599         int err = 0, i;
4600         int dsi_instance;
4601         char *ganged_reg_name[2] = {"ganged_dsia_regs", "ganged_dsib_regs"};
4602         char *dsi_clk_name[2] = {"dsia", "dsib"};
4603         char *dsi_lp_clk_name[2] = {"dsialp", "dsiblp"};
4604         struct device_node *np = dc->ndev->dev.of_node;
4605 #ifdef CONFIG_OF
4606         struct device_node *np_dsi =
4607                 of_find_node_by_path(DSI_NODE);
4608 #else
4609         struct device_node *np_dsi = NULL;
4610 #endif
4611         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4612         if (!dsi) {
4613                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
4614                 of_node_put(np_dsi);
4615                 return -ENOMEM;
4616         }
4617
4618         dsi->max_instances = dc->out->dsi->ganged_type ? MAX_DSI_INSTANCE : 1;
4619         dsi_instance = (int)dc->out->dsi->dsi_instance;
4620         for (i = 0; i < dsi->max_instances; i++) {
4621                 if (np) {
4622                         if (np_dsi && of_device_is_available(np_dsi)) {
4623                                 if (!dc->out->dsi->ganged_type)
4624                                         of_address_to_resource(np_dsi,
4625                                                 dsi_instance, &dsi_res);
4626                                 else /* ganged type */
4627                                         of_address_to_resource(np_dsi,
4628                                                 i, &dsi_res);
4629                                 res = &dsi_res;
4630                         } else {
4631                                 err = -EINVAL;
4632                                 goto err_free_dsi;
4633                         }
4634                 } else {
4635                         res = platform_get_resource_byname(dc->ndev,
4636                                         IORESOURCE_MEM,
4637                                         dc->out->dsi->ganged_type ?
4638                                         ganged_reg_name[i] : "dsi_regs");
4639                 }
4640                 if (!res) {
4641                         dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
4642                         err = -ENOENT;
4643                         goto err_free_dsi;
4644                 }
4645
4646                 base_res = request_mem_region(res->start, resource_size(res),
4647                                         dc->ndev->name);
4648                 if (!base_res) {
4649                         dev_err(&dc->ndev->dev,
4650                                 "dsi: request_mem_region failed\n");
4651                         err = -EBUSY;
4652                         goto err_free_dsi;
4653                 }
4654
4655                 base = ioremap(res->start, resource_size(res));
4656                 if (!base) {
4657                         dev_err(&dc->ndev->dev,
4658                                 "dsi: registers can't be mapped\n");
4659                         err = -EBUSY;
4660                         goto err_release_regs;
4661                 }
4662
4663                 dsi_pdata = dc->pdata->default_out->dsi;
4664                 if (!dsi_pdata) {
4665                         dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
4666                         goto err_release_regs;
4667                 }
4668
4669                 dsi_clk = dsi_pdata->dsi_instance ?
4670                                 clk_get(&dc->ndev->dev,
4671                                 dsi_clk_name[DSI_INSTANCE_1]) :
4672                                 clk_get(&dc->ndev->dev, dsi_clk_name[i]);
4673                 dsi_lp_clk = dsi_pdata->dsi_instance ?
4674                                 clk_get(&dc->ndev->dev,
4675                                 dsi_lp_clk_name[DSI_INSTANCE_1]) :
4676                                 clk_get(&dc->ndev->dev, dsi_lp_clk_name[i]);
4677
4678                 if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_lp_clk)) {
4679                         dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
4680                         err = -EBUSY;
4681                         goto err_dsi_clk_put;
4682                 }
4683
4684                 dsi->base[i] = base;
4685                 dsi->base_res[i] = base_res;
4686                 dsi->dsi_clk[i] = dsi_clk;
4687                 dsi->dsi_lp_clk[i] = dsi_lp_clk;
4688         }
4689
4690         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
4691
4692         if (IS_ERR_OR_NULL(dsi_fixed_clk)) {
4693                 dev_err(&dc->ndev->dev, "dsi: can't get fixed clock\n");
4694                 err = -EBUSY;
4695                 goto err_release_regs;
4696         }
4697
4698         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
4699         if (IS_ERR_OR_NULL(dc_clk)) {
4700                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
4701                         dev_name(&dc->ndev->dev));
4702                 err = -EBUSY;
4703                 goto err_dsi_fixed_clk_put;
4704         }
4705
4706         mutex_init(&dsi->lock);
4707         dsi->dc = dc;
4708         dsi->dc_clk = dc_clk;
4709         dsi->dsi_fixed_clk = dsi_fixed_clk;
4710
4711         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
4712         if (err < 0)
4713                 goto err_dc_clk_put;
4714
4715         tegra_dc_set_outdata(dc, dsi);
4716         __tegra_dc_dsi_init(dc);
4717
4718         /*
4719          * Enable DPD mode for DSI pads if required.
4720          */
4721         if (!dsi->info.ganged_type &&
4722                 (dsi->info.controller_vs >= DSI_VS_1)) {
4723                 if (dsi->info.dpd_dsi_pads & DSI_DPD_EN)
4724                         tegra_io_dpd_enable(&dsi_io);
4725                 if (dsi->info.dpd_dsi_pads & DSIB_DPD_EN)
4726                         tegra_io_dpd_enable(&dsib_io);
4727                 if (dsi->info.dpd_dsi_pads & DSIC_DPD_EN)
4728                         tegra_io_dpd_enable(&dsic_io);
4729                 if (dsi->info.dpd_dsi_pads & DSID_DPD_EN)
4730                         tegra_io_dpd_enable(&dsid_io);
4731         }
4732
4733         of_node_put(np_dsi);
4734         return 0;
4735
4736 err_dc_clk_put:
4737         clk_put(dc_clk);
4738 err_dsi_fixed_clk_put:
4739         clk_put(dsi_fixed_clk);
4740 err_dsi_clk_put:
4741         for (i = 0; i < dsi->max_instances; i++) {
4742                 clk_put(dsi->dsi_lp_clk[i]);
4743                 clk_put(dsi->dsi_clk[i]);
4744         }
4745 err_release_regs:
4746         for (i = 0; i < dsi->max_instances; i++)
4747                 release_resource(dsi->base_res[i]);
4748 err_free_dsi:
4749         kfree(dsi);
4750
4751         of_node_put(np_dsi);
4752         return err;
4753 }
4754
4755 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
4756 {
4757         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4758         u16 i;
4759         u32 val;
4760
4761         mutex_lock(&dsi->lock);
4762         tegra_dc_io_start(dc);
4763
4764         if (dsi->out_ops && dsi->out_ops->destroy)
4765                 dsi->out_ops->destroy(dsi);
4766
4767         /* free up the pdata */
4768         for (i = 0; i < dsi->info.n_init_cmd; i++) {
4769                 if (dsi->info.dsi_init_cmd[i].pdata)
4770                         kfree(dsi->info.dsi_init_cmd[i].pdata);
4771         }
4772         kfree(dsi->info.dsi_init_cmd);
4773
4774         /* Disable dc stream */
4775         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
4776                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4777
4778         /* Disable dsi phy clock */
4779         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
4780                 tegra_dsi_hs_clk_out_disable(dc, dsi);
4781
4782         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4783         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4784
4785         for (i = 0; i < dsi->max_instances; i++) {
4786                 iounmap(dsi->base[i]);
4787                 release_resource(dsi->base_res[i]);
4788         }
4789         clk_put(dsi->dc_clk);
4790         for (i = 0; i < dsi->max_instances; i++)
4791                 clk_put(dsi->dsi_clk[i]);
4792
4793         tegra_dc_io_end(dc);
4794         mutex_unlock(&dsi->lock);
4795         mutex_destroy(&dsi->lock);
4796         kfree(dsi);
4797 }
4798
4799 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
4800                                                         u32 settings)
4801 {
4802         struct clk *parent_clk = NULL;
4803         struct clk *base_clk = NULL;
4804         int i = 0;
4805
4806         for (i = 0; i < dsi->max_instances; i++) {
4807                 parent_clk = clk_get_parent(dsi->dsi_clk[i]);
4808                 base_clk = clk_get_parent(parent_clk);
4809
4810 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
4811                 if (dsi->info.dsi_instance)
4812                         tegra_clk_cfg_ex(base_clk,
4813                                         TEGRA_CLK_PLLD_CSI_OUT_ENB,
4814                                         settings);
4815                 else
4816                         tegra_clk_cfg_ex(base_clk,
4817                                         TEGRA_CLK_PLLD_DSI_OUT_ENB,
4818                                         settings);
4819 #else
4820                 tegra_clk_cfg_ex(base_clk,
4821                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
4822                                 settings);
4823 #endif
4824         }
4825 }
4826
4827 static int tegra_dsi_te_on_off(struct tegra_dc_dsi_data *dsi, bool flag)
4828 {
4829         int ret;
4830
4831         struct tegra_dsi_cmd te_enable[] = {
4832                 DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
4833                                 DSI_DCS_SET_TEARING_EFFECT_ON, 0x0),
4834                 DSI_DLY_MS(0),
4835         };
4836
4837         struct tegra_dsi_cmd te_disable[] = {
4838                 DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
4839                                 DSI_DCS_SET_TEARING_EFFECT_OFF, 0x0),
4840                 DSI_DLY_MS(0),
4841         };
4842
4843         if (flag)
4844                 ret = tegra_dsi_send_panel_cmd(dsi->dc, dsi, te_enable,
4845                                         ARRAY_SIZE(te_enable));
4846         else
4847                 ret = tegra_dsi_send_panel_cmd(dsi->dc, dsi, te_disable,
4848                                         ARRAY_SIZE(te_disable));
4849
4850         return ret;
4851 }
4852
4853 static int _tegra_dsi_host_suspend(struct tegra_dc *dc,
4854                                         struct tegra_dc_dsi_data *dsi,
4855                                         u32 suspend_aggr)
4856 {
4857         u32 val = 0;
4858         int err = 0;
4859
4860         switch (suspend_aggr) {
4861         case DSI_HOST_SUSPEND_LV2:
4862                 if (!dsi->ulpm) {
4863                         err = tegra_dsi_enter_ulpm(dsi);
4864                         if (err < 0) {
4865                                 dev_err(&dc->ndev->dev,
4866                                         "DSI failed to enter ulpm\n");
4867                                 goto fail;
4868                         }
4869                 }
4870
4871                 tegra_dsi_pad_disable(dsi);
4872
4873                 /* Suspend core-logic */
4874                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4875                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4876
4877                 /* disable HS logic */
4878                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
4879                 val |= DSI_PAD_PDVCLAMP(0x1);
4880                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
4881
4882                 /* fall through */
4883         case DSI_HOST_SUSPEND_LV1:
4884                 /* Disable dsi fast and slow clock */
4885                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
4886                 /* fall through */
4887         case DSI_HOST_SUSPEND_LV0:
4888                 /* Disable dsi source clock */
4889                 tegra_dsi_clk_disable(dsi);
4890                 break;
4891         case DSI_NO_SUSPEND:
4892                 break;
4893         default:
4894                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
4895                                                 "is not supported.\n");
4896         }
4897
4898         tegra_dvfs_set_rate(dc->clk, 0);
4899
4900         return 0;
4901 fail:
4902         return err;
4903 }
4904
4905 static int _tegra_dsi_host_resume(struct tegra_dc *dc,
4906                                         struct tegra_dc_dsi_data *dsi,
4907                                         u32 suspend_aggr)
4908 {
4909         u32 val;
4910         int err;
4911
4912         switch (dsi->info.suspend_aggr) {
4913         case DSI_HOST_SUSPEND_LV0:
4914                 tegra_dsi_clk_enable(dsi);
4915                 break;
4916         case DSI_HOST_SUSPEND_LV1:
4917                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4918                 tegra_dsi_clk_enable(dsi);
4919                 break;
4920         case DSI_HOST_SUSPEND_LV2:
4921                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4922                 tegra_dsi_clk_enable(dsi);
4923
4924                 /* enable HS logic */
4925                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
4926                 val &= ~DSI_PAD_PDVCLAMP(0x1);
4927                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
4928
4929                 tegra_dsi_writel(dsi,
4930                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
4931                         DSI_POWER_CONTROL);
4932
4933                 if (dsi->ulpm) {
4934                         err = tegra_dsi_enter_ulpm(dsi);
4935                         if (err < 0) {
4936                                 dev_err(&dc->ndev->dev,
4937                                         "DSI failed to enter ulpm\n");
4938                                 goto fail;
4939                         }
4940
4941                         tegra_dsi_pad_enable(dsi);
4942
4943                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4944                                 dev_err(&dc->ndev->dev,
4945                                         "DSI failed to exit ulpm\n");
4946                                 goto fail;
4947                         }
4948                 } else {
4949                         tegra_dsi_pad_enable(dsi);
4950                 }
4951                 break;
4952         case DSI_NO_SUSPEND:
4953                 break;
4954         default:
4955                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
4956                                                 "is not supported.\n");
4957         }
4958
4959         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
4960
4961         return 0;
4962 fail:
4963         return err;
4964 }
4965
4966 static int tegra_dsi_host_suspend_trylock(struct tegra_dc *dc,
4967                                         struct tegra_dc_dsi_data *dsi)
4968 {
4969         if (!mutex_trylock(&dc->one_shot_lock))
4970                 goto fail;
4971         if (!mutex_trylock(&dc->lp_lock))
4972                 goto unlock_one_shot_lock;
4973         if (!mutex_trylock(&dc->lock))
4974                 goto unlock_lp_lock;
4975         if (!mutex_trylock(&dsi->host_lock))
4976                 goto unlock_dc_lock;
4977
4978         return 1;
4979
4980 unlock_dc_lock:
4981         mutex_unlock(&dc->lock);
4982 unlock_lp_lock:
4983         mutex_unlock(&dc->lp_lock);
4984 unlock_one_shot_lock:
4985         mutex_unlock(&dc->one_shot_lock);
4986 fail:
4987         return 0;
4988 }
4989
4990 static void tegra_dsi_host_suspend_unlock(struct tegra_dc *dc,
4991                                         struct tegra_dc_dsi_data *dsi)
4992 {
4993         mutex_unlock(&dsi->host_lock);
4994         mutex_unlock(&dc->lock);
4995         mutex_unlock(&dc->lp_lock);
4996         mutex_unlock(&dc->one_shot_lock);
4997 }
4998
4999 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
5000 {
5001         int err = 0;
5002         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5003
5004         if (!dsi->enabled)
5005                 return -EINVAL;
5006
5007         while (!tegra_dsi_host_suspend_trylock(dc, dsi))
5008                 cond_resched();
5009
5010         if (dsi->host_suspended || atomic_read(&dsi->host_ref)) {
5011                 tegra_dsi_host_suspend_unlock(dc, dsi);
5012                 return 0;
5013         }
5014
5015         tegra_dc_io_start(dc);
5016
5017         dsi->host_suspended = true;
5018
5019         tegra_dsi_stop_dc_stream(dc, dsi);
5020
5021         tegra_dsi_te_on_off(dsi, false);
5022
5023         err = _tegra_dsi_host_suspend(dc, dsi, dsi->info.suspend_aggr);
5024         if (err < 0) {
5025                 dev_err(&dc->ndev->dev,
5026                         "DSI host suspend failed\n");
5027                 goto fail;
5028         }
5029
5030         /* Shutting down. Drop any reference to dc clk */
5031         while (tegra_is_clk_enabled(dc->clk))
5032                 tegra_dc_put(dc);
5033
5034         pm_runtime_put_sync(&dc->ndev->dev);
5035 fail:
5036         tegra_dc_io_end(dc);
5037         tegra_dsi_host_suspend_unlock(dc, dsi);
5038         return err;
5039 }
5040
5041 static bool tegra_dc_dsi_osidle(struct tegra_dc *dc)
5042 {
5043         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5044
5045         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
5046                 return dsi->host_suspended;
5047         else
5048                 return false;
5049 }
5050
5051 static void tegra_dsi_bl_off(struct backlight_device *bd)
5052 {
5053         if (!bd)
5054                 return;
5055
5056         bd->props.brightness = 0;
5057         backlight_update_status(bd);
5058 }
5059
5060 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
5061                                 struct tegra_dc_dsi_data *dsi)
5062 {
5063         int val = 0;
5064         int err = 0;
5065
5066         if (!dsi->enabled)
5067                 return 0;
5068
5069         cancel_delayed_work(&dsi->idle_work);
5070
5071         tegra_dsi_bl_off(get_backlight_device_by_name(dsi->info.bl_name));
5072
5073         /* Suspend DSI panel */
5074         err = tegra_dsi_send_panel_cmd(dc, dsi,
5075                         dsi->info.dsi_suspend_cmd,
5076                         dsi->info.n_suspend_cmd);
5077
5078         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
5079         if (err < 0) {
5080                 dev_err(&dc->ndev->dev,
5081                 "DSI failed to go to LP mode\n");
5082                 goto fail;
5083         }
5084
5085         /*
5086          * Certain panels need dc frames be sent after
5087          * putting panel to sleep.
5088          */
5089         if (dsi->info.panel_send_dc_frames)
5090                 tegra_dsi_send_dc_frames(dc, dsi, 2);
5091
5092         if (!dsi->ulpm) {
5093                 err = tegra_dsi_enter_ulpm(dsi);
5094                 if (err < 0) {
5095                         dev_err(&dc->ndev->dev,
5096                                 "DSI failed to enter ulpm\n");
5097                         goto fail;
5098                 }
5099         }
5100
5101         tegra_dsi_pad_disable(dsi);
5102
5103         /* Suspend core-logic */
5104         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
5105         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
5106
5107         /* Disable dsi fast and slow clock */
5108         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
5109
5110         /* Disable dsi source clock */
5111         tegra_dsi_clk_disable(dsi);
5112
5113         dsi->enabled = false;
5114         dsi->host_suspended = true;
5115
5116         return 0;
5117 fail:
5118         return err;
5119 }
5120
5121 static void tegra_dc_dsi_postpoweroff(struct tegra_dc *dc)
5122 {
5123         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5124
5125         /* Do not disable regulator when device is shutting down */
5126         if (!dsi->device_shutdown && !dsi->enabled && dsi->avdd_dsi_csi)
5127                 regulator_disable(dsi->avdd_dsi_csi);
5128 }
5129 static void tegra_dc_dsi_shutdown(struct tegra_dc *dc)
5130 {
5131         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5132
5133         dsi->device_shutdown = true;
5134 }
5135 static int tegra_dsi_host_resume(struct tegra_dc *dc)
5136 {
5137         int err = 0;
5138         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5139
5140         if (!dsi->enabled)
5141                 return -EINVAL;
5142
5143         cancel_delayed_work(&dsi->idle_work);
5144
5145         mutex_lock(&dsi->host_lock);
5146         if (!dsi->host_suspended) {
5147                 mutex_unlock(&dsi->host_lock);
5148                 return 0;
5149         }
5150
5151         tegra_dc_io_start(dc);
5152
5153         pm_runtime_get_sync(&dc->ndev->dev);
5154
5155         err = _tegra_dsi_host_resume(dc, dsi, dsi->info.suspend_aggr);
5156         if (err < 0) {
5157                 dev_err(&dc->ndev->dev,
5158                         "DSI host resume failed\n");
5159                 goto fail;
5160         }
5161
5162         tegra_dsi_te_on_off(dsi, true);
5163
5164         tegra_dsi_start_dc_stream(dc, dsi);
5165         dsi->host_suspended = false;
5166 fail:
5167         tegra_dc_io_end(dc);
5168         mutex_unlock(&dsi->host_lock);
5169         return err;
5170 }
5171
5172 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
5173 {
5174         int err;
5175         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5176
5177         if (dsi->host_suspended)
5178                 tegra_dsi_host_resume(dc);
5179
5180         sysedp_set_state(dsi->sysedpc, 0);
5181         mutex_lock(&dsi->lock);
5182         tegra_dc_io_start(dc);
5183
5184         if (!dsi->info.suspend_stop_stream_late)
5185                 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
5186                         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
5187
5188         if (dsi->out_ops && dsi->out_ops->disable)
5189                 dsi->out_ops->disable(dsi);
5190
5191         if (dsi->info.power_saving_suspend) {
5192                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
5193                         dev_err(&dc->ndev->dev,
5194                                 "DSI failed to enter deep sleep\n");
5195                         goto fail;
5196                 }
5197         } else {
5198                 if (dsi->info.dsi_early_suspend_cmd) {
5199                         err = tegra_dsi_send_panel_cmd(dc, dsi,
5200                                 dsi->info.dsi_early_suspend_cmd,
5201                                 dsi->info.n_early_suspend_cmd);
5202                         if (err < 0) {
5203                                 dev_err(&dc->ndev->dev,
5204                                 "dsi: Error sending early suspend cmd\n");
5205                                 goto fail;
5206                         }
5207                 }
5208
5209                 if (!dsi->ulpm) {
5210                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
5211                                 dev_err(&dc->ndev->dev,
5212                                         "DSI failed to enter ulpm\n");
5213                                 goto fail;
5214                         }
5215                 }
5216         }
5217
5218         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
5219                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
5220
5221 fail:
5222         mutex_unlock(&dsi->lock);
5223         tegra_dc_io_end(dc);
5224 }
5225
5226 #ifdef CONFIG_PM
5227 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
5228 {
5229         struct tegra_dc_dsi_data *dsi;
5230
5231         dsi = tegra_dc_get_outdata(dc);
5232
5233         if (!dsi->enabled)
5234                 return;
5235
5236         if (dsi->host_suspended)
5237                 tegra_dsi_host_resume(dc);
5238
5239         tegra_dc_io_start(dc);
5240         mutex_lock(&dsi->lock);
5241
5242         if (dsi->out_ops && dsi->out_ops->suspend)
5243                 dsi->out_ops->suspend(dsi);
5244
5245         if (!dsi->info.power_saving_suspend) {
5246                 if (dsi->ulpm) {
5247                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
5248                                 dev_err(&dc->ndev->dev,
5249                                         "DSI failed to exit ulpm");
5250                                 goto fail;
5251                         }
5252                 }
5253
5254                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
5255                         dev_err(&dc->ndev->dev,
5256                                 "DSI failed to enter deep sleep\n");
5257                         goto fail;
5258                 }
5259         }
5260 fail:
5261         mutex_unlock(&dsi->lock);
5262         tegra_dc_io_end(dc);
5263 }
5264
5265 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
5266 {
5267         struct tegra_dc_dsi_data *dsi;
5268
5269         dsi = tegra_dc_get_outdata(dc);
5270
5271         /* No dsi config required since tegra_dc_dsi_enable
5272          * will reconfigure the controller from scratch
5273          */
5274
5275          if (dsi->out_ops && dsi->out_ops->resume)
5276                 dsi->out_ops->resume(dsi);
5277 }
5278 #endif
5279
5280 static int tegra_dc_dsi_init(struct tegra_dc *dc)
5281 {
5282         struct tegra_dc_dsi_data *dsi;
5283         char sysedp_name[50];
5284         int err = 0;
5285
5286         err = _tegra_dc_dsi_init(dc);
5287         if (err < 0) {
5288                 dev_err(&dc->ndev->dev,
5289                         "dsi: Instance A init failed\n");
5290                 goto err;
5291         }
5292
5293         dsi = tegra_dc_get_outdata(dc);
5294
5295         dsi->avdd_dsi_csi =  regulator_get(&dc->ndev->dev, "avdd_dsi_csi");
5296         if (IS_ERR_OR_NULL(dsi->avdd_dsi_csi)) {
5297                 dev_err(&dc->ndev->dev, "dsi: avdd_dsi_csi reg get failed\n");
5298                 err = -ENODEV;
5299                 goto err_reg;
5300         }
5301
5302         dsi->mipi_cal = tegra_mipi_cal_init_sw(dc);
5303         if (IS_ERR(dsi->mipi_cal)) {
5304                 dev_err(&dc->ndev->dev, "dsi: mipi_cal sw init failed\n");
5305                 err = PTR_ERR(dsi->mipi_cal);
5306                 goto err_mipi;
5307         }
5308
5309         sprintf(sysedp_name, "dsi_%d", dsi->dc->ndev->id);
5310         dsi->sysedpc = sysedp_create_consumer(sysedp_name, sysedp_name);
5311
5312         return 0;
5313 err_mipi:
5314         if (dsi->avdd_dsi_csi)
5315                 regulator_put(dsi->avdd_dsi_csi);
5316 err_reg:
5317         _tegra_dc_dsi_destroy(dc);
5318         tegra_dc_set_outdata(dc, NULL);
5319 err:
5320         return err;
5321 }
5322
5323 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
5324 {
5325         struct regulator *avdd_dsi_csi;
5326         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5327
5328         avdd_dsi_csi = dsi->avdd_dsi_csi;
5329
5330         _tegra_dc_dsi_destroy(dc);
5331         regulator_put(avdd_dsi_csi);
5332         tegra_mipi_cal_destroy(dc);
5333 }
5334
5335 static long tegra_dc_dsi_setup_clk(struct tegra_dc *dc, struct clk *clk)
5336 {
5337         unsigned long rate;
5338         struct clk *parent_clk;
5339         struct clk *base_clk;
5340         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5341
5342
5343         /* divide by 1000 to avoid overflow */
5344         dc->mode.pclk /= 1000;
5345         rate = (dc->mode.pclk * dc->shift_clk_div.mul * 2)
5346                                 / dc->shift_clk_div.div;
5347         rate *= 1000;
5348         dc->mode.pclk *= 1000;
5349
5350         if (dc->initialized)
5351                 goto skip_setup;
5352
5353         if (clk == dc->clk) {
5354                 parent_clk = clk_get_sys(NULL,
5355                                 dc->out->parent_clk ? : "pll_d_out0");
5356                 base_clk = clk_get_parent(parent_clk);
5357         } else {
5358                 if (dc->pdata->default_out->dsi->dsi_instance) {
5359                         parent_clk = clk_get_sys(NULL,
5360                                 dc->out->parent_clk ? : "pll_d2");
5361                         base_clk = clk_get_parent(parent_clk);
5362                 } else {
5363                         parent_clk = clk_get_sys(NULL,
5364                                 dc->out->parent_clk ? : "pll_d_out0");
5365                         base_clk = clk_get_parent(parent_clk);
5366                 }
5367         }
5368         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
5369
5370         if (rate != clk_get_rate(base_clk))
5371                 clk_set_rate(base_clk, rate);
5372
5373         if (clk_get_parent(clk) != parent_clk)
5374                 clk_set_parent(clk, parent_clk);
5375
5376 skip_setup:
5377         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
5378
5379         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
5380 }
5381
5382 static void tegra_dc_dsi_vrr_enable(struct tegra_dc *dc, bool enable)
5383 {
5384         struct tegra_vrr *vrr  = dc->out->vrr;
5385
5386         if (vrr)
5387                 vrr->enable = enable;
5388 }
5389
5390 void tegra_dsi_vrr_update_monspecs(struct tegra_dc *dc,
5391         struct list_head *head)
5392 {
5393         struct tegra_vrr *vrr;
5394         struct list_head *pos;
5395         struct fb_modelist *modelist;
5396         struct fb_videomode *m;
5397         struct fb_videomode m_vrr;
5398
5399         if (!head || !head->next)
5400                 return;
5401
5402         vrr = dc->out->vrr;
5403
5404         if (!vrr || !vrr->capability)
5405                 return;
5406
5407         /* Check whether VRR modes were already added */
5408         list_for_each(pos, head) {
5409                 modelist = list_entry(pos, struct fb_modelist, list);
5410                 m = &modelist->mode;
5411
5412                 if (m->vmode & FB_VMODE_VRR)
5413                         return;
5414         }
5415
5416         /* For DSI VRR, the runtime mode (as opposed to initialization
5417          * mode) is the first mode in the list. We mark that first mode
5418          * as VRR-compatible by adding FB_VMODE_VRR to a duplicated instance
5419          * of this mode. */
5420         modelist = list_entry(head->next, struct fb_modelist, list);
5421         m = &modelist->mode;
5422         m_vrr = *m;
5423         m_vrr.vmode |= FB_VMODE_VRR;
5424         fb_add_videomode(&m_vrr, head);
5425 }
5426
5427 static void tegra_dc_dsi_modeset_notifier(struct tegra_dc *dc)
5428 {
5429         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5430
5431         if (dsi->info.ganged_type)
5432                 tegra_dsi_pix_correction(dc, dsi);
5433 }
5434
5435 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
5436         .init = tegra_dc_dsi_init,
5437         .destroy = tegra_dc_dsi_destroy,
5438         .enable = tegra_dc_dsi_enable,
5439         .postpoweron = tegra_dc_dsi_postpoweron,
5440         .disable = tegra_dc_dsi_disable,
5441         .postpoweroff = tegra_dc_dsi_postpoweroff,
5442         .hold = tegra_dc_dsi_hold_host,
5443         .release = tegra_dc_dsi_release_host,
5444         .shutdown = tegra_dc_dsi_shutdown,
5445 #ifdef CONFIG_PM
5446         .suspend = tegra_dc_dsi_suspend,
5447         .resume = tegra_dc_dsi_resume,
5448 #endif
5449         .setup_clk = tegra_dc_dsi_setup_clk,
5450         .osidle = tegra_dc_dsi_osidle,
5451         .vrr_enable = tegra_dc_dsi_vrr_enable,
5452         .vrr_update_monspecs = tegra_dsi_vrr_update_monspecs,
5453         .modeset_notifier = tegra_dc_dsi_modeset_notifier,
5454 };