2 * drivers/video/tegra/dc/dc_priv.h
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Erik Gilling <konkers@android.com>
7 * Copyright (c) 2010-2016, NVIDIA CORPORATION, All rights reserved.
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #ifndef __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_DEFS_H
21 #define __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_DEFS_H
23 #include <linux/mutex.h>
24 #include <linux/wait.h>
26 #include <linux/clk.h>
27 #include <linux/completion.h>
28 #include <linux/switch.h>
29 #include <linux/nvhost.h>
30 #include <linux/types.h>
31 #include <linux/clk/tegra.h>
32 #include <linux/tegra-soc.h>
36 #include <mach/tegra_dc_ext.h>
37 #include <linux/platform/tegra/isomgr.h>
41 #define NEED_UPDATE_EMC_ON_EVERY_FRAME (windows_idle_detection_time == 0)
43 /* 28 bit offset for window clip number */
44 #define CURSOR_CLIP_SHIFT_BITS(win) (win << 28)
45 #define CURSOR_CLIP_GET_WINDOW(reg) ((reg >> 28) & 3)
47 #define BLANK_ALL (~0)
49 static inline u32 ALL_UF_INT(void)
51 if (tegra_platform_is_fpga())
53 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || \
54 defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
55 defined(CONFIG_ARCH_TEGRA_11x_SOC)
56 return WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
57 #elif defined(CONFIG_TEGRA_NVDISPLAY)
60 return WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | HC_UF_INT |
61 WIN_D_UF_INT | WIN_T_UF_INT;
65 #if defined(CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
66 #define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
68 #define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * 2)
73 struct tegra_dc_blend {
74 unsigned z[DC_N_WINDOWS];
75 unsigned flags[DC_N_WINDOWS];
76 u8 alpha[DC_N_WINDOWS];
79 struct tegra_dc_out_ops {
80 /* initialize output. dc clocks are not on at this point */
81 int (*init)(struct tegra_dc *dc);
82 /* destroy output. dc clocks are not on at this point */
83 void (*destroy)(struct tegra_dc *dc);
84 /* shutdown output. dc clocks are on at this point */
85 void (*shutdown)(struct tegra_dc *dc);
86 /* detect connected display. can sleep.*/
87 bool (*detect)(struct tegra_dc *dc);
88 /* enable output. dc clocks are on at this point */
89 void (*enable)(struct tegra_dc *dc);
90 /* enable dc client. Panel is enable at this point */
91 void (*postpoweron)(struct tegra_dc *dc);
92 /* disable output. dc clocks are on at this point */
93 void (*disable)(struct tegra_dc *dc);
94 /* dc client is disabled. dc clocks are on at this point */
95 void (*postpoweroff) (struct tegra_dc *dc);
96 /* hold output. keeps dc clocks on. */
97 void (*hold)(struct tegra_dc *dc);
98 /* release output. dc clocks may turn off after this. */
99 void (*release)(struct tegra_dc *dc);
100 /* idle routine of output. dc clocks may turn off after this. */
101 void (*idle)(struct tegra_dc *dc);
102 /* suspend output. dc clocks are on at this point */
103 void (*suspend)(struct tegra_dc *dc);
104 /* resume output. dc clocks are on at this point */
105 void (*resume)(struct tegra_dc *dc);
106 /* mode filter. to provide a list of supported modes*/
107 bool (*mode_filter)(const struct tegra_dc *dc,
108 struct fb_videomode *mode);
109 /* setup pixel clock and parent clock programming */
110 long (*setup_clk)(struct tegra_dc *dc, struct clk *clk);
112 * return true if display client is suspended during OSidle.
113 * If true, dc will not wait on any display client event
116 bool (*osidle)(struct tegra_dc *dc);
117 /* callback before new mode is programmed.
118 * dc clocks are on at this point */
119 void (*modeset_notifier)(struct tegra_dc *dc);
120 /* Set up interface and sink for partial frame update.
122 int (*partial_update) (struct tegra_dc *dc, unsigned int *xoff,
123 unsigned int *yoff, unsigned int *width, unsigned int *height);
124 /* refcounted enable of pads and clocks before performing DDC/I2C. */
125 int (*ddc_enable)(struct tegra_dc *dc);
126 /* refcounted disable of pads and clocks after performing DDC/I2C. */
127 int (*ddc_disable)(struct tegra_dc *dc);
128 /* Enable/disable VRR */
129 void (*vrr_enable)(struct tegra_dc *dc, bool enable);
130 /* Mark VRR-compatible modes in fb_info->info->modelist */
131 void (*vrr_update_monspecs)(struct tegra_dc *dc,
132 struct list_head *head);
133 /* return if hpd asserted or deasserted */
134 bool (*hpd_state) (struct tegra_dc *dc);
135 /* Configure controller to receive hotplug events */
136 int (*hotplug_init)(struct tegra_dc *dc);
137 int (*set_hdr)(struct tegra_dc *dc);
140 struct tegra_dc_shift_clk_div {
141 unsigned long mul; /* numerator */
142 unsigned long div; /* denominator */
145 struct tegra_dc_nvsr_data;
147 enum tegra_dc_cursor_size {
148 TEGRA_DC_CURSOR_SIZE_32X32 = 0,
149 TEGRA_DC_CURSOR_SIZE_64X64 = 1,
150 TEGRA_DC_CURSOR_SIZE_128X128 = 2,
151 TEGRA_DC_CURSOR_SIZE_256X256 = 3,
154 enum tegra_dc_cursor_format {
155 TEGRA_DC_CURSOR_FORMAT_2BIT_LEGACY = 0,
156 TEGRA_DC_CURSOR_FORMAT_RGBA_NON_PREMULT_ALPHA = 1,
157 TEGRA_DC_CURSOR_FORMAT_RGBA_PREMULT_ALPHA = 3,
158 TEGRA_DC_CURSOR_FORMAT_RGBA_XOR = 4,
162 struct platform_device *ndev;
163 struct tegra_dc_platform_data *pdata;
165 struct resource *base_res;
170 #ifdef CONFIG_TEGRA_ISOMGR
171 tegra_isomgr_handle isomgr_handle;
175 struct clk *emc_la_clk;
176 long bw_kbps; /* bandwidth in KBps */
178 struct tegra_dc_shift_clk_div shift_clk_div;
188 /* Some of the setup code could reset display even if
189 * DC is already by bootloader. This one-time mark is
190 * used to suppress such code blocks during system boot,
191 * a.k.a the call stack above tegra_dc_probe().
195 struct tegra_dc_out *out;
196 struct tegra_dc_out_ops *out_ops;
199 struct tegra_dc_mode mode;
202 #ifndef CONFIG_TEGRA_NVDISPLAY
203 struct tegra_dc_win windows[DC_N_WINDOWS];
205 struct tegra_dc_win shadow_windows[DC_N_WINDOWS];
207 struct tegra_dc_blend blend;
209 struct tegra_dc_hdr hdr;
211 #if defined(CONFIG_TEGRA_DC_CMU)
212 struct tegra_dc_cmu cmu;
213 #elif defined(CONFIG_TEGRA_DC_CMU_V2)
214 struct tegra_dc_lut cmu;
217 #if defined(CONFIG_TEGRA_DC_CMU) || defined(CONFIG_TEGRA_DC_CMU_V2)
218 struct tegra_dc_cmu cmu_shadow;
220 /* Is CMU set by bootloader */
222 bool cmu_shadow_dirty;
223 bool cmu_shadow_force_update;
226 wait_queue_head_t wq;
227 wait_queue_head_t timestamp_wq;
229 struct mutex lp_lock;
231 struct mutex one_shot_lock;
233 struct resource *fb_mem;
234 struct tegra_fb_info *fb;
235 #ifdef CONFIG_ADF_TEGRA
236 struct tegra_adf_info *adf;
241 unsigned long int valid_windows;
243 unsigned long underflow_mask;
244 struct work_struct reset_work;
247 struct switch_dev modeset_switch;
250 struct completion frame_end_complete;
251 struct completion crc_complete;
254 struct work_struct vblank_work;
255 long vblank_ref_count;
256 struct work_struct frame_end_work;
257 struct work_struct vpulse2_work;
258 long vpulse2_ref_count;
268 u64 underflow_frames;
271 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
272 struct tegra_dc_ext *ext;
275 struct tegra_dc_feature *feature;
278 #ifdef CONFIG_DEBUG_FS
279 struct dentry *debugdir;
281 struct tegra_dc_lut fb_lut;
282 struct delayed_work underflow_work;
283 u32 one_shot_delay_ms;
284 struct delayed_work one_shot_work;
285 s64 frame_end_timestamp;
286 atomic_t frame_end_ref;
294 struct tegra_dc_win tmp_wins[DC_N_WINDOWS];
296 struct tegra_edid *edid;
298 struct tegra_dc_nvsr_data *nvsr;
300 bool disp_active_dirty;
302 struct tegra_dc_cursor {
305 dma_addr_t phys_addr;
311 enum tegra_dc_cursor_size size;
312 enum tegra_dc_cursor_format format;
316 bool switchdev_registered;
318 struct notifier_block slgc_notifier;
321 bool hdr_cache_dirty;