2 * arch/arm/boot/dts/tegra124-vcm30_t124.dtsi
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include "tegra124.dtsi"
22 #include <tegra124-platforms/tegra124-vcm30t124-fixed-reg.dtsi>
29 nvidia,tegra-hypervisor-mode;
33 nvidia,clock-always-on;
36 /* vcm30t124 mcm doesn't need hda device */
38 compatible = "nvidia,tegra30-hda";
43 * vcm30t124 mcm dtsi assumes all uart ports as high speed
45 * The board file has to update the compatible property to
46 * "nvidia,tegra20-uart" for debug uart port
49 compatible = "nvidia,tegra114-hsuart";
54 compatible = "nvidia,tegra114-hsuart";
59 compatible = "nvidia,tegra114-hsuart";
64 compatible = "nvidia,tegra114-hsuart";
71 compatible = "spidev";
73 spi-max-frequency = <25000000>;
84 compatible = "spidev";
86 spi-max-frequency = <25000000>;
93 compatible = "spidev";
95 spi-max-frequency = <25000000>;
102 compatible = "spidev";
104 spi-max-frequency = <25000000>;
110 nvidia,gpio_ss1_sata = <0>;
113 * BIT0 - BIT7 : SS ports
114 * BIT8 - BIT15 : USB2 UTMI ports
115 * BIT16 - BIT23 : HSIC ports
116 * BIT24 - BIT31 : ULPI ports
117 * XXXX XXXP XXXX XXHH XXXX XUUU XXXX XXSS
119 nvidia,portmap = <0x402>; /* SSP1, USB2P2 */
120 /* XXXX .. XSSS XSSS */
121 nvidia,ss_portmap = <0x20>; /* SSP1 on USB2P2 */
124 * BIT 2 (0/1): PCIE-0/SSP0
125 * BIT 1 (0/1): PCIE-1/SSP1
126 * BIT 0 (0/1): SATA/SSP1
128 nvidia,lane_owner = <0x2>; /* PCIE-0, SSP1 and SATA */
129 nvidia,ulpicap = <0>; /* No ulpi support */
133 nvidia,port0_status = <1>;
134 nvidia,port1_status = <1>;
139 nvidia,enable-sata-port;
146 ddr-trim-delay = <0x4>;
151 ddr-clk-limit = <51000000>;
152 max-clk-limit = <200000000>;
153 pll_source = "pll_m", "pll_p";
154 vmmc-supply = <&vmmc_dummy>;
161 ddr-trim-delay = <0x3>;
165 ddr-clk-limit = <30000000>;
166 max-clk-limit = <51000000>;
167 pll_source = "pll_m", "pll_p";
168 vmmc-supply = <&vmmc_dummy>;
173 cd-gpios = <&gpio 133 0>;
174 wp-gpios = <&gpio 132 0>;
180 max-clk-limit = <204000000>;
181 pll_source = "pll_m", "pll_p";
182 vmmc-supply = <&vmmc_dummy>;
187 nvidia,timing-default = <0x30300273>, <0x00030302>;
188 nvidia,timing-read = <0x30300273>, <0x00030302>;
189 nvidia,nor-mux-mode = <0x0>;
190 nvidia,nor-read-mode = <0x1>;
191 nvidia,nor-page-length = <0x2>;
192 nvidia,nor-ready-active = <0x0>;
193 nvidia,flash-map-name = "cfi_probe";
194 nvidia,flash-width = <0x2>;
195 nvidia,num-chips = <0x1>;
196 use-advanced-sector-protection;
200 nvidia,num_cs_gpio = <0x0>;
201 nvidia,phy_addr = <0x0 0x48000000>;
202 nvidia,phy_size = <0x04000000>;