2 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
4 * Derived from the PCAN project file driver/src/pcan_pci.c:
6 * Copyright (C) 2001-2006 PEAK System-Technik GmbH
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the version 2 of the GNU General Public License
10 * as published by the Free Software Foundation
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software Foundation,
19 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 #include <linux/kernel.h>
23 #include <linux/version.h>
24 #include <linux/module.h>
25 #include <linux/interrupt.h>
26 #include <linux/netdevice.h>
27 #include <linux/delay.h>
28 #include <linux/pci.h>
29 #include <socketcan/can.h>
30 #include <socketcan/can/dev.h>
31 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)
39 #define DRV_NAME "peak_pci"
41 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
42 #error This driver does not support Kernel versions < 2.6.23
45 MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
46 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCI cards");
47 MODULE_SUPPORTED_DEVICE("PEAK PCAN PCI CAN card");
48 MODULE_LICENSE("GPL v2");
52 struct pci_dev *pci_dev;
53 struct net_device *slave_dev;
54 volatile void __iomem *conf_addr;
57 #define PEAK_PCI_SINGLE 0 /* single channel device */
58 #define PEAK_PCI_MASTER 1 /* multi channel master device */
59 #define PEAK_PCI_SLAVE 2 /* multi channel slave device */
61 #define PEAK_PCI_CAN_CLOCK (16000000 / 2)
63 #define PEAK_PCI_CDR_SINGLE (CDR_CBP | CDR_CLKOUT_MASK | CDR_CLK_OFF)
64 #define PEAK_PCI_CDR_MASTER (CDR_CBP | CDR_CLKOUT_MASK)
66 #define PEAK_PCI_OCR OCR_TX0_PUSHPULL
69 * Important PITA registers
71 #define PITA_ICR 0x00 /* interrupt control register */
72 #define PITA_GPIOICR 0x18 /* general purpose I/O interface
74 #define PITA_MISC 0x1C /* miscellanoes register */
76 #define PCI_CONFIG_PORT_SIZE 0x1000 /* size of the config io-memory */
77 #define PCI_PORT_SIZE 0x0400 /* size of a channel io-memory */
79 #define PEAK_PCI_VENDOR_ID 0x001C /* the PCI device and vendor IDs */
80 #define PEAK_PCI_DEVICE_ID 0x0001
82 static struct pci_device_id peak_pci_tbl[] = {
83 {PEAK_PCI_VENDOR_ID, PEAK_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
87 MODULE_DEVICE_TABLE(pci, peak_pci_tbl);
89 static u8 peak_pci_read_reg(const struct sja1000_priv *priv, int port)
91 return readb(priv->reg_base + (port << 2));
94 static void peak_pci_write_reg(const struct sja1000_priv *priv,
97 writeb(val, priv->reg_base + (port << 2));
100 static void peak_pci_post_irq(const struct sja1000_priv *priv)
102 struct peak_pci *board = priv->priv;
105 /* Select and clear in Pita stored interrupt */
106 icr_low = readw(board->conf_addr + PITA_ICR);
107 if (board->channel == PEAK_PCI_SLAVE) {
108 if (icr_low & 0x0001)
109 writew(0x0001, board->conf_addr + PITA_ICR);
111 if (icr_low & 0x0002)
112 writew(0x0002, board->conf_addr + PITA_ICR);
116 static void peak_pci_del_chan(struct net_device *dev, int init_step)
118 struct sja1000_priv *priv = netdev_priv(dev);
119 struct peak_pci *board;
124 priv = netdev_priv(dev);
132 case 0: /* Full cleanup */
133 printk(KERN_INFO "Removing %s device %s\n",
134 DRV_NAME, dev->name);
135 unregister_sja1000dev(dev);
137 icr_high = readw(board->conf_addr + PITA_ICR + 2);
138 if (board->channel == PEAK_PCI_SLAVE)
142 writew(icr_high, board->conf_addr + PITA_ICR + 2);
144 iounmap(priv->reg_base);
146 if (board->channel != PEAK_PCI_SLAVE)
147 iounmap((void *)board->conf_addr);
149 free_sja1000dev(dev);
155 static int peak_pci_add_chan(struct pci_dev *pdev, int channel,
156 struct net_device **master_dev)
158 struct net_device *dev;
159 struct sja1000_priv *priv;
160 struct peak_pci *board;
165 dev = alloc_sja1000dev(sizeof(struct peak_pci));
170 priv = netdev_priv(dev);
173 board->pci_dev = pdev;
174 board->channel = channel;
176 if (channel != PEAK_PCI_SLAVE) {
178 addr = pci_resource_start(pdev, 0);
179 board->conf_addr = ioremap(addr, PCI_CONFIG_PORT_SIZE);
180 if (board->conf_addr == 0) {
186 /* Set GPIO control register */
187 writew(0x0005, board->conf_addr + PITA_GPIOICR + 2);
189 /* Enable single or dual channel */
190 if (channel == PEAK_PCI_MASTER)
191 writeb(0x00, board->conf_addr + PITA_GPIOICR);
193 writeb(0x04, board->conf_addr + PITA_GPIOICR);
195 writeb(0x05, board->conf_addr + PITA_MISC + 3);
197 /* Leave parport mux mode */
198 writeb(0x04, board->conf_addr + PITA_MISC + 3);
200 struct sja1000_priv *master_priv = netdev_priv(*master_dev);
201 struct peak_pci *master_board = master_priv->priv;
202 master_board->slave_dev = dev;
203 board->conf_addr = master_board->conf_addr;
206 addr = pci_resource_start(pdev, 1);
207 if (channel == PEAK_PCI_SLAVE)
208 addr += PCI_PORT_SIZE;
210 priv->reg_base = ioremap(addr, PCI_PORT_SIZE);
211 if (priv->reg_base == 0) {
217 priv->read_reg = peak_pci_read_reg;
218 priv->write_reg = peak_pci_write_reg;
219 priv->post_irq = peak_pci_post_irq;
221 priv->can.clock.freq = PEAK_PCI_CAN_CLOCK;
223 priv->ocr = PEAK_PCI_OCR;
225 if (channel == PEAK_PCI_MASTER)
226 priv->cdr = PEAK_PCI_CDR_MASTER;
228 priv->cdr = PEAK_PCI_CDR_SINGLE;
230 /* Setup interrupt handling */
231 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
232 priv->irq_flags = SA_SHIRQ;
234 priv->irq_flags = IRQF_SHARED;
236 dev->irq = pdev->irq;
237 icr_high = readw(board->conf_addr + PITA_ICR + 2);
238 if (channel == PEAK_PCI_SLAVE)
242 writew(icr_high, board->conf_addr + PITA_ICR + 2);
245 SET_NETDEV_DEV(dev, &pdev->dev);
247 /* Register SJA1000 device */
248 err = register_sja1000dev(dev);
250 printk(KERN_ERR "Registering %s device failed (err=%d)\n",
255 if (channel != PEAK_PCI_SLAVE)
258 printk(KERN_INFO "%s: %s at reg_base=0x%p conf_addr=%p irq=%d\n",
259 DRV_NAME, dev->name, priv->reg_base, board->conf_addr, dev->irq);
264 peak_pci_del_chan(dev, init_step);
268 static int __devinit peak_pci_init_one(struct pci_dev *pdev,
269 const struct pci_device_id *ent)
273 struct net_device *master_dev = NULL;
275 printk(KERN_INFO "%s: initializing device %04x:%04x\n",
276 DRV_NAME, pdev->vendor, pdev->device);
278 err = pci_enable_device(pdev);
282 err = pci_request_regions(pdev, DRV_NAME);
286 err = pci_read_config_word(pdev, 0x2e, &sub_sys_id);
288 goto failure_cleanup;
290 err = pci_write_config_word(pdev, 0x44, 0);
292 goto failure_cleanup;
294 if (sub_sys_id > 3) {
295 err = peak_pci_add_chan(pdev,
296 PEAK_PCI_MASTER, &master_dev);
298 goto failure_cleanup;
300 err = peak_pci_add_chan(pdev,
301 PEAK_PCI_SLAVE, &master_dev);
303 goto failure_cleanup;
305 err = peak_pci_add_chan(pdev, PEAK_PCI_SINGLE,
308 goto failure_cleanup;
311 pci_set_drvdata(pdev, master_dev);
316 peak_pci_del_chan(master_dev, 0);
318 pci_release_regions(pdev);
325 static void __devexit peak_pci_remove_one(struct pci_dev *pdev)
327 struct net_device *dev = pci_get_drvdata(pdev);
328 struct sja1000_priv *priv = netdev_priv(dev);
329 struct peak_pci *board = priv->priv;
331 if (board->slave_dev)
332 peak_pci_del_chan(board->slave_dev, 0);
333 peak_pci_del_chan(dev, 0);
335 pci_release_regions(pdev);
336 pci_disable_device(pdev);
337 pci_set_drvdata(pdev, NULL);
340 static struct pci_driver peak_pci_driver = {
342 .id_table = peak_pci_tbl,
343 .probe = peak_pci_init_one,
344 .remove = __devexit_p(peak_pci_remove_one),
347 static int __init peak_pci_init(void)
349 return pci_register_driver(&peak_pci_driver);
352 static void __exit peak_pci_exit(void)
354 pci_unregister_driver(&peak_pci_driver);
357 module_init(peak_pci_init);
358 module_exit(peak_pci_exit);