1 Index: rtems-051009/c/src/lib/libbsp/m68k/mo376/include/bsp.h
2 ===================================================================
3 --- rtems.orig/c/src/lib/libbsp/m68k/mo376/include/bsp.h
4 +++ rtems/c/src/lib/libbsp/m68k/mo376/include/bsp.h
8 - * This include file contains all mrm board IO definitions.
9 + * This include file contains all mo376 board IO definitions.
11 * COPYRIGHT (c) 1989-1999.
12 * On-Line Applications Research Corporation (OAR).
13 @@ -41,6 +41,30 @@ extern "C" {
14 /* #define CONFIGURE_INTERRUPT_STACK_MEMORY (TBD * 1024) */
17 + * Network driver configuration
19 +struct rtems_bsdnet_ifconfig;
20 +extern int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching);
21 +#define RTEMS_BSP_NETWORK_DRIVER_NAME "cs8900"
22 +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach
24 +/* CS8900 ethernet interface definitions */
26 +#define CS8900_DEVICES (1)
27 +#define CS8900_IO_BASE (0x0300)
28 +#define CS8900_MEMORY_BASE (0x1000)
29 +#define CS8900_DATA_BUS_SWAPPED
30 +#define CS8900_IO_MODE
31 +#define CS8900_RX_QUEUE_SIZE (50)
33 +#define ETHERNET_BASE (0xf8a000)
34 +#define ETHERNET_IRQ_LEVEL (2)
35 +#define ETHERNET_IRQ_PRIORITY (2)
36 +#define ETHERNET_IRQ_VECTOR (26)
37 +/* #define ETHERNET_IRQ_VECTOR (AUTOVEC_VECTOR + ETHERNET_IRQ_LEVEL) */
38 +#define ETHERNET_MAC_ADDRESS {0x00,0x00,0xc0,0x2c,0x54,0xa4}
41 * Simple spin delay in microsecond units for device drivers.
42 * This is very dependent on the clock speed of the target.
44 Index: rtems-051009/c/src/lib/libbsp/m68k/mo376/clock/ckinit.c
45 ===================================================================
46 --- rtems.orig/c/src/lib/libbsp/m68k/mo376/clock/ckinit.c
47 +++ rtems/c/src/lib/libbsp/m68k/mo376/clock/ckinit.c
48 @@ -60,7 +60,7 @@ void Install_clock(
49 Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
51 /* enable 1mS interrupts */
52 - *PITR = (unsigned short int)( SAM(0x09,0,PITM) );/* load counter */
53 + *PITR = (unsigned short int)( SAM(0x08,0,PITM) );/* load counter */
54 *PICR = (unsigned short int) /* enable interrupt */
55 ( SAM(ISRL_PIT,8,PIRQL) | SAM(CLOCK_VECTOR,0,PIV) );
57 Index: rtems-051009/c/src/lib/libbsp/m68k/mo376/misc/gdbinit68
58 ===================================================================
59 --- rtems.orig/c/src/lib/libbsp/m68k/mo376/misc/gdbinit68
60 +++ rtems/c/src/lib/libbsp/m68k/mo376/misc/gdbinit68
63 # $Id: gdbinit68,v 1.1 2001/05/25 16:28:46 joel Exp $
65 -echo Setting up the environment for mrm debuging.\n
66 +echo Setting up the environment for mo376 debuging.\n
68 -target bdm /dev/bdmcpu320
70 +# invoke by "source run376.gdb"
81 +#target bdm /dev/m683xx-bdm/icd0
82 +#target bdm /dev/icd_bdm0
83 +#target bdm /dev/pd_bdm0
86 +#target bdm bdm-cpu32-icd1
90 +#target remote /dev/ttyS1
92 +# automatic resed of board before "run" command execution
93 +# depends on correct "cpu32init" file in current ditectory
96 +# confirmation of dangerous operations (kill, run, ..)
99 +#===========================================================
100 +# sets chipselects and configuration
102 +echo bdm_hw_init ...\n
116 +# system configuration
118 +# 0xFFFA00 - SIMCR - SIM Configuration Register
119 +# 15 14 13 12 11 10 9 8 7 6 5 4 3 0
120 +# EXOFF FRZSW FRZBM 0 SLVEN 0 SHEN SUPV MM 0 0 IARB
121 +# 0 0 0 0 DATA11 0 0 0 1 1 0 0 1 1 1 1
122 +# set *(short *)0xfffa00=0x42cf
123 +set *(short *)0xfffa00=0x40cf
125 +# 0xFFFA21 - SYPCR - System Protection Control Register
127 +# SWE SWP SWT HME BME BMT
128 +# 1 MODCLK 0 0 0 0 0 0
129 +set *(char *)0xfffa21=0x06
131 +# 0xYFFA27 - SWSR - Software Service Register
132 +# write 0x55 0xAA for watchdog
134 +# 0xFFFA04 - SYNCR Clock Synthesizer Control Register
135 +# 15 14 13 8 7 6 5 4 3 2 1 0
136 +# W X Y EDIV 0 0 SLIMP SLOCK RSTEN STSIM STEXT
137 +# 0 0 1 1 1 1 1 1 0 0 0 U U 0 0 0
138 +#set *(short *)0xfffa04=0xd408
139 +# set 21 MHz system clock for ref 4 MHz
141 +# $YFFA17 - PEPAR - Port E Pin Assignment Register
143 +# PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0
144 +# SIZ1 SIZ0 AS DS RMC AVEC DSACK1 DSACK0
145 +# 1 .. control signal, 0 .. port F
146 +# after reset determined by DATA8
147 +set *(char*)0xfffa17=0xf4
149 +# 0xFFFA1F - PFPAR - Port F Pin Assignment Register
151 +# PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0
152 +# INT7 INT6 INT5 INT4 INT3 INT2 INT1 MODCLK
153 +# 1 .. control signal, 0 .. port F
154 +# after reset determined by DATA9
155 +set *(char*)0xfffa1f=0
157 +# Setup internal RAM
159 +# setup STANBY RAM at 0x8000
161 +set *(short *)0xFFFB40=0x8000
163 +set *(int *)0xFFFB44=0xFFD000
165 +set *(short *)0xFFFB40=0
167 +# setup TPU RAM at 0x8000
169 +set *(short *)0xFFFB00=0x8000
171 +set *(short *)0xFFFB04=0xFFE000>>8
173 +set *(short *)0xFFFB00=0
175 +# 0xYFFA44 - CSPAR0 - Chip Select Pin Assignment Register 0
176 +# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
177 +# 0 0 CSPA0[6] CSPA0[5] CSPA0[4] CSPA0[3] CSPA0[2] CSPA0[1] CSBOOT
178 +# 0 0 DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1 1 DATA0
179 +# CS5 CS4 CS3 CS2 CS1 CS0 CSBOOT
180 +# FC2 PC2 FC1 PC1 FC0 PC0 BGACK BG BR
182 +# 00 Discrete Output
183 +# 01 Alternate Function
184 +# 10 Chip Select (8-Bit Port)
185 +# 11 Chip Select (16-Bit Port)
187 +set *(short *)0xfffa44=0x3bff
188 +# CS4 8-bit rest 16-bit
191 +# 0xFFFA46 - CSPAR1 - Chip Select Pin Assignment Register 1
192 +# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
193 +# 0 0 0 0 0 0 CSPA1[4] CSPA1[3] CSPA1[2] CSPA1[1] CSPA1[0]
194 +# 0 0 0 0 0 0 DATA7 1 DATA76 1 DATA75 1 DATA74 1 DATA73 1
195 +# CS10 CS9 CS8 CS7 CS6
196 +# A23 ECLK A22 PC6 A21 PC5 A20 PC4 A19 PC3
198 +set *(short *)0xfffa46=0x03a9
199 +# CS7,CS8,CS9 8-bit CS10 16-bit and A19
202 +# Chip selects configuration
204 +# 0xFFFA48 - CSBARBT - Chip-Select Base Address Register Boot ROM
205 +# 0xFFFA4C..0xFFFA74 - CSBAR[10:0] - Chip-Select Base Address Registers
206 +# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
207 +# A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 BLKSZ
208 +# reset 0x0003 for CSBARBT and 0x0000 for CSBAR[10:0]
210 +# BLKSZ Size Address Lines Compared
211 +# 000 2k ADDR[23:11]
212 +# 001 8k ADDR[23:13]
213 +# 010 16k ADDR[23:14]
214 +# 011 64k ADDR[23:16]
215 +# 100 128k ADDR[23:17]
216 +# 101 256k ADDR[23:18]
217 +# 110 512k ADDR[23:19]
218 +# 111 1M ADDR[23:20]
221 +# 0xFFFA4A - CSORBT - Chip-Select Option Register Boot ROM
222 +# 0xFFFA4E..0xFFFA76 - CSOR[10:0] - Chip-Select Option Registers
223 +# 15 14 13 12 11 10 9 6 5 4 3 1 0
224 +# MODE BYTE R/W STRB DSACK SPACE IPL AVEC
225 +# 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 - for CSORBT
227 +# BYTE 00 Disable, 01 Lower Byte, 10 Upper Byte, 11 Both Bytes
228 +# R/W 00 Reserved,01 Read Only, 10 Write Only, 11 Read/Write
229 +# SPACE 00 CPU, 01 User, 10 Supervisor, 11 Supervisor/User
231 +set *(short *)0xfffa48=(0x800000>>8)&0xfff8 | 7
232 +set *(short *)0xfffa4a=(0<<15)|(3<<13)|(3<<11)|(0<<10)|(0<<6)|(3<<4)
233 +# BOOT ROM 0x800000 1MB RW UL
235 +set *(short *)0xfffa4c=(0x900000>>8)&0xfff8 | 7
236 +set *(short *)0xfffa4e=(0<<15)|(3<<13)|(3<<11)|(0<<10)|(0<<6)|(3<<4)
237 +# CS0 ROM 0x900000 1MB RW UL
239 +#set *(long *)0xfffa50=0x0003303e
240 +# CS1 RAM 0x000000 64k WR L
242 +set *(short *)0xfffa54=(0x000000>>8)&0xfff8 | 7
243 +set *(short *)0xfffa56=(0<<15)|(3<<13)|(3<<11)|(0<<10)|(0<<6)|(3<<4)
244 +# CS2 RAM 0x000000 1MB RW UL - Main RAM first 1MB
246 +#set *(short *)0xfffa58=(0x100000>>8)&0xfff8 | 7
247 +#set *(short *)0xfffa5A=(0<<15)|(3<<13)|(3<<11)|(0<<10)|(0<<6)|(3<<4)
248 +# CS3 RAM 0x100000 1MB RW UL - Main RAM second 1MB
250 +set *(short *)0xfffa5c=(0xf00000>>8)&0xfff8 | 6
251 +set *(short *)0xfffa5e=(0<<15)|(3<<13)|(3<<11)|(1<<10)|(2<<6)|(3<<4)
252 +# CS4 PER 0xf00000 512kB RW UL - CMOS RAM, RTC, other devices
254 +#set *(long *)0xfffa60=0xffe8783f
257 +#set *(long *)0xfffa64=0x100438f0
258 +# CS6 R/R 0x100000 128k RW L
260 +set *(short *)0xfffa68=(0xf87000>>8)&0xfff8 | 0
261 +set *(short *)0xfffa6a=(0<<15)|(3<<13)|(3<<11)|(1<<10)|(1<<6)|(3<<4)
262 +# CS7 PER 0xf87000 2k RW UL - MO_PWR
264 +set *(short *)0xfffa6c=(0xf88000>>8)&0xfff8 | 0
265 +set *(short *)0xfffa6e=(0<<15)|(3<<13)|(3<<11)|(1<<10)|(1<<6)|(3<<4)
266 +# CS8 PER 0xf88000 2k RO UL - IRC
268 +set *(short *)0xfffa70=(0xf89000>>8)&0xfff8 | 0
269 +set *(short *)0xfffa72=(0<<15)|(3<<13)|(3<<11)|(1<<10)|(3<<6)|(3<<4)
270 +# CS9 PER 0xf89000 2k WR UL - KBD
272 +#set *(long *)0xfffa74=0x01035030
273 +# CS10 RAM 0x010000 64k WR U
278 +#set *(long *)0xfffa58=0x02036870
279 +# CS3 RAM 0x020000 64k RO UL
281 +#set *(long *)0xfffa64=0x02033030
282 +# CS6 RAM 0x020000 64k WR L
284 +#set *(long *)0xfffa68=0x02035030
285 +# CS7 RAM 0x020000 64k WR U
290 +# SR=PS Status Register
291 +# 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0
292 +# T1 T0 S 0 0 IP___ 0 0 0 X N Z V C
293 +# 0 0 1 0 0 1 1 1 0 0 0 U U U U U
298 +#===========================================================
300 +# sets well defined values into VBR
303 + set $vbr_val=(unsigned)$vbr
305 + set *(unsigned*)($vbr_val+$vec_num*4)=($vec_num*16)+0xf0000
310 +# Test writability of RAM location
311 +define bdm_test_ram_acc
314 + set $ram_addr=(unsigned int)$arg0
315 + set $old_ram_val0=*(int*)$ram_addr
316 + set $old_ram_val1=*(int*)($ram_addr+4)
317 + set *(int*)($ram_addr+3)=0xff234567
318 + set *(int*)$ram_addr=0x12345678
319 + if *(int*)$ram_addr!=0x12345678
320 + printf "Error1 %08X\n",*(int*)$ram_addr
322 + set *(char*)$ram_addr=0xab
323 + if *(int*)$ram_addr!=0xab345678
324 + printf "Error2 %08X\n",*(int*)$ram_addr
326 + set *(char*)($ram_addr+1)=0xcd
327 + if *(int*)$ram_addr!=0xabcd5678
328 + printf "Error3 %08X\n",*(int*)$ram_addr
330 + set *(char*)($ram_addr+3)=0x01
331 + if *(int*)$ram_addr!=0xabcd5601
332 + printf "Error4 %08X\n",*(int*)$ram_addr
334 + set *(char*)($ram_addr+2)=0xef
335 + if *(int*)$ram_addr!=0xabcdef01
336 + printf "Error5 %08X\n",*(int*)$ram_addr
338 + if *(int*)$ram_addr!=0xabcdef01
339 + printf "Error5 %08X\n",*(int*)$ram_addr
341 + if *(int*)($ram_addr+1)!=0xcdef0123
342 + printf "Error6 %08X\n",*(int*)$ram_addr
344 + if *(int*)($ram_addr+2)!=0xef012345
345 + printf "Error7 %08X\n",*(int*)$ram_addr
347 + if *(int*)($ram_addr+2)!=0xef012345
348 + printf "Error8 %08X\n",*(int*)$ram_addr
350 + if *(int*)($ram_addr+3)!=0x01234567
351 + printf "Error9 %08X\n",*(int*)$ram_addr
353 + set *(int*)$ram_addr=$old_ram_val0
354 + set *(int*)($ram_addr+4)=$old_ram_val1
357 +# Read flash identification
358 +define bdm_read_flash_id
359 + set $flash_base=(int)$arg0&~0xffff
360 + output /x $flash_base
362 + set *(char*)($flash_base+0x555*2+1)=0xf0
363 + set *(char*)($flash_base+0x555*2+1)=0xaa
364 + set *(char*)($flash_base+0x2aa*2+1)=0x55
365 + set *(char*)($flash_base+0x555*2+1)=0x90
366 + p /x *(char*)($flash_base+0x00*2+1)
367 + set *(char*)($flash_base+0x555*2+1)=0xf0
368 + set *(char*)($flash_base+0x555*2+1)=0xaa
369 + set *(char*)($flash_base+0x2aa*2+1)=0x55
370 + set *(char*)($flash_base+0x555*2+1)=0x90
371 + p /x *(char*)($flash_base+0x01*2+1)
374 +define bdm_read_flash1_id
375 + bdm_read_flash_id 0x800000
378 +define bdm_read_flash2_id
379 + bdm_read_flash_id 0x900000
382 +define bdm_test_flash_write
383 + set $flash_base=(int)$arg0 & ~0xffff
384 + output /x $flash_base
386 + set *(char*)($flash_base+0x555*2+1)=0xf0
387 + set *(char*)($flash_base+0x555*2+1)=0xaa
388 + set *(char*)($flash_base+0x2aa*2+1)=0x55
389 + set *(char*)($flash_base+0x555*2+1)=0xA0
390 + set *(char*)($arg0)=$arg1
393 +define bdm_test_pwm0
395 + #BIUMCR - BIU Module Configuration Register $YFF400
396 + set *(short*)0xfff400=*(short*)0xfff400&~0x8000
397 + #CPCR - CPSM Control Register $YFF408
398 + set *(short*)0xfff408=*(short*)0xfff408|8
399 + #PWM5SIC - PWM5 Status/Interrupt/Control Register $YFF428
400 + set *(short*)0xfff428=0x18
401 + #PWM5A1 - PWM5 Period Register $YFF42A
402 + set *(short*)0xfff42a=512
403 + #PWM5B1 - PWM5 Pulse Width Register $YFF42C
404 + set *(short*)0xfff42c=0
407 + set *(short*)0xf87000=0
411 + set *(char*)0xf87000=1
414 + set *(char*)0xf87000=2
415 + set $pwm_val=-($arg0)
419 + set *(short*)0xfff208=0x8000
421 + set *(short*)0xfff206=~0x8000
423 + #PWM5B1 - PWM5 Pulse Width Register $YFF42C
424 + set *(short*)0xfff42c=$pwm_val
428 +define bdm_test_usd_irc
429 + set $usd_irc_d=0xf88000
430 + set $usd_irc_c=0xf88001
433 + set *(unsigned char*)0xf88020=0
435 + set *(unsigned char*)$usd_irc_c=0x38
437 + set *(unsigned char*)$usd_irc_c=0x49
439 + set *(unsigned char*)$usd_irc_c=0x61
440 + # RLD - Reset BP, BT CT CPT S
441 + set *(unsigned char*)$usd_irc_c=0x05
443 + set *(unsigned char*)$usd_irc_d=0x02
444 + # RLD - Reset BP, PR0 -> PSC
445 + set *(unsigned char*)$usd_irc_c=0x1B
447 + # RLD - Reset BP, CNTR -> OL
448 + set *(unsigned char*)$usd_irc_c=0x11
450 + set $usd_irc_val=((int)(*(unsigned char*)$usd_irc_d))
451 + set $usd_irc_val+=((int)(*(unsigned char*)$usd_irc_d))<<8
452 + set $usd_irc_val+=((int)(*(unsigned char*)$usd_irc_d))<<16
453 + print /x $usd_irc_val
467 Index: rtems-051009/c/src/lib/libbsp/m68k/mo376/include/mo376.h
468 ===================================================================
469 --- rtems.orig/c/src/lib/libbsp/m68k/mo376/include/mo376.h
470 +++ rtems/c/src/lib/libbsp/m68k/mo376/include/mo376.h
472 #define EFI_INT1 25 /* CTS interrupt */
475 -/* System Clock definitions */
476 -#define XTAL 32768.0 /* crystal frequency in Hz */
477 +#define SIM_PFPAR (SIM_CRB + 0x1f)
480 -/* Default MRM clock rate (8.388688 MHz) set by CPU32: */
481 -#define MRM_W 0 /* system clock parameters */
485 +/* System Clock definitions */
486 +#define XTAL 4000000.0 /* crystal frequency in Hz */
490 -#define MRM_W 1 /* system clock parameters */
497 +/* Default MO376 clock rate (21.000 MHz) set by CPU32: */
498 #define MRM_W 1 /* system clock parameters */
504 -#define SYS_CLOCK (XTAL*4.0*(MRM_Y+1)*(1 << (2*MRM_W+MRM_X)))
506 +/*#define SYS_CLOCK (XTAL*4.0*(MRM_Y+1)*(1 << (2*MRM_W+MRM_X)))*/
508 +#define SYS_CLOCK (XTAL/32.0*(MRM_Y+1)*(1 << (2*MRM_W+MRM_X)))
509 #define SCI_BAUD 19200 /* RS232 Baud Rate */
511 /* macros/functions */
512 Index: rtems-051009/c/src/lib/libbsp/m68k/mo376/startup/linkcmds_ROM
513 ===================================================================
514 --- rtems.orig/c/src/lib/libbsp/m68k/mo376/startup/linkcmds_ROM
515 +++ rtems/c/src/lib/libbsp/m68k/mo376/startup/linkcmds_ROM
520 -STARTUP(except_vect_332_ROM.o)
521 +/* Not needed, mo376 uses initialization by mo_flashbb */
522 +/* STARTUP(except_vect_332_ROM.o) */
526 @@ -39,18 +40,18 @@ __DYNAMIC = 0;
530 - rom : ORIGIN = 0x90000, LENGTH = 0x70000
531 - ram : ORIGIN = 0x03000, LENGTH = 0x7d000
532 + ram : ORIGIN = 0x001000, LENGTH = 0x0ff000
533 + rom : ORIGIN = 0x808000, LENGTH = 0x0f8000
536 -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x003000;
537 -_RamSize = DEFINED(_RamSize) ? _RamSize : 0x7d000;
538 +_RamBase = DEFINED(_RamBase) ? _RamBase : 0x001000;
539 +_RamSize = DEFINED(_RamSize) ? _RamSize : 0x0ff000;
540 _RamEnd = _RamBase + _RamSize;
542 -__end_of_ram = 0x080000;
543 +__end_of_ram = 0x100000;
544 _copy_data_from_rom = 1;
545 -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x10000;
546 -_StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
547 +_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x40000;
548 +_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
552 Index: rtems-051009/c/src/lib/libbsp/m68k/mo376/spurious/spinit.c
553 ===================================================================
554 --- rtems.orig/c/src/lib/libbsp/m68k/mo376/spurious/spinit.c
555 +++ rtems/c/src/lib/libbsp/m68k/mo376/spurious/spinit.c
556 @@ -33,8 +33,8 @@ rtems_isr Spurious_Isr(
557 rtems_vector_number vector
564 const char * const VectDescrip[] = {
565 _Spurious_Error_[0], _Spurious_Error_[0], _Spurious_Error_[1],
566 _Spurious_Error_[2], _Spurious_Error_[3], _Spurious_Error_[4],
567 @@ -60,11 +60,11 @@ rtems_isr Spurious_Isr(
568 _Spurious_Error_[27], _Spurious_Error_[28]};
571 - //asm volatile ( "movea.l %%sp,%0 " : "=a" (sp) : "0" (sp) );
572 + asm volatile ( "movea.l %%sp,%0 " : "=a" (sp) : "0" (sp) );
574 _CPU_ISR_Set_level( 7 );
578 RAW_PUTS("\n\rRTEMS: Spurious interrupt: ");
579 RAW_PUTS((char *)VectDescrip[( (vector>64) ? 64 : vector )]);
580 RAW_PUTS("\n\rRTEMS: Vector: ");
581 @@ -89,6 +89,7 @@ void Spurious_Initialize(void)
589 @@ -96,6 +97,7 @@ void Spurious_Initialize(void)
591 /* These vectors used by CPU32bug - don't overwrite them. */
596 (void) set_vector( Spurious_Isr, vector, 1 );
597 Index: rtems-051009/c/src/lib/libbsp/m68k/mo376/startup/linkcmds
598 ===================================================================
599 --- rtems.orig/c/src/lib/libbsp/m68k/mo376/startup/linkcmds
600 +++ rtems/c/src/lib/libbsp/m68k/mo376/startup/linkcmds
601 @@ -33,15 +33,15 @@ __DYNAMIC = 0;
603 * Declare some sizes.
605 -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x10000;
606 -_RamSize = DEFINED(_RamSize) ? _RamSize : 0x70000;
607 +_RamBase = DEFINED(_RamBase) ? _RamBase : 0x001000;
608 +_RamSize = DEFINED(_RamSize) ? _RamSize : 0x0ff000;
609 _RamEnd = _RamBase + _RamSize;
610 -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x10000;
611 -_StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
612 +_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x40000;
613 +_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
617 - ram : ORIGIN = 0x10000, LENGTH = 0x70000
618 + ram : ORIGIN = 0x001000, LENGTH = 0x0ff000
621 _copy_data_from_rom = 0;
622 Index: rtems-051009/make/custom/mo376.cfg
623 ===================================================================
624 --- rtems.orig/make/custom/mo376.cfg
625 +++ rtems/make/custom/mo376.cfg
626 @@ -16,8 +16,16 @@ RTEMS_BSP_FAMILY=mo376
627 # and (hopefully) optimize for it.
630 +# Debugging flags: If we debug with optimization on, single-stepping
631 +# sometimes looks a little odd, but there won't be any surprises later.
632 +CFLAGS_DEBUG_V += -O2 -ggdb
633 +CXXFLAGS_DEBUG_V += -O2 -ggdb
635 # optimize flag: typically -0, could use -O4 or -fast, -O4 is ok for RTEMS
636 -CFLAGS_OPTIMIZE_V=-O4 -fomit-frame-pointer
637 +CFLAGS_OPTIMIZE_V=-O4 -fomit-frame-pointer -ggdb
638 +CXXFLAGS_OPTIMIZE_V=-O4 -ggdb
642 # The following are definitions of make-exe which will work using ld as
643 # is currently required. It is expected that as of gcc 2.8, the end user
644 Index: rtems-051009/c/src/lib/libbsp/m68k/mo376/startup/start_c.c
645 ===================================================================
646 --- rtems.orig/c/src/lib/libbsp/m68k/mo376/startup/start_c.c
647 +++ rtems/c/src/lib/libbsp/m68k/mo376/startup/start_c.c
648 @@ -60,12 +60,12 @@ void start_c() {
650 /* Port E and F Data Direction Register */
651 /* see section 9 of the SIM Reference Manual */
652 - *DDRE = (unsigned char) 0xff;
653 - *DDRF = (unsigned char) 0xfd;
654 + *DDRE = (unsigned char) 0x01;
655 + *DDRF = (unsigned char) 0x00;
657 /* Port E and F Pin Assignment Register */
658 /* see section 9 of the SIM Reference Manual */
659 - *PEPAR = (unsigned char) 0;
660 + *PEPAR = (unsigned char) 0xf4;
661 *PFPAR = (unsigned char) 0;
663 /* end of SIM initalization code */