2 c/src/lib/libbsp/m68k/mcf5235/start/start.S | 1
3 c/src/lib/libbsp/m68k/mcf5235/startup/init5235.c | 75 ++++++++++++-----------
4 2 files changed, 42 insertions(+), 34 deletions(-)
6 Index: rtems-4.6.99.3/c/src/lib/libbsp/m68k/mcf5235/start/start.S
7 ===================================================================
8 --- rtems-4.6.99.3.orig/c/src/lib/libbsp/m68k/mcf5235/start/start.S 2006-12-07 16:00:00.000000000 +0100
9 +++ rtems-4.6.99.3/c/src/lib/libbsp/m68k/mcf5235/start/start.S 2006-12-07 16:09:00.000000000 +0100
11 move.l #0x01000000,d0 | Set system frequency to 150 MHz
12 move.l d0, (0x40120000)
13 move.w #0x2700,sr | Disable interrupts
14 + move.l #INITIAL_STACK,sp
16 move.l #__SRAMBASE+1,d0 | Enable the MCF5235 internal SRAM
17 movec d0,%rambar | ...so we have a stack
18 Index: rtems-4.6.99.3/c/src/lib/libbsp/m68k/mcf5235/startup/init5235.c
19 ===================================================================
20 --- rtems-4.6.99.3.orig/c/src/lib/libbsp/m68k/mcf5235/startup/init5235.c 2006-12-07 16:03:50.000000000 +0100
21 +++ rtems-4.6.99.3/c/src/lib/libbsp/m68k/mcf5235/startup/init5235.c 2006-12-07 16:21:37.000000000 +0100
23 MCF5235_GPIO_UART=0x3FFF;
24 MCF5235_GPIO_PAR_AD=0xE1;
26 - //Setup the Chip Selects so CS0 is flash
27 - MCF5235_CS_CSAR0 =(0xFFE00000 & 0xffff0000)>>16;
28 - MCF5235_CS_CSMR0 = 0x001f0001;
29 - MCF5235_CS_CSCR0 = 0x1980;
32 - for(x=0; x<20000; x++)
36 - MCF5235_SDRAMC_DCR = 0x042E;
37 - MCF5235_SDRAMC_DACR0 = 0x00001300;
38 - MCF5235_SDRAMC_DMR0 = (0x00FC0000) | (0x00000001);
39 - for(x=0; x<20000; x++)
43 - // set ip ( bit 3 ) in dacr
44 - MCF5235_SDRAMC_DACR0 |= (0x00000008) ;
46 - *((unsigned long *)MM_SDRAM_BASE) = 0xDEADBEEF;
48 - MCF5235_SDRAMC_DACR0 |= (0x00008000);
50 - for(x=0; x<20000; x++)
55 - MCF5235_SDRAMC_DACR0 |= (0x00000040);
56 - *((short *)MM_SDRAM_BASE) = 0;
57 - for(x=0; x<60000; x++)
60 + /* Find actual execution address */
61 + asm ("\tlea.l @pc,%0\n\t" : "=r" (temp) );
63 + /* Initialization of SDRAM leads to disaster if code runs from it */
64 + if ((temp ^ MM_SDRAM_BASE) & ~0x000fffff) {
65 + //Setup the Chip Selects so CS0 is flash
66 + MCF5235_CS_CSAR0 =(0xFFE00000 & 0xffff0000)>>16;
67 + MCF5235_CS_CSMR0 = 0x001f0001;
68 + MCF5235_CS_CSCR0 = 0x1980;
71 + for(x=0; x<20000; x++)
75 + MCF5235_SDRAMC_DCR = 0x042E;
76 + MCF5235_SDRAMC_DACR0 = 0x00001300;
77 + MCF5235_SDRAMC_DMR0 = (0x00FC0000) | (0x00000001);
78 + for(x=0; x<20000; x++)
82 + // set ip ( bit 3 ) in dacr
83 + MCF5235_SDRAMC_DACR0 |= (0x00000008) ;
85 + *((unsigned long *)MM_SDRAM_BASE) = 0xDEADBEEF;
87 + MCF5235_SDRAMC_DACR0 |= (0x00008000);
89 + for(x=0; x<20000; x++)
94 + MCF5235_SDRAMC_DACR0 |= (0x00000040);
95 + *((short *)MM_SDRAM_BASE) = 0;
96 + for(x=0; x<60000; x++)
102 *((unsigned long*)MM_SDRAM_BASE)=0x12345678;
104 /* Copy the interrupt vector table to address 0x0 in SDRAM */