1 /** @file sys_selftest.h
2 * @brief System Memory Header File
7 * - Efuse Self Test Functions
9 * which are relevant for the System driver.
12 /* (c) Texas Instruments 2009-2012, All rights reserved. */
14 #ifndef __SYS_SELFTEST_H__
15 #define __SYS_SELFTEST_H__
17 //#include "sys_common.h"
18 //#include "sys_core.h"
20 //#include "sys_vim.h"
21 //#include "ti_drv_adc.h"
22 //#include "ti_drv_can.h"
23 //#include "ti_drv_mibspi.h"
24 //#include "ti_drv_het.h"
25 //#include "ti_drv_htu.h"
26 //#include "ti_drv_esm.h"
29 /* USER CODE BEGIN (0) */
32 #define flash1bitError (*(unsigned int *) 0xF00803F0)
33 #define flash2bitError (*(unsigned int *) 0xF00803F8)
35 #define tcramA1bitError (*(unsigned int *)(0x08400000))
36 #define tcramA2bitError (*(unsigned int *)(0x08400010))
38 #define tcramB1bitError (*(unsigned int *)(0x08400008))
39 #define tcramB2bitError (*(unsigned int *)(0x08400018))
41 #define tcramA1bit (*(unsigned int *)0x08000000)
42 #define tcramA2bit (*(unsigned int *)0x08000010)
44 #define tcramB1bit (*(unsigned int *)0x08000008)
45 #define tcramB2bit (*(unsigned int *)0x08000018)
47 #define flashBadECC (*(unsigned int *)0x20080000)
49 #define CCMSR (*(unsigned int *)0xFFFFF600U)
50 #define CCMKEYR (*(unsigned int *)0xFFFFF604U)
52 #define DMA_PARCR (*(unsigned int *)0xFFFFF1A8U)
53 #define DMA_PARADDR (*(unsigned int *)0xFFFFF1ACU)
55 #define DMARAMLOC (*(unsigned int *)0xFFF80000U)
56 #define DMARAMPARLOC (*(unsigned int *)0xFFF80A00U)
62 * @brief Alias names for pbist Port number
64 * This enumeration is used to provide alias names for the pbist Port number
70 PBIST_PORT0 = 0, /**< Alias for PBIST Port 0 */
71 PBIST_PORT1 = 1 /**< Alias for PBIST Port 1 */
74 * @brief Alias names for pbist Algorithm
76 * This enumeration is used to provide alias names for the pbist Algorithm
77 * - PBIST_TripleReadSlow
78 * - PBIST_TripleReadFast
83 * - PBIST_MapColumn_DP
84 * - PBIST_MapColumn_SP
85 * - PBIST_Precharge_DP
86 * - PBIST_Precharge_SP
91 * - PBIST_PPMOSOpenSlice1_DP
92 * - PBIST_PPMOSOpenSlice1_SP
93 * - PBIST_PPMOSOpenSlice2_DP
94 * - PBIST_PPMOSOpenSlice2_SP
99 PBIST_TripleReadSlow = 0x00000001,
100 PBIST_TripleReadFast = 0x00000002,
101 PBIST_March13N_DP = 0x00000004,
102 PBIST_March13N_SP = 0x00000008,
103 PBIST_DOWN1a_DP = 0x00000010,
104 PBIST_DOWN1a_SP = 0x00000020,
105 PBIST_MapColumn_DP = 0x00000040,
106 PBIST_MapColumn_SP = 0x00000080,
107 PBIST_Precharge_DP = 0x00000100,
108 PBIST_Precharge_SP = 0x00000200,
109 PBIST_DTXN2a_DP = 0x00000400,
110 PBIST_DTXN2a_SP = 0x00000800,
111 PBIST_PMOSOpen_DP = 0x00001000,
112 PBIST_PMOSOpen_SP = 0x00002000,
113 PBIST_PPMOSOpenSlice1_DP = 0x00004000,
114 PBIST_PPMOSOpenSlice1_SP = 0x00008000,
115 PBIST_PPMOSOpenSlice2_DP = 0x00010000,
116 PBIST_PPMOSOpenSlice2_SP = 0x00020000
119 /* PBIST General Definitions */
121 /** @struct pbistBase
122 * @brief PBIST Base Register Definition
124 * This structure is used to access the PBIST module egisters.
126 /** @typedef pbistBASE_t
127 * @brief PBIST Register Frame Type Definition
129 * This type is used to access the PBIST Registers.
131 typedef volatile struct pbistBase
133 #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) /* 0x0160: RAM Configuration Register */
134 uint32_t RLS : 2U; /* 0x0160: RAM Latency Select */
135 uint32_t PLS : 4U; /* 0x0160: Pipeline Latency Select */
136 uint32_t SMS : 2U; /* 0x0160: Sense Margin Select Register */
137 uint32_t DWR : 8U; /* 0x0160: Data Width Register */
138 uint32_t RDS : 8U; /* 0x0160: Return Data Select */
139 uint32_t RGS : 8U; /* 0x0160: RAM Group Select */
141 uint32_t RGS : 8U; /* 0x0160: RAM Group Select */
142 uint32_t RDS : 8U; /* 0x0160: Return Data Select */
143 uint32_t DWR : 8U; /* 0x0160: Data Width Register */
144 uint32_t SMS : 2U; /* 0x0160: Sense Margin Select Register */
145 uint32_t PLS : 4U; /* 0x0160: Pipeline Latency Select */
146 uint32_t RLS : 2U; /* 0x0160: RAM Latency Select */
149 uint32_t DLR; /* 0x0164: Datalogger Register */
150 uint32_t : 32U; /* 0x0168 */
151 uint32_t : 32U; /* 0x016C */
152 uint32_t : 32U; /* 0x0170 */
153 uint32_t : 32U; /* 0x0174 */
154 uint32_t : 32U; /* 0x0178 */
155 uint32_t : 32U; /* 0x017C */
156 uint32_t PACT; /* 0x0180: PBIST Activate Register */
157 uint32_t PBISTID; /* 0x0184: PBIST ID Register */
158 uint32_t OVER; /* 0x0188: Override Register */
159 uint32_t : 32U; /* 0x018C */
160 uint32_t FSRF0; /* 0x0190: Fail Status Fail Register 0 */
161 uint32_t FSRF1; /* 0x0194: Fail Status Fail Register 1 */
162 uint32_t FSRC0; /* 0x0198: Fail Status Count Register 0 */
163 uint32_t FSRC1; /* 0x019C: Fail Status Count Register 1 */
164 uint32_t FSRA0; /* 0x01A0: Fail Status Address 0 Register */
165 uint32_t FSRA1; /* 0x01A4: Fail Status Address 1 Register */
166 uint32_t FSRDL0; /* 0x01A8: Fail Status Data Register 0 */
167 uint32_t : 32U; /* 0x01AC */
168 uint32_t FSRDL1; /* 0x01B0: Fail Status Data Register 1 */
169 uint32_t : 32U; /* 0x01B4 */
170 uint32_t : 32U; /* 0x01B8 */
171 uint32_t : 32U; /* 0x01BC */
172 uint32_t ROM; /* 0x01C0: ROM Mask Register */
173 uint32_t ALGO; /* 0x01C4: Algorithm Mask Register */
174 uint32_t RINFOL; /* 0x01C8: RAM Info Mask Lower Register */
175 uint32_t RINFOU; /* 0x01CC: RAM Info Mask Upper Register */
178 #define pbistREG ((pbistBASE_t *)0xFFFFE560U)
180 /* USER CODE BEGIN (1) */
183 /** @fn void memoryPort0TestFailNotification(uint32_t groupSelect, uint32_t dataSelect, uint32_t address, uint32_t data)
184 * @brief Memory Port 0 test fail notification
185 * @param[in] groupSelect Failing Ram group select:
186 * @param[in] dataSelect Failing Ram data select:
187 * @param[in] address Failing Ram offset:
188 * @param[in] data Failing data at address:
190 * @note This function has to be provide by the user.
192 void memoryPort0TestFailNotification(uint32_t groupSelect, uint32_t dataSelect, uint32_t address, uint32_t data);
194 /** @fn void memoryPort1TestFailNotification(uint32_t groupSelect, uint32_t dataSelect, uint32_t address, uint32_t data)
195 * @brief Memory Port 1 test fail notification
196 * @param[in] groupSelect Failing Ram group select:
197 * @param[in] dataSelect Failing Ram data select:
198 * @param[in] address Failing Ram offset:
199 * @param[in] data Failing data at address:
201 * @note This function has to be provide by the user.
203 void memoryPort1TestFailNotification(uint32_t groupSelect, uint32_t dataSelect, uint32_t address, uint32_t data);
210 /* STC General Definitions */
212 /* STC Test Intervals supported in the Device */
213 #define STC_INTERVAL 24
214 #define STC_MAX_TIMEOUT 0xFFFFFFFF
217 * @brief STC Base Register Definition
219 * This structure is used to access the STC module egisters.
221 /** @typedef stcBASE_t
222 * @brief STC Register Frame Type Definition
224 * This type is used to access the STC Registers.
226 typedef volatile struct stcBase
228 uint32_t STCGCR0; /**< 0x0000: STC Control Register 0 */
229 uint32_t STCGCR1; /**< 0x0004: STC Control Register 1 */
230 uint32_t STCTPR; /**< 0x0008: STC Self-Test Run Timeout Counter Preload Register */
231 uint32_t STCCADDR; /**< 0x000C: STC Self-Test Current ROM Address Register */
232 uint32_t STCCICR; /**< 0x0010: STC Self-Test Current Interval Count Register */
233 uint32_t STCGSTAT; /**< 0x0014: STC Self-Test Global Status Register */
234 uint32_t STCFSTAT; /**< 0x0018: STC Self-Test Fail Status Register */
235 uint32_t CPU1_CURMISR3; /**< 0x001C: STC CPU1 Current MISR Register */
236 uint32_t CPU1_CURMISR2; /**< 0x0020: STC CPU1 Current MISR Register */
237 uint32_t CPU1_CURMISR1; /**< 0x0024: STC CPU1 Current MISR Register */
238 uint32_t CPU1_CURMISR0; /**< 0x0028: STC CPU1 Current MISR Register */
239 uint32_t CPU2_CURMISR3; /**< 0x002C: STC CPU1 Current MISR Register */
240 uint32_t CPU2_CURMISR2; /**< 0x0030: STC CPU1 Current MISR Register */
241 uint32_t CPU2_CURMISR1; /**< 0x0034: STC CPU1 Current MISR Register */
242 uint32_t CPU2_CURMISR0; /**< 0x0038: STC CPU1 Current MISR Register */
243 uint32_t STCSCSCR; /**< 0x003C: STC Signature Compare Self-Check Register */
246 #define stcREG ((stcBASE_t *)0xFFFFE600U)
253 typedef volatile struct efcBase
255 unsigned int INSTRUCTION; /* 0x0 INSTRUCTION AN DUMPWORD REGISTER */
256 unsigned int ADDRESS; /* 0x4 ADDRESS REGISTER */
257 unsigned int DATA_UPPER; /* 0x8 DATA UPPER REGISTER */
258 unsigned int DATA_LOWER; /* 0xc DATA LOWER REGISTER */
259 unsigned int SYSTEM_CONFIG; /* 0x10 SYSTEM CONFIG REGISTER */
260 unsigned int SYSTEM_STATUS; /* 0x14 SYSTEM STATUS REGISTER */
261 unsigned int ACCUMULATOR; /* 0x18 ACCUMULATOR REGISTER */
262 unsigned int BOUNDARY; /* 0x1C BOUNDARY REGISTER */
263 unsigned int KEY_FLAG; /* 0x20 KEY FLAG REGISTER */
264 unsigned int KEY; /* 0x24 KEY REGISTER */
265 unsigned int : 32; /* 0x28 RESERVED */
266 unsigned int PINS; /* 0x2C PINS REGISTER */
267 unsigned int CRA; /* 0x30 CRA */
268 unsigned int READ; /* 0x34 READ REGISTER */
269 unsigned int PROGRAMME; /* 0x38 PROGRAMME REGISTER */
270 unsigned int ERROR; /* 0x3C ERROR STATUS REGISTER */
271 unsigned int SINGLE_BIT; /* 0x40 SINGLE BIT ERROR */
272 unsigned int TWO_BIT_ERROR; /* 0x44 DOUBLE BIT ERROR */
273 unsigned int SELF_TEST_CYCLES; /* 0x48 SELF TEST CYCLEX */
274 unsigned int SELF_TEST_SIGN; /* 0x4C SELF TEST SIGNATURE */
277 #define efcREG ((efcBASE_t *)0xFFF8C000U)
279 #define INPUT_ENABLE 0x0000000F
280 #define INPUT_DISABLE 0x00000000
282 #define SYS_WS_READ_STATES 0x00000000
285 #define SYS_REPAIR_EN_0 0x00000000
286 #define SYS_REPAIR_EN_3 0x00000100
287 #define SYS_REPAIR_EN_5 0x00000200
289 #define SYS_DEID_AUTOLOAD_EN 0x00000400
290 #define SYS_DEID_AUTOLOAD_EN 0x00000400
292 #define EFC_FDI_EN 0x00000800
293 #define EFC_FDI_DIS 0x00000000
295 #define SYS_ECC_OVERRIDE_EN 0x00001000
296 #define SYS_ECC_OVERRIDE_DIS 0x00000000
298 #define SYS_ECC_SELF_TEST_EN 0x00002000
299 #define SYS_ECC_SELF_TEST_DIS 0x00000000
301 #define OUTPUT_ENABLE 0x0003C000
302 #define OUTPUT_DISABLE 0x00000000
304 /*********** OUTPUT **************/
306 #define EFC_AUTOLOAD_ERROR_EN 0x00040000
307 #define EFC_INSTRUCTION_ERROR_EN 0x00080000
308 #define EFC_INSTRUCTION_INFO_EN 0x00100000
309 #define EFC_SELF_TEST_ERROR_EN 0x00200000
312 #define EFC_AUTOLOAD_ERROR_DIS 0x00000000
313 #define EFC_INSTRUCTION_ERROR_DIS 0x00000000
314 #define EFC_INSTRUCTION_INFO_DIS 0x00000000
315 #define EFC_SELF_TEST_ERROR_DIS 0x00000000
317 #define DISABLE_READ_ROW0 0x00800000
319 /********************************************************************/
321 #define SYS_REPAIR_0 0x00000010
322 #define SYS_REPAIR_3 0x00000010
323 #define SYS_REPAIR_5 0x00000020
325 #define SYS_DEID_AUTOLOAD 0x00000040
326 #define SYS_FCLRZ 0x00000080
327 #define EFC_READY 0x00000100
328 #define SYS_ECC_OVERRIDE 0x00000200
329 #define EFC_AUTOLOAD_ERROR 0x00000400
330 #define EFC_INSTRUCTION_ERROR 0x00000800
331 #define EFC_INSTRUCTION_INFO 0x00001000
332 #define SYS_ECC_SELF_TEST 0x00002000
333 #define EFC_SELF_TEST_ERROR 0x00004000
334 #define EFC_SELF_TEST_DONE 0x00008000
336 /************** 0x3C error status register ******************************************************/
338 #define TIME_OUT 0x01
339 #define AUTOLOAD_NO_FUSEROM_DATA 0x02
340 #define AUTOLOAD_SIGN_FAIL 0x03
341 #define AUTOLOAD_PROG_INTERRUPT 0x04
342 #define AUTOLOAD_TWO_BIT_ERR 0x05
343 #define PROGRAME_WR_P_SET 0x06
344 #define PROGRAME_MNY_DATA_ITERTN 0x07
345 #define PROGRAME_MNY_CNTR_ITERTN 0x08
346 #define UN_PROGRAME_BIT_SET 0x09
347 #define REDUNDANT_REPAIR_ROW 0x0A
348 #define PROGRAME_MNY_CRA_ITERTN 0x0B
349 #define PROGRAME_SAME_DATA 0x0C
350 #define PROGRAME_CMP_SKIP 0x0D
351 #define PROGRAME_ABORT 0x0E
352 #define PROGRAME_INCORRECT_KEY 0x0F
353 #define FUSEROM_LASTROW_STUCK 0x10
354 #define AUTOLOAD_SINGLE_BIT_ERR 0x15
355 #define DUMPWORD_TWO_BIT_ERR 0x16
356 #define DUMPWORD_ONE_BIT_ERR 0x17
357 #define SELF_TEST_ERROR 0x18
359 #define INSTRUCTION_DONE 0x20
361 /************** Efuse Instruction set ******************************************************/
363 #define TEST_UNPROGRAME_ROM 0x01000000
364 #define PROGRAME_CRA 0x02000000
365 #define DUMP_WORD 0x04000000
366 #define LOAD_FUSE_SCAN_CHAIN 0x05000000
367 #define PROGRAME_DATA 0x07000000
368 #define RUN_AUTOLOAD_8 0x08000000
369 #define RUN_AUTOLOAD_A 0x0A000000
373 /* safety Init Interface Functions */
374 void ccmSelfCheck(void);
375 void ccmFail(unsigned int);
377 void stcSelfCheck(void);
378 void stcSelfCheckFail(void);
379 void cpuSelfTest(unsigned int no_of_intervals, unsigned int max_timeout, boolean_t restart_test);
380 void cpuSelfTestFail(void);
382 void _memoryInit_(uint32_t);
384 void pbistSelfCheck(void);
385 void pbistRun(unsigned int, unsigned int);
386 void pbistStop(void);
387 void pbistSelfCheckFail(void);
388 boolean_t pbistIsTestCompleted(void);
389 boolean_t pbistIsTestPassed(void);
390 boolean_t pbistPortTestStatus(uint32_t port);
393 void efcSelfTest(void);
394 boolean_t efcStuckZeroTest(void);
395 boolean_t checkefcSelfTest(void);
396 void efcClass1Error(void);
397 void efcClass2Error(void);
399 void fmcBus2Check(void);
400 void fmcECCcheck(void);
401 void fmcClass1Error(void);
402 void fmcClass2Error(void);
404 void checkB0RAMECC(void);
405 void checkB1RAMECC(void);
406 void tcramClass1Error(void);
407 void tcramClass2Error(void);
409 void checkFlashECC(void);
410 void flashClass1Error(void);
411 void flashClass2Error(void);
413 void vimParityCheck(void);
414 void dmaParityCheck(void);
415 void adc1ParityCheck(void);
416 void adc2ParityCheck(void);
417 void het1ParityCheck(void);
418 void htu1ParityCheck(void);
419 void het2ParityCheck(void);
420 void htu2ParityCheck(void);
421 void can1ParityCheck(void);
422 void can2ParityCheck(void);
423 void can3ParityCheck(void);
424 void mibspi1ParityCheck(void);
425 void mibspi3ParityCheck(void);
426 void mibspi5ParityCheck(void);
428 /* USER CODE BEGIN (2) */
431 #endif /* __SYS_SELFTEST_H__ */