4 /* ************************************************* */
6 /* ************************************************* */
7 #define PHY_BMCR 0x0 /* Basic Mode Control Register */
8 #define PHY_BMSR 0x01 /* Basic Mode Status Register */
9 #define PHY_ANAR 0x4 /* Auto-Negotiation Advertisement Register */
10 #define PHY_LEDCR 0x18 /* LED Direct Control Register */
11 #define PHY_PHYCR 0x19 /* PHY Control Register */
12 #define PHY_PHYCR2 0x1C /* PHY Control Register 2 */
13 #define PHY_STS 0x10 /* PHY Status Register */
14 #define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */
17 #define PHY_RESET_m (1 << 15)
18 #define PHY_SPEED_m (1 << 13)
19 #define PHY_AUTONEG_EN_m (1 << 12) /* ! */
20 #define PHY_POWERDOWN_m (1 << 11)
21 #define PHY_DUPLEX_m (1 << 8)
22 #define PHY_AUTONEG_REST (1 << 9)
25 #define PHY_A_NEG_COMPLETE_m (1 << 5)
28 #define PHY_100BASET4_m (1 << 9)
29 #define PHY_100BASETXDUPL_m (1 << 8)
30 #define PHY_100BASETX_m (1 << 7)
31 #define PHY_10BASETDUPL_m (1 << 6)
32 #define PHY_10BASET_m (1 << 5)
35 /* ************************************************* */
36 void PHY_partner_ability_get(unsigned int mdioBaseAddr, unsigned int phyAddr, unsigned short *data);
37 void PHY_configure(unsigned int mdioBaseAddr, unsigned int phyAddr);