]> rtime.felk.cvut.cz Git - pes-rpp/rpp-test-sw.git/commitdiff
EMAC: TX interrupt seems to be ok.
authorRostislav Lisovy <lisovy@gmail.com>
Fri, 19 Oct 2012 16:54:39 +0000 (18:54 +0200)
committerRostislav Lisovy <lisovy@gmail.com>
Fri, 19 Oct 2012 16:54:39 +0000 (18:54 +0200)
EMAC interrupts are set to FIQ (in Halcogen config. is still IRQ).

include/sys_vim.h
source/emac_test.c
source/sys_startup.c

index ed972146a74fad7baecf42417fc798b76b18a348..719e642dc1d06cde232fe912e8f34d62aad8a987 100644 (file)
@@ -38,11 +38,6 @@ typedef void (*t_isrFuncPTR)();
 \r
 #define VIM_CHANNELS 96U\r
 \r
-/* USER CODE BEGIN (2) */\r
-void EMACCore0RxIsr(void);\r
-void EMACCore0TxIsr(void);\r
-/* USER CODE END */\r
-\r
 /* Interrupt Handlers */\r
 \r
 extern void phantomInterrupt(void);\r
@@ -64,6 +59,8 @@ extern void spi4HighLevelInterrupt(void);
 extern void adc2Group1Interrupt(void);\r
 extern void spi4LowLevelInterrupt(void);\r
 extern void sciHighLevelInterrupt(void);\r
+extern void EMACCore0RxIsr(void);\r
+extern void EMACCore0TxIsr(void);\r
 \r
 \r
 /* Vim Register Frame Definition */\r
index a6d36d7ae3321d0f28b45ddd8e21b1640fc7c6a6..b8edfba2b35bc413c654d7a192565cfd9f5e562e 100644 (file)
@@ -25,8 +25,11 @@ int channel = 0;
 
 unsigned int phyalive;
 unsigned int phylink;
-EMAC_Desc fr1;
-eth_frame_t efr1;
+EMAC_Desc fr1 __attribute__((aligned(4)));
+EMAC_Desc rx_desc __attribute__((aligned(4)));
+uint8_t rx_buff[1024] __attribute__((aligned(4)));
+
+eth_frame_t efr1 __attribute__((aligned(4)));
 char *buff = "asdfasdfasdfasdf";
 
 
@@ -38,16 +41,20 @@ void dummy_wait()
                ;
 }
 
+#pragma INTERRUPT(EMACCore0RxIsr, FIQ)
 void EMACCore0RxIsr(void)
 {
-
+       EMACCoreIntAck(emacBase, EMAC_INT_CORE0_RX);
 }
 
+#pragma INTERRUPT(EMACCore0TxIsr, FIQ)
 void EMACCore0TxIsr(void)
 {
-       //EMACTxCPWrite(emacBase, channel, NULL);
-       EMACCoreIntAck(emacBase, EMAC_INT_CORE0_RX);
-       EMACCoreIntAck(emacBase, EMAC_INT_CORE0_TX);
+       /* Is not being processed by the EMAC anymore */
+       if (!(fr1.PktFlgLen & EMAC_DSC_FLAG_OWNER)) {
+               EMACTxCPWrite(emacBase, channel, (unsigned int)&fr1);
+               EMACCoreIntAck(emacBase, EMAC_INT_CORE0_TX);
+       }
 }
 
 int emac_test(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
@@ -71,6 +78,13 @@ int emac_test(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
        gioSetBit(dmmPORT, DMM_CLK, 1);
        dummy_wait();
 */
+       /* Prepare RX descriptors */
+       rx_desc.pBuffer = rx_buff;
+       rx_desc.PktFlgLen = sizeof(rx_buff) | EMAC_DSC_FLAG_OWNER;
+       rx_desc.pNext = NULL;
+       rx_desc.BufOffLen = 0;
+       //FIXME
+
        /* Fill some testing Ethernet frame with relevant data */
        efr1.destination[0] = 0x00;
        efr1.destination[1] = 0x21;
@@ -128,18 +142,26 @@ int emac_test(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
                        ;
        }
 
-       EMACTxIntPulseEnable(emacBase, emacCtrlBase, 0, 0);
-       EMACRxIntPulseEnable(emacBase, emacCtrlBase, 0, 0);
-
-       //EMACCoreIntAck(emacBase, EMAC_INT_CORE0_RX); // ?
-       //EMACCoreIntAck(emacBase, EMAC_INT_CORE0_TX); // ?
+       for (chan = 0; chan < 8; chan++) {
+               EMACTxHdrDescPtrWrite(emacBase, 0, chan);
+               EMACRxHdrDescPtrWrite(emacBase, 0, chan);
+       }
 
-       //EMACNumFreeBufSet(emacBase, 0, 10);
-       //EMACRxEnable(emacBase);
+       EMACRxBroadCastEnable(emacBase, channel);
+       EMACNumFreeBufSet(emacBase, channel, 10);
        EMACTxEnable(emacBase);
+       EMACRxEnable(emacBase);
 
-       EMACMIIEnable(emacBase);
+       EMACTxIntPulseEnable(emacBase, emacCtrlBase, 0, channel);
+       EMACRxIntPulseEnable(emacBase, emacCtrlBase, 0, channel);
 
+       EMACCoreIntAck(emacBase, EMAC_INT_CORE0_RX);
+       EMACCoreIntAck(emacBase, EMAC_INT_CORE0_TX);
+
+
+       EMACRxHdrDescPtrWrite(emacBase, (unsigned int)&rx_desc, channel);
+
+       EMACMIIEnable(emacBase);
 
        phylink = MDIOPhyLinkStatusGet(mdioBase);
        if (!phylink)
@@ -155,15 +177,8 @@ int emac_test(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
                fr1.PktFlgLen = (EMAC_DSC_FLAG_SOP | EMAC_DSC_FLAG_EOP | EMAC_DSC_FLAG_OWNER | 65);
 
                EMACTxHdrDescPtrWrite(emacBase, (unsigned int)&fr1, channel);
-               dummy_wait();
-
-               EMACCoreIntAck(emacBase, EMAC_INT_CORE0_TX);
-
-               EMACTxCPWrite(emacBase, channel, (unsigned int)&fr1);
-               dummy_wait();
-               EMACCoreIntAck(emacBase, EMAC_INT_CORE0_TX);
-
                print((uint8_t *)"Packet sent\r\n");
+               dummy_wait();
        }
 
        return 0;
index ebf4bd8254aadea75a52f67e6a85dbe517530f14..4b05371e67deb0705efd3bc45e9e5a137041dec3 100644 (file)
@@ -86,11 +86,12 @@ typedef volatile struct vimRam
 static const t_isrFuncPTR s_vim_init[] =\r
 {\r
     &phantomInterrupt,\r
-    &esmHighInterrupt,\r
+    &esmHighInterrupt,         // 0\r
     &phantomInterrupt,\r
     &vPreemptiveTick,\r
     &phantomInterrupt,\r
     &phantomInterrupt,\r
+    &phantomInterrupt,         // 5\r
     &phantomInterrupt,\r
     &phantomInterrupt,\r
     &phantomInterrupt,\r
@@ -159,8 +160,12 @@ static const t_isrFuncPTR s_vim_init[] =
     &phantomInterrupt,\r
     &phantomInterrupt,\r
     &phantomInterrupt,\r
+    &phantomInterrupt,         // 75\r
     &phantomInterrupt,\r
+    &EMACCore0TxIsr,\r
     &phantomInterrupt,\r
+    &EMACCore0RxIsr,\r
+    &phantomInterrupt,         // 80\r
     &phantomInterrupt,\r
     &phantomInterrupt,\r
     &phantomInterrupt,\r
@@ -778,9 +783,9 @@ void _c_int00()
                     | (SYS_IRQ << 10U)\r
                     | (SYS_IRQ << 11U)\r
                     | (SYS_IRQ << 12U)\r
-                    | (SYS_IRQ << 13U)\r
+                    | (SYS_FIQ << 13U)\r
                     | (SYS_IRQ << 14U)\r
-                    | (SYS_IRQ << 15U)\r
+                    | (SYS_FIQ << 15U)\r
                     | (SYS_IRQ << 16U)\r
                     | (SYS_IRQ << 17U)\r
                     | (SYS_IRQ << 18U)\r
@@ -912,9 +917,9 @@ void _c_int00()
                         | (0U << 10U)\r
                         | (0U << 11U)\r
                         | (0U << 12U)\r
-                        | (0U << 13U)\r
+                        | (1U << 13U)          // EMACCore0TxIsr\r
                         | (0U << 14U)\r
-                        | (0U << 15U)\r
+                        | (1U << 15U)          // EMACCore0RxIsr\r
                         | (0U << 16U)\r
                         | (0U << 17U)\r
                         | (0U << 18U)\r