Added support for CAN using interrupts

author Michal Horn <hornmich@fel.cvut.cz>

Tue, 14 Aug 2012 12:13:36 +0000 (14:13 +0200)

committer Michal Horn <hornmich@fel.cvut.cz>

Tue, 14 Aug 2012 12:13:36 +0000 (14:13 +0200)
author Michal Horn <hornmich@fel.cvut.cz>
Tue, 14 Aug 2012 12:13:36 +0000 (14:13 +0200)
committer Michal Horn <hornmich@fel.cvut.cz>
Tue, 14 Aug 2012 12:13:36 +0000 (14:13 +0200)
diff --git a/CommandStoring.dil b/CommandStoring.dil

index 0bde8e9995c380822e5b2946bbe927d565760dd4..db5d026f11f47110d47a76d8877e51f3e65b33a7 100644 (file)
--- a/CommandStoring.dil
+++ b/CommandStoring.dil
@@ -1,4 +1,4 @@
-# TMS570LS3137ZWT 08/13/12 14:44:07\r
+# TMS570LS3137ZWT 08/14/12 12:57:59\r
  # \r
  ARCH=TMS570LS3137ZWT\r
  # \r
@@ -196,7 +196,7 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=0\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0\r
-DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=1\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_TYPE.VALUE=IRQ\r
  DRIVER.SYSTEM.VAR.VIM_PARITY_ENABLE.VALUE=FALSE\r
  DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_DP_PBISTCHECK_ENA.VALUE=0x00008000\r
@@ -272,8 +272,8 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=1
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_TYPE.VALUE=IRQ\r
  DRIVER.SYSTEM.VAR.PMM_ENABLE.VALUE=1\r
  DRIVER.SYSTEM.VAR.EMIF_ENABLE.VALUE=0\r
-DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=0\r
-DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=1\r
  DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x0008\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_NAME.VALUE=phantomInterrupt\r
  DRIVER.SYSTEM.VAR.CLKT_PLL1_OUTPUT_DIV.VALUE=2\r
@@ -755,7 +755,7 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_5_DISABLE.VALUE=0
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=1\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_ENABLE.VALUE=0\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_ENABLE.VALUE=0\r
-DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=1\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_ENABLE.VALUE=0\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_TYPE.VALUE=IRQ\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0\r
@@ -775,7 +775,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_ENABLE.VALUE=0
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_TYPE.VALUE=IRQ\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_TYPE.VALUE=IRQ\r
  DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_TYPE.VALUE=IRQ\r
-DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=1\r
  DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DOUT.VALUE=0\r
  DRIVER.SYSTEM.VAR.PBIST_ALGO_1.VALUE=0\r
  DRIVER.SYSTEM.VAR.FLASH_DATA_0_WAIT_STATE_FREQ.VALUE=50.0\r
@@ -2966,7 +2966,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA.VALUE=0x00000000
  DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005\r
-DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x80000000\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0\r
  DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ID.VALUE=62\r
@@ -3462,7 +3462,7 @@ DRIVER.CAN.VAR.CAN_1_PORT_TX_FUN.VALUE=1
  DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ENA.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ENA.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ENA.VALUE=0x00000000\r
-DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000C00\r
  DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000\r
@@ -3781,7 +3781,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_20_MASK.VALUE=0x000007FF
  DRIVER.CAN.VAR.CAN_2_MESSAGE_12_MASK.VALUE=0x000007FF\r
  DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF\r
  DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000\r
-DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000C00\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ID.VALUE=34\r
@@ -3935,7 +3935,7 @@ DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=75.000
  DRIVER.CAN.VAR.CAN_2_MESSAGE_21_MASK.VALUE=0x000007FF\r
  DRIVER.CAN.VAR.CAN_2_MESSAGE_13_MASK.VALUE=0x000007FF\r
  DRIVER.CAN.VAR.CAN_2_MESSAGE_8_MASK.VALUE=0x000007FF\r
-DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ENA.VALUE=0x80000000\r
  DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ID.VALUE=62\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ID.VALUE=54\r
@@ -3948,7 +3948,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DLC.VALUE=8
  DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DLC.VALUE=8\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DLC.VALUE=8\r
  DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=1\r
-DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA.VALUE=0x00000000\r
  DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA.VALUE=0x00000000\r
diff --git a/Debug/CmdProcTISCI.map b/Debug/CmdProcTISCI.map

index c9467dc98c470f5353255add1abb3a371ce8f884..eeedd0c8e576ad5602a8321ca2bd1043d09018c5 100644 (file)
--- a/Debug/CmdProcTISCI.map
+++ b/Debug/CmdProcTISCI.map
@@ -1,10 +1,10 @@
  ******************************************************************************
                    TMS470 Linker Unix v4.9.1                    
  ******************************************************************************
->> Linked Tue Aug 14 11:10:23 2012
+>> Linked Tue Aug 14 13:49:16 2012
  
  OUTPUT FILE NAME:   <CmdProcTISCI.out>
-ENTRY POINT SYMBOL: "_c_int00"  address: 000045e0
+ENTRY POINT SYMBOL: "_c_int00"  address: 0000732c
  
  
  MEMORY CONFIGURATION
@@ -12,25 +12,25 @@ MEMORY CONFIGURATION
           name            origin    length      used     unused   attr    fill
  ----------------------  --------  ---------  --------  --------  ----  --------
    VECTORS               00000000   00000020  00000020  00000000     X
-  FLASH0                00000020   0017ffe0  000088a8  00177738  R  X
+  FLASH0                00000020   0017ffe0  0000bb9c  00174444  R  X
    FLASH1                00180000   00180000  00000000  00180000  R  X
    STACKS                08000000   00001500  00000000  00001500  RW  
-  RAM                   08001500   00026b00  00004234  000228cc  RW  
+  RAM                   08001500   00026b00  0000423c  000228c4  RW  
  
  
  SEGMENT ALLOCATION MAP
  
  run origin  load origin   length   init length attrs members
  ----------  ----------- ---------- ----------- ----- -------
-00000000    00000000    000088c8   000088c8    r-x
+00000000    00000000    0000bbc0   0000bbc0    r-x
    00000000    00000000    00000020   00000020    r-x .intvecs
-  00000020    00000020    00007fb4   00007fb4    r-x .text
-  00007fd4    00007fd4    00000834   00000834    r-- .const
-  00008808    00008808    000000c0   000000c0    r-- .cinit
-08001500    08001500    00004144   00000000    rw-
-  08001500    08001500    00004144   00000000    rw- .bss
-08005644    08005644    000000f0   000000f0    rw-
-  08005644    08005644    000000f0   000000f0    rw- .data
+  00000020    00000020    0000b220   0000b220    r-x .text
+  0000b240    0000b240    000008b4   000008b4    r-- .const
+  0000baf8    0000baf8    000000c8   000000c8    r-- .cinit
+08001500    08001500    00004148   00000000    rw-
+  08001500    08001500    00004148   00000000    rw- .bss
+08005648    08005648    000000f4   000000f4    rw-
+  08005648    08005648    000000f4   000000f4    rw- .data
  
  
  SECTION ALLOCATION MAP
@@ -41,78 +41,82 @@ section   page    origin      length       input sections
  .intvecs   0    00000000    00000020     
                    00000000    00000020     sys_intvecs.obj (.intvecs)
  
-.text      0    00000020    00007fb4     
-                  00000020    000014c8     sys_selftest.obj (.text)
-                  000014e8    00001460     os_tasks.obj (.text)
-                  00002948    00000b48     os_queue.obj (.text)
-                  00003490    00000b18     cmd_proc.obj (.text)
-                  00003fa8    00000638     os_port.obj (.text)
-                  000045e0    000005a8     sys_startup.obj (.text:retain)
-                  00004b88    00000540     sci.obj (.text)
-                  000050c8    0000043c     esm.obj (.text)
-                  00005504    000003cc     cmd_io_line.obj (.text)
-                  000058d0    000003bc     cmdio_tisci.obj (.text)
-                  00005c8c    00000384     sci.obj (.text:retain)
-                  00006010    00000384     sys_core.obj (.text)
-                  00006394    00000308     system.obj (.text)
-                  0000669c    00000300     pinmux.obj (.text)
-                  0000699c    000002b8     i2str.obj (.text)
-                  00006c54    0000029c     commands.obj (.text)
-                  00006ef0    00000240     os_list.obj (.text)
-                  00007130    00000220     esm.obj (.text:retain)
-                  00007350    000001d4     cmd_io.obj (.text)
-                  00007524    00000180     cmd_proc_freertos_tms570.obj (.text)
-                  000076a4    0000016c     os_portasm.obj (.text)
-                  00007810    00000150     cmd_proc_run.obj (.text)
-                  00007960    000000e8     os_heap.obj (.text)
-                  00007a48    000000c0     dabort.obj (.text)
-                  00007b08    0000009c     rtsv7R4_T_be_v3D16_eabi.lib : memcpy_t2.obj (.text)
-                  00007ba4    00000088     notification.obj (.text)
-                  00007c2c    00000078     rtsv7R4_T_be_v3D16_eabi.lib : memset_t2.obj (.text)
-                  00007ca4    00000060                                 : copy_decompress_rle.obj (.text)
-                  00007d04    00000054                                 : u_div32.obj (.text)
-                  00007d58    00000050                                 : atoi.obj (.text)
-                  00007da8    00000050                                 : atol.obj (.text)
-                  00007df8    0000004c                                 : cpy_tbl.obj (.text)
-                  00007e44    00000048     sys_main.obj (.text)
-                  00007e8c    00000044     rtsv7R4_T_be_v3D16_eabi.lib : exit.obj (.text)
-                  00007ed0    00000030                                 : strncpy.obj (.text)
-                  00007f00    00000026                                 : strncmp.obj (.text)
-                  00007f26    00000002     --HOLE-- [fill = 0]
-                  00007f28    00000018                                 : _lock.obj (.text)
-                  00007f40    00000016                                 : strchr.obj (.text)
-                  00007f56    00000014                                 : strlen.obj (.text)
-                  00007f6a    00000012                                 : copy_zero_init.obj (.text:decompress:ZI)
-                  00007f7c    00000010                                 : isalnum.obj (.text)
-                  00007f8c    00000010                                 : isdigit.obj (.text)
-                  00007f9c    00000010                                 : isspace.obj (.text)
-                  00007fac    00000010                                 : strcpy.obj (.text)
-                  00007fbc    0000000e                                 : copy_decompress_none.obj (.text:decompress:none)
-                  00007fca    00000006                                 : copy_decompress_rle.obj (.text:decompress:rle24)
-                  00007fd0    00000004     sys_phantom.obj (.text:retain)
+.text      0    00000020    0000b220     
+                  00000020    00002d4c     can.obj (.text)
+                  00002d6c    000014c8     sys_selftest.obj (.text)
+                  00004234    00001460     os_tasks.obj (.text)
+                  00005694    00000b48     os_queue.obj (.text)
+                  000061dc    00000b18     cmd_proc.obj (.text)
+                  00006cf4    00000638     os_port.obj (.text)
+                  0000732c    000005ac     sys_startup.obj (.text:retain)
+                  000078d8    00000540     sci.obj (.text)
+                  00007e18    0000043c     esm.obj (.text)
+                  00008254    00000424     commands.obj (.text)
+                  00008678    000003cc     cmd_io_line.obj (.text)
+                  00008a44    000003bc     cmdio_tisci.obj (.text)
+                  00008e00    00000384     sci.obj (.text:retain)
+                  00009184    00000384     sys_core.obj (.text)
+                  00009508    00000308     system.obj (.text)
+                  00009810    00000300     pinmux.obj (.text)
+                  00009b10    000002e0     can.obj (.text:retain)
+                  00009df0    000002b8     i2str.obj (.text)
+                  0000a0a8    00000240     os_list.obj (.text)
+                  0000a2e8    00000220     esm.obj (.text:retain)
+                  0000a508    000001d4     cmd_io.obj (.text)
+                  0000a6dc    00000180     cmd_proc_freertos_tms570.obj (.text)
+                  0000a85c    0000016c     os_portasm.obj (.text)
+                  0000a9c8    00000150     cmd_proc_run.obj (.text)
+                  0000ab18    00000120     notification.obj (.text)
+                  0000ac38    000000e8     os_heap.obj (.text)
+                  0000ad20    000000c0     dabort.obj (.text)
+                  0000ade0    0000009c     rtsv7R4_T_be_v3D16_eabi.lib : memcpy_t2.obj (.text)
+                  0000ae7c    00000078                                 : memset_t2.obj (.text)
+                  0000aef4    00000064     sys_main.obj (.text)
+                  0000af58    00000060     rtsv7R4_T_be_v3D16_eabi.lib : copy_decompress_rle.obj (.text)
+                  0000afb8    00000054                                 : u_div32.obj (.text)
+                  0000b00c    00000050                                 : atoi.obj (.text)
+                  0000b05c    00000050                                 : atol.obj (.text)
+                  0000b0ac    0000004c                                 : cpy_tbl.obj (.text)
+                  0000b0f8    00000044                                 : exit.obj (.text)
+                  0000b13c    00000030                                 : strncpy.obj (.text)
+                  0000b16c    00000026                                 : strncmp.obj (.text)
+                  0000b192    00000002     --HOLE-- [fill = 0]
+                  0000b194    00000018                                 : _lock.obj (.text)
+                  0000b1ac    00000016                                 : strchr.obj (.text)
+                  0000b1c2    00000014                                 : strlen.obj (.text)
+                  0000b1d6    00000012                                 : copy_zero_init.obj (.text:decompress:ZI)
+                  0000b1e8    00000010                                 : isalnum.obj (.text)
+                  0000b1f8    00000010                                 : isdigit.obj (.text)
+                  0000b208    00000010                                 : isspace.obj (.text)
+                  0000b218    00000010                                 : strcpy.obj (.text)
+                  0000b228    0000000e                                 : copy_decompress_none.obj (.text:decompress:none)
+                  0000b236    00000006                                 : copy_decompress_rle.obj (.text:decompress:rle24)
+                  0000b23c    00000004     sys_phantom.obj (.text:retain)
  
-.const     0    00007fd4    00000834     
-                  00007fd4    00000304     commands.obj (.const:.string)
-                  000082d8    00000204     sys_startup.obj (.const:s_vim_init)
-                  000084dc    00000187     commands.obj (.const)
-                  00008663    00000001     --HOLE-- [fill = 0]
-                  00008664    00000101     rtsv7R4_T_be_v3D16_eabi.lib : ctype.obj (.const:_ctypes_)
-                  00008765    00000003     --HOLE-- [fill = 0]
-                  00008768    00000038     cmd_proc_freertos_tms570.obj (.const:$P$T0$1)
-                  000087a0    00000026     commands.obj (.const:$P$T0$1)
-                  000087c6    00000002     --HOLE-- [fill = 0]
-                  000087c8    00000023     commands.obj (.const:$P$T1$2)
-                  000087eb    00000001     --HOLE-- [fill = 0]
-                  000087ec    0000001c     cmdio_std_line.obj (.const)
+.const     0    0000b240    000008b4     
+                  0000b240    00000344     commands.obj (.const:.string)
+                  0000b584    00000204     sys_startup.obj (.const:s_vim_init)
+                  0000b788    000001a7     commands.obj (.const)
+                  0000b92f    00000001     --HOLE-- [fill = 0]
+                  0000b930    00000101     rtsv7R4_T_be_v3D16_eabi.lib : ctype.obj (.const:_ctypes_)
+                  0000ba31    00000003     --HOLE-- [fill = 0]
+                  0000ba34    00000038     cmd_proc_freertos_tms570.obj (.const:$P$T0$1)
+                  0000ba6c    00000026     commands.obj (.const:$P$T1$2)
+                  0000ba92    00000002     --HOLE-- [fill = 0]
+                  0000ba94    00000023     commands.obj (.const:$P$T2$3)
+                  0000bab7    00000001     --HOLE-- [fill = 0]
+                  0000bab8    00000020     can.obj (.const)
+                  0000bad8    0000001c     cmdio_std_line.obj (.const)
  
-.cinit     0    00008808    000000c0     
-                  00008808    00000099     (.cinit..data.load) [load image, compression = rle]
-                  000088a1    00000003     --HOLE-- [fill = 0]
-                  000088a4    0000000c     (__TI_handler_table)
-                  000088b0    00000008     (.cinit..bss.load) [load image, compression = zero_init]
-                  000088b8    00000010     (__TI_cinit_table)
+.cinit     0    0000baf8    000000c8     
+                  0000baf8    0000009d     (.cinit..data.load) [load image, compression = rle]
+                  0000bb95    00000003     --HOLE-- [fill = 0]
+                  0000bb98    0000000c     (__TI_handler_table)
+                  0000bba4    00000004     --HOLE-- [fill = 0]
+                  0000bba8    00000008     (.cinit..bss.load) [load image, compression = zero_init]
+                  0000bbb0    00000010     (__TI_cinit_table)
  
-.bss       0    08001500    00004144     UNINITIALIZED
+.bss       0    08001500    00004148     UNINITIALIZED
                    08001500    00003fa0     os_heap.obj (.bss:xHeap)
                    080054a0    00000064     os_tasks.obj (.bss:pxReadyTasksLists)
                    08005504    00000058     os_tasks.obj (.bss)
@@ -121,29 +125,30 @@ section   page    origin      length       input sections
                    08005604    0000001c     sci.obj (.bss)
                    08005620    00000018     cmdio_tisci.obj (.bss)
                    08005638    00000008     cmd_proc_freertos_tms570.obj (.bss)
-                  08005640    00000004     commands.obj (.bss)
+                  08005640    00000008     commands.obj (.bss)
  
-.data      0    08005644    000000f0     
-                  08005644    0000005c     commands.obj (.data)
-                  080056a0    00000030     cmdio_std_line.obj (.data)
-                  080056d0    00000030     os_tasks.obj (.data)
-                  08005700    0000001c     cmdio_tisci.obj (.data)
-                  0800571c    00000008     rtsv7R4_T_be_v3D16_eabi.lib : _lock.obj (.data)
-                  08005724    00000008                                 : exit.obj (.data)
-                  0800572c    00000004     os_heap.obj (.data)
-                  08005730    00000004     os_port.obj (.data)
+.data      0    08005648    000000f4     
+                  08005648    0000003c     commands.obj (.data)
+                  08005684    00000030     cmdio_std_line.obj (.data)
+                  080056b4    00000030     os_tasks.obj (.data)
+                  080056e4    00000024     commands.obj (.data:cmd_list_main)
+                  08005708    0000001c     cmdio_tisci.obj (.data)
+                  08005724    00000008     rtsv7R4_T_be_v3D16_eabi.lib : _lock.obj (.data)
+                  0800572c    00000008                                 : exit.obj (.data)
+                  08005734    00000004     os_heap.obj (.data)
+                  08005738    00000004     os_port.obj (.data)
  
  
  LINKER GENERATED COPY TABLES
  
-__TI_cinit_table @ 000088b8 records: 2, size/record: 8, table size: 16
-       .data: load addr=00008808, load size=00000099 bytes, run addr=08005644, run size=000000f0 bytes, compression=rle
-       .bss: load addr=000088b0, load size=00000008 bytes, run addr=08001500, run size=00004144 bytes, compression=zero_init
+__TI_cinit_table @ 0000bbb0 records: 2, size/record: 8, table size: 16
+       .data: load addr=0000baf8, load size=0000009d bytes, run addr=08005648, run size=000000f4 bytes, compression=rle
+       .bss: load addr=0000bba8, load size=00000008 bytes, run addr=08001500, run size=00004148 bytes, compression=zero_init
  
  
  LINKER GENERATED HANDLER TABLE
  
-__TI_handler_table @ 000088a4 records: 3, size/record: 4, table size: 12
+__TI_handler_table @ 0000bb98 records: 3, size/record: 4, table size: 12
         index: 0, handler: __TI_zero_init
         index: 1, handler: __TI_decompress_rle24
         index: 2, handler: __TI_decompress_none
@@ -153,306 +158,329 @@ GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
  
  address    name
  --------   ----
-00007e8d   C$$EXIT
-000088b8   __TI_CINIT_Base
-000088c8   __TI_CINIT_Limit
-000088a4   __TI_Handler_Table_Base
-000088b0   __TI_Handler_Table_Limit
-0000638c   __TI_PINIT_Base
-00006390   __TI_PINIT_Limit
-00007fbd   __TI_decompress_none
-00007fcb   __TI_decompress_rle24
+0000b0f9   C$$EXIT
+0000bbb0   __TI_CINIT_Base
+0000bbc0   __TI_CINIT_Limit
+0000bb98   __TI_Handler_Table_Base
+0000bba4   __TI_Handler_Table_Limit
+00009500   __TI_PINIT_Base
+00009504   __TI_PINIT_Limit
+0000b229   __TI_decompress_none
+0000b237   __TI_decompress_rle24
  00000000   __TI_static_base__
-00007f6b   __TI_zero_init
-00007c2d   __aeabi_memclr
-00007c2d   __aeabi_memclr4
-00007c2d   __aeabi_memclr8
-00007b09   __aeabi_memcpy
-00007b09   __aeabi_memcpy4
-00007b09   __aeabi_memcpy8
-00007c2f   __aeabi_memset
-00007c2f   __aeabi_memset4
-00007c2f   __aeabi_memset8
-00007d04   __aeabi_uidivmod
+0000b1d7   __TI_zero_init
+0000ae7d   __aeabi_memclr
+0000ae7d   __aeabi_memclr4
+0000ae7d   __aeabi_memclr8
+0000ade1   __aeabi_memcpy
+0000ade1   __aeabi_memcpy4
+0000ade1   __aeabi_memcpy8
+0000ae7f   __aeabi_memset
+0000ae7f   __aeabi_memset4
+0000ae7f   __aeabi_memset8
+0000afb8   __aeabi_uidivmod
  ffffffff   __binit__
  ffffffff   __c_args__
-000045e0   _c_int00
-08005724   _cleanup_ptr
-000062b4   _coreClearAuxiliaryDataFault_
-000062d0   _coreClearAuxiliaryInstructionFault_
-0000627c   _coreClearDataFaultAddress_
-00006244   _coreClearDataFault_
-00006298   _coreClearInstructionFaultAddress_
-00006260   _coreClearInstructionFault_
-000061a8   _coreDisableEventBusExport_
-0000620c   _coreDisableFlashEcc_
-000061d8   _coreDisableRamEcc_
-00006190   _coreEnableEventBusExport_
-000061f0   _coreEnableFlashEcc_
-00006224   _coreEnableIrqVicOffset_
-000061c0   _coreEnableRamEcc_
-00006178   _coreEnableVfp_
-000062ac   _coreGetAuxiliaryDataFault_
-000062c8   _coreGetAuxiliaryInstructionFault_
-00006274   _coreGetDataFaultAddress_
-0000623c   _coreGetDataFault_
-00006290   _coreGetInstructionFaultAddress_
-00006258   _coreGetInstructionFault_
-00006010   _coreInitRegisters_
-00006110   _coreInitStackPointer_
-00008664   _ctypes_
-00007a48   _dabort
-000062ec   _disable_FIQ_interrupt_
-000062f4   _disable_IRQ_interrupt_
-000062e4   _disable_interrupt_
-08005728   _dtors_ptr
-000062fc   _enable_interrupt_
-00006304   _esmCcmErrorsClear_
-0000615c   _getCPSRValue_
-00006164   _gotoCPUIdle_
-0800571c   _lock
-00000138   _memoryInit_
-00007f35   _nop
-00007f2f   _register_lock
-00007f29   _register_unlock
-08005720   _unlock
-00007e91   abort
-00000e28   adc1ParityCheck
-00000e94   adc2ParityCheck
-00007d59   atoi
-00007da9   atol
+0000732c   _c_int00
+0800572c   _cleanup_ptr
+00009428   _coreClearAuxiliaryDataFault_
+00009444   _coreClearAuxiliaryInstructionFault_
+000093f0   _coreClearDataFaultAddress_
+000093b8   _coreClearDataFault_
+0000940c   _coreClearInstructionFaultAddress_
+000093d4   _coreClearInstructionFault_
+0000931c   _coreDisableEventBusExport_
+00009380   _coreDisableFlashEcc_
+0000934c   _coreDisableRamEcc_
+00009304   _coreEnableEventBusExport_
+00009364   _coreEnableFlashEcc_
+00009398   _coreEnableIrqVicOffset_
+00009334   _coreEnableRamEcc_
+000092ec   _coreEnableVfp_
+00009420   _coreGetAuxiliaryDataFault_
+0000943c   _coreGetAuxiliaryInstructionFault_
+000093e8   _coreGetDataFaultAddress_
+000093b0   _coreGetDataFault_
+00009404   _coreGetInstructionFaultAddress_
+000093cc   _coreGetInstructionFault_
+00009184   _coreInitRegisters_
+00009284   _coreInitStackPointer_
+0000b930   _ctypes_
+0000ad20   _dabort
+00009460   _disable_FIQ_interrupt_
+00009468   _disable_IRQ_interrupt_
+00009458   _disable_interrupt_
+08005730   _dtors_ptr
+00009470   _enable_interrupt_
+00009478   _esmCcmErrorsClear_
+000092d0   _getCPSRValue_
+000092d8   _gotoCPUIdle_
+08005724   _lock
+00002e84   _memoryInit_
+0000b1a1   _nop
+0000b19b   _register_lock
+0000b195   _register_unlock
+08005728   _unlock
+0000b0fd   abort
+00003b74   adc1ParityCheck
+00003be0   adc2ParityCheck
+0000b00d   atoi
+0000b05d   atol
  ffffffff   binit
-00000f00   can1ParityCheck
-00000f80   can2ParityCheck
-00001010   can3ParityCheck
-00000104   ccmFail
-00000020   ccmSelfCheck
-00000854   checkB0RAMECC
-00000978   checkB1RAMECC
-00000a98   checkFlashECC
-000006d8   checkefcSelfTest
-00005b08   clearBuffer
-00005ae8   clearInputBuffer
-00005af8   clearOutputBuffer
-000085fc   cmd_des_char
-00008614   cmd_des_charmid
-0000856c   cmd_des_error
-000084dc   cmd_des_help
-0000862c   cmd_des_hiddedn
-000085e4   cmd_des_num
-0000853c   cmd_des_opchar_test
-0000859c   cmd_des_opchar_testro
-00008584   cmd_des_param
-000085cc   cmd_des_prefix
-000085b4   cmd_des_test
-00008554   cmd_des_testio
-000084f4   cmd_des_val
-0000850c   cmd_des_valro
-00008524   cmd_des_valwo
-00003da0   cmd_do_help
-00003bd8   cmd_do_rw_int
-00003c78   cmd_do_rw_long
-00003b38   cmd_do_rw_short
-00003ab4   cmd_do_stamp
-00006db8   cmd_do_test
-00006df0   cmd_do_testcmdio
-00006d9c   cmd_do_testerror
-00006c54   cmd_do_testopchar
-00006d28   cmd_do_testparam
-00005574   cmd_ed_line_buf
-08005700   cmd_io_buf
-000057a4   cmd_io_line_in
-000056ac   cmd_io_line_out
-0000568c   cmd_io_line_putc
-0000587c   cmd_io_line_rdline
-00007394   cmd_io_puts
-000074a0   cmd_io_read_bychar
-000087ec   cmd_io_std_line
-00007428   cmd_io_write_bychar
-0800569c   cmd_list
-08005644   cmd_list_1
-0800565c   cmd_list_2
-0800567c   cmd_list_main
-000039e4   cmd_num_suffix
-00003968   cmd_opchar_check
-00003d18   cmd_opchar_replong
-0000784c   cmd_processor_run
-00007df9   copy_in
-00000224   cpuSelfTest
-00000b68   cpuSelfTestFail
-00000b60   custom_dabort
-00000be0   dmaParityCheck
-080056a0   ed_line_buf_in_std
-080056b8   ed_line_buf_out_std
+00009b10   can1HighLevelInterrupt
+00009bcc   can1LowLevelInterrupt
+00003c4c   can1ParityCheck
+00009c68   can2HighLevelInterrupt
+00009d24   can2LowLevelInterrupt
+00003ccc   can2ParityCheck
+00003d5c   can3ParityCheck
+00002c8c   canDisableErrorNotification
+00002c6c   canEnableErrorNotification
+0000ab60   canErrorNotification
+000029e0   canGetData
+00002c48   canGetErrorLevel
+00002c24   canGetLastError
+00000030   canInit
+00002d38   canIoRxGetBit
+00002cac   canIoSetDirection
+00002ce4   canIoSetPort
+00002d1c   canIoTxGetBit
+00002bc8   canIsMessageBoxValid
+00002b6c   canIsRxMessageArrived
+00002b10   canIsTxMessagePending
+0000ab84   canMessageNotification
+08005640   canMsgReceived
+000028fc   canTransmit
+00002e50   ccmFail
+00002d6c   ccmSelfCheck
+000035a0   checkB0RAMECC
+000036c4   checkB1RAMECC
+000037e4   checkFlashECC
+00003424   checkefcSelfTest
+00008c7c   clearBuffer
+00008c5c   clearInputBuffer
+00008c6c   clearOutputBuffer
+0000b8c0   cmd_des_char
+0000b8d8   cmd_des_charmid
+0000b830   cmd_des_error
+0000b7a0   cmd_des_help
+0000b8f0   cmd_des_hiddedn
+0000b8a8   cmd_des_num
+0000b800   cmd_des_opchar_test
+0000b860   cmd_des_opchar_testro
+0000b848   cmd_des_param
+0000b890   cmd_des_prefix
+0000b878   cmd_des_test
+0000b788   cmd_des_testcanloopback
+0000b818   cmd_des_testio
+0000b7b8   cmd_des_val
+0000b7d0   cmd_des_valro
+0000b7e8   cmd_des_valwo
+00006aec   cmd_do_help
+00006924   cmd_do_rw_int
+000069c4   cmd_do_rw_long
+00006884   cmd_do_rw_short
+00006800   cmd_do_stamp
+000084e4   cmd_do_test
+00008254   cmd_do_testcanloopback
+0000851c   cmd_do_testcmdio
+000084c8   cmd_do_testerror
+00008380   cmd_do_testopchar
+00008454   cmd_do_testparam
+000086e8   cmd_ed_line_buf
+08005708   cmd_io_buf
+00008918   cmd_io_line_in
+00008820   cmd_io_line_out
+00008800   cmd_io_line_putc
+000089f0   cmd_io_line_rdline
+0000a54c   cmd_io_puts
+0000a658   cmd_io_read_bychar
+0000bad8   cmd_io_std_line
+0000a5e0   cmd_io_write_bychar
+08005680   cmd_list
+08005648   cmd_list_1
+08005660   cmd_list_2
+080056e4   cmd_list_main
+00006730   cmd_num_suffix
+000066b4   cmd_opchar_check
+00006a64   cmd_opchar_replong
+0000aa04   cmd_processor_run
+0000b0ad   copy_in
+00002f70   cpuSelfTest
+000038b4   cpuSelfTestFail
+000038ac   custom_dabort
+0000392c   dmaParityCheck
+08005684   ed_line_buf_in_std
+0800569c   ed_line_buf_out_std
  0800555c   ed_line_in_std
  080055b0   ed_line_out_std
-000005a0   efcCheck
-00000770   efcClass1Error
-00000774   efcClass2Error
-000006b0   efcSelfTest
-000005fc   efcStuckZeroTest
-00005278   esmActivateNormalOperation
-00005364   esmClearStatus
-000053a4   esmClearStatusBuffer
-0000523c   esmDisableError
-000052b4   esmDisableInterrupt
-00005210   esmEnableError
-00005288   esmEnableInterrupt
-000051f4   esmError
-000053f0   esmGetStatus
-00005454   esmGetStatusBuffer
-00007ba4   esmGroup1Notification
-00007bb0   esmGroup2Notification
-00007130   esmHighInterrupt
-000050c8   esmInit
-00007274   esmLowInterrupt
-000053d0   esmSetCounterPreloadValue
-000052e0   esmSetInterruptLevel
-00005268   esmTriggerErrorPinReset
-00007e99   exit
-00000b58   flashClass1Error
-00000b5c   flashClass2Error
-00000778   fmcBus2Check
-0000084c   fmcClass1Error
-00000850   fmcClass2Error
-000007b4   fmcECCcheck
+000032ec   efcCheck
+000034bc   efcClass1Error
+000034c0   efcClass2Error
+000033fc   efcSelfTest
+00003348   efcStuckZeroTest
+00007fc8   esmActivateNormalOperation
+000080b4   esmClearStatus
+000080f4   esmClearStatusBuffer
+00007f8c   esmDisableError
+00008004   esmDisableInterrupt
+00007f60   esmEnableError
+00007fd8   esmEnableInterrupt
+00007f44   esmError
+00008140   esmGetStatus
+000081a4   esmGetStatusBuffer
+0000ab18   esmGroup1Notification
+0000ab24   esmGroup2Notification
+0000a2e8   esmHighInterrupt
+00007e18   esmInit
+0000a42c   esmLowInterrupt
+00008120   esmSetCounterPreloadValue
+00008030   esmSetInterruptLevel
+00007fb8   esmTriggerErrorPinReset
+0000b105   exit
+000038a4   flashClass1Error
+000038a8   flashClass2Error
+000034c4   fmcBus2Check
+00003598   fmcClass1Error
+0000359c   fmcClass2Error
+00003500   fmcECCcheck
  08005608   g_sciTransfer
-000059a8   genericPrint
-00005960   genericRead
-00000c54   het1ParityCheck
-00000d30   het2ParityCheck
-00000cbc   htu1ParityCheck
-00000db4   htu2ParityCheck
-0000699c   i2str
+00008b1c   genericPrint
+00008ad4   genericRead
+000039a0   het1ParityCheck
+00003a7c   het2ParityCheck
+00003a08   htu1ParityCheck
+00003b00   htu2ParityCheck
+00009df0   i2str
  0800562c   inBuffer
-00007524   initCmdProc
-000058d0   initIoBuffer
-00007f7d   isalnum
-00007f8d   isdigit
-00007f9d   isspace
-00007e44   main
-000064a8   mapClocks
-00007b09   memcpy
-00007bbc   memoryPort0TestFailNotification
-00007bd4   memoryPort1TestFailNotification
-00007c35   memset
-000010a4   mibspi1ParityCheck
-0000118c   mibspi3ParityCheck
-00001284   mibspi5ParityCheck
-0000669c   muxInit
+0000a6dc   initCmdProc
+00008a44   initIoBuffer
+0000b1e9   isalnum
+0000b1f9   isdigit
+0000b209   isspace
+0000aef4   main
+0000961c   mapClocks
+0000ade1   memcpy
+0000ab30   memoryPort0TestFailNotification
+0000ab48   memoryPort1TestFailNotification
+0000ae85   memset
+00003df0   mibspi1ParityCheck
+00003ed8   mibspi3ParityCheck
+00003fd0   mibspi5ParityCheck
+00009810   muxInit
  08005620   outBuffer
-000004ec   pbistIsTestCompleted
-00000508   pbistIsTestPassed
-00000544   pbistPortTestStatus
-000003e4   pbistRun
-000002a4   pbistSelfCheck
-000003e0   pbistSelfCheckFail
-000004bc   pbistStop
-00006450   periphInit
-00007fd0   phantomInterrupt
-00005930   print
-00003544   proc_cmd_line
-00007644   processCmd
+00003238   pbistIsTestCompleted
+00003254   pbistIsTestPassed
+00003290   pbistPortTestStatus
+00003130   pbistRun
+00002ff0   pbistSelfCheck
+0000312c   pbistSelfCheckFail
+00003208   pbistStop
+000095c4   periphInit
+0000b23c   phantomInterrupt
+00008aa4   print
+00006290   proc_cmd_line
+0000a7fc   processCmd
  08005638   processCmdHandler
  0800563c   prompt
-00007960   pvPortMalloc
-080056d0   pxCurrentTCB
-00003fa8   pxPortInitialiseStack
-00005948   read
-00004f8c   sciDisableLoopback
-00005010   sciDisableNotification
-00004f58   sciEnableLoopback
-00004fa8   sciEnableNotification
-00005c8c   sciHighLevelInterrupt
-00004b88   sciInit
-00004e5c   sciIsRxReady
-00004cfc   sciIsTxReady
-00005e24   sciLowLevelInterrupt
-00007bec   sciNotification
-00004ed0   sciReceive
-00004ea8   sciReceiveByte
-00004e78   sciRxError
-00004d48   sciSend
-00004d18   sciSendByte
-00004c7c   sciSetBaudrate
-00004c5c   sciSetFunctional
-00006410   setupFlash
-00006394   setupPLL
-00003510   skip_white
-0000017c   stcSelfCheck
-00000b64   stcSelfCheckFail
-00007f41   strchr
-00007fad   strcpy
-00007f57   strlen
-00007f01   strncmp
-00007ed1   strncpy
-00006580   systemInit
-0000660c   systemPowerDown
-00000a90   tcramClass1Error
-00000a94   tcramClass2Error
-00005b8c   tisci_getc
-00005b50   tisci_putc
-00005bfc   tisci_read
-00005bbc   tisci_write
-000063c8   trimLPO
-08005730   ulCriticalNesting
-000030bc   uxQueueMessagesWaiting
-000030e0   uxQueueMessagesWaitingFromISR
-00001ebc   uxTaskGetNumberOfTasks
-0000269c   uxTaskGetStackHighWaterMark
-0000184c   uxTaskPriorityGet
-00006ef0   vListInitialise
-00006f48   vListInitialiseItem
-00006fe8   vListInsert
-00006f64   vListInsertEnd
-000070ac   vListRemove
-0000449c   vPortEndScheduler
-000044a0   vPortEnterCritical
-000044b8   vPortExitCritical
-00007a08   vPortFree
-00007a18   vPortInitialiseBlocks
-000076a4   vPortStartFirstTask
-000077fc   vPortYield
-000076d8   vPortYieldProcessor
-00007760   vPreemptiveTick
-00003100   vQueueDelete
-000017e4   vTaskDelay
-000016e8   vTaskDelayUntil
-00001cd8   vTaskEndScheduler
-00001ed0   vTaskIncrementTick
-000023c4   vTaskMissedYield
-00002170   vTaskPlaceOnEventList
-00002860   vTaskPriorityDisinherit
-0000275c   vTaskPriorityInherit
-00001890   vTaskPrioritySet
-00001b98   vTaskResume
-000022bc   vTaskSetTimeOutState
-00001c5c   vTaskStartScheduler
-00001a2c   vTaskSuspend
-00001cf4   vTaskSuspendAll
-000020a8   vTaskSwitchContext
-08005640   val
-00000b6c   vimParityCheck
-00007a28   xPortGetFreeHeapSize
-00004488   xPortStartScheduler
-00002948   xQueueCreate
-00002b34   xQueueCreateCountingSemaphore
-00002a78   xQueueCreateMutex
-00002dc4   xQueueGenericReceive
-00002b70   xQueueGenericSend
-00002cf8   xQueueGenericSendFromISR
-000033ec   xQueueIsQueueEmptyFromISR
-00003458   xQueueIsQueueFullFromISR
-00002ff0   xQueueReceiveFromISR
-000022ec   xTaskCheckForTimeOut
-000014e8   xTaskGenericCreate
-000026ec   xTaskGetCurrentTaskHandle
-0000270c   xTaskGetSchedulerState
-00001e78   xTaskGetTickCount
-00001e98   xTaskGetTickCountFromISR
-00001b04   xTaskIsTaskSuspended
-000021e4   xTaskRemoveFromEventList
-00001d08   xTaskResumeAll
+0000ac38   pvPortMalloc
+080056b4   pxCurrentTCB
+00006cf4   pxPortInitialiseStack
+00008abc   read
+00007cdc   sciDisableLoopback
+00007d60   sciDisableNotification
+00007ca8   sciEnableLoopback
+00007cf8   sciEnableNotification
+00008e00   sciHighLevelInterrupt
+000078d8   sciInit
+00007bac   sciIsRxReady
+00007a4c   sciIsTxReady
+00008f98   sciLowLevelInterrupt
+0000abec   sciNotification
+00007c20   sciReceive
+00007bf8   sciReceiveByte
+00007bc8   sciRxError
+00007a98   sciSend
+00007a68   sciSendByte
+000079cc   sciSetBaudrate
+000079ac   sciSetFunctional
+00009584   setupFlash
+00009508   setupPLL
+0000625c   skip_white
+00002ec8   stcSelfCheck
+000038b0   stcSelfCheckFail
+0000b1ad   strchr
+0000b219   strcpy
+0000b1c3   strlen
+0000b16d   strncmp
+0000b13d   strncpy
+000096f4   systemInit
+00009780   systemPowerDown
+000037dc   tcramClass1Error
+000037e0   tcramClass2Error
+00008d00   tisci_getc
+00008cc4   tisci_putc
+00008d70   tisci_read
+00008d30   tisci_write
+0000953c   trimLPO
+08005738   ulCriticalNesting
+00005e08   uxQueueMessagesWaiting
+00005e2c   uxQueueMessagesWaitingFromISR
+00004c08   uxTaskGetNumberOfTasks
+000053e8   uxTaskGetStackHighWaterMark
+00004598   uxTaskPriorityGet
+0000a0a8   vListInitialise
+0000a100   vListInitialiseItem
+0000a1a0   vListInsert
+0000a11c   vListInsertEnd
+0000a264   vListRemove
+000071e8   vPortEndScheduler
+000071ec   vPortEnterCritical
+00007204   vPortExitCritical
+0000ace0   vPortFree
+0000acf0   vPortInitialiseBlocks
+0000a85c   vPortStartFirstTask
+0000a9b4   vPortYield
+0000a890   vPortYieldProcessor
+0000a918   vPreemptiveTick
+00005e4c   vQueueDelete
+00004530   vTaskDelay
+00004434   vTaskDelayUntil
+00004a24   vTaskEndScheduler
+00004c1c   vTaskIncrementTick
+00005110   vTaskMissedYield
+00004ebc   vTaskPlaceOnEventList
+000055ac   vTaskPriorityDisinherit
+000054a8   vTaskPriorityInherit
+000045dc   vTaskPrioritySet
+000048e4   vTaskResume
+00005008   vTaskSetTimeOutState
+000049a8   vTaskStartScheduler
+00004778   vTaskSuspend
+00004a40   vTaskSuspendAll
+00004df4   vTaskSwitchContext
+08005644   val
+000038b8   vimParityCheck
+0000ad00   xPortGetFreeHeapSize
+000071d4   xPortStartScheduler
+00005694   xQueueCreate
+00005880   xQueueCreateCountingSemaphore
+000057c4   xQueueCreateMutex
+00005b10   xQueueGenericReceive
+000058bc   xQueueGenericSend
+00005a44   xQueueGenericSendFromISR
+00006138   xQueueIsQueueEmptyFromISR
+000061a4   xQueueIsQueueFullFromISR
+00005d3c   xQueueReceiveFromISR
+00005038   xTaskCheckForTimeOut
+00004234   xTaskGenericCreate
+00005438   xTaskGetCurrentTaskHandle
+00005458   xTaskGetSchedulerState
+00004bc4   xTaskGetTickCount
+00004be4   xTaskGetTickCountFromISR
+00004850   xTaskIsTaskSuspended
+00004f30   xTaskRemoveFromEventList
+00004a54   xTaskResumeAll
  
  
  GLOBAL SYMBOLS: SORTED BY Symbol Address 
@@ -460,281 +488,303 @@ GLOBAL SYMBOLS: SORTED BY Symbol Address
  address    name
  --------   ----
  00000000   __TI_static_base__
-00000020   ccmSelfCheck
-00000104   ccmFail
-00000138   _memoryInit_
-0000017c   stcSelfCheck
-00000224   cpuSelfTest
-000002a4   pbistSelfCheck
-000003e0   pbistSelfCheckFail
-000003e4   pbistRun
-000004bc   pbistStop
-000004ec   pbistIsTestCompleted
-00000508   pbistIsTestPassed
-00000544   pbistPortTestStatus
-000005a0   efcCheck
-000005fc   efcStuckZeroTest
-000006b0   efcSelfTest
-000006d8   checkefcSelfTest
-00000770   efcClass1Error
-00000774   efcClass2Error
-00000778   fmcBus2Check
-000007b4   fmcECCcheck
-0000084c   fmcClass1Error
-00000850   fmcClass2Error
-00000854   checkB0RAMECC
-00000978   checkB1RAMECC
-00000a90   tcramClass1Error
-00000a94   tcramClass2Error
-00000a98   checkFlashECC
-00000b58   flashClass1Error
-00000b5c   flashClass2Error
-00000b60   custom_dabort
-00000b64   stcSelfCheckFail
-00000b68   cpuSelfTestFail
-00000b6c   vimParityCheck
-00000be0   dmaParityCheck
-00000c54   het1ParityCheck
-00000cbc   htu1ParityCheck
-00000d30   het2ParityCheck
-00000db4   htu2ParityCheck
-00000e28   adc1ParityCheck
-00000e94   adc2ParityCheck
-00000f00   can1ParityCheck
-00000f80   can2ParityCheck
-00001010   can3ParityCheck
-000010a4   mibspi1ParityCheck
-0000118c   mibspi3ParityCheck
-00001284   mibspi5ParityCheck
-000014e8   xTaskGenericCreate
-000016e8   vTaskDelayUntil
-000017e4   vTaskDelay
-0000184c   uxTaskPriorityGet
-00001890   vTaskPrioritySet
-00001a2c   vTaskSuspend
-00001b04   xTaskIsTaskSuspended
-00001b98   vTaskResume
-00001c5c   vTaskStartScheduler
-00001cd8   vTaskEndScheduler
-00001cf4   vTaskSuspendAll
-00001d08   xTaskResumeAll
-00001e78   xTaskGetTickCount
-00001e98   xTaskGetTickCountFromISR
-00001ebc   uxTaskGetNumberOfTasks
-00001ed0   vTaskIncrementTick
-000020a8   vTaskSwitchContext
-00002170   vTaskPlaceOnEventList
-000021e4   xTaskRemoveFromEventList
-000022bc   vTaskSetTimeOutState
-000022ec   xTaskCheckForTimeOut
-000023c4   vTaskMissedYield
-0000269c   uxTaskGetStackHighWaterMark
-000026ec   xTaskGetCurrentTaskHandle
-0000270c   xTaskGetSchedulerState
-0000275c   vTaskPriorityInherit
-00002860   vTaskPriorityDisinherit
-00002948   xQueueCreate
-00002a78   xQueueCreateMutex
-00002b34   xQueueCreateCountingSemaphore
-00002b70   xQueueGenericSend
-00002cf8   xQueueGenericSendFromISR
-00002dc4   xQueueGenericReceive
-00002ff0   xQueueReceiveFromISR
-000030bc   uxQueueMessagesWaiting
-000030e0   uxQueueMessagesWaitingFromISR
-00003100   vQueueDelete
-000033ec   xQueueIsQueueEmptyFromISR
-00003458   xQueueIsQueueFullFromISR
-00003510   skip_white
-00003544   proc_cmd_line
-00003968   cmd_opchar_check
-000039e4   cmd_num_suffix
-00003ab4   cmd_do_stamp
-00003b38   cmd_do_rw_short
-00003bd8   cmd_do_rw_int
-00003c78   cmd_do_rw_long
-00003d18   cmd_opchar_replong
-00003da0   cmd_do_help
-00003fa8   pxPortInitialiseStack
-00004488   xPortStartScheduler
-0000449c   vPortEndScheduler
-000044a0   vPortEnterCritical
-000044b8   vPortExitCritical
-000045e0   _c_int00
-00004b88   sciInit
-00004c5c   sciSetFunctional
-00004c7c   sciSetBaudrate
-00004cfc   sciIsTxReady
-00004d18   sciSendByte
-00004d48   sciSend
-00004e5c   sciIsRxReady
-00004e78   sciRxError
-00004ea8   sciReceiveByte
-00004ed0   sciReceive
-00004f58   sciEnableLoopback
-00004f8c   sciDisableLoopback
-00004fa8   sciEnableNotification
-00005010   sciDisableNotification
-000050c8   esmInit
-000051f4   esmError
-00005210   esmEnableError
-0000523c   esmDisableError
-00005268   esmTriggerErrorPinReset
-00005278   esmActivateNormalOperation
-00005288   esmEnableInterrupt
-000052b4   esmDisableInterrupt
-000052e0   esmSetInterruptLevel
-00005364   esmClearStatus
-000053a4   esmClearStatusBuffer
-000053d0   esmSetCounterPreloadValue
-000053f0   esmGetStatus
-00005454   esmGetStatusBuffer
-00005574   cmd_ed_line_buf
-0000568c   cmd_io_line_putc
-000056ac   cmd_io_line_out
-000057a4   cmd_io_line_in
-0000587c   cmd_io_line_rdline
-000058d0   initIoBuffer
-00005930   print
-00005948   read
-00005960   genericRead
-000059a8   genericPrint
-00005ae8   clearInputBuffer
-00005af8   clearOutputBuffer
-00005b08   clearBuffer
-00005b50   tisci_putc
-00005b8c   tisci_getc
-00005bbc   tisci_write
-00005bfc   tisci_read
-00005c8c   sciHighLevelInterrupt
-00005e24   sciLowLevelInterrupt
-00006010   _coreInitRegisters_
-00006110   _coreInitStackPointer_
-0000615c   _getCPSRValue_
-00006164   _gotoCPUIdle_
-00006178   _coreEnableVfp_
-00006190   _coreEnableEventBusExport_
-000061a8   _coreDisableEventBusExport_
-000061c0   _coreEnableRamEcc_
-000061d8   _coreDisableRamEcc_
-000061f0   _coreEnableFlashEcc_
-0000620c   _coreDisableFlashEcc_
-00006224   _coreEnableIrqVicOffset_
-0000623c   _coreGetDataFault_
-00006244   _coreClearDataFault_
-00006258   _coreGetInstructionFault_
-00006260   _coreClearInstructionFault_
-00006274   _coreGetDataFaultAddress_
-0000627c   _coreClearDataFaultAddress_
-00006290   _coreGetInstructionFaultAddress_
-00006298   _coreClearInstructionFaultAddress_
-000062ac   _coreGetAuxiliaryDataFault_
-000062b4   _coreClearAuxiliaryDataFault_
-000062c8   _coreGetAuxiliaryInstructionFault_
-000062d0   _coreClearAuxiliaryInstructionFault_
-000062e4   _disable_interrupt_
-000062ec   _disable_FIQ_interrupt_
-000062f4   _disable_IRQ_interrupt_
-000062fc   _enable_interrupt_
-00006304   _esmCcmErrorsClear_
-0000638c   __TI_PINIT_Base
-00006390   __TI_PINIT_Limit
-00006394   setupPLL
-000063c8   trimLPO
-00006410   setupFlash
-00006450   periphInit
-000064a8   mapClocks
-00006580   systemInit
-0000660c   systemPowerDown
-0000669c   muxInit
-0000699c   i2str
-00006c54   cmd_do_testopchar
-00006d28   cmd_do_testparam
-00006d9c   cmd_do_testerror
-00006db8   cmd_do_test
-00006df0   cmd_do_testcmdio
-00006ef0   vListInitialise
-00006f48   vListInitialiseItem
-00006f64   vListInsertEnd
-00006fe8   vListInsert
-000070ac   vListRemove
-00007130   esmHighInterrupt
-00007274   esmLowInterrupt
-00007394   cmd_io_puts
-00007428   cmd_io_write_bychar
-000074a0   cmd_io_read_bychar
-00007524   initCmdProc
-00007644   processCmd
-000076a4   vPortStartFirstTask
-000076d8   vPortYieldProcessor
-00007760   vPreemptiveTick
-000077fc   vPortYield
-0000784c   cmd_processor_run
-00007960   pvPortMalloc
-00007a08   vPortFree
-00007a18   vPortInitialiseBlocks
-00007a28   xPortGetFreeHeapSize
-00007a48   _dabort
-00007b09   __aeabi_memcpy
-00007b09   __aeabi_memcpy4
-00007b09   __aeabi_memcpy8
-00007b09   memcpy
-00007ba4   esmGroup1Notification
-00007bb0   esmGroup2Notification
-00007bbc   memoryPort0TestFailNotification
-00007bd4   memoryPort1TestFailNotification
-00007bec   sciNotification
-00007c2d   __aeabi_memclr
-00007c2d   __aeabi_memclr4
-00007c2d   __aeabi_memclr8
-00007c2f   __aeabi_memset
-00007c2f   __aeabi_memset4
-00007c2f   __aeabi_memset8
-00007c35   memset
-00007d04   __aeabi_uidivmod
-00007d59   atoi
-00007da9   atol
-00007df9   copy_in
-00007e44   main
-00007e8d   C$$EXIT
-00007e91   abort
-00007e99   exit
-00007ed1   strncpy
-00007f01   strncmp
-00007f29   _register_unlock
-00007f2f   _register_lock
-00007f35   _nop
-00007f41   strchr
-00007f57   strlen
-00007f6b   __TI_zero_init
-00007f7d   isalnum
-00007f8d   isdigit
-00007f9d   isspace
-00007fad   strcpy
-00007fbd   __TI_decompress_none
-00007fcb   __TI_decompress_rle24
-00007fd0   phantomInterrupt
-000084dc   cmd_des_help
-000084f4   cmd_des_val
-0000850c   cmd_des_valro
-00008524   cmd_des_valwo
-0000853c   cmd_des_opchar_test
-00008554   cmd_des_testio
-0000856c   cmd_des_error
-00008584   cmd_des_param
-0000859c   cmd_des_opchar_testro
-000085b4   cmd_des_test
-000085cc   cmd_des_prefix
-000085e4   cmd_des_num
-000085fc   cmd_des_char
-00008614   cmd_des_charmid
-0000862c   cmd_des_hiddedn
-00008664   _ctypes_
-000087ec   cmd_io_std_line
-000088a4   __TI_Handler_Table_Base
-000088b0   __TI_Handler_Table_Limit
-000088b8   __TI_CINIT_Base
-000088c8   __TI_CINIT_Limit
+00000030   canInit
+000028fc   canTransmit
+000029e0   canGetData
+00002b10   canIsTxMessagePending
+00002b6c   canIsRxMessageArrived
+00002bc8   canIsMessageBoxValid
+00002c24   canGetLastError
+00002c48   canGetErrorLevel
+00002c6c   canEnableErrorNotification
+00002c8c   canDisableErrorNotification
+00002cac   canIoSetDirection
+00002ce4   canIoSetPort
+00002d1c   canIoTxGetBit
+00002d38   canIoRxGetBit
+00002d6c   ccmSelfCheck
+00002e50   ccmFail
+00002e84   _memoryInit_
+00002ec8   stcSelfCheck
+00002f70   cpuSelfTest
+00002ff0   pbistSelfCheck
+0000312c   pbistSelfCheckFail
+00003130   pbistRun
+00003208   pbistStop
+00003238   pbistIsTestCompleted
+00003254   pbistIsTestPassed
+00003290   pbistPortTestStatus
+000032ec   efcCheck
+00003348   efcStuckZeroTest
+000033fc   efcSelfTest
+00003424   checkefcSelfTest
+000034bc   efcClass1Error
+000034c0   efcClass2Error
+000034c4   fmcBus2Check
+00003500   fmcECCcheck
+00003598   fmcClass1Error
+0000359c   fmcClass2Error
+000035a0   checkB0RAMECC
+000036c4   checkB1RAMECC
+000037dc   tcramClass1Error
+000037e0   tcramClass2Error
+000037e4   checkFlashECC
+000038a4   flashClass1Error
+000038a8   flashClass2Error
+000038ac   custom_dabort
+000038b0   stcSelfCheckFail
+000038b4   cpuSelfTestFail
+000038b8   vimParityCheck
+0000392c   dmaParityCheck
+000039a0   het1ParityCheck
+00003a08   htu1ParityCheck
+00003a7c   het2ParityCheck
+00003b00   htu2ParityCheck
+00003b74   adc1ParityCheck
+00003be0   adc2ParityCheck
+00003c4c   can1ParityCheck
+00003ccc   can2ParityCheck
+00003d5c   can3ParityCheck
+00003df0   mibspi1ParityCheck
+00003ed8   mibspi3ParityCheck
+00003fd0   mibspi5ParityCheck
+00004234   xTaskGenericCreate
+00004434   vTaskDelayUntil
+00004530   vTaskDelay
+00004598   uxTaskPriorityGet
+000045dc   vTaskPrioritySet
+00004778   vTaskSuspend
+00004850   xTaskIsTaskSuspended
+000048e4   vTaskResume
+000049a8   vTaskStartScheduler
+00004a24   vTaskEndScheduler
+00004a40   vTaskSuspendAll
+00004a54   xTaskResumeAll
+00004bc4   xTaskGetTickCount
+00004be4   xTaskGetTickCountFromISR
+00004c08   uxTaskGetNumberOfTasks
+00004c1c   vTaskIncrementTick
+00004df4   vTaskSwitchContext
+00004ebc   vTaskPlaceOnEventList
+00004f30   xTaskRemoveFromEventList
+00005008   vTaskSetTimeOutState
+00005038   xTaskCheckForTimeOut
+00005110   vTaskMissedYield
+000053e8   uxTaskGetStackHighWaterMark
+00005438   xTaskGetCurrentTaskHandle
+00005458   xTaskGetSchedulerState
+000054a8   vTaskPriorityInherit
+000055ac   vTaskPriorityDisinherit
+00005694   xQueueCreate
+000057c4   xQueueCreateMutex
+00005880   xQueueCreateCountingSemaphore
+000058bc   xQueueGenericSend
+00005a44   xQueueGenericSendFromISR
+00005b10   xQueueGenericReceive
+00005d3c   xQueueReceiveFromISR
+00005e08   uxQueueMessagesWaiting
+00005e2c   uxQueueMessagesWaitingFromISR
+00005e4c   vQueueDelete
+00006138   xQueueIsQueueEmptyFromISR
+000061a4   xQueueIsQueueFullFromISR
+0000625c   skip_white
+00006290   proc_cmd_line
+000066b4   cmd_opchar_check
+00006730   cmd_num_suffix
+00006800   cmd_do_stamp
+00006884   cmd_do_rw_short
+00006924   cmd_do_rw_int
+000069c4   cmd_do_rw_long
+00006a64   cmd_opchar_replong
+00006aec   cmd_do_help
+00006cf4   pxPortInitialiseStack
+000071d4   xPortStartScheduler
+000071e8   vPortEndScheduler
+000071ec   vPortEnterCritical
+00007204   vPortExitCritical
+0000732c   _c_int00
+000078d8   sciInit
+000079ac   sciSetFunctional
+000079cc   sciSetBaudrate
+00007a4c   sciIsTxReady
+00007a68   sciSendByte
+00007a98   sciSend
+00007bac   sciIsRxReady
+00007bc8   sciRxError
+00007bf8   sciReceiveByte
+00007c20   sciReceive
+00007ca8   sciEnableLoopback
+00007cdc   sciDisableLoopback
+00007cf8   sciEnableNotification
+00007d60   sciDisableNotification
+00007e18   esmInit
+00007f44   esmError
+00007f60   esmEnableError
+00007f8c   esmDisableError
+00007fb8   esmTriggerErrorPinReset
+00007fc8   esmActivateNormalOperation
+00007fd8   esmEnableInterrupt
+00008004   esmDisableInterrupt
+00008030   esmSetInterruptLevel
+000080b4   esmClearStatus
+000080f4   esmClearStatusBuffer
+00008120   esmSetCounterPreloadValue
+00008140   esmGetStatus
+000081a4   esmGetStatusBuffer
+00008254   cmd_do_testcanloopback
+00008380   cmd_do_testopchar
+00008454   cmd_do_testparam
+000084c8   cmd_do_testerror
+000084e4   cmd_do_test
+0000851c   cmd_do_testcmdio
+000086e8   cmd_ed_line_buf
+00008800   cmd_io_line_putc
+00008820   cmd_io_line_out
+00008918   cmd_io_line_in
+000089f0   cmd_io_line_rdline
+00008a44   initIoBuffer
+00008aa4   print
+00008abc   read
+00008ad4   genericRead
+00008b1c   genericPrint
+00008c5c   clearInputBuffer
+00008c6c   clearOutputBuffer
+00008c7c   clearBuffer
+00008cc4   tisci_putc
+00008d00   tisci_getc
+00008d30   tisci_write
+00008d70   tisci_read
+00008e00   sciHighLevelInterrupt
+00008f98   sciLowLevelInterrupt
+00009184   _coreInitRegisters_
+00009284   _coreInitStackPointer_
+000092d0   _getCPSRValue_
+000092d8   _gotoCPUIdle_
+000092ec   _coreEnableVfp_
+00009304   _coreEnableEventBusExport_
+0000931c   _coreDisableEventBusExport_
+00009334   _coreEnableRamEcc_
+0000934c   _coreDisableRamEcc_
+00009364   _coreEnableFlashEcc_
+00009380   _coreDisableFlashEcc_
+00009398   _coreEnableIrqVicOffset_
+000093b0   _coreGetDataFault_
+000093b8   _coreClearDataFault_
+000093cc   _coreGetInstructionFault_
+000093d4   _coreClearInstructionFault_
+000093e8   _coreGetDataFaultAddress_
+000093f0   _coreClearDataFaultAddress_
+00009404   _coreGetInstructionFaultAddress_
+0000940c   _coreClearInstructionFaultAddress_
+00009420   _coreGetAuxiliaryDataFault_
+00009428   _coreClearAuxiliaryDataFault_
+0000943c   _coreGetAuxiliaryInstructionFault_
+00009444   _coreClearAuxiliaryInstructionFault_
+00009458   _disable_interrupt_
+00009460   _disable_FIQ_interrupt_
+00009468   _disable_IRQ_interrupt_
+00009470   _enable_interrupt_
+00009478   _esmCcmErrorsClear_
+00009500   __TI_PINIT_Base
+00009504   __TI_PINIT_Limit
+00009508   setupPLL
+0000953c   trimLPO
+00009584   setupFlash
+000095c4   periphInit
+0000961c   mapClocks
+000096f4   systemInit
+00009780   systemPowerDown
+00009810   muxInit
+00009b10   can1HighLevelInterrupt
+00009bcc   can1LowLevelInterrupt
+00009c68   can2HighLevelInterrupt
+00009d24   can2LowLevelInterrupt
+00009df0   i2str
+0000a0a8   vListInitialise
+0000a100   vListInitialiseItem
+0000a11c   vListInsertEnd
+0000a1a0   vListInsert
+0000a264   vListRemove
+0000a2e8   esmHighInterrupt
+0000a42c   esmLowInterrupt
+0000a54c   cmd_io_puts
+0000a5e0   cmd_io_write_bychar
+0000a658   cmd_io_read_bychar
+0000a6dc   initCmdProc
+0000a7fc   processCmd
+0000a85c   vPortStartFirstTask
+0000a890   vPortYieldProcessor
+0000a918   vPreemptiveTick
+0000a9b4   vPortYield
+0000aa04   cmd_processor_run
+0000ab18   esmGroup1Notification
+0000ab24   esmGroup2Notification
+0000ab30   memoryPort0TestFailNotification
+0000ab48   memoryPort1TestFailNotification
+0000ab60   canErrorNotification
+0000ab84   canMessageNotification
+0000abec   sciNotification
+0000ac38   pvPortMalloc
+0000ace0   vPortFree
+0000acf0   vPortInitialiseBlocks
+0000ad00   xPortGetFreeHeapSize
+0000ad20   _dabort
+0000ade1   __aeabi_memcpy
+0000ade1   __aeabi_memcpy4
+0000ade1   __aeabi_memcpy8
+0000ade1   memcpy
+0000ae7d   __aeabi_memclr
+0000ae7d   __aeabi_memclr4
+0000ae7d   __aeabi_memclr8
+0000ae7f   __aeabi_memset
+0000ae7f   __aeabi_memset4
+0000ae7f   __aeabi_memset8
+0000ae85   memset
+0000aef4   main
+0000afb8   __aeabi_uidivmod
+0000b00d   atoi
+0000b05d   atol
+0000b0ad   copy_in
+0000b0f9   C$$EXIT
+0000b0fd   abort
+0000b105   exit
+0000b13d   strncpy
+0000b16d   strncmp
+0000b195   _register_unlock
+0000b19b   _register_lock
+0000b1a1   _nop
+0000b1ad   strchr
+0000b1c3   strlen
+0000b1d7   __TI_zero_init
+0000b1e9   isalnum
+0000b1f9   isdigit
+0000b209   isspace
+0000b219   strcpy
+0000b229   __TI_decompress_none
+0000b237   __TI_decompress_rle24
+0000b23c   phantomInterrupt
+0000b788   cmd_des_testcanloopback
+0000b7a0   cmd_des_help
+0000b7b8   cmd_des_val
+0000b7d0   cmd_des_valro
+0000b7e8   cmd_des_valwo
+0000b800   cmd_des_opchar_test
+0000b818   cmd_des_testio
+0000b830   cmd_des_error
+0000b848   cmd_des_param
+0000b860   cmd_des_opchar_testro
+0000b878   cmd_des_test
+0000b890   cmd_des_prefix
+0000b8a8   cmd_des_num
+0000b8c0   cmd_des_char
+0000b8d8   cmd_des_charmid
+0000b8f0   cmd_des_hiddedn
+0000b930   _ctypes_
+0000bad8   cmd_io_std_line
+0000bb98   __TI_Handler_Table_Base
+0000bba4   __TI_Handler_Table_Limit
+0000bbb0   __TI_CINIT_Base
+0000bbc0   __TI_CINIT_Limit
  0800555c   ed_line_in_std
  080055b0   ed_line_out_std
  08005608   g_sciTransfer
@@ -742,22 +792,23 @@ address    name
  0800562c   inBuffer
  08005638   processCmdHandler
  0800563c   prompt
-08005640   val
-08005644   cmd_list_1
-0800565c   cmd_list_2
-0800567c   cmd_list_main
-0800569c   cmd_list
-080056a0   ed_line_buf_in_std
-080056b8   ed_line_buf_out_std
-080056d0   pxCurrentTCB
-08005700   cmd_io_buf
-0800571c   _lock
-08005720   _unlock
-08005724   _cleanup_ptr
-08005728   _dtors_ptr
-08005730   ulCriticalNesting
+08005640   canMsgReceived
+08005644   val
+08005648   cmd_list_1
+08005660   cmd_list_2
+08005680   cmd_list
+08005684   ed_line_buf_in_std
+0800569c   ed_line_buf_out_std
+080056b4   pxCurrentTCB
+080056e4   cmd_list_main
+08005708   cmd_io_buf
+08005724   _lock
+08005728   _unlock
+0800572c   _cleanup_ptr
+08005730   _dtors_ptr
+08005738   ulCriticalNesting
  ffffffff   __binit__
  ffffffff   __c_args__
  ffffffff   binit
  
-[300 symbols]
+[323 symbols]
diff --git a/Debug/CmdProcTISCI.out b/Debug/CmdProcTISCI.out

index f87a02660bed653fa9ced61ca8bc07408e409ffb..85506c8686c149be81ee483330e4597ca46bbf94 100644 (file)

Binary files a/Debug/CmdProcTISCI.out and b/Debug/CmdProcTISCI.out differ
diff --git a/Debug/ccsObjs.opt b/Debug/ccsObjs.opt

index c1d6f03aafcb6cd79640f67b1d27f2a320c25457..6f0224db88cc86fb033263b70c17b2d6a4dd1005 100644 (file)
--- a/Debug/ccsObjs.opt
+++ b/Debug/ccsObjs.opt
@@ -1 +1 @@
-"./source/system.obj" "./source/sys_startup.obj" "./source/sys_selftest.obj" "./source/sys_pmu.obj" "./source/sys_phantom.obj" "./source/sys_mpu.obj" "./source/sys_main.obj" "./source/sys_intvecs.obj" "./source/sys_core.obj" "./source/sci.obj" "./source/pinmux.obj" "./source/os_timer.obj" "./source/os_tasks.obj" "./source/os_queue.obj" "./source/os_portasm.obj" "./source/os_port.obj" "./source/os_list.obj" "./source/os_heap.obj" "./source/os_croutine.obj" "./source/notification.obj" "./source/i2str.obj" "./source/esm.obj" "./source/dabort.obj" "./source/commands.obj" "./source/cmdio_tisci.obj" "./source/cmdio_std_line.obj" "./source/cmd_proc_run.obj" "./source/cmd_proc_freertos_tms570.obj" "./source/cmd_proc.obj" "./source/cmd_io_line.obj" "./source/cmd_io.obj" -l"rtsv7R4_T_be_v3D16_eabi.lib" "../source/sys_link.cmd" 
-\ No newline at end of file
+"./source/system.obj" "./source/sys_startup.obj" "./source/sys_selftest.obj" "./source/sys_pmu.obj" "./source/sys_phantom.obj" "./source/sys_mpu.obj" "./source/sys_main.obj" "./source/sys_intvecs.obj" "./source/sys_core.obj" "./source/sci.obj" "./source/pinmux.obj" "./source/os_timer.obj" "./source/os_tasks.obj" "./source/os_queue.obj" "./source/os_portasm.obj" "./source/os_port.obj" "./source/os_list.obj" "./source/os_heap.obj" "./source/os_croutine.obj" "./source/notification.obj" "./source/i2str.obj" "./source/esm.obj" "./source/dma.obj" "./source/dabort.obj" "./source/commands.obj" "./source/cmdio_tisci.obj" "./source/cmdio_std_line.obj" "./source/cmd_proc_run.obj" "./source/cmd_proc_freertos_tms570.obj" "./source/cmd_proc.obj" "./source/cmd_io_line.obj" "./source/cmd_io.obj" "./source/can.obj" -l"rtsv7R4_T_be_v3D16_eabi.lib" "../source/sys_link.cmd" 
+\ No newline at end of file
diff --git a/Debug/makefile b/Debug/makefile

index 1ee085657d3c7ab055a03930eab0553b0f17b70b..23585c9c5aeab67f848bb15ecfc779e2a1e21707 100644 (file)
--- a/Debug/makefile
+++ b/Debug/makefile
@@ -28,6 +28,7 @@ $(GEN_CMDS__FLAG) \
  "./source/notification.obj" \
  "./source/i2str.obj" \
  "./source/esm.obj" \
+"./source/dma.obj" \
  "./source/dabort.obj" \
  "./source/commands.obj" \
  "./source/cmdio_tisci.obj" \
@@ -37,6 +38,7 @@ $(GEN_CMDS__FLAG) \
  "./source/cmd_proc.obj" \
  "./source/cmd_io_line.obj" \
  "./source/cmd_io.obj" \
+"./source/can.obj" \
  -l"rtsv7R4_T_be_v3D16_eabi.lib" \
  "../source/sys_link.cmd" \
  
@@ -150,8 +152,8 @@ CmdProcTISCI.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
  # Other Targets
  clean:
         -$(RM) $(TMS470_EXECUTABLE_OUTPUTS__QUOTED) "CmdProcTISCI.out"
-       -$(RM) "source/cmd_io.pp" "source/cmd_io_line.pp" "source/cmd_proc.pp" "source/cmd_proc_freertos_tms570.pp" "source/cmd_proc_run.pp" "source/cmdio_std_line.pp" "source/cmdio_tisci.pp" "source/commands.pp" "source/esm.pp" "source/i2str.pp" "source/notification.pp" "source/os_croutine.pp" "source/os_heap.pp" "source/os_list.pp" "source/os_port.pp" "source/os_queue.pp" "source/os_tasks.pp" "source/os_timer.pp" "source/pinmux.pp" "source/sci.pp" "source/sys_main.pp" "source/sys_phantom.pp" "source/sys_selftest.pp" "source/sys_startup.pp" "source/system.pp" 
-       -$(RM) "source/cmd_io.obj" "source/cmd_io_line.obj" "source/cmd_proc.obj" "source/cmd_proc_freertos_tms570.obj" "source/cmd_proc_run.obj" "source/cmdio_std_line.obj" "source/cmdio_tisci.obj" "source/commands.obj" "source/dabort.obj" "source/esm.obj" "source/i2str.obj" "source/notification.obj" "source/os_croutine.obj" "source/os_heap.obj" "source/os_list.obj" "source/os_port.obj" "source/os_portasm.obj" "source/os_queue.obj" "source/os_tasks.obj" "source/os_timer.obj" "source/pinmux.obj" "source/sci.obj" "source/sys_core.obj" "source/sys_intvecs.obj" "source/sys_main.obj" "source/sys_mpu.obj" "source/sys_phantom.obj" "source/sys_pmu.obj" "source/sys_selftest.obj" "source/sys_startup.obj" "source/system.obj" 
+       -$(RM) "source/can.pp" "source/cmd_io.pp" "source/cmd_io_line.pp" "source/cmd_proc.pp" "source/cmd_proc_freertos_tms570.pp" "source/cmd_proc_run.pp" "source/cmdio_std_line.pp" "source/cmdio_tisci.pp" "source/commands.pp" "source/dma.pp" "source/esm.pp" "source/i2str.pp" "source/notification.pp" "source/os_croutine.pp" "source/os_heap.pp" "source/os_list.pp" "source/os_port.pp" "source/os_queue.pp" "source/os_tasks.pp" "source/os_timer.pp" "source/pinmux.pp" "source/sci.pp" "source/sys_main.pp" "source/sys_phantom.pp" "source/sys_selftest.pp" "source/sys_startup.pp" "source/system.pp" 
+       -$(RM) "source/can.obj" "source/cmd_io.obj" "source/cmd_io_line.obj" "source/cmd_proc.obj" "source/cmd_proc_freertos_tms570.obj" "source/cmd_proc_run.obj" "source/cmdio_std_line.obj" "source/cmdio_tisci.obj" "source/commands.obj" "source/dabort.obj" "source/dma.obj" "source/esm.obj" "source/i2str.obj" "source/notification.obj" "source/os_croutine.obj" "source/os_heap.obj" "source/os_list.obj" "source/os_port.obj" "source/os_portasm.obj" "source/os_queue.obj" "source/os_tasks.obj" "source/os_timer.obj" "source/pinmux.obj" "source/sci.obj" "source/sys_core.obj" "source/sys_intvecs.obj" "source/sys_main.obj" "source/sys_mpu.obj" "source/sys_phantom.obj" "source/sys_pmu.obj" "source/sys_selftest.obj" "source/sys_startup.obj" "source/system.obj" 
         -$(RM) "source/dabort.pp" "source/os_portasm.pp" "source/sys_core.pp" "source/sys_intvecs.pp" "source/sys_mpu.pp" "source/sys_pmu.pp" 
         -@echo 'Finished clean'
         -@echo ' '
diff --git a/Debug/source/can.obj b/Debug/source/can.obj

new file mode 100644 (file)

index 0000000..edb5bd2

Binary files /dev/null and b/Debug/source/can.obj differ
diff --git a/Debug/source/can.pp b/Debug/source/can.pp

new file mode 100644 (file)

index 0000000..966e904
--- /dev/null
+++ b/Debug/source/can.pp
@@ -0,0 +1,9 @@
+# FIXED
+
+source/can.obj: ../source/can.c
+source/can.obj: ../include/can.h
+source/can.obj: ../include/sys_common.h
+
+../source/can.c: 
+../include/can.h: 
+../include/sys_common.h: 
diff --git a/Debug/source/ccsSrcs.opt b/Debug/source/ccsSrcs.opt

index bb296b630086781161dae92872cb971ccd17943c..515d1fd1dcf6c933ff706803bce8096fd296bab5 100644 (file)
--- a/Debug/source/ccsSrcs.opt
+++ b/Debug/source/ccsSrcs.opt
@@ -1 +1 @@
-"../source/cmd_io.c" "../source/cmd_io_line.c" "../source/cmd_proc.c" "../source/cmd_proc_freertos_tms570.c" "../source/cmd_proc_run.c" "../source/cmdio_std_line.c" "../source/cmdio_tisci.c" "../source/commands.c" "../source/dabort.asm" "../source/esm.c" "../source/i2str.c" "../source/notification.c" "../source/os_croutine.c" "../source/os_heap.c" "../source/os_list.c" "../source/os_port.c" "../source/os_portasm.asm" "../source/os_queue.c" "../source/os_tasks.c" "../source/os_timer.c" "../source/pinmux.c" "../source/sci.c" "../source/sys_core.asm" "../source/sys_intvecs.asm" "../source/sys_main.c" "../source/sys_mpu.asm" "../source/sys_phantom.c" "../source/sys_pmu.asm" "../source/sys_selftest.c" "../source/sys_startup.c" "../source/system.c" 
-\ No newline at end of file
+"../source/can.c" "../source/cmd_io.c" "../source/cmd_io_line.c" "../source/cmd_proc.c" "../source/cmd_proc_freertos_tms570.c" "../source/cmd_proc_run.c" "../source/cmdio_std_line.c" "../source/cmdio_tisci.c" "../source/commands.c" "../source/dabort.asm" "../source/dma.c" "../source/esm.c" "../source/i2str.c" "../source/notification.c" "../source/os_croutine.c" "../source/os_heap.c" "../source/os_list.c" "../source/os_port.c" "../source/os_portasm.asm" "../source/os_queue.c" "../source/os_tasks.c" "../source/os_timer.c" "../source/pinmux.c" "../source/sci.c" "../source/sys_core.asm" "../source/sys_intvecs.asm" "../source/sys_main.c" "../source/sys_mpu.asm" "../source/sys_phantom.c" "../source/sys_pmu.asm" "../source/sys_selftest.c" "../source/sys_startup.c" "../source/system.c" 
+\ No newline at end of file
diff --git a/Debug/source/cmd_proc_freertos_tms570.obj b/Debug/source/cmd_proc_freertos_tms570.obj

index 88d96df401c7649f65f45b976a91a7f6ed3b4b68..0405e11b19e41c2bb7139477719b19e5c41cccc4 100644 (file)

Binary files a/Debug/source/cmd_proc_freertos_tms570.obj and b/Debug/source/cmd_proc_freertos_tms570.obj differ
diff --git a/Debug/source/cmdio_tisci.obj b/Debug/source/cmdio_tisci.obj

index 6fe1b4ec4465a83305ff535d9460c6162f018ab4..068896d6cb79e1ff3884d3d96a0abbd246ff6e2d 100644 (file)

Binary files a/Debug/source/cmdio_tisci.obj and b/Debug/source/cmdio_tisci.obj differ
diff --git a/Debug/source/commands.obj b/Debug/source/commands.obj

index 924bf5654f4a683145da7d5115bbf726d1cf3d48..3f62f1efdd37487c5cf8e6345196ee95ab7abf9e 100644 (file)

Binary files a/Debug/source/commands.obj and b/Debug/source/commands.obj differ
diff --git a/Debug/source/commands.pp b/Debug/source/commands.pp

index 8f7033dd5bf4521adb400e9c4ed093689882d7c5..5edacba0a4f897ab8a7567aef53159196ffdf909 100644 (file)
--- a/Debug/source/commands.pp
+++ b/Debug/source/commands.pp
@@ -22,6 +22,7 @@ source/commands.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
  source/commands.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
  source/commands.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h
  source/commands.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h
+source/commands.obj: ../include/can.h
  
  ../source/commands.c: 
  ../include/cmd_proc.h: 
@@ -45,3 +46,4 @@ source/commands.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h
  /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h: 
  /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h: 
  /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h: 
+../include/can.h: 
diff --git a/Debug/source/dma.obj b/Debug/source/dma.obj

new file mode 100644 (file)

index 0000000..962a053

Binary files /dev/null and b/Debug/source/dma.obj differ
diff --git a/Debug/source/dma.pp b/Debug/source/dma.pp

new file mode 100644 (file)

index 0000000..0e3c86c
--- /dev/null
+++ b/Debug/source/dma.pp
@@ -0,0 +1,9 @@
+# FIXED
+
+source/dma.obj: ../source/dma.c
+source/dma.obj: ../include/dma.h
+source/dma.obj: ../include/sys_common.h
+
+../source/dma.c: 
+../include/dma.h: 
+../include/sys_common.h: 
diff --git a/Debug/source/esm.obj b/Debug/source/esm.obj

index 9c4fa482d42a942c56e3354dba1105503de5e6d1..de2340c577b4178fe08d18b3871c20b0450a7475 100644 (file)

Binary files a/Debug/source/esm.obj and b/Debug/source/esm.obj differ
diff --git a/Debug/source/notification.obj b/Debug/source/notification.obj

index 3f87299fcdb75f9b9cafd6b65b4ce96758369b06..e44834dfa2cc9e4089f0de09ad773d1e4cbb775b 100644 (file)

Binary files a/Debug/source/notification.obj and b/Debug/source/notification.obj differ
diff --git a/Debug/source/notification.pp b/Debug/source/notification.pp

index dd2ebf64ef246263a4a0b3fd264eea1736f0bc2d..541dd4bdeba874287470fed9cbd5df9db85b122b 100644 (file)
--- a/Debug/source/notification.pp
+++ b/Debug/source/notification.pp
@@ -17,6 +17,7 @@ source/notification.obj: ../include/gio.h
  source/notification.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
  source/notification.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
  source/notification.obj: ../include/htu.h
+source/notification.obj: ../include/can.h
  source/notification.obj: ../include/sci.h
  source/notification.obj: ../include/gio.h
  source/notification.obj: ../include/FreeRTOS.h
@@ -48,6 +49,7 @@ source/notification.obj: ../include/os_list.h
  /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h: 
  /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h: 
  ../include/htu.h: 
+../include/can.h: 
  ../include/sci.h: 
  ../include/gio.h: 
  ../include/FreeRTOS.h: 
diff --git a/Debug/source/os_croutine.obj b/Debug/source/os_croutine.obj

index c85791b703461b7686ee0b2392115cc68b62c38c..0b1794359b8d81bef6e502f473555d88f055fd32 100644 (file)

Binary files a/Debug/source/os_croutine.obj and b/Debug/source/os_croutine.obj differ
diff --git a/Debug/source/os_heap.obj b/Debug/source/os_heap.obj

index b967dc0b3ce8df4b0d5958f6d0da88ac08145874..3caed1b6969953e1385511d1fae0eb85693f2061 100644 (file)

Binary files a/Debug/source/os_heap.obj and b/Debug/source/os_heap.obj differ
diff --git a/Debug/source/os_list.obj b/Debug/source/os_list.obj

index b968d5c8299dc67d5ceec0c0bcd3df9b89286669..c4dba7eb72f7db6e1e3fc40dce839f3ffad90140 100644 (file)

Binary files a/Debug/source/os_list.obj and b/Debug/source/os_list.obj differ
diff --git a/Debug/source/os_port.obj b/Debug/source/os_port.obj

index f5ed6beff742f7f16690d16077da1660cef792a4..ae544c3a3b7561227583e68842bd569edfcbe4ec 100644 (file)

Binary files a/Debug/source/os_port.obj and b/Debug/source/os_port.obj differ
diff --git a/Debug/source/os_queue.obj b/Debug/source/os_queue.obj

index 1ccf20f50de4c8083b3903e7daf2a766fd6369a1..97adcd142eb691b6745c0e2827eeb017b5d1099c 100644 (file)

Binary files a/Debug/source/os_queue.obj and b/Debug/source/os_queue.obj differ
diff --git a/Debug/source/os_tasks.obj b/Debug/source/os_tasks.obj

index 0c7696ac1d08f8c859a32b6b62dc1c9f966e478d..c08e0799f9189dc9f212438cfea12892c698074e 100644 (file)

Binary files a/Debug/source/os_tasks.obj and b/Debug/source/os_tasks.obj differ
diff --git a/Debug/source/os_timer.obj b/Debug/source/os_timer.obj

index b4d484712ef891834120809fdfac046f2d979cfb..9e20e2f1ec00eead95c541fe3bb7bd003528c575 100644 (file)

Binary files a/Debug/source/os_timer.obj and b/Debug/source/os_timer.obj differ
diff --git a/Debug/source/pinmux.obj b/Debug/source/pinmux.obj

index 4190352ce5ba0430fada06a2ed1c30c1f67f6faf..3b1ea647883f241c290996570d6b31e70ede21bb 100644 (file)

Binary files a/Debug/source/pinmux.obj and b/Debug/source/pinmux.obj differ
diff --git a/Debug/source/sci.obj b/Debug/source/sci.obj

index dd320fef4d1de127f1f0a2b4f125ea0b7d02f892..a799c03ad7eff605107c1cb866a3d08af4d57f07 100644 (file)

Binary files a/Debug/source/sci.obj and b/Debug/source/sci.obj differ
diff --git a/Debug/source/subdir_rules.mk b/Debug/source/subdir_rules.mk

index 4ff43fae133ea24f8c740d60e8c5e72ee2698018..95f2bf362f545c36f2888b3e95db08d06e290f8b 100644 (file)
--- a/Debug/source/subdir_rules.mk
+++ b/Debug/source/subdir_rules.mk
@@ -3,6 +3,13 @@
  ################################################################################
  
  # Each subdirectory must supply rules for building sources it contributes
+source/can.obj: ../source/can.c $(GEN_OPTS) $(GEN_SRCS)
+       @echo 'Building file: $<'
+       @echo 'Invoking: ARM Compiler'
+       "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/can.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+       @echo 'Finished building: $<'
+       @echo ' '
+
  source/cmd_io.obj: ../source/cmd_io.c $(GEN_OPTS) $(GEN_SRCS)
         @echo 'Building file: $<'
         @echo 'Invoking: ARM Compiler'
@@ -66,6 +73,13 @@ source/dabort.obj: ../source/dabort.asm $(GEN_OPTS) $(GEN_SRCS)
         @echo 'Finished building: $<'
         @echo ' '
  
+source/dma.obj: ../source/dma.c $(GEN_OPTS) $(GEN_SRCS)
+       @echo 'Building file: $<'
+       @echo 'Invoking: ARM Compiler'
+       "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/dma.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+       @echo 'Finished building: $<'
+       @echo ' '
+
  source/esm.obj: ../source/esm.c $(GEN_OPTS) $(GEN_SRCS)
         @echo 'Building file: $<'
         @echo 'Invoking: ARM Compiler'
diff --git a/Debug/source/subdir_vars.mk b/Debug/source/subdir_vars.mk

index 0328ad8de3b535e21679407a35f836e786fe3bb3..61a4b51be635e5dcb40ee11cdf5301d334a43099 100644 (file)
--- a/Debug/source/subdir_vars.mk
+++ b/Debug/source/subdir_vars.mk
@@ -15,6 +15,7 @@ ASM_SRCS += \
  ../source/sys_pmu.asm 
  
  C_SRCS += \
+../source/can.c \
  ../source/cmd_io.c \
  ../source/cmd_io_line.c \
  ../source/cmd_proc.c \
@@ -23,6 +24,7 @@ C_SRCS += \
  ../source/cmdio_std_line.c \
  ../source/cmdio_tisci.c \
  ../source/commands.c \
+../source/dma.c \
  ../source/esm.c \
  ../source/i2str.c \
  ../source/notification.c \
@@ -42,6 +44,7 @@ C_SRCS += \
  ../source/system.c 
  
  OBJS += \
+./source/can.obj \
  ./source/cmd_io.obj \
  ./source/cmd_io_line.obj \
  ./source/cmd_proc.obj \
@@ -51,6 +54,7 @@ OBJS += \
  ./source/cmdio_tisci.obj \
  ./source/commands.obj \
  ./source/dabort.obj \
+./source/dma.obj \
  ./source/esm.obj \
  ./source/i2str.obj \
  ./source/notification.obj \
@@ -83,6 +87,7 @@ ASM_DEPS += \
  ./source/sys_pmu.pp 
  
  C_DEPS += \
+./source/can.pp \
  ./source/cmd_io.pp \
  ./source/cmd_io_line.pp \
  ./source/cmd_proc.pp \
@@ -91,6 +96,7 @@ C_DEPS += \
  ./source/cmdio_std_line.pp \
  ./source/cmdio_tisci.pp \
  ./source/commands.pp \
+./source/dma.pp \
  ./source/esm.pp \
  ./source/i2str.pp \
  ./source/notification.pp \
@@ -110,6 +116,7 @@ C_DEPS += \
  ./source/system.pp 
  
  C_DEPS__QUOTED += \
+"source/can.pp" \
  "source/cmd_io.pp" \
  "source/cmd_io_line.pp" \
  "source/cmd_proc.pp" \
@@ -118,6 +125,7 @@ C_DEPS__QUOTED += \
  "source/cmdio_std_line.pp" \
  "source/cmdio_tisci.pp" \
  "source/commands.pp" \
+"source/dma.pp" \
  "source/esm.pp" \
  "source/i2str.pp" \
  "source/notification.pp" \
@@ -137,6 +145,7 @@ C_DEPS__QUOTED += \
  "source/system.pp" 
  
  OBJS__QUOTED += \
+"source/can.obj" \
  "source/cmd_io.obj" \
  "source/cmd_io_line.obj" \
  "source/cmd_proc.obj" \
@@ -146,6 +155,7 @@ OBJS__QUOTED += \
  "source/cmdio_tisci.obj" \
  "source/commands.obj" \
  "source/dabort.obj" \
+"source/dma.obj" \
  "source/esm.obj" \
  "source/i2str.obj" \
  "source/notification.obj" \
@@ -178,6 +188,7 @@ ASM_DEPS__QUOTED += \
  "source/sys_pmu.pp" 
  
  C_SRCS__QUOTED += \
+"../source/can.c" \
  "../source/cmd_io.c" \
  "../source/cmd_io_line.c" \
  "../source/cmd_proc.c" \
@@ -186,6 +197,7 @@ C_SRCS__QUOTED += \
  "../source/cmdio_std_line.c" \
  "../source/cmdio_tisci.c" \
  "../source/commands.c" \
+"../source/dma.c" \
  "../source/esm.c" \
  "../source/i2str.c" \
  "../source/notification.c" \
diff --git a/Debug/source/sys_main.obj b/Debug/source/sys_main.obj

index c0ead36cc57280f0a89edf0ad4c5f408673283a3..b5f70fd43916b96db455f854d1b307c649c4067a 100644 (file)

Binary files a/Debug/source/sys_main.obj and b/Debug/source/sys_main.obj differ
diff --git a/Debug/source/sys_main.pp b/Debug/source/sys_main.pp

index d48867feb7c2796f5a8f7d9aa5ea8e3685bf14a4..e30de7aadb452c4be3790e4c88ac844ba98664d8 100644 (file)
--- a/Debug/source/sys_main.pp
+++ b/Debug/source/sys_main.pp
@@ -23,6 +23,7 @@ source/sys_main.obj: ../include/os_task.h
  source/sys_main.obj: ../include/os_list.h
  source/sys_main.obj: ../include/sci.h
  source/sys_main.obj: ../include/gio.h
+source/sys_main.obj: ../include/can.h
  
  ../source/sys_main.c: 
  ../include/sys_common.h: 
@@ -47,3 +48,4 @@ source/sys_main.obj: ../include/gio.h
  ../include/os_list.h: 
  ../include/sci.h: 
  ../include/gio.h: 
+../include/can.h: 
diff --git a/Debug/source/sys_phantom.obj b/Debug/source/sys_phantom.obj

index 4048316717364059880fbd561c4fc8824a903adb..cacfff088a7ed982b4d4d045123ca2dfb18d3d2a 100644 (file)

Binary files a/Debug/source/sys_phantom.obj and b/Debug/source/sys_phantom.obj differ
diff --git a/Debug/source/sys_selftest.obj b/Debug/source/sys_selftest.obj

index 295a639139ad72b2229803633c3cbe92a26a72eb..0bc56841ef244879344a88fa7135375a3186de0d 100644 (file)

Binary files a/Debug/source/sys_selftest.obj and b/Debug/source/sys_selftest.obj differ
diff --git a/Debug/source/sys_startup.obj b/Debug/source/sys_startup.obj

index 6bde14a25758407f3fe0450b56f207e785dcb132..c71192f20d98f8affd94acde96b8d7f10a80a644 100644 (file)

Binary files a/Debug/source/sys_startup.obj and b/Debug/source/sys_startup.obj differ
diff --git a/Debug/source/system.obj b/Debug/source/system.obj

index f2f47dc324418e9dae71f8210d06ab6f93468a49..b5e23eebbc9ff3798d2db7c96bf9924d41f015b3 100644 (file)

Binary files a/Debug/source/system.obj and b/Debug/source/system.obj differ
diff --git a/include/dma.h b/include/dma.h

new file mode 100644 (file)

index 0000000..a3e746e
--- /dev/null
+++ b/include/dma.h
@@ -0,0 +1,305 @@
+/** @file dma.h\r
+*   @brief DMA Driver Definition File\r
+*   @date 22.Aug.2011\r
+*   @version 1.01.000\r
+*   \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2010, All rights reserved. */\r
+\r
+#ifndef __DMA_H__\r
+#define __DMA_H__\r
+\r
+\r
+#include "sys_common.h"\r
+\r
+/* dma configuration definitions */\r
+\r
+#define BLOCK_TRANSFER      1\r
+#define FRAME_TRANSFER      0\r
+\r
+#define AUTOINIT_ON         1\r
+#define AUTOINIT_OFF        0\r
+\r
+#define ADDR_FIXED          0\r
+#define ADDR_INC1           1\r
+#define ADDR_RESERVED       2\r
+#define ADDR_OFFSET         3\r
+\r
+/** @enum dmaREQTYPE\r
+*   @brief DMA TRANSFER Type definitions \r
+*\r
+*   Used to define DMA transfer type\r
+*/\r
+enum dmaREQTYPE\r
+{\r
+    DMA_HW = 0x0,\r
+    DMA_SW = 0x1\r
+};\r
+\r
+\r
+/** @enum dmaCHANNEL\r
+*   @brief DMA CHANNEL definitions \r
+*\r
+*   Used to define DMA Channel Number\r
+*/\r
+enum dmaCHANNEL\r
+{\r
+    DMA_CH0  = 0x00,\r
+    DMA_CH1  = 0x01,\r
+    DMA_CH2  = 0x02,\r
+    DMA_CH3  = 0x03,\r
+    DMA_CH4  = 0x04,\r
+    DMA_CH5  = 0x05,\r
+    DMA_CH6  = 0x06,\r
+    DMA_CH7  = 0x07,\r
+    DMA_CH8  = 0x08,\r
+    DMA_CH9  = 0x09,\r
+    DMA_CH10 = 0x0A,\r
+    DMA_CH11 = 0x0B,\r
+    DMA_CH12 = 0x0C,\r
+    DMA_CH13 = 0x0D,\r
+    DMA_CH14 = 0x0E,\r
+    DMA_CH15 = 0x0F,\r
+    DMA_CH16 = 0x10,\r
+    DMA_CH17 = 0x11,\r
+    DMA_CH18 = 0x12,\r
+    DMA_CH19 = 0x13,\r
+    DMA_CH20 = 0x14,\r
+    DMA_CH21 = 0x15,\r
+    DMA_CH22 = 0x16,\r
+    DMA_CH23 = 0x17,\r
+    DMA_CH24 = 0x18,\r
+    DMA_CH25 = 0x19,\r
+    DMA_CH26 = 0x1A,\r
+    DMA_CH27 = 0x1B,\r
+    DMA_CH28 = 0x1C,\r
+    DMA_CH29 = 0x1D,\r
+    DMA_CH30 = 0x1E,\r
+    DMA_CH31 = 0x1F,\r
+    DMA_CH32 = 0x20\r
+};\r
+\r
+/** @enum dmaACCESS\r
+*   @brief DMA ACESS WIDTH definitions \r
+*\r
+*   Used to define DMA access width\r
+*/\r
+\r
+enum dmaACCESS\r
+{\r
+ ACCESS_8_BIT   =  0,\r
+ ACCESS_16_BIT  =  1,\r
+ ACCESS_32_BIT  =  2,\r
+ ACCESS_64_BIT  =  3\r
+};\r
+\r
+\r
+/** @struct g_dmaCTRL\r
+*   @brief Interrupt mode globals\r
+*\r
+*/\r
+typedef struct  dmaCTRLPKT\r
+{\r
+    uint32_t SADD;       /* initial source address           */\r
+    uint32_t DADD;       /* initial destination address      */\r
+    uint32_t CHCTRL;     /* channel count                    */\r
+    uint32_t FRCNT;      /* frame   count                    */\r
+    uint32_t ELCNT;      /* element count                    */\r
+    uint32_t ELDOFFSET;  /* element destination offset       */\r
+    uint32_t ELSOFFSET;  /* element source offset            */\r
+    uint32_t FRDOFFSET;  /* frame detination offset          */\r
+    uint32_t FRSOFFSET;  /* frame source offset              */\r
+    uint32_t PORTASGN;   /* dma port                         */\r
+    uint32_t RDSIZE;     /* read element size                */\r
+    uint32_t WRSIZE;     /* write element size               */\r
+    uint32_t TTYPE;      /* trigger type - frame/block       */\r
+    uint32_t ADDMODERD;  /* addresssing mode for source      */\r
+    uint32_t ADDMODEWR;  /* addresssing mode for destination */\r
+    uint32_t AUTOINIT;   /* auto-init mode                   */\r
+    uint32_t COMBO;      /* next ctrl packet trigger         */\r
+} g_dmaCTRL;\r
+\r
+\r
+\r
+/** @struct dmaBASE_t\r
+*   @brief DMA Register Definition\r
+*\r
+*   This structure is used to access the DMA module egisters.\r
+*/\r
+typedef volatile struct DMABase\r
+{\r
+\r
+    uint32_t GCTRL;      /**<  0x0000 global control register                */\r
+    uint32_t PEND;       /**<  0x0004 channel pending register               */\r
+    uint32_t FBREG;      /**<  0x0008 fall back register                     */\r
+    uint32_t DMASTAT;    /**<  0x000C status register                        */\r
+    uint32_t : 32U;      /**<  0x0010 reserved                               */\r
+    uint32_t HWCHENAS;   /**<  0x0014 hw channel enable set                  */\r
+    uint32_t : 32U;      /**<  0x0018 reserved                               */\r
+    uint32_t HWCHENAR;   /**<  0x001C hw channel enable reset                */\r
+    uint32_t : 32U;      /**<  0x0020 reserved                               */\r
+    uint32_t SWCHENAS;   /**<  0x0024 sw channel enable set                  */\r
+    uint32_t : 32U;      /**<  0x0028 reserved                               */\r
+    uint32_t SWCHENAR;   /**<  0x002C sw channel enable reset                */\r
+    uint32_t : 32U;      /**<  0x0030 reserved                               */\r
+    uint32_t CHPRIOS;    /**<  0x0034 channel priority set                   */\r
+    uint32_t : 32U;      /**<  0x0038 reserved                               */\r
+    uint32_t CHPRIOR;    /**<  0x003C channel priority reset                 */\r
+    uint32_t : 32U;      /**<  0x0040 reserved                               */\r
+    uint32_t GCHIENAS;   /**<  0x0044 global channel interrupt enable set    */\r
+    uint32_t : 32U;      /**<  0x0048                                        */\r
+    uint32_t GCHIENAR;   /**<  0x004C global channel interrupt enable set    */\r
+    uint32_t : 32U;      /**<  0x0050                                        */\r
+    uint32_t DREQASI[8U];/**<  0x0054 - 0x70                                 */\r
+    uint32_t : 32U;      /**<  0x0074 reserved                               */\r
+    uint32_t : 32U;      /**<  0x0078 reserved                               */\r
+    uint32_t : 32U;      /**<  0x007C reserved                               */\r
+    uint32_t : 32U;      /**<  0x0080 reserved                               */\r
+    uint32_t : 32U;      /**<  0x0084 reserved                               */\r
+    uint32_t : 32U;      /**<  0x0088 reserved                               */\r
+    uint32_t : 32U;      /**<  0x008C reserved                               */\r
+    uint32_t : 32U;      /**<  0x0090 reserved                               */\r
+    uint32_t PAR[4U];    /**<  0x0094 - 0xA0                                 */\r
+    uint32_t : 32U;      /**<  0x00A4                                        */\r
+    uint32_t : 32U;      /**<  0x00A8                                        */\r
+    uint32_t : 32U;      /**<  0x00AC                                        */\r
+    uint32_t : 32U;      /**<  0x00B0                                        */\r
+    uint32_t FTCMAP;     /**<  0x00B4                                        */\r
+    uint32_t : 32U;      /**<  0x00B8 reserved  */\r
+    uint32_t LFSMAP;     /**<  0x00BC           */\r
+    uint32_t : 32U;      /**<  0x00C0 reserved  */\r
+    uint32_t HBCMAP;     /**<  0x00C4           */\r
+    uint32_t : 32U;      /**<  0x00C8 reserved  */\r
+    uint32_t BTCMAP;     /**<  0x00CC           */\r
+    uint32_t : 32U;      /**<  0x00D0 reserved  */\r
+    uint32_t BERMAP;     /**<  0x00D4           */\r
+    uint32_t : 32U;      /**<  0x00D8 reserved  */\r
+    uint32_t FTCINTENAS; /**<  0x00DC           */\r
+    uint32_t : 32U;      /**<  0x00E0 reserved  */\r
+    uint32_t FTCINTENAR; /**<  0x00E4           */\r
+    uint32_t : 32U;      /**<  0x00E8 reserved  */\r
+    uint32_t LFSINTENAS; /**<  0x00EC           */\r
+    uint32_t : 32U;      /**<  0x00F0 reserved  */\r
+    uint32_t LFSINTENAR; /**<  0x00F4           */\r
+    uint32_t : 32U;      /**<  0x00F8 reserved  */\r
+    uint32_t HBCINTENAS; /**<  0x00FC           */\r
+    uint32_t : 32U;      /**<  0x0100 reserved  */\r
+    uint32_t HBCINTENAR; /**<  0x0104           */\r
+    uint32_t : 32U;      /**<  0x0108 reserved  */\r
+    uint32_t BTCINTENAS; /**<  0x010C           */\r
+    uint32_t : 32U;      /**<  0x0110 reserved  */\r
+    uint32_t BTCINTENAR; /**<  0x0114           */\r
+    uint32_t : 32U;      /**<  0x0118 reserved  */\r
+    uint32_t GINTFLAG;   /**<  0x011C           */\r
+    uint32_t : 32U;      /**<  0x0120 reserved  */\r
+    uint32_t FTCFLAG;    /**<  0x0124           */\r
+    uint32_t : 32U;      /**<  0x0128 reserved  */\r
+    uint32_t LFSFLAG;    /**<  0x012C           */\r
+    uint32_t : 32U;      /**<  0x0130 reserved  */\r
+    uint32_t HBCFLAG;    /**<  0x0134           */\r
+    uint32_t : 32U;      /**<  0x0138 reserved  */\r
+    uint32_t BTCFLAG;    /**<  0x013C           */\r
+    uint32_t : 32U;      /**<  0x0140 reserved  */\r
+    uint32_t BERFLAG;    /**<  0x0144           */\r
+    uint32_t : 32U;      /**<  0x0148 reserved  */\r
+    uint32_t FTCAOFFSET; /**<  0x014C           */\r
+    uint32_t LFSAOFFSET; /**<  0x0150           */\r
+    uint32_t HBCAOFFSET; /**<  0x0154           */\r
+    uint32_t BTCAOFFSET; /**<  0x0158           */\r
+    uint32_t BERAOFFSET; /**<  0x015C           */\r
+    uint32_t FTCBOFFSET; /**<  0x0160           */\r
+    uint32_t LFSBOFFSET; /**<  0x0164           */\r
+    uint32_t HBCBOFFSET; /**<  0x0168           */\r
+    uint32_t BTCBOFFSET; /**<  0x016C           */\r
+    uint32_t BERBOFFSET; /**<  0x0170           */\r
+    uint32_t TERBOFFSET; /**<  0x0174           */\r
+    uint32_t PTCRL;      /**<  0x0178           */\r
+    uint32_t RTCTRL;     /**<  0x017C           */\r
+    uint32_t DCTRL;      /**<  0x0180           */\r
+    uint32_t WPR;        /**<  0x0184           */\r
+    uint32_t WMR;        /**<  0x0188           */\r
+    uint32_t PAACSADDR;  /**<  0x018C           */\r
+    uint32_t PAACDADDR;  /**<  0x0190           */\r
+    uint32_t PAACTC;     /**<  0x0194           */\r
+    uint32_t PBACSADDR;  /**<  0x0198           */\r
+    uint32_t PBACDADDR;  /**<  0x019C           */\r
+    uint32_t PBACTC;     /**<  0x01A0           */\r
+    uint32_t : 32U;      /**<  0x01A4 reserved  */\r
+    uint32_t DMAPCR;     /**<  0x01A8           */\r
+    uint32_t DMAPAR;     /**<  0x01AC           */\r
+    uint32_t DMAMPCTRL;  /**<  0x01B0           */\r
+    uint32_t DMAMPST;    /**<  0x01B4           */\r
+    uint32_t DMAMPR0S;   /**<  0x01B8           */\r
+    uint32_t DMAMPR0E;   /**<  0x01BC           */\r
+    uint32_t DMAMPR1S;   /**<  0x01C0           */\r
+    uint32_t DMAMPR1E;   /**<  0x01C4           */\r
+    uint32_t DMAMPR2S;   /**<  0x01C8           */\r
+    uint32_t DMAMPR2E;   /**<  0x01CC           */\r
+    uint32_t DMAMPR3S;   /**<  0x01D0           */\r
+    uint32_t DMAMPR3E;   /**<  0x01D4           */\r
+} dmaBASE_t;\r
+\r
+\r
+/** @def dmaREG\r
+*   @brief DMA1 Register Frame Pointer\r
+*\r
+*   This pointer is used by the DMA driver to access the DMA module registers.\r
+*/\r
+#define dmaREG ((dmaBASE_t *)0xFFFFF000U)\r
+\r
+\r
+\r
+typedef volatile struct\r
+{\r
+     \r
+     struct                                     /* 0x000-0x400 */\r
+     {\r
+      uint32_t ISADDR;\r
+      uint32_t IDADDR;\r
+      uint32_t ITCOUNT; \r
+      uint32_t : 32;    \r
+      uint32_t CHCTRL;\r
+      uint32_t EIOFF;\r
+      uint32_t FIOFF;\r
+      uint32_t : 32;  \r
+     }PCP[32U];\r
+\r
+     struct                                     /* 0x400-0x800   */\r
+     {\r
+       uint32_t res[256];\r
+     } RESERVED;\r
+\r
+     struct                                     /* 0x800-0xA00 */\r
+     {\r
+      uint32_t CSADDR;\r
+      uint32_t CDADDR;\r
+      uint32_t CTCOUNT;\r
+      uint32_t : 32; \r
+     }WCP[32U];\r
+\r
+} dmaRAMBASE_t;\r
+\r
+#define dmaRAMREG ((dmaRAMBASE_t *)0xFFF80000U)\r
+\r
+/* DMA Interface Functions */\r
+void dmaEnable(void);\r
+void dmaSetCtrlPacket(uint32_t channel);\r
+void dmaSetChEnable(uint32_t channel,uint32_t type);\r
+void dmaReqAssign(uint32_t channel,uint32_t reqline);\r
+void dmaEnableNotification(uint32_t flags);\r
+void dmaDisableNotification(uint32_t flags);\r
+\r
+\r
+/** @fn void dmaNotification(dmaBASE_t *DMA, uint32_t flags)\r
+*   @brief Interrupt callback\r
+*   @param[in] DMA   - DMA module base address\r
+*   @param[in] flags - copy of error interrupt flags\r
+*\r
+* This is a callback that is provided by the application and is called apon\r
+* an interrupt.  The parameter passed to the callback is a copy of the \r
+* interrupt flag register.\r
+*/\r
+void dmaNotification(dmaBASE_t *DMA, uint32_t flags);\r
+\r
+#endif\r
diff --git a/include/sys_vim.h b/include/sys_vim.h

index 43be29e27478a7d6370ec1ca5ec9ce3964d03cfa..70416d1ca93473469df38210d1dca90948407e15 100644 (file)
--- a/include/sys_vim.h
+++ b/include/sys_vim.h
@@ -47,6 +47,8 @@ extern void phantomInterrupt(void);
  extern void esmHighInterrupt(void);\r
  extern void phantomInterrupt(void);\r
  extern void vPreemptiveTick(void);\r
+extern void can1HighLevelInterrupt(void);\r
+extern void can2HighLevelInterrupt(void);\r
  extern void sciHighLevelInterrupt(void);\r
  \r
  \r
diff --git a/source/can.c b/source/can.c

new file mode 100644 (file)

index 0000000..ffee243
--- /dev/null
+++ b/source/can.c
@@ -0,0 +1,3029 @@
+/** @file can.c \r
+*   @brief CAN Driver Source File\r
+*   @date 15.Mar.2012\r
+*   @version 03.01.00\r
+*\r
+*   This file contains:\r
+*   - API Funcions\r
+*   - Interrupt Handlers\r
+*   .\r
+*   which are relevant for the CAN driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* Include Files */\r
+\r
+#include "can.h"\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+\r
+/* Global and Static Variables */\r
+\r
+#ifndef __little_endian__\r
+    static const uint32_t s_canByteOrder[] = {3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U};\r
+#endif\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+\r
+/** @fn void canInit(void)\r
+*   @brief Initializes CAN Driver\r
+*\r
+*   This function initializes the CAN driver.\r
+*\r
+*/\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+void canInit(void)\r
+{\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+    /** @b Initialize @b CAN1: */\r
+\r
+    /** - Setup control register\r
+    *     - Disable automatic wakeup on bus activity\r
+    *     - Local power down mode disabled\r
+    *     - Disable DMA request lines\r
+    *     - Enable global Interrupt Line 0 and 1\r
+    *     - Disable debug mode\r
+    *     - Release from software reset\r
+    *     - Enable/Disable parity or ECC\r
+    *     - Enable/Disable auto bus on timer\r
+    *     - Setup message completion before entering debug state\r
+    *     - Setup normal operation mode\r
+    *     - Request write access to the configuration registers\r
+    *     - Setup automatic retransmission of messages\r
+    *     - Disable error interrups\r
+    *     - Disable status interrupts\r
+    *     - Enter initialization mode\r
+    */\r
+    canREG1->CTL = 0x00000000U \r
+                    | 0x00000000U \r
+                                | 0x00000005U \r
+                 | 0x000200043U;\r
+\r
+    /** - Clear all pending error flags and reset current status */\r
+    canREG1->ES = 0x0000031FU;\r
+\r
+    /** - Assign interrupt level for messages */\r
+    canREG1->INTMUXx[0U] = 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U;\r
+\r
+    canREG1->INTMUXx[1U] = 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U;\r
+\r
+    /** - Setup auto bus on timer pewriod */\r
+    canREG1->ABOTR = 0U;\r
+\r
+    /** - Initialize message 1 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x80000000U | 0x40000000U | 0x20000000U | ((1U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 1;\r
+\r
+    /** - Initialize message 2 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((2U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 2;\r
+\r
+    /** - Initialize message 3 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((3U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 3;\r
+\r
+    /** - Initialize message 4 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 4;\r
+\r
+    /** - Initialize message 5 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 5;\r
+\r
+    /** - Initialize message 6 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 6;\r
+\r
+    /** - Initialize message 7 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 7;\r
+\r
+    /** - Initialize message 8 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 8;\r
+\r
+    /** - Initialize message 9 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 9;\r
+\r
+    /** - Initialize message 10 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 10;\r
+\r
+    /** - Initialize message 11 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 11;\r
+\r
+    /** - Initialize message 12 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 12;\r
+\r
+    /** - Initialize message 13 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 13;\r
+\r
+    /** - Initialize message 14 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 14;\r
+\r
+    /** - Initialize message 15 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 15;\r
+\r
+    /** - Initialize message 16 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 16;\r
+\r
+    /** - Initialize message 17 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 17;\r
+\r
+    /** - Initialize message 18 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 18;\r
+\r
+    /** - Initialize message 19 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 19;\r
+\r
+    /** - Initialize message 20 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 20;\r
+\r
+    /** - Initialize message 21 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 21;\r
+\r
+    /** - Initialize message 22 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 22;\r
+\r
+    /** - Initialize message 23 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 23;\r
+\r
+    /** - Initialize message 24 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 24;\r
+\r
+    /** - Initialize message 25 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 25;\r
+\r
+    /** - Initialize message 26 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 26;\r
+\r
+    /** - Initialize message 27 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 27;\r
+\r
+    /** - Initialize message 28 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 28;\r
+\r
+    /** - Initialize message 29 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 29;\r
+\r
+    /** - Initialize message 30 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 30;\r
+\r
+    /** - Initialize message 31 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 31;\r
+\r
+    /** - Initialize message 32 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 32;\r
+\r
+    /** - Initialize message 33 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((33U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 33;\r
+\r
+    /** - Initialize message 34 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((34U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 34;\r
+\r
+    /** - Initialize message 35 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((35U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 35;\r
+\r
+    /** - Initialize message 36 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((36U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 36;\r
+\r
+    /** - Initialize message 37 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((37U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 37;\r
+\r
+    /** - Initialize message 38 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((38U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 38;\r
+\r
+    /** - Initialize message 39 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((39U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 39;\r
+\r
+    /** - Initialize message 40 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((40U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 40;\r
+\r
+    /** - Initialize message 41 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((41U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 41;\r
+\r
+    /** - Initialize message 42 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((42U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 42;\r
+\r
+    /** - Initialize message 43 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((43U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 43;\r
+\r
+    /** - Initialize message 44 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((44U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 44;\r
+\r
+    /** - Initialize message 45 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((45U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 45;\r
+\r
+    /** - Initialize message 46 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((46U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 46;\r
+\r
+    /** - Initialize message 47 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((47U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 47;\r
+\r
+    /** - Initialize message 48 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((48U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 48;\r
+\r
+    /** - Initialize message 49 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((49U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 49;\r
+\r
+    /** - Initialize message 50 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((50U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 50;\r
+\r
+    /** - Initialize message 51 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((51U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 51;\r
+\r
+    /** - Initialize message 52 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((52U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 52;\r
+\r
+    /** - Initialize message 53 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((53U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 53;\r
+\r
+    /** - Initialize message 54 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((54U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 54;\r
+\r
+    /** - Initialize message 55 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((55U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 55;\r
+\r
+    /** - Initialize message 56 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((56U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 56;\r
+\r
+    /** - Initialize message 57 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((57U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 57;\r
+\r
+    /** - Initialize message 58 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((58U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 58;\r
+\r
+    /** - Initialize message 59 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((59U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 59;\r
+\r
+    /** - Initialize message 60 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((60U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 60;\r
+\r
+    /** - Initialize message 61 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((61U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 61;\r
+\r
+    /** - Initialize message 62 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((62U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 62;\r
+\r
+    /** - Initialize message 63 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((63U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF1CMD  = 0xF8;\r
+    canREG1->IF1NO   = 63;\r
+\r
+    /** - Initialize message 64 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((64U & 0x1FFFFFFFU) << 0U);\r
+    canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG1->IF2CMD  = 0xF8;\r
+    canREG1->IF2NO   = 64;\r
+\r
+    /** - Setup IF1 for data transmission \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set IF1 control byte\r
+    */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1CMD  = 0x87;\r
+\r
+    /** - Setup IF2 for reading data\r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set IF1 control byte\r
+    */\r
+    while (canREG1->IF2STAT & 0x80);\r
+\r
+    canREG1->IF2CMD = 0x17;\r
+    /** - Setup bit timing \r
+    *     - Setup baud rate prescaler extension\r
+    *     - Setup TSeg2\r
+    *     - Setup TSeg1\r
+    *     - Setup sample jump width\r
+    *     - Setup baud rate prescaler\r
+    */\r
+    canREG1->BTR = (0U << 16U) |\r
+                   ((2U - 1U) << 12U) |\r
+                   (((3U + 2U) - 1U) << 8U) |\r
+                   ((2U - 1U) << 6U) |\r
+                   19U;\r
+\r
+     /** - CAN1 Port output values */\r
+    canREG1->TIOC = (1  << 18 )\r
+                   | (0  << 17 )   \r
+                   | (1  << 3 )  \r
+                   | (0  << 2 )    \r
+                   | (0 << 1 )  \r
+                   | (0  );     \r
+    canREG1->RIOC = (1  << 18 )    \r
+                   | (0  << 17 )   \r
+                   | (1  << 3 )  \r
+                   | (0  << 2 )\r
+                   | (0 <<1 )  \r
+                   | (0  );        \r
+\r
+\r
+    /** - Leave configuration and initialization mode  */\r
+    canREG1->CTL &= ~0x00000041U;\r
+\r
+\r
+    /** @b Initialize @b CAN2: */\r
+\r
+    /** - Setup control register\r
+    *     - Disable automatic wakeup on bus activity\r
+    *     - Local power down mode disabled\r
+    *     - Disable DMA request lines\r
+    *     - Enable global Interrupt Line 0 and 1\r
+    *     - Disable debug mode\r
+    *     - Release from software reset\r
+    *     - Enable/Disable parity or ECC\r
+    *     - Enable/Disable auto bus on timer\r
+    *     - Setup message completion before entering debug state\r
+    *     - Setup normal operation mode\r
+    *     - Request write access to the configuration registers\r
+    *     - Setup automatic retransmission of messages\r
+    *     - Disable error interrups\r
+    *     - Disable status interrupts\r
+    *     - Enter initialization mode\r
+    */\r
+    canREG2->CTL = 0x00000000U \r
+                    | 0x00000000U \r
+                                | 0x00000005U \r
+                 | 0x000200043U;\r
+\r
+    /** - Clear all pending error flags and reset current status */\r
+    canREG2->ES = 0x0000031FU;\r
+\r
+\r
+    /** - Assign interrupt level for messages */\r
+    canREG2->INTMUXx[0U] = 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U;\r
+\r
+    canREG2->INTMUXx[1U] = 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U\r
+                         | 0x00000000U;\r
+\r
+\r
+    /** - Setup auto bus on timer pewriod */\r
+    canREG2->ABOTR = 0U;\r
+\r
+    /** - Initialize message 1 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x80000000U | 0x40000000U | 0x00000000U | ((1U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 1;\r
+\r
+    /** - Initialize message 2 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((2U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 2;\r
+\r
+    /** - Initialize message 3 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((3U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 3;\r
+\r
+    /** - Initialize message 4 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 4;\r
+\r
+    /** - Initialize message 5 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 5;\r
+\r
+    /** - Initialize message 6 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 6;\r
+\r
+    /** - Initialize message 7 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 7;\r
+\r
+    /** - Initialize message 8 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 8;\r
+\r
+    /** - Initialize message 9 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 9;\r
+\r
+    /** - Initialize message 10 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 10;\r
+\r
+    /** - Initialize message 11 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 11;\r
+\r
+    /** - Initialize message 12 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 12;\r
+\r
+    /** - Initialize message 13 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 13;\r
+\r
+    /** - Initialize message 14 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 14;\r
+\r
+    /** - Initialize message 15 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 15;\r
+\r
+    /** - Initialize message 16 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 16;\r
+\r
+    /** - Initialize message 17 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 17;\r
+\r
+    /** - Initialize message 18 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 18;\r
+\r
+    /** - Initialize message 19 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 19;\r
+\r
+    /** - Initialize message 20 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 20;\r
+\r
+    /** - Initialize message 21 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 21;\r
+\r
+    /** - Initialize message 22 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 22;\r
+\r
+    /** - Initialize message 23 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 23;\r
+\r
+    /** - Initialize message 24 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 24;\r
+\r
+    /** - Initialize message 25 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 25;\r
+\r
+    /** - Initialize message 26 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 26;\r
+\r
+    /** - Initialize message 27 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 27;\r
+\r
+    /** - Initialize message 28 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 28;\r
+\r
+    /** - Initialize message 29 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 29;\r
+\r
+    /** - Initialize message 30 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 30;\r
+\r
+    /** - Initialize message 31 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 31;\r
+\r
+    /** - Initialize message 32 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 32;\r
+\r
+    /** - Initialize message 33 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((33U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 33;\r
+\r
+    /** - Initialize message 34 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((34U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 34;\r
+\r
+    /** - Initialize message 35 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((35U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 35;\r
+\r
+    /** - Initialize message 36 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((36U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 36;\r
+\r
+    /** - Initialize message 37 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((37U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 37;\r
+\r
+    /** - Initialize message 38 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((38U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 38;\r
+\r
+    /** - Initialize message 39 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((39U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 39;\r
+\r
+    /** - Initialize message 40 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((40U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 40;\r
+\r
+    /** - Initialize message 41 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((41U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 41;\r
+\r
+    /** - Initialize message 42 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((42U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 42;\r
+\r
+    /** - Initialize message 43 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((43U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 43;\r
+\r
+    /** - Initialize message 44 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((44U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 44;\r
+\r
+    /** - Initialize message 45 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((45U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 45;\r
+\r
+    /** - Initialize message 46 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((46U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 46;\r
+\r
+    /** - Initialize message 47 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((47U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 47;\r
+\r
+    /** - Initialize message 48 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((48U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 48;\r
+\r
+    /** - Initialize message 49 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((49U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 49;\r
+\r
+    /** - Initialize message 50 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((50U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 50;\r
+\r
+    /** - Initialize message 51 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((51U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 51;\r
+\r
+    /** - Initialize message 52 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((52U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 52;\r
+\r
+    /** - Initialize message 53 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((53U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 53;\r
+\r
+    /** - Initialize message 54 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((54U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 54;\r
+\r
+    /** - Initialize message 55 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((55U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 55;\r
+\r
+    /** - Initialize message 56 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((56U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 56;\r
+\r
+    /** - Initialize message 57 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((57U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 57;\r
+\r
+    /** - Initialize message 58 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((58U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 58;\r
+\r
+    /** - Initialize message 59 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((59U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 59;\r
+\r
+    /** - Initialize message 60 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((60U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 60;\r
+\r
+    /** - Initialize message 61 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((61U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 61;\r
+\r
+    /** - Initialize message 62 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((62U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 62;\r
+\r
+    /** - Initialize message 63 \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF1 control byte\r
+    *     - Set IF1 message number\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((63U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF1CMD  = 0xF8;\r
+    canREG2->IF1NO   = 63;\r
+\r
+    /** - Initialize message 64 \r
+    *     - Wait until IF2 is ready for use \r
+    *     - Set message mask\r
+    *     - Set message control word\r
+    *     - Set message arbitration\r
+    *     - Set IF2 control byte\r
+    *     - Set IF2 message number\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2MSK  = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2ARB  = 0x00000000U | 0x40000000U | 0x20000000U | ((64U & 0x1FFFFFFFU) << 0U);\r
+    canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+    canREG2->IF2CMD  = 0xF8;\r
+    canREG2->IF2NO   = 64;\r
+\r
+    /** - Setup IF1 for data transmission \r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set IF1 control byte\r
+    */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1CMD  = 0x87;\r
+\r
+    /** - Setup IF2 for reading data\r
+    *     - Wait until IF1 is ready for use \r
+    *     - Set IF1 control byte\r
+    */\r
+    while (canREG2->IF2STAT & 0x80);\r
+\r
+    canREG2->IF2CMD = 0x17;\r
+    /** - Setup bit timing \r
+    *     - Setup baud rate prescaler extension\r
+    *     - Setup TSeg2\r
+    *     - Setup TSeg1\r
+    *     - Setup sample jump width\r
+    *     - Setup baud rate prescaler\r
+    */\r
+    canREG2->BTR = (0U << 16U) |\r
+                   ((2U - 1U) << 12U) |\r
+                   (((3U + 2U) - 1U) << 8U) |\r
+                   ((2U - 1U) << 6U) |\r
+                   19U;\r
+\r
+   /** - CAN2 Port output values */\r
+    canREG2->TIOC = (1  << 18 )\r
+                   | (0  << 17 )   \r
+                   | (1  << 3 )  \r
+                   | (0  << 2 )    \r
+                   | (0 << 1 )  \r
+                   | (0  );     \r
+    canREG2->RIOC = (1  << 18 )    \r
+                   | (0  << 17 )   \r
+                   | (1  << 3 )  \r
+                   | (0  << 2 )\r
+                   | (0 <<1 )  \r
+                   | (0  );       \r
+\r
+    /** - Leave configuration and initialization mode  */\r
+    canREG2->CTL &= ~0x00000041U;\r
+\r
+\r
+    /**   @note This function has to be called before the driver can be used.\n\r
+    *           This function has to be executed in priviledged mode.\n\r
+    */\r
+\r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn uint32_t canTransmit(canBASE_t *node, uint32_t messageBox, const uint8_t *data)\r
+*   @brief Transmits a CAN message\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*   @param[in] messageBox Message box number of CAN node:\r
+*              - canMESSAGE_BOX1: CAN message box 1\r
+*              - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+*              - canMESSAGE_BOX64: CAN message box 64\r
+*   @param[in] data Pointer to CAN TX data\r
+*   @return The function will return:\r
+*           - 0: When the setup of the TX message box wasn't successful   \r
+*           - 1: When the setup of the TX message box was successful   \r
+*\r
+*   This function writes a CAN message into a CAN message box.\r
+*\r
+*/\r
+\r
+/* USER CODE BEGIN (6) */\r
+/* USER CODE END */\r
+\r
+uint32_t canTransmit(canBASE_t *node, uint32_t messageBox, const uint8_t *data)\r
+{\r
+    uint32_t i;\r
+    uint32_t success  = 0U;\r
+    uint32_t regIndex = (messageBox - 1U) >> 5U;\r
+    uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (7) */\r
+/* USER CODE END */\r
+\r
+    /** - Check for pending message:\r
+    *     - pending message, return 0\r
+    *     - no pending message, start new transmission \r
+    */\r
+    if (node->TXRQx[regIndex] & bitIndex)\r
+    {\r
+        return success;\r
+    }\r
+\r
+    /** - Wait until IF1 is ready for use */\r
+    while (node->IF1STAT & 0x80);\r
+\r
+    /** - Copy TX data into IF1 */\r
+    for (i = 0U; i < 8U; i++)\r
+    {\r
+#ifdef __little_endian__\r
+        node->IF1DATx[i] = *data++;\r
+#else\r
+        node->IF1DATx[s_canByteOrder[i]] = *data++;\r
+#endif\r
+    }\r
+\r
+    /** - Copy TX data into mesasge box */\r
+    node->IF1NO = messageBox;\r
+\r
+    success = 1U; \r
+\r
+    /**   @note The function canInit has to be called before this function can be used.\n\r
+    *           The user is responsible to initialize the message box.\r
+    */\r
+\r
+/* USER CODE BEGIN (8) */\r
+/* USER CODE END */\r
+\r
+    return success;\r
+}\r
+\r
+\r
+/** @fn uint32_t canGetData(canBASE_t *node, uint32_t messageBox, uint8_t * const data)\r
+*   @brief Gets received a CAN message\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*   @param[in] messageBox Message box number of CAN node:\r
+*              - canMESSAGE_BOX1: CAN message box 1\r
+*              - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+*              - canMESSAGE_BOX64: CAN message box 64\r
+*   @param[out] data Pointer to store CAN RX data\r
+*   @return The function will return:\r
+*           - 0: When RX message box hasn't received new data   \r
+*           - 1: When RX data are stored in the data buffer   \r
+*           - 3: When RX data are stored in the data buffer and a message was lost   \r
+*\r
+*   This function writes a CAN message into a CAN message box.\r
+*\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (9) */\r
+/* USER CODE END */\r
+\r
+uint32_t canGetData(canBASE_t *node, uint32_t messageBox, uint8_t * const data)\r
+{\r
+    uint32_t       i;\r
+    uint32_t       size;\r
+    uint8_t *pData    = (uint8_t *)data;\r
+    uint32_t       success  = 0U;\r
+    uint32_t       regIndex = (messageBox - 1U) >> 5U;\r
+    uint32_t       bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (10) */\r
+/* USER CODE END */\r
+\r
+    /** - Check if new data have been arrived:\r
+    *     - no new data, return 0\r
+    *     - new data, get received message \r
+    */\r
+    if (!(node->NWDATx[regIndex] & bitIndex))\r
+    {\r
+        return success;\r
+    }\r
+\r
+    /** - Wait until IF2 is ready for use */\r
+    while (node->IF2STAT & 0x80);\r
+\r
+    /** - Copy data into IF2 */\r
+    node->IF2NO = messageBox;\r
+\r
+    /** - Wait until data are copied into IF2 */\r
+    while (node->IF2STAT & 0x80);\r
+\r
+    /** - Get number of received bytes */\r
+    size = node->IF2MCTL & 0xFU;\r
+\r
+    /** - Copy RX data into destination buffer */\r
+    for (i = 0U; i < size; i++)\r
+    {\r
+#ifdef __little_endian__\r
+        *pData++ = node->IF2DATx[i];\r
+#else\r
+        *pData++ = node->IF2DATx[s_canByteOrder[i]];\r
+#endif\r
+    }\r
+\r
+    success = 1U;\r
+\r
+    /** - Check if data have been lost:\r
+    *     - no data lost, return 1\r
+    *     - data lost, return 3 \r
+    */\r
+    if (node->IF2MCTL & 0x4000U)\r
+    {\r
+        success = 3U;\r
+    }\r
+\r
+    /**   @note The function canInit has to be called before this function can be used.\n\r
+    *           The user is responsible to initialize the message box.\r
+    */\r
+\r
+/* USER CODE BEGIN (11) */\r
+/* USER CODE END */\r
+\r
+    return success;\r
+}\r
+\r
+\r
+/** @fn uint32_t canIsTxMessagePending(canBASE_t *node, uint32_t messageBox)\r
+*   @brief Gets Tx message box transmission status\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*   @param[in] messageBox Message box number of CAN node:\r
+*              - canMESSAGE_BOX1: CAN message box 1\r
+*              - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+*              - canMESSAGE_BOX64: CAN message box 64\r
+*   @return The function will return the tx request flag\r
+*\r
+*   Checks to see if the Tx message box has a pending Tx request, returns\r
+*   0 is flag not set otherwise will return the Tx request flag itself.\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (12) */\r
+/* USER CODE END */\r
+\r
+uint32_t canIsTxMessagePending(canBASE_t *node, uint32_t messageBox)\r
+{\r
+    uint32_t flag;\r
+    uint32_t regIndex = (messageBox - 1U) >> 5U;\r
+    uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (13) */\r
+/* USER CODE END */\r
+\r
+    /** - Read Tx request reigster */\r
+    flag = node->TXRQx[regIndex] & bitIndex;\r
+\r
+/* USER CODE BEGIN (14) */\r
+/* USER CODE END */\r
+\r
+    return flag;\r
+}\r
+\r
+\r
+/** @fn uint32_t canIsRxMessageArrived(canBASE_t *node, uint32_t messageBox)\r
+*   @brief Gets Rx message box reception status\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*   @param[in] messageBox Message box number of CAN node:\r
+*              - canMESSAGE_BOX1: CAN message box 1\r
+*              - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+*              - canMESSAGE_BOX64: CAN message box 64\r
+*   @return The function will return the new data flag\r
+*\r
+*   Checks to see if the Rx message box has pending Rx data, returns\r
+*   0 is flag not set otherwise will return the Tx request flag itself.\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (15) */\r
+/* USER CODE END */\r
+\r
+uint32_t canIsRxMessageArrived(canBASE_t *node, uint32_t messageBox)\r
+{\r
+    uint32_t flag;\r
+    uint32_t regIndex = (messageBox - 1U) >> 5U;\r
+    uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (16) */\r
+/* USER CODE END */\r
+\r
+    /** - Read Tx request register */\r
+    flag = node->NWDATx[regIndex] & bitIndex;\r
+\r
+/* USER CODE BEGIN (17) */\r
+/* USER CODE END */\r
+\r
+    return flag;\r
+}\r
+\r
+\r
+/** @fn uint32_t canIsMessageBoxValid(canBASE_t *node, uint32_t messageBox)\r
+*   @brief Chechs if message box is valid\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*   @param[in] messageBox Message box number of CAN node:\r
+*              - canMESSAGE_BOX1: CAN message box 1\r
+*              - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+*              - canMESSAGE_BOX64: CAN message box 64\r
+*   @return The function will return the new data flag\r
+*\r
+*   Checks to see if the message box is valid for operation, returns\r
+*   0 is flag not set otherwise will return the validation flag itself.\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (18) */\r
+/* USER CODE END */\r
+\r
+uint32_t canIsMessageBoxValid(canBASE_t *node, uint32_t messageBox)\r
+{\r
+    uint32_t flag;\r
+    uint32_t regIndex = (messageBox - 1U) >> 5U;\r
+    uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (19) */\r
+/* USER CODE END */\r
+\r
+    /** - Read Tx request register */\r
+    flag = node->MSGVALx[regIndex] & bitIndex;\r
+\r
+/* USER CODE BEGIN (20) */\r
+/* USER CODE END */\r
+\r
+    return flag;\r
+}\r
+\r
+\r
+/** @fn uint32_t canGetLastError(canBASE_t *node)\r
+*   @brief Gets last RX/TX-Error of CAN message traffic\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*   @return The function will return:\r
+*           - canERROR_OK (0): When no CAN error occured   \r
+*           - canERROR_STUFF (1): When a stuff error occured on RX message    \r
+*           - canERROR_FORMAT (2): When a form/format error occured on RX message   \r
+*           - canERROR_ACKNOWLEDGE (3): When a TX message wasn't acknowledged  \r
+*           - canERROR_BIT1 (4): When a TX message monitored dominant level where recessive is expected   \r
+*           - canERROR_BIT0 (5): When a TX message monitored recessive level where dominant is expected   \r
+*           - canERROR_CRC (6): When a RX message has wrong CRC value   \r
+*           - canERROR_NO (7): When no error occured since last call of this function   \r
+*\r
+*   This function returns the last occured error code of an RX or TX message,\r
+*   since the last call of this function.\r
+*\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (21) */\r
+/* USER CODE END */\r
+\r
+uint32_t canGetLastError(canBASE_t *node)\r
+{\r
+    uint32_t errorCode;\r
+\r
+/* USER CODE BEGIN (22) */\r
+/* USER CODE END */\r
+\r
+    /** - Get last error code */\r
+    errorCode = node->ES & 7U;\r
+\r
+    /**   @note The function canInit has to be called before this function can be used. */\r
+\r
+/* USER CODE BEGIN (23) */\r
+/* USER CODE END */\r
+\r
+    return errorCode;\r
+}\r
+\r
+\r
+/** @fn uint32_t canGetErrorLevel(canBASE_t *node)\r
+*   @brief Gets error level of a CAN node\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*   @return The function will return:\r
+*           - canLEVEL_ACTIVE (0x00): When RX- and TX error counters are below 96   \r
+*           - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and 127     \r
+*           - canLEVEL_PASSIVE (0x20): When RX- or TX error counter are between 128 and 255     \r
+*           - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255     \r
+*\r
+*   This function returns the current error level of a CAN node.\r
+*\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (24) */\r
+/* USER CODE END */\r
+\r
+uint32_t canGetErrorLevel(canBASE_t *node)\r
+{\r
+    uint32_t errorLevel;\r
+\r
+/* USER CODE BEGIN (25) */\r
+/* USER CODE END */\r
+\r
+    /** - Get error level */\r
+    errorLevel = node->ES & 0xE0U;\r
+\r
+    /**   @note The function canInit has to be called before this function can be used. */\r
+\r
+/* USER CODE BEGIN (26) */\r
+/* USER CODE END */\r
+\r
+    return errorLevel;\r
+}\r
+\r
+\r
+/** @fn void canEnableErrorNotification(canBASE_t *node)\r
+*   @brief Enable error notification\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*\r
+*   This function will enable the notification for the reaching the error levels warning, passive and bus off.\r
+*/\r
+\r
+/* USER CODE BEGIN (27) */\r
+/* USER CODE END */\r
+\r
+void canEnableErrorNotification(canBASE_t *node)\r
+{\r
+/* USER CODE BEGIN (28) */\r
+/* USER CODE END */\r
+\r
+    node->CTL |= 8U;\r
+\r
+    /**   @note The function canInit has to be called before this function can be used. */\r
+\r
+/* USER CODE BEGIN (29) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void canDisableErrorNotification(canBASE_t *node)\r
+*   @brief Disable error notification\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*\r
+*   This function will disable the notification for the reaching the error levels warning, passive and bus off.\r
+*/\r
+\r
+/* USER CODE BEGIN (30) */\r
+/* USER CODE END */\r
+\r
+void canDisableErrorNotification(canBASE_t *node)\r
+{\r
+/* USER CODE BEGIN (31) */\r
+/* USER CODE END */\r
+\r
+    node->CTL &= ~8U;\r
+\r
+    /**   @note The function canInit has to be called before this function can be used. */\r
+\r
+/* USER CODE BEGIN (32) */\r
+/* USER CODE END */\r
+}\r
+\r
+/** @fn void canIoSetDirection(canBASE_t *node,uint32_t TxDir,uint32_t RxDir)\r
+*   @brief Set Port Direction\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*   @param[in] TxDir - TX Pin direction\r
+*   @param[in] RxDir - RX Pin direction\r
+*\r
+*   Set the direction of CAN pins at runtime when configured as IO pins.\r
+*/\r
+void canIoSetDirection(canBASE_t *node,uint32_t TxDir,uint32_t RxDir)\r
+{\r
+    node->TIOC = TxDir << 2;\r
+    node->RIOC = RxDir << 2;\r
+}\r
+\r
+/** @fn void canIoSetPort(canBASE_t *node, uint32_t TxValue, uint32_t RxValue)\r
+*   @brief Write Port Value\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*   @param[in] TxValue - TX Pin value 0 or 1\r
+*   @param[in] RxValue - RX Pin value 0 or 1\r
+*\r
+*   Writes a value to TX and RX pin of a given CAN module when configured as IO pins.\r
+*/\r
+void canIoSetPort(canBASE_t *node, uint32_t TxValue, uint32_t RxValue)\r
+{\r
+/* USER CODE BEGIN (33) */\r
+/* USER CODE END */\r
+\r
+    node->TIOC = TxValue << 1;\r
+    node->RIOC = RxValue << 1;\r
+\r
+/* USER CODE BEGIN (34) */\r
+/* USER CODE END */\r
+}\r
+\r
+/** @fn uint32_t canIoTxGetBit(canBASE_t *node)\r
+*   @brief Read TX Bit\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*\r
+*   Reads a the current value from the TX pin of the given CAN port\r
+*/\r
+uint32_t canIoTxGetBit(canBASE_t *node)\r
+{\r
+/* USER CODE BEGIN (35) */\r
+/* USER CODE END */\r
+\r
+    return (node->TIOC >> 0) & 1U;\r
+}\r
+\r
+/** @fn uint32_t canIoRxGetBit(canBASE_t *node)\r
+*   @brief Read RX Bit\r
+*   @param[in] node Pointer to CAN node:\r
+*              - canREG1: CAN1 node pointer\r
+*              - canREG2: CAN2 node pointer\r
+*              - canREG3: CAN3 node pointer\r
+*\r
+*   Reads a the current value from the RX pin of the given CAN port\r
+*/\r
+uint32_t canIoRxGetBit(canBASE_t *node)\r
+{\r
+/* USER CODE BEGIN (36) */\r
+/* USER CODE END */\r
+\r
+    return (node->RIOC >> 0) & 1U;\r
+}\r
+\r
+/** @fn void can1HighLevelInterrupt(void)\r
+*   @brief CAN1 Level 0 Interrupt Handler\r
+*/\r
+\r
+/* USER CODE BEGIN (37) */\r
+/* USER CODE END */\r
+\r
+\r
+#pragma INTERRUPT(can1HighLevelInterrupt, IRQ)\r
+\r
+void can1HighLevelInterrupt(void)\r
+{\r
+    uint32_t value = canREG1->INT;\r
+\r
+/* USER CODE BEGIN (38) */\r
+/* USER CODE END */\r
+\r
+    if (value == 0x8000U)\r
+    {\r
+        canErrorNotification(canREG1, canREG1->ES & 0xE0U);\r
+        return;\r
+    }\r
+\r
+    /** - Setup IF1 for clear pending interrupt flag */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1CMD = 0x08;\r
+    canREG1->IF1NO  = value;\r
+\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1CMD = 0x87;\r
+\r
+    canMessageNotification(canREG1, value);\r
+\r
+/* USER CODE BEGIN (39) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void can1LowLevelInterrupt(void)\r
+*   @brief CAN1 Level 1 Interrupt Handler\r
+*/\r
+\r
+/* USER CODE BEGIN (40) */\r
+/* USER CODE END */\r
+\r
+#pragma INTERRUPT(can1LowLevelInterrupt, IRQ)\r
+\r
+void can1LowLevelInterrupt(void)\r
+{\r
+    uint32_t messageBox = canREG1->INT >> 16U;\r
+\r
+/* USER CODE BEGIN (41) */\r
+/* USER CODE END */\r
+\r
+    /** - Setup IF1 for clear pending interrupt flag */\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1CMD = 0x08;\r
+    canREG1->IF1NO  = messageBox;\r
+\r
+    while (canREG1->IF1STAT & 0x80);\r
+\r
+    canREG1->IF1CMD = 0x87;\r
+\r
+    canMessageNotification(canREG1, messageBox);\r
+\r
+/* USER CODE BEGIN (42) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void can2HighLevelInterrupt(void)\r
+*   @brief CAN2 Level 0 Interrupt Handler\r
+*/\r
+\r
+/* USER CODE BEGIN (43) */\r
+/* USER CODE END */\r
+\r
+#pragma INTERRUPT(can2HighLevelInterrupt, IRQ)\r
+\r
+void can2HighLevelInterrupt(void)\r
+{\r
+    uint32_t value = canREG2->INT;\r
+\r
+/* USER CODE BEGIN (44) */\r
+/* USER CODE END */\r
+\r
+    if (value == 0x8000U)\r
+    {\r
+        canErrorNotification(canREG2, canREG2->ES & 0xE0U);\r
+        return;\r
+    }\r
+\r
+    /** - Setup IF1 for clear pending interrupt flag */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1CMD = 0x08;\r
+    canREG2->IF1NO  = value;\r
+\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1CMD = 0x87;\r
+\r
+    canMessageNotification(canREG2, value);\r
+\r
+/* USER CODE BEGIN (45) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void can2LowLevelInterrupt(void)\r
+*   @brief CAN2 Level 1 Interrupt Handler\r
+*/\r
+\r
+/* USER CODE BEGIN (46) */\r
+/* USER CODE END */\r
+\r
+#pragma INTERRUPT(can2LowLevelInterrupt, IRQ)\r
+\r
+void can2LowLevelInterrupt(void)\r
+{\r
+    uint32_t messageBox = canREG2->INT >> 16U;\r
+\r
+/* USER CODE BEGIN (47) */\r
+/* USER CODE END */\r
+\r
+    /** - Setup IF1 for clear pending interrupt flag */\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1CMD = 0x08;\r
+    canREG2->IF1NO  = messageBox;\r
+\r
+    while (canREG2->IF1STAT & 0x80);\r
+\r
+    canREG2->IF1CMD = 0x87;\r
+\r
+    canMessageNotification(canREG2, messageBox);\r
+\r
+/* USER CODE BEGIN (48) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+\r
diff --git a/source/commands.c b/source/commands.c

index a5340c9d980c4cbdb12f6439c063b800fa59a3d7..072d29dd2b389f49a6d56c76963a6457fb8fa780 100644 (file)
--- a/source/commands.c
+++ b/source/commands.c
@@ -13,13 +13,47 @@
  #include "cmdio_tisci.h"
  #include "string.h"
  #include "stdio.h"
+#include "can.h"
  
  cmd_des_t const **cmd_list;
+xSemaphoreHandle canMsgReceived;
+
  
  /* ------------------------------
   * User defined command functions
   * ------------------------------
   */
+int cmd_do_testcanloopback(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+       canMsgReceived = xSemaphoreCreateCounting(1, 0);
+       print((uint8_t *)"\r\nTesting CAN loopback\r\n");
+       print((uint8_t *)"Sending message...");
+
+       uint32_t cnt=0, error =0;
+       uint8_t tx_data[8] = {'T', 'E', 'S', 'T', ' ', 'C', 'A', 'N'};
+       uint8_t rx_data[8];
+
+       canTransmit(canREG1, canMESSAGE_BOX1, tx_data); /* transmitting 8 different chunks 1 by 1 */
+
+       xSemaphoreTake(canMsgReceived, portMAX_DELAY);
+       canGetData(canREG2, canMESSAGE_BOX1, rx_data); /* copy to RAM */
+
+       for(cnt=0;cnt<8;cnt++)
+     {
+          if(tx_data[cnt] != rx_data[cnt])
+          {
+               error++; /* data error */
+          }
+     }
+       print((uint8_t *)"message received\r\nErrors: ");
+       char errBuf[1];
+       i2str(errBuf, error, 1, 10);
+       print((uint8_t *)errBuf);
+       print((uint8_t *)"\r\n");
+       vSemaphoreDelete(canMsgReceived);
+       return 0;
+}
+
  int cmd_do_testopchar(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
  {
    int opchar;
@@ -99,6 +133,11 @@ int val;
   * Command definitions
   * -------------------
   */
+cmd_des_t const cmd_des_testcanloopback={
+    0, 0,
+    "CANLOOPBACK","sends message from CAN1 to CAN2 in message box 1",
+    cmd_do_testcanloopback, (void *)&cmd_list
+};
  cmd_des_t const cmd_des_help={
      0, 0,
      "HELP","prints help for commands\r\n",
@@ -202,6 +241,7 @@ cmd_des_t const *cmd_list_2[]={
  cmd_des_t const *cmd_list_main[]={
    &cmd_des_help,
    &cmd_des_error,
+  &cmd_des_testcanloopback,
    CMD_DES_INCLUDE_SUBLIST(cmd_list_1),
    CMD_DES_CONTINUE_AT(cmd_list_2),
    &cmd_des_hiddedn,
diff --git a/source/dma.c b/source/dma.c

new file mode 100644 (file)

index 0000000..692d049
--- /dev/null
+++ b/source/dma.c
@@ -0,0 +1,109 @@
+/** @file dma.c \r
+*   @brief DMA Driver Inmplmentation File\r
+*   @date 22.Aug.2011\r
+*   @version 1.01.000\r
+*\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2010, All rights reserved. */\r
+\r
+\r
+#include "dma.h"\r
+\r
+g_dmaCTRL g_dmaCTRLPKT;\r
+\r
+/** @fn void dmaEnable(void)\r
+*   @brief enables dma module\r
+*\r
+*   This function brings DMA out of reset\r
+*/\r
+\r
+void dmaEnable(void)\r
+{\r
+  dmaREG->GCTRL  = 0x00000001; /* reset dma       */\r
+  dmaREG->GCTRL |= 0x00010000; /* enable dma      */\r
+  dmaREG->GCTRL |= 0x00000300; /* stop at suspend */   \r
+}\r
+\r
+\r
+\r
+/** @fn void dmaReqAssign(uint32_t channel,uint32_t reqline)\r
+*   @brief Initializes the DMA Driver\r
+*\r
+*   This function assigns dma request lines to channels\r
+*/\r
+\r
+void dmaReqAssign(uint32_t channel,uint32_t reqline)\r
+{\r
+    register uint32_t i=0,j=0;\r
+\r
+    i = channel >> 2;              /* Find the register to configure */\r
+    j = channel -(i<<2);           /* Find the offset of the type    */\r
+    j = 3-j;                       /* reverse the byte order         */\r
+    j = j<<3;                      /* find the bit location          */\r
+\r
+    /* mapping channel 'i' to request line 'j' */\r
+    dmaREG->DREQASI[i] &= ~(0xff<<j);   \r
+    dmaREG->DREQASI[i] |= (reqline<<j);\r
+}\r
+\r
+\r
+\r
+/** @fn void dmaSetCtrlPacket(uint32_t channel)\r
+*   @brief Initializes the DMA Driver\r
+*\r
+*   This function sets control packet\r
+*/\r
+\r
+void dmaSetCtrlPacket(uint32_t channel)\r
+{\r
+    register uint32_t i=0,j=0;\r
+    \r
+    dmaRAMREG->PCP[channel].ISADDR  =  g_dmaCTRLPKT.SADD;\r
+    \r
+    dmaRAMREG->PCP[channel].IDADDR  =  g_dmaCTRLPKT.DADD;\r
+    \r
+    dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16) | g_dmaCTRLPKT.ELCNT;\r
+  \r
+    dmaRAMREG->PCP[channel].CHCTRL  = (g_dmaCTRLPKT.RDSIZE    << 14) | (g_dmaCTRLPKT.WRSIZE    << 12) | (g_dmaCTRLPKT.TTYPE << 8)| \\r
+                                      (g_dmaCTRLPKT.ADDMODERD << 3 ) | (g_dmaCTRLPKT.ADDMODEWR << 1 ) | (g_dmaCTRLPKT.AUTOINIT);\r
+\r
+    dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16);\r
+\r
+    dmaRAMREG->PCP[channel].EIOFF   = (g_dmaCTRLPKT.ELDOFFSET << 16) | (g_dmaCTRLPKT.ELSOFFSET);\r
+  \r
+    dmaRAMREG->PCP[channel].FIOFF   = (g_dmaCTRLPKT.FRDOFFSET << 16) | (g_dmaCTRLPKT.FRSOFFSET);\r
+\r
+    i = channel >> 3;                /* Find the register to write                    */\r
+    j = channel -(i << 3);           /* Find the offset of the 4th bit                */\r
+    j = 7 -j;                        /* Reverse the order of the 4th bit offset       */\r
+    j = j<<2;                        /* Find the bit location of the 4th bit to write */\r
+\r
+    dmaREG->PAR[i] &= ~(0xf<<j);\r
+    dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN<<j);\r
+}\r
+\r
+\r
+\r
+/** @fn void dmaSetCtrlPacket(uint32_t channel)\r
+*   @brief Initializes the DMA Driver\r
+*\r
+*   This function sets control packet\r
+*/\r
+\r
+void dmaSetChEnable(uint32_t channel,uint32_t type)\r
+{\r
+    if(type == DMA_HW)\r
+    {\r
+     dmaREG->HWCHENAS = (1 << channel);\r
+    }\r
+    else if(type == DMA_SW)\r
+    {\r
+     dmaREG->SWCHENAS = (1 << channel);\r
+    }\r
+}\r
+\r
+\r
+\r
+/**/\r
+\r
diff --git a/source/notification.c b/source/notification.c

index a737780b179af1a7fff103ac7c814e7d5d0b15b6..49c2f35096326dcc31cdb9644b09b1391f180de3 100644 (file)
--- a/source/notification.c
+++ b/source/notification.c
@@ -13,6 +13,7 @@
  \r
  #include "esm.h"\r
  #include "sys_selftest.h"\r
+#include "can.h"\r
  #include "sci.h"\r
  /* USER CODE BEGIN (0) */\r
  #include "FreeRTOS.h"\r
@@ -21,6 +22,7 @@
  \r
  extern xQueueHandle inputCharacterQueue;\r
  extern uint8_t character;\r
+extern xSemaphoreHandle canMsgReceived;\r
  /* USER CODE END */\r
  \r
  void esmGroup1Notification(uint32_t channel)\r
@@ -70,6 +72,37 @@ void memoryPort1TestFailNotification(uint32_t groupSelect, uint32_t dataSelect,
  \r
  /* USER CODE BEGIN (8) */\r
  /* USER CODE END */\r
+void canErrorNotification(canBASE_t *node, uint32_t notification)\r
+{\r
+/*  enter user code and remove the while loop... */\r
+/* USER CODE BEGIN (13) */\r
+       if (notification != canERROR_OK) while(1) ;\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+/* USER CODE BEGIN (14) */\r
+/* USER CODE END */\r
+\r
+void canMessageNotification(canBASE_t *node, uint32_t messageBox)  \r
+{\r
+/*  enter user code and remove the while loop... */\r
+/* USER CODE BEGIN (15) */\r
+    if(node==canREG2)\r
+    {\r
+       if (messageBox == canMESSAGE_BOX1)\r
+       {\r
+               /* node 2 - receive testloopback message complete */\r
+                        while(!canIsRxMessageArrived(canREG2, canMESSAGE_BOX1));\r
+                        xSemaphoreGiveFromISR(canMsgReceived, NULL);\r
+       }\r
+    }\r
+\r
+/* USER CODE END */\r
+}\r
+\r
+/* USER CODE BEGIN (16) */\r
+/* USER CODE END */\r
  \r
  void sciNotification(sciBASE_t *sci, uint32_t flags)     \r
  {\r
diff --git a/source/sci.c b/source/sci.c

index 8cd0210ec791be73a18ff83df9de2b9be73d91fe..93345eb03fd880a8a37dc60cd0cddf30a99d4f76 100644 (file)
--- a/source/sci.c
+++ b/source/sci.c
@@ -511,6 +511,7 @@ void sciHighLevelInterrupt(void)
          break;\r
      }\r
  /* USER CODE END */\r
+\r
  /* USER CODE BEGIN (27) */\r
  /* USER CODE END */\r
  }\r
diff --git a/source/sys_main.c b/source/sys_main.c

index 0d8aa25e6ec816397c273b64ee71ff5257892506..d4039d8986a8298eea4c6432e4ccfabd0a457ab5 100644 (file)
--- a/source/sys_main.c
+++ b/source/sys_main.c
@@ -21,6 +21,7 @@
  #include "cmd_proc_freertos_tms570.h"\r
  #include "FreeRTOS.h"\r
  #include "os_task.h"\r
+#include "can.h"\r
  /* USER CODE END */\r
  \r
  \r
@@ -41,6 +42,10 @@ void main(void)
  {\r
  /* USER CODE BEGIN (3) */\r
         sciInit();\r
+       canInit();\r
+    canEnableErrorNotification(canREG1);\r
+    canEnableErrorNotification(canREG2);\r
+\r
         _enable_IRQ();\r
         initCmdProc(1, (uint8_t*)"\r\nType commands\r\n", (uint8_t *)"\r\n--> ");\r
  \r
diff --git a/source/sys_startup.c b/source/sys_startup.c

index f1ac20e7312600efb4c210fd259fe9f587680dca..400645d712d9da73ccd952f879c66dd1f203f490 100644 (file)
--- a/source/sys_startup.c
+++ b/source/sys_startup.c
@@ -102,6 +102,7 @@ static const t_isrFuncPTR s_vim_init[] =
      &phantomInterrupt,\r
      &phantomInterrupt,\r
      &phantomInterrupt,\r
+    &can1HighLevelInterrupt,\r
      &phantomInterrupt,\r
      &phantomInterrupt,\r
      &phantomInterrupt,\r
@@ -120,8 +121,7 @@ static const t_isrFuncPTR s_vim_init[] =
      &phantomInterrupt,\r
      &phantomInterrupt,\r
      &phantomInterrupt,\r
-    &phantomInterrupt,\r
-    &phantomInterrupt,\r
+    &can2HighLevelInterrupt,\r
      &phantomInterrupt,\r
      &phantomInterrupt,\r
      &phantomInterrupt,\r
@@ -849,7 +849,7 @@ void _c_int00()
                          | (0U << 13U)\r
                          | (0U << 14U)\r
                          | (0U << 15U)\r
-                        | (0U << 16U)\r
+                        | (1U << 16U)\r
                          | (0U << 17U)\r
                          | (0U << 18U)\r
                          | (0U << 19U)\r
@@ -869,7 +869,7 @@ void _c_int00()
      vimREG->REQMASKSET1 = 0U\r
                          | (0U << 1U)\r
                          | (0U << 2U)\r
-                        | (0U << 3U)\r
+                        | (1U << 3U)\r
                          | (0U << 4U)\r
                          | (0U << 5U)\r
                          | (0U << 6U)\r
author	Michal Horn <hornmich@fel.cvut.cz>
	Tue, 14 Aug 2012 12:13:36 +0000 (14:13 +0200)
committer	Michal Horn <hornmich@fel.cvut.cz>
	Tue, 14 Aug 2012 12:13:36 +0000 (14:13 +0200)
CommandStoring.dil		patch \| blob \| history
Debug/CmdProcTISCI.map		patch \| blob \| history
Debug/CmdProcTISCI.out		patch \| blob \| history
Debug/ccsObjs.opt		patch \| blob \| history
Debug/makefile		patch \| blob \| history
Debug/source/can.obj	[new file with mode: 0644]	patch \| blob
Debug/source/can.pp	[new file with mode: 0644]	patch \| blob
Debug/source/ccsSrcs.opt		patch \| blob \| history
Debug/source/cmd_proc_freertos_tms570.obj		patch \| blob \| history
Debug/source/cmdio_tisci.obj		patch \| blob \| history
Debug/source/commands.obj		patch \| blob \| history
Debug/source/commands.pp		patch \| blob \| history
Debug/source/dma.obj	[new file with mode: 0644]	patch \| blob
Debug/source/dma.pp	[new file with mode: 0644]	patch \| blob
Debug/source/esm.obj		patch \| blob \| history
Debug/source/notification.obj		patch \| blob \| history
Debug/source/notification.pp		patch \| blob \| history
Debug/source/os_croutine.obj		patch \| blob \| history
Debug/source/os_heap.obj		patch \| blob \| history
Debug/source/os_list.obj		patch \| blob \| history
Debug/source/os_port.obj		patch \| blob \| history
Debug/source/os_queue.obj		patch \| blob \| history
Debug/source/os_tasks.obj		patch \| blob \| history
Debug/source/os_timer.obj		patch \| blob \| history
Debug/source/pinmux.obj		patch \| blob \| history
Debug/source/sci.obj		patch \| blob \| history
Debug/source/subdir_rules.mk		patch \| blob \| history
Debug/source/subdir_vars.mk		patch \| blob \| history
Debug/source/sys_main.obj		patch \| blob \| history
Debug/source/sys_main.pp		patch \| blob \| history
Debug/source/sys_phantom.obj		patch \| blob \| history
Debug/source/sys_selftest.obj		patch \| blob \| history
Debug/source/sys_startup.obj		patch \| blob \| history
Debug/source/system.obj		patch \| blob \| history
include/dma.h	[new file with mode: 0644]	patch \| blob
include/sys_vim.h		patch \| blob \| history
source/can.c	[new file with mode: 0644]	patch \| blob
source/commands.c		patch \| blob \| history
source/dma.c	[new file with mode: 0644]	patch \| blob
source/notification.c		patch \| blob \| history
source/sci.c		patch \| blob \| history
source/sys_main.c		patch \| blob \| history
source/sys_startup.c		patch \| blob \| history