-# TMS570LS3137ZWT 10/01/12 15:05:08\r
+# TMS570LS3137ZWT 10/04/12 15:49:44\r
# \r
ARCH=TMS570LS3137ZWT\r
# \r
DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_TYPE.VALUE=IRQ\r
DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_ENABLE.VALUE=0\r
DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_ENABLE.VALUE=0\r
-DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=1\r
DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_DP_SELECTED.VALUE=1\r
DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_MAPPING.VALUE=8\r
DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_NAME.VALUE=vPreemptiveTick\r
DRIVER.RTP.VAR.RTP_PORT_BIT16_DOUT.VALUE=0\r
DRIVER.RTP.VAR.RTP_PORT_BIT2_PDR.VALUE=0\r
DRIVER.DMM.VAR.DMM_PORT_BIT14_PULL.VALUE=2\r
-DRIVER.DMM.VAR.DMM_PORT_BIT17_DOUT.VALUE=0\r
+DRIVER.DMM.VAR.DMM_PORT_BIT17_DOUT.VALUE=1\r
DRIVER.DMM.VAR.DMM_PORT_BIT17_PSL.VALUE=1\r
DRIVER.DMM.VAR.DMM_PORT_BIT4_PULDIS.VALUE=1\r
DRIVER.DMM.VAR.DMM_PORT_BIT1_DIR.VALUE=1\r
DRIVER.DMM.VAR.DMM_PORT_BIT5_DOUT.VALUE=0\r
DRIVER.DMM.VAR.DMM_PORT_BIT13_PULL.VALUE=2\r
DRIVER.DMM.VAR.DMM_PORT_BIT16_DOUT.VALUE=0\r
-DRIVER.DMM.VAR.DMM_PORT_BIT17_FUN.VALUE=1\r
+DRIVER.DMM.VAR.DMM_PORT_BIT17_FUN.VALUE=0\r
DRIVER.DMM.VAR.DMM_PORT_BIT15_PSL.VALUE=1\r
DRIVER.DMM.VAR.DMM_PORT_BIT17_PULDIS.VALUE=0\r
DRIVER.DMM.VAR.DMM_PORT_BIT17_PDR.VALUE=0\r
<HDR6EMAC>\r
<NAME>mdio.h</NAME>\r
</HDR6EMAC>\r
- <SRC1EMAC/>\r
- <SRC2EMAC/>\r
+ <SRC1EMAC>\r
+ <NAME>emac.c</NAME>\r
+ </SRC1EMAC>\r
+ <SRC2EMAC>\r
+ <NAME>mdio.c</NAME>\r
+ </SRC2EMAC>\r
<HDRDCC>\r
<NAME>dcc.h</NAME>\r
</HDRDCC>\r
<PATH>include\mdio.h</PATH>\r
</HDR6EMAC>\r
<SRC1EMAC>\r
- <PATH/>\r
+ <PATH>source\emac.c</PATH>\r
</SRC1EMAC>\r
<SRC2EMAC>\r
- <PATH/>\r
+ <PATH>source\mdio.c</PATH>\r
</SRC2EMAC>\r
</FILENAMES>\r
</EMAC>\r
--- /dev/null
+#ifndef _EMAC_TEST_H_
+#define _EMAC_TEST_H_
+
+/* ************************************************* */
+/* Emac frame buffer related stuff */
+/* ************************************************* */
+typedef struct _EMAC_Desc {
+ struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */
+ uint8_t *pBuffer; /* Pointer to data buffer */
+ uint32_t BufOffLen; /* Buffer Offset(MSW) and Length(LSW) */
+ uint32_t PktFlgLen; /* Packet Flags(MSW) and Length(LSW) */
+} EMAC_Desc;
+
+/* Packet Flags */
+#define EMAC_DSC_FLAG_SOP 0x80000000u
+#define EMAC_DSC_FLAG_EOP 0x40000000u
+#define EMAC_DSC_FLAG_OWNER 0x20000000u
+#define EMAC_DSC_FLAG_EOQ 0x10000000u
+#define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u
+#define EMAC_DSC_FLAG_PASSCRC 0x04000000u
+
+/* ************************************************* */
+/* Ethernet frame */
+/* ************************************************* */
+typedef struct {
+ uint8_t destination[6];
+ uint8_t source[6];
+ uint16_t len;
+ uint8_t data[50];
+ uint32_t fcs;
+} eth_frame_t;
+
+/* ************************************************* */
+int emac_test(void);
+#endif /* _EMAC_TEST_H_ */
--- /dev/null
+#ifndef _PHY_H_
+#define _PHY_H_
+
+/* ************************************************* */
+/* PHY */
+/* ************************************************* */
+#define PHY_BMCR 0x0 /* Basic Mode Control Register */
+#define PHY_BMSR 0x01 /* Basic Mode Status Register */
+#define PHY_ANAR 0x4 /* Auto-Negotiation Advertisement Register */
+#define PHY_LEDCR 0x18 /* LED Direct Control Register */
+#define PHY_PHYCR 0x19 /* PHY Control Register */
+#define PHY_PHYCR2 0x1C /* PHY Control Register 2 */
+#define PHY_STS 0x10 /* PHY Status Register */
+#define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */
+
+/* BMCR */
+#define PHY_RESET_m (1 << 15)
+#define PHY_SPEED_m (1 << 13)
+#define PHY_AUTONEG_EN_m (1 << 12) /* ! */
+#define PHY_POWERDOWN_m (1 << 11)
+#define PHY_DUPLEX_m (1 << 8)
+#define PHY_AUTONEG_REST (1 << 9)
+
+/* BMSR */
+#define PHY_A_NEG_COMPLETE_m (1 << 5)
+
+/* ANAR & ANLPAR */
+#define PHY_100BASET4_m (1 << 9)
+#define PHY_100BASETXDUPL_m (1 << 8)
+#define PHY_100BASETX_m (1 << 7)
+#define PHY_10BASETDUPL_m (1 << 6)
+#define PHY_10BASET_m (1 << 5)
+
+
+/* ************************************************* */
+void PHY_partner_ability_get(unsigned int mdioBaseAddr, unsigned int phyAddr, unsigned short *data);
+void PHY_configure(unsigned int mdioBaseAddr, unsigned int phyAddr);
+
+
+#endif /* _PHY_H_ */
#include "hout.h"
#include "vbat.h"
#include "lin.h"
+#include "emac_test.h"
/** @brief Count of AD channels in ADC1
*/
cmd_do_test_mout_fault, (void *)&cmd_list
};
/** @brief command descriptor for test hout fault state command */
-cmd_des_t const cmd_des_test_hout_fail={
+cmd_des_t const cmd_des_test_ethernet = {
0, 0,
"HOUTFAIL","Test if some HOUT port is in fault state",
cmd_do_test_hout_fault, (void *)&cmd_list
};
+cmd_des_t const cmd_des_test_hout_fail={
+ 0, 0,
+ "ETHERNET", "Try to send few ethernet frames",
+ emac_test, (void *)&cmd_list
+};
/** @brief command descriptor for show help command */
cmd_des_t const cmd_des_help={
0, 0,
&cmd_des_test_hout_fail,
&cmd_des_test_mout_fail,
&cmd_des_test_sdram,
+ &cmd_des_test_ethernet,
NULL
};
*\r
* This function initializes the DMM module.\r
*/\r
+\r
+/* ***************************************************** */\r
+/* Modify only by hand -- do not use Halcogen! */\r
+/* !!! Ignore comments -- they are wrong !!! */\r
+/* ***************************************************** */\r
void dmmInit(void)\r
{\r
-\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
- /** @b intalise @b DMM */\r
-\r
- /** @b initalise @b DMM @b Port */\r
dmmREG->PC3 = 0 /* DATA[0] */\r
- | (0 << 1) /* DATA[1] */\r
+ | (0 << 1)\r
| (0 << 2) /* DATA[2] */\r
| (0 << 3) /* DATA[3] */\r
| (0 << 4) /* DATA[4] */\r
| (0 << 14) /* DATA[14] */\r
| (0 << 15) /* DATA[15] */\r
| (0 << 16) /* DMM SYNC */\r
- | (0 << 17) /* DMM CLK */\r
+ | (0 << 17)\r
| (0 << 18); /* DMM ENA */\r
\r
/** - DMM Port direction */\r
- dmmREG->PC1 = 1 /* DMM SYNC */\r
- | (1 << 1) /* DMM CLK */\r
- | (1 << 2) /* DATA[0] */\r
- | (1 << 3) /* DATA[1] */\r
- | (1 << 4) /* DATA[2] */\r
- | (1 << 5) /* DATA[3] */\r
- | (1 << 6) /* DATA[4] */\r
- | (0 << 7) /* DATA[5] */\r
- | (0 << 8) /* DATA[6] */\r
- | (0 << 9) /* DATA[7] */\r
- | (0 << 10) /* DATA[8] */\r
- | (1 << 11) /* DATA[9] */\r
- | (0 << 12) /* DATA[10] */\r
- | (1 << 13) /* DATA[11] */\r
- | (1 << 14) /* DATA[12] */\r
- | (1 << 15) /* DATA[13] */\r
- | (0 << 16) /* DATA[14] */\r
- | (1 << 17) /* DATA[15] */\r
+ dmmREG->PC1 = 1 /* DATA[0] */\r
+ | (1 << 1)\r
+ | (1 << 2) /* DATA[2] */\r
+ | (1 << 3) /* DATA[3] */\r
+ | (1 << 4) /* DATA[4] */\r
+ | (1 << 5) /* DATA[5] */\r
+ | (1 << 6) /* DATA[6] */\r
+ | (0 << 7) /* DATA[7] */\r
+ | (0 << 8) /* DATA[8] */\r
+ | (0 << 9) /* DATA[9] */\r
+ | (0 << 10) /* DATA[10] */\r
+ | (1 << 11) /* DATA[11] */\r
+ | (0 << 12) /* DATA[12] */\r
+ | (1 << 13) /* DATA[13] */\r
+ | (1 << 14) /* DATA[14] */\r
+ | (0 << 15) /* DATA[15] */\r
+ | (0 << 16) /* DMM SYNC */\r
+ | (1 << 17)\r
| (1 << 18); /* DMM ENA */\r
\r
/** - DMM Port open drain enable */\r
dmmREG->PC6 = 0 /* DATA[0] */\r
- | (0 << 1) /* DATA[1] */\r
- | (1 << 2) /* DATA[2] */\r
- | (1 << 3) /* DATA[3] */\r
- | (1 << 4) /* DATA[4] */\r
+ | (0 << 1)\r
+ | (0 << 2) /* DATA[2] */\r
+ | (0 << 3) /* DATA[3] */\r
+ | (0 << 4) /* DATA[4] */\r
| (0 << 5) /* DATA[5] */\r
| (0 << 6) /* DATA[6] */\r
| (0 << 7) /* DATA[7] */\r
| (0 << 14) /* DATA[14] */\r
| (0 << 15) /* DATA[15] */\r
| (0 << 16) /* DMM SYNC */\r
- | (0 << 17) /* DMM CLK */\r
+ | (0 << 17)\r
| (0 << 18); /* DMM ENA */\r
\r
\r
/** - DMM Port pullup / pulldown selection */\r
dmmREG->PC8 = 0 /* DATA[0] */\r
- | (0 << 1) /* DATA[1] */\r
+ | (1 << 1)\r
| (0 << 2) /* DATA[2] */\r
| (0 << 3) /* DATA[3] */\r
| (0 << 4) /* DATA[4] */\r
| (1 << 14) /* DATA[14] */\r
| (1 << 15) /* DATA[15] */\r
| (1 << 16) /* DMM SYNC */\r
- | (0 << 17) /* DMM CLK */\r
+ | (1 << 17)\r
| (1 << 18); /* DMM ENA */\r
\r
\r
/** - DMM Port pullup / pulldown enable*/\r
dmmREG->PC7 = 1 /* DATA[0] */\r
- | (0 << 1) /* DATA[1] */\r
- | (0 << 2) /* DATA[2] */\r
- | (0 << 3) /* DATA[3] */\r
- | (0 << 4) /* DATA[4] */\r
- | (0 << 5) /* DATA[5] */\r
- | (0 << 6) /* DATA[6] */\r
+ | (1 << 1)\r
+ | (1 << 2) /* DATA[2] */\r
+ | (1 << 3) /* DATA[3] */\r
+ | (1 << 4) /* DATA[4] */\r
+ | (1 << 5) /* DATA[5] */\r
+ | (1 << 6) /* DATA[6] */\r
| (0 << 7) /* DATA[7] */\r
| (0 << 8) /* DATA[8] */\r
| (0 << 9) /* DATA[9] */\r
| (0 << 14) /* DATA[14] */\r
| (0 << 15) /* DATA[15] */\r
| (0 << 16) /* DMM SYNC */\r
- | (0 << 17) /* DMM CLK */\r
+ | (1 << 17)\r
| (0 << 18); /* DMM ENA */\r
\r
/* DMM set all pins to functional */\r
dmmREG->PC0 = 0 /* DATA[0] */\r
- | (0 << 1) /* DATA[1] */\r
+ | (0 << 1)\r
| (0 << 2) /* DATA[2] */\r
| (0 << 3) /* DATA[3] */\r
| (0 << 4) /* DATA[4] */\r
| (0 << 5) /* DATA[5] */\r
- | (0 << 6) /* DATA[6] */\r
+ | (1 << 6) /* DATA[6] */\r
| (1 << 7) /* DATA[7] */\r
| (1 << 8) /* DATA[8] */\r
| (1 << 9) /* DATA[9] */\r
| (1 << 12) /* DATA[12] */\r
| (0 << 13) /* DATA[13] */\r
| (1 << 14) /* DATA[14] */\r
- | (0 << 15) /* DATA[15] */\r
+ | (1 << 15) /* DATA[15] */\r
| (1 << 16) /* DMM SYNC */\r
- | (0 << 17) /* DMM CLK */\r
+ | (0 << 17)\r
| (1 << 18); /* DMM ENA */\r
\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-\r
}\r
--- /dev/null
+/**\r
+ * \file emac.c\r
+ *\r
+ * \brief EMAC APIs.\r
+ *\r
+ * This file contains the device abstraction layer APIs for EMAC.\r
+ */\r
+\r
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
+ * ALL RIGHTS RESERVED\r
+ */\r
+\r
+#include "sys_common.h"\r
+#include "hw_reg_access.h"\r
+#include "emac.h"\r
+#include "hw_emac.h"\r
+#include "hw_emac_ctrl.h"\r
+\r
+/*******************************************************************************\r
+* INTERNAL MACRO DEFINITIONS\r
+*******************************************************************************/\r
+#define EMAC_CONTROL_RESET (0x01u)\r
+#define EMAC_SOFT_RESET (0x01u)\r
+#define EMAC_MAX_HEADER_DESC (8u)\r
+#define EMAC_UNICAST_DISABLE (0xFFu)\r
+\r
+/*******************************************************************************\r
+* API FUNCTION DEFINITIONS\r
+*******************************************************************************/\r
+/**\r
+ * \brief Enables the TXPULSE Interrupt Generation.\r
+ *\r
+ * \param emacBase Base address of the EMAC Module registers.\r
+ * \param emacCtrlBase Base address of the EMAC CONTROL module registers\r
+ * \param ctrlCore Control core for which the interrupt to be enabled.\r
+ * \param channel Channel number for which interrupt to be enabled\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACTxIntPulseEnable(unsigned int emacBase, unsigned int emacCtrlBase,\r
+ unsigned int ctrlCore, unsigned int channel)\r
+{\r
+ HWREG(emacBase + EMAC_TXINTMASKSET) |= (1 << channel);\r
+\r
+ HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) |= (1 << channel);\r
+}\r
+\r
+/**\r
+ * \brief Disables the TXPULSE Interrupt Generation.\r
+ *\r
+ * \param emacBase Base address of the EMAC Module registers.\r
+ * \param emacCtrlBase Base address of the EMAC CONTROL module registers\r
+ * \param ctrlCore Control core for which the interrupt to be disabled.\r
+ * \param channel Channel number for which interrupt to be disabled\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACTxIntPulseDisable(unsigned int emacBase, unsigned int emacCtrlBase,\r
+ unsigned int ctrlCore, unsigned int channel)\r
+{\r
+ HWREG(emacBase + EMAC_TXINTMASKCLEAR) |= (1 << channel);\r
+\r
+ HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) &= ~(1 << channel);\r
+}\r
+\r
+/**\r
+ * \brief Enables the RXPULSE Interrupt Generation.\r
+ *\r
+ * \param emacBase Base address of the EMAC Module registers.\r
+ * \param emacCtrlBase Base address of the EMAC CONTROL module registers\r
+ * \param ctrlCore Control core for which the interrupt to be enabled.\r
+ * \param channel Channel number for which interrupt to be enabled\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACRxIntPulseEnable(unsigned int emacBase, unsigned int emacCtrlBase,\r
+ unsigned int ctrlCore, unsigned int channel)\r
+{\r
+ HWREG(emacBase + EMAC_RXINTMASKSET) |= (1 << channel);\r
+\r
+ HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) |= (1 << channel);\r
+}\r
+\r
+/**\r
+ * \brief Disables the RXPULSE Interrupt Generation.\r
+ *\r
+ * \param emacBase Base address of the EMAC Module registers.\r
+ * \param emacCtrlBase Base address of the EMAC CONTROL module registers\r
+ * \param ctrlCore Control core for which the interrupt to be disabled.\r
+ * \param channel Channel number for which interrupt to be disabled\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACRxIntPulseDisable(unsigned int emacBase, unsigned int emacCtrlBase,\r
+ unsigned int ctrlCore, unsigned int channel)\r
+{\r
+ HWREG(emacBase + EMAC_RXINTMASKCLEAR) |= (1 << channel);\r
+\r
+ HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) &= ~(1 << channel);\r
+}\r
+/**\r
+ * \brief This API sets the RMII speed. The RMII Speed can be 10 Mbps or \r
+ * 100 Mbps\r
+ *\r
+ * \param emacBase Base address of the EMAC Module registers.\r
+ * \param speed speed for setting.\r
+ * speed can take the following values. \n\r
+ * EMAC_RMIISPEED_10MBPS - 10 Mbps \n\r
+ * EMAC_RMIISPEED_100MBPS - 100 Mbps. \r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACRMIISpeedSet(unsigned int emacBase, unsigned int speed)\r
+{\r
+ HWREG(emacBase + EMAC_MACCONTROL) &= ~EMAC_MACCONTROL_RMIISPEED;\r
+ \r
+ HWREG(emacBase + EMAC_MACCONTROL) |= speed;\r
+}\r
+\r
+/**\r
+ * \brief This API enables the MII control block\r
+ *\r
+ * \param emacBase Base address of the EMAC Module registers.\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACMIIEnable(unsigned int emacBase)\r
+{\r
+ HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_GMIIEN;\r
+}\r
+\r
+/**\r
+ * \brief This API sets the duplex mode of operation(full/half) for MAC.\r
+ *\r
+ * \param emacBase Base address of the EMAC Module registers.\r
+ * \param duplexMode duplex mode of operation.\r
+ * duplexMode can take the following values. \n\r
+ * EMAC_DUPLEX_FULL - Full Duplex \n\r
+ * EMAC_DUPLEX_HALF - Half Duplex.\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACDuplexSet(unsigned int emacBase, unsigned int duplexMode)\r
+{\r
+ HWREG(emacBase + EMAC_MACCONTROL) &= ~EMAC_MACCONTROL_FULLDUPLEX;\r
+ \r
+ HWREG(emacBase + EMAC_MACCONTROL) |= duplexMode;\r
+}\r
+\r
+/**\r
+ * \brief API to enable the transmit in the TX Control Register\r
+ * After the transmit is enabled, any write to TXHDP of\r
+ * a channel will start transmission\r
+ *\r
+ * \param emacBase Base Address of the EMAC Module Registers.\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACTxEnable(unsigned int emacBase)\r
+{\r
+ HWREG(emacBase + EMAC_TXCONTROL) = EMAC_TXCONTROL_TXEN;\r
+}\r
+\r
+/**\r
+ * \brief API to enable the receive in the RX Control Register\r
+ * After the transmit is enabled, and write to RXHDP of\r
+ * a channel, the data can be received in the destination\r
+ * specified by the corresponding RX buffer descriptor.\r
+ *\r
+ * \param emacBase Base Address of the EMAC Module Registers.\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACRxEnable(unsigned int emacBase)\r
+{\r
+ HWREG(emacBase + EMAC_RXCONTROL) = EMAC_RXCONTROL_RXEN;\r
+}\r
+\r
+/**\r
+ * \brief API to write the TX HDP register. If transmit is enabled,\r
+ * write to the TX HDP will immediately start transmission.\r
+ * The data will be taken from the buffer pointer of the TX buffer\r
+ * descriptor written to the TX HDP\r
+ *\r
+ * \param emacBase Base Address of the EMAC Module Registers.\n\r
+ * \param descHdr Address of the TX buffer descriptor\r
+ * \param channel Channel Number\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+volatile unsigned int lastInputdescHdr = 0;\r
+volatile unsigned int valHDPbefWrite = 0;\r
+void EMACTxHdrDescPtrWrite(unsigned int emacBase, unsigned int descHdr,\r
+ unsigned int channel)\r
+{\r
+ valHDPbefWrite = HWREG(emacBase + EMAC_TXHDP(channel));\r
+ HWREG(emacBase + EMAC_TXHDP(channel)) = descHdr;\r
+ lastInputdescHdr = descHdr;\r
+}\r
+\r
+/**\r
+ * \brief API to write the RX HDP register. If receive is enabled,\r
+ * write to the RX HDP will enable data reception to point to\r
+ * the corresponding RX buffer descriptor's buffer pointer.\r
+ *\r
+ * \param emacBase Base Address of the EMAC Module Registers.\n\r
+ * \param descHdr Address of the RX buffer descriptor\r
+ * \param channel Channel Number\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACRxHdrDescPtrWrite(unsigned int emacBase, unsigned int descHdr,\r
+ unsigned int channel)\r
+{\r
+ HWREG(emacBase + EMAC_RXHDP(channel)) = descHdr;\r
+}\r
+\r
+/**\r
+ * \brief This API Initializes the EMAC and EMAC Control modules. The\r
+ * EMAC Control module is reset, the CPPI RAM is cleared. also,\r
+ * all the interrupts are disabled. This API doesnot enable any\r
+ * interrupt or operation of the EMAC.\r
+ *\r
+ * \param emacCtrlBase Base Address of the EMAC Control module\r
+ * registers.\n\r
+ * \param emacBase Base address of the EMAC module registers\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACInit(unsigned int emacCtrlBase, unsigned int emacBase)\r
+{\r
+ unsigned int cnt;\r
+\r
+ /* Reset the EMAC Control Module. This clears the CPPI RAM also */\r
+ HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) = EMAC_CONTROL_RESET;\r
+\r
+ while(HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) & EMAC_CONTROL_RESET);\r
+\r
+ /* Reset the EMAC Control Module. This clears the CPPI RAM also */\r
+ HWREG(emacBase + EMAC_SOFTRESET) = EMAC_SOFT_RESET;\r
+\r
+ while(HWREG(emacBase + EMAC_SOFTRESET) & EMAC_SOFT_RESET);\r
+\r
+ HWREG(emacBase + EMAC_MACCONTROL)= 0;\r
+ HWREG(emacBase + EMAC_RXCONTROL)= 0;\r
+ HWREG(emacBase + EMAC_TXCONTROL)= 0;\r
+\r
+ /* Initialize all the header descriptor pointer registers */\r
+ for(cnt = 0; cnt< EMAC_MAX_HEADER_DESC; cnt++)\r
+ {\r
+ HWREG(emacBase + EMAC_RXHDP(cnt)) = 0;\r
+ HWREG(emacBase + EMAC_TXHDP(cnt)) = 0;\r
+ HWREG(emacBase + EMAC_RXCP(cnt)) = 0;\r
+ HWREG(emacBase + EMAC_TXCP(cnt)) = 0;\r
+ HWREG(emacBase + EMAC_RXFREEBUFFER(cnt)) = 0xFF;\r
+ }\r
+ /* Clear the interrupt enable for all the channels */\r
+ HWREG(emacBase + EMAC_TXINTMASKCLEAR) = 0xFF;\r
+ HWREG(emacBase + EMAC_RXINTMASKCLEAR) = 0xFF;\r
+\r
+ HWREG(emacBase + EMAC_MACHASH1) = 0;\r
+ HWREG(emacBase + EMAC_MACHASH2) = 0;\r
+\r
+ HWREG(emacBase + EMAC_RXBUFFEROFFSET) = 0;\r
+}\r
+\r
+/**\r
+ * \brief Sets the MAC Address in MACSRCADDR registers.\r
+ *\r
+ * \param emacBase Base Address of the EMAC module registers.\r
+ * \param macAddr Start address of a MAC address array.\r
+ * The array[0] shall be the LSB of the MAC address\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACMACSrcAddrSet(unsigned int emacBase, unsigned char *macAddr)\r
+{\r
+ HWREG(emacBase + EMAC_MACSRCADDRHI) = macAddr[5] |(macAddr[4] << 8)\r
+ |(macAddr[3] << 16) |(macAddr[2] << 24);\r
+ HWREG(emacBase + EMAC_MACSRCADDRLO) = macAddr[1] | (macAddr[0] << 8);\r
+}\r
+\r
+/**\r
+ * \brief Sets the MAC Address in MACADDR registers.\r
+ *\r
+ * \param emacBase Base Address of the EMAC module registers.\r
+ * \param channel Channel Number\r
+ * \param matchFilt Match or Filter\r
+ * \param macAddr Start address of a MAC address array.\r
+ * The array[0] shall be the LSB of the MAC address\r
+ * matchFilt can take the following values \n\r
+ * EMAC_MACADDR_NO_MATCH_NO_FILTER - Address is not used to match\r
+ * or filter incoming packet. \n\r
+ * EMAC_MACADDR_FILTER - Address is used to filter incoming packets \n\r
+ * EMAC_MACADDR_MATCH - Address is used to match incoming packets \n\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACMACAddrSet(unsigned int emacBase, unsigned int channel,\r
+ unsigned char *macAddr, unsigned int matchFilt)\r
+{\r
+ HWREG(emacBase + EMAC_MACINDEX) = channel;\r
+\r
+ HWREG(emacBase + EMAC_MACADDRHI) = macAddr[5] |(macAddr[4] << 8)\r
+ |(macAddr[3] << 16) |(macAddr[2] << 24);\r
+ HWREG(emacBase + EMAC_MACADDRLO) = macAddr[1] | (macAddr[0] << 8)\r
+ | matchFilt | (channel << 16);\r
+}\r
+\r
+/**\r
+ * \brief Acknowledges an interrupt processed to the EMAC Control Core.\r
+ *\r
+ * \param emacBase Base Address of the EMAC module registers.\r
+ * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control\r
+ * module.\r
+ * eoiFlag can take the following values \n\r
+ * EMAC_INT_CORE0_TX - Core 0 TX Interrupt\r
+ * EMAC_INT_CORE1_TX - Core 1 TX Interrupt\r
+ * EMAC_INT_CORE2_TX - Core 2 TX Interrupt\r
+ * EMAC_INT_CORE0_RX - Core 0 RX Interrupt\r
+ * EMAC_INT_CORE1_RX - Core 1 RX Interrupt\r
+ * EMAC_INT_CORE2_RX - Core 2 RX Interrupt\r
+ * \return None\r
+ * \r
+ **/\r
+void EMACCoreIntAck(unsigned int emacBase, unsigned int eoiFlag)\r
+{\r
+ /* Acknowledge the EMAC Control Core */\r
+ HWREG(emacBase + EMAC_MACEOIVECTOR) = eoiFlag;\r
+}\r
+\r
+/**\r
+ * \brief Writes the the TX Completion Pointer for a specific channel\r
+ *\r
+ * \param emacBase Base Address of the EMAC module registers.\r
+ * \param channel Channel Number.\r
+ * \param comPtr Completion Pointer Value to be written\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACTxCPWrite(unsigned int emacBase, unsigned int channel, unsigned int comPtr)\r
+{\r
+ HWREG(emacBase + EMAC_TXCP(channel)) = comPtr;\r
+}\r
+\r
+/**\r
+ * \brief Writes the the RX Completion Pointer for a specific channel\r
+ *\r
+ * \param emacBase Base Address of the EMAC module registers.\r
+ * \param channel Channel Number.\r
+ * \param comPtr Completion Pointer Value to be written\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACRxCPWrite(unsigned int emacBase, unsigned int channel, unsigned int comPtr)\r
+{\r
+ HWREG(emacBase + EMAC_RXCP(channel)) = comPtr;\r
+}\r
+\r
+/**\r
+ * \brief Acknowledges an interrupt processed to the EMAC module. After\r
+ * processing an interrupt, the last processed buffer descriptor is\r
+ * written to the completion pointer. Also this API acknowledges\r
+ * the EMAC Control Module that the RX interrupt is processed for\r
+ * a specified core\r
+ *\r
+ * \param emacBase Base Address of the EMAC module registers.\r
+ * \param channel Channel Number\r
+ * \param comPtr Completion Pointer value. This shall be the buffer\r
+ * descriptor address last processed.\r
+ * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control\r
+ module.\r
+ * eoiFlag can take the following values \n\r
+ * EMAC_INT_CORE0_RX - Core 0 RX Interrupt\r
+ * EMAC_INT_CORE1_RX - Core 1 RX Interrupt\r
+ * EMAC_INT_CORE2_RX - Core 2 RX Interrupt\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACRxIntAckToClear(unsigned int emacBase, unsigned int channel,\r
+ unsigned int comPtr, unsigned eoiFlag)\r
+{\r
+ HWREG(emacBase + EMAC_RXCP(channel)) = comPtr;\r
+\r
+ /* Acknowledge the EMAC Control Core */\r
+ HWREG(emacBase + EMAC_MACEOIVECTOR) = eoiFlag;\r
+}\r
+\r
+/**\r
+ * \brief Enables a specific channel to receive broadcast frames\r
+ *\r
+ * \param emacBase Base Address of the EMAC module registers.\r
+ * \param channel Channel Number.\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACRxBroadCastEnable(unsigned int emacBase, unsigned int channel)\r
+{\r
+ HWREG(emacBase + EMAC_RXMBPENABLE) &= ~EMAC_RXMBPENABLE_RXBROADCH;\r
+\r
+ HWREG(emacBase + EMAC_RXMBPENABLE) |=\r
+ EMAC_RXMBPENABLE_RXBROADEN | \r
+ (channel << EMAC_RXMBPENABLE_RXBROADCH_SHIFT);\r
+}\r
+\r
+/**\r
+ * \brief Enables unicast for a specific channel\r
+ *\r
+ * \param emacBase Base Address of the EMAC module registers.\r
+ * \param channel Channel Number.\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACRxUnicastSet(unsigned int emacBase, unsigned int channel)\r
+{\r
+ HWREG(emacBase + EMAC_RXUNICASTSET) |= (1 << channel);\r
+}\r
+\r
+/**\r
+ * \brief Set the free buffers for a specific channel\r
+ *\r
+ * \param emacBase Base Address of the EMAC module registers.\r
+ * \param channel Channel Number.\r
+ * \param nBuf Number of free buffers\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void EMACNumFreeBufSet(unsigned int emacBase, unsigned int channel,\r
+ unsigned int nBuf)\r
+{\r
+ HWREG(emacBase + EMAC_RXFREEBUFFER(channel)) = nBuf;\r
+}\r
+\r
+/**\r
+ * \brief Gets the interrupt vectors of EMAC, which are pending\r
+ *\r
+ * \param emacBase Base Address of the EMAC module registers.\r
+ *\r
+ * \return Vectors\r
+ *\r
+ **/\r
+unsigned int EMACIntVectorGet(unsigned int emacBase)\r
+{\r
+ return (HWREG(emacBase + EMAC_MACINVECTOR));\r
+}\r
+\r
+/***************************** End Of File ***********************************/\r
--- /dev/null
+#include "sys_common.h"
+#include "system.h"
+#include "string.h"
+#include "cmdio_tisci.h"
+
+#include "emac.h"
+#include "mdio.h"
+#include "hw_mdio.h"
+#include "hw_emac.h"
+
+#include "emac_test.h"
+#include "phy.h"
+#include "dmm.h"
+
+unsigned int emacCtrlBase = EMAC_CTRL_BASE;
+unsigned int emacBase = EMAC_BASE;
+unsigned int emacCtrlRamBase = EMAC_CTRL_RAM_BASE;
+unsigned int mdioBase = MDIO_BASE;
+
+
+uint8_t emacAddress[6] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab};
+uint32_t emacPhyAddress = 0x1;
+int channel = 0;
+
+
+unsigned int phyalive;
+unsigned int phylink;
+EMAC_Desc fr1;
+eth_frame_t efr1;
+char *buff = "asdfasdfasdfasdf";
+
+
+void dummy_wait()
+{
+ volatile int i;
+
+ for (i = 0; i < 65555; i ++)
+ ;
+}
+
+void EMACCore0RxIsr(void)
+{
+
+}
+
+void EMACCore0TxIsr(void)
+{
+ //EMACTxCPWrite(emacBase, channel, NULL);
+ EMACCoreIntAck(emacBase, EMAC_INT_CORE0_RX);
+ EMACCoreIntAck(emacBase, EMAC_INT_CORE0_TX);
+}
+
+int emac_test(void)
+{
+ int chan;
+ volatile unsigned int delay = 0xfff;
+ unsigned short data;
+ int j;
+
+ // Deactivate reset pin
+ #define DMM_CLK 1
+ dmmREG->PC4 = (1 << DMM_CLK); /* Set to H */
+ dummy_wait();
+ dmmREG->PC5 = (1 << DMM_CLK); /* Set to L */
+ dummy_wait();
+ dmmREG->PC4 = (1 << DMM_CLK); /* Set to H */
+ dummy_wait();
+/*
+ gioSetBit(dmmPORT, DMM_CLK, 0);
+ dummy_wait();
+ gioSetBit(dmmPORT, DMM_CLK, 1);
+ dummy_wait();
+*/
+ /* Fill some testing ethernet frame with relevant data */
+ efr1.destination[0] = 0x00;
+ efr1.destination[1] = 0x21;
+ efr1.destination[2] = 0x70;
+ efr1.destination[3] = 0xb5;
+ efr1.destination[4] = 0x4b;
+ efr1.destination[5] = 0xea;
+ efr1.source[0] = 0xff;
+ efr1.source[1] = 0xff;
+ efr1.source[2] = 0xff;
+ efr1.source[3] = 0xff;
+ efr1.source[4] = 0xff;
+ efr1.source[5] = 0xff;
+
+ efr1.len = 46;
+ efr1.data[0] = 0xaa;
+
+ _enable_IRQ();
+
+
+ EMACInit(emacCtrlBase, emacBase);
+ MDIOInit(mdioBase, 0x0, 0x0);
+ dummy_wait(); // FIXME
+
+ EMACMACSrcAddrSet(emacBase, emacAddress);
+ for (chan = 0; chan < 8; chan++)
+ EMACMACAddrSet(emacBase, chan, emacAddress, EMAC_MACADDR_NO_MATCH_NO_FILTER);
+
+ //do {
+ phyalive = MDIOPhyAliveStatusGet(mdioBase);
+ if (!phyalive) {
+ print((uint8_t *)"PHY not alive\r\n");
+ return -1;
+ }
+ //} while (phyalive == 0);
+ phylink = MDIOPhyLinkStatusGet(mdioBase);
+ if (!phylink) {
+ print((uint8_t *)"PHY link down\r\n");
+ return -1;
+ }
+
+
+ PHY_configure(mdioBase, emacPhyAddress);
+
+ /* Set the EMAC with the negotiation results if it is successful */
+ PHY_partner_ability_get(mdioBase, emacPhyAddress, &data);
+ if (data & PHY_100BASETXDUPL_m) {
+ EMACDuplexSet(emacBase, EMAC_DUPLEX_FULL);
+ dummy_wait();
+ } else if (data & PHY_100BASETX_m) {
+ EMACDuplexSet(emacBase, EMAC_DUPLEX_HALF);
+ dummy_wait();
+ } else {
+ while(1)
+ ;
+ }
+
+ EMACTxIntPulseEnable(emacBase, emacCtrlBase, 0, 0);
+ EMACRxIntPulseEnable(emacBase, emacCtrlBase, 0, 0);
+
+ //EMACCoreIntAck(emacBase, EMAC_INT_CORE0_RX); // ?
+ //EMACCoreIntAck(emacBase, EMAC_INT_CORE0_TX); // ?
+
+ //EMACNumFreeBufSet(emacBase, 0, 10);
+ //EMACRxEnable(emacBase);
+ EMACTxEnable(emacBase);
+
+
+ EMACMIIEnable(emacBase);
+
+
+ for (j = 0; j < 8; j++) {
+ fr1.pNext = NULL;
+ fr1.pBuffer = (uint8_t*)&efr1;
+ fr1.BufOffLen = 65;
+ fr1.PktFlgLen = (EMAC_DSC_FLAG_SOP | EMAC_DSC_FLAG_EOP | EMAC_DSC_FLAG_OWNER | 65);
+
+ EMACTxHdrDescPtrWrite(emacBase, (unsigned int)&fr1, channel);
+ dummy_wait();
+
+ EMACCoreIntAck(emacBase, EMAC_INT_CORE0_TX);
+
+ EMACTxCPWrite(emacBase, channel, (unsigned int)&fr1);
+ dummy_wait();
+ EMACCoreIntAck(emacBase, EMAC_INT_CORE0_TX);
+
+ print((uint8_t *)"Packet sent\r\n");
+ }
+
+ return 0;
+}
--- /dev/null
+/**\r
+ * \file mdio.c\r
+ *\r
+ * \brief MDIO APIs.\r
+ *\r
+ * This file contains the device abstraction layer APIs for MDIO.\r
+ */\r
+\r
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
+ * ALL RIGHTS RESERVED\r
+ */\r
+\r
+\r
+#include "sys_common.h"\r
+#include "hw_reg_access.h"\r
+#include "mdio.h"\r
+#include "hw_mdio.h"\r
+\r
+/*******************************************************************************\r
+* INTERNAL MACRO DEFINITIONS\r
+*******************************************************************************/\r
+#define PHY_REG_MASK (0x1Fu)\r
+#define PHY_ADDR_MASK (0x1Fu)\r
+#define PHY_DATA_MASK (0xFFFFu)\r
+#define PHY_REG_SHIFT (21u)\r
+#define PHY_ADDR_SHIFT (16u)\r
+\r
+/*******************************************************************************\r
+* API FUNCTION DEFINITIONS\r
+*******************************************************************************/\r
+\r
+/**\r
+ * \brief Reads a PHY register using MDIO.\r
+ *\r
+ * \param baseAddr Base Address of the MDIO Module Registers.\r
+ * \param phyAddr PHY Adress.\r
+ * \param regNum Register Number to be read.\r
+ * \param dataPtr Pointer where the read value shall be written.\r
+ *\r
+ * \return status of the read \n\r
+ * TRUE - read is successful.\n\r
+ * FALSE - read is not acknowledged properly.\r
+ *\r
+ **/\r
+unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned int phyAddr,\r
+ unsigned int regNum, volatile unsigned short *dataPtr)\r
+{\r
+ /* Wait till transaction completion if any */\r
+ while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);\r
+\r
+ HWREG(baseAddr + MDIO_USERACCESS0)\r
+ = (MDIO_USERACCESS0_READ | MDIO_USERACCESS0_GO\r
+ |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT)\r
+ |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT));\r
+\r
+ /* wait for command completion */\r
+ while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);\r
+\r
+ /* Store the data if the read is acknowledged */\r
+ if((HWREG(baseAddr + MDIO_USERACCESS0)) & MDIO_USERACCESS0_ACK)\r
+ {\r
+ *dataPtr = (unsigned short)((HWREG(baseAddr + MDIO_USERACCESS0))\r
+ & PHY_DATA_MASK);\r
+ return TRUE;\r
+ }\r
+\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ * \brief Writes a PHY register using MDIO.\r
+ *\r
+ * \param baseAddr Base Address of the MDIO Module Registers.\r
+ * \param phyAddr PHY Adress.\r
+ * \param regNum Register Number to be read.\r
+ * \param RegVal Value to be written.\r
+ *\r
+ * \return None\r
+ *\r
+ **/\r
+void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int phyAddr,\r
+ unsigned int regNum, unsigned short RegVal)\r
+{\r
+ /* Wait till transaction completion if any */\r
+ while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);\r
+\r
+ HWREG(baseAddr + MDIO_USERACCESS0) =\r
+ (MDIO_USERACCESS0_WRITE\r
+ | MDIO_USERACCESS0_GO\r
+ |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT)\r
+ |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT)\r
+ | RegVal);\r
+\r
+ /* wait for command completion*/\r
+ while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);\r
+}\r
+/**\r
+ * \brief Reads the alive status of all PHY connected to this MDIO.\r
+ * The bit correponding to the PHY address will be set if the PHY\r
+ * is alive.\r
+ *\r
+ * \param baseAddr Base Address of the MDIO Module Registers.\r
+ *\r
+ * \return MDIO alive register state\r
+ *\r
+ **/\r
+unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr)\r
+{\r
+ return (HWREG(baseAddr + MDIO_ALIVE));\r
+}\r
+\r
+/**\r
+ * \brief Reads the link status of all PHY connected to this MDIO.\r
+ * The bit correponding to the PHY address will be set if the PHY\r
+ * link is active.\r
+ *\r
+ * \param baseAddr Base Address of the MDIO Module Registers.\r
+ *\r
+ * \return MDIO link register state\r
+ *\r
+ **/\r
+unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr)\r
+{\r
+ return (HWREG(baseAddr + MDIO_LINK));\r
+}\r
+\r
+/**\r
+ * \brief Initializes the MDIO peripheral. This enables the MDIO state\r
+ * machine, uses standard pre-amble and set the clock divider value.\r
+ *\r
+ * \param baseAddr Base Address of the MDIO Module Registers.\r
+ * \param mdioInputFreq The clock input to the MDIO module\r
+ * \param mdioOutputFreq The clock output required on the MDIO bus\r
+ * \return None\r
+ *\r
+ **/\r
+#define MDIO_CTRL_ENABLE_m (1 << 30)\r
+#define MDIO_CTRL_CLKDIV_m (0xff)\r
+#define MDIO_HIGHEST_USER_CHANNEL_m (0xf)\r
+#define MDIO_HIGHEST_USER_CHANNEL_sh 24\r
+\r
+void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,\r
+ unsigned int mdioOutputFreq)\r
+{\r
+ //HWREG(baseAddr + MDIO_CONTROL) = 0x41000020u;\r
+\r
+ HWREG(baseAddr + MDIO_CONTROL) = (1 << MDIO_HIGHEST_USER_CHANNEL_sh) |\r
+ MDIO_CTRL_ENABLE_m | (0x60 & MDIO_CTRL_CLKDIV_m);\r
+}\r
+\r
+/***************************** End Of File ***********************************/\r
--- /dev/null
+#include "sys_common.h"
+
+#include "emac.h"
+#include "mdio.h"
+#include "hw_mdio.h"
+#include "hw_emac.h"
+
+#include "phy.h"
+
+void PHY_partner_ability_get(unsigned int mdioBaseAddr, unsigned int phyAddr, unsigned short *data)
+{
+ int ret;
+
+ //do {
+ ret = MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ANAR, data);
+ //} while (ret == FALSE);
+}
+
+void PHY_configure(unsigned int mdioBaseAddr, unsigned int phyAddr)
+{
+ volatile unsigned short data = 0;
+
+ /* Enable Auto Negotiation */
+ MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BMCR, 0);
+ MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BMCR, PHY_RESET_m | PHY_AUTONEG_EN_m);
+
+ /* Write Auto Negotiation capabilities */
+ MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ANAR, &data);
+ data |= (PHY_100BASETXDUPL_m | PHY_100BASETX_m | PHY_10BASETDUPL_m | PHY_10BASET_m);
+ MDIOPhyRegWrite(mdioBaseAddr, phyAddr,
+ PHY_ANAR, data);
+
+ /* Start Auto Negotiation */
+ MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BMCR, &data);
+ data |= PHY_AUTONEG_REST;
+ MDIOPhyRegWrite(mdioBaseAddr, phyAddr,
+ PHY_BMCR, data);
+
+ /* Get the auto negotiation status*/
+ /* Wait till auto negotiation is complete */
+ do {
+ MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BMSR, &data);
+ } while ((data & PHY_A_NEG_COMPLETE_m) == 0);
+}
#include "emif.h"\r
#include "dmm.h"\r
#include "lin.h"\r
+#include "emac_test.h"\r
/* USER CODE END */\r
\r
\r
hetInit();\r
sciInit();\r
canInit();\r
- adcInit();\r
- linInit();\r
- emif_SDRAMInit();\r
- dmmInit();\r
+ adcInit();\r
+ linInit();\r
+ emif_SDRAMInit();\r
+ dmmInit();\r
_enable_IRQ();\r
\r
initCmdProc(1, (uint8_t*)"\r\nType commands\r\n", (uint8_t *)"\r\n--> ");\r
projects / pes-rpp / rpp-test-sw.git / commitdiff