6 * This file contains the device abstraction layer APIs for MDIO.
9 /* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
15 #include "sys/hw_reg_access.h"
16 #include "sys/ti_drv_mdio.h"
17 #include "sys/hw_mdio.h"
19 /*******************************************************************************
20 * INTERNAL MACRO DEFINITIONS
21 *******************************************************************************/
22 #define PHY_REG_MASK (0x1Fu)
23 #define PHY_ADDR_MASK (0x1Fu)
24 #define PHY_DATA_MASK (0xFFFFu)
25 #define PHY_REG_SHIFT (21u)
26 #define PHY_ADDR_SHIFT (16u)
28 /*******************************************************************************
29 * API FUNCTION DEFINITIONS
30 *******************************************************************************/
33 * \brief Reads a PHY register using MDIO.
35 * \param baseAddr Base Address of the MDIO Module Registers.
36 * \param phyAddr PHY Adress.
37 * \param regNum Register Number to be read.
38 * \param dataPtr Pointer where the read value shall be written.
40 * \return status of the read \n
41 * TRUE - read is successful.\n
42 * FALSE - read is not acknowledged properly.
45 unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned int phyAddr,
46 unsigned int regNum, volatile unsigned short *dataPtr)
48 /* Wait till transaction completion if any */
49 while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
51 HWREG(baseAddr + MDIO_USERACCESS0)
52 = (MDIO_USERACCESS0_READ | MDIO_USERACCESS0_GO
53 |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT)
54 |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT));
56 /* wait for command completion */
57 while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
59 /* Store the data if the read is acknowledged */
60 if((HWREG(baseAddr + MDIO_USERACCESS0)) & MDIO_USERACCESS0_ACK)
62 *dataPtr = (unsigned short)((HWREG(baseAddr + MDIO_USERACCESS0))
71 * \brief Writes a PHY register using MDIO.
73 * \param baseAddr Base Address of the MDIO Module Registers.
74 * \param phyAddr PHY Adress.
75 * \param regNum Register Number to be read.
76 * \param RegVal Value to be written.
81 void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int phyAddr,
82 unsigned int regNum, unsigned short RegVal)
84 /* Wait till transaction completion if any */
85 while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
87 HWREG(baseAddr + MDIO_USERACCESS0) =
88 (MDIO_USERACCESS0_WRITE
90 |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT)
91 |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT)
94 /* wait for command completion*/
95 while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
98 * \brief Reads the alive status of all PHY connected to this MDIO.
99 * The bit correponding to the PHY address will be set if the PHY
102 * \param baseAddr Base Address of the MDIO Module Registers.
104 * \return MDIO alive register state
107 unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr)
109 return (HWREG(baseAddr + MDIO_ALIVE));
113 * \brief Reads the link status of all PHY connected to this MDIO.
114 * The bit correponding to the PHY address will be set if the PHY
117 * \param baseAddr Base Address of the MDIO Module Registers.
119 * \return MDIO link register state
122 unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr)
124 return (HWREG(baseAddr + MDIO_LINK));
128 * \brief Initializes the MDIO peripheral. This enables the MDIO state
129 * machine, uses standard pre-amble and set the clock divider value.
131 * \param baseAddr Base Address of the MDIO Module Registers.
132 * \param mdioInputFreq The clock input to the MDIO module
133 * \param mdioOutputFreq The clock output required on the MDIO bus
137 #define MDIO_CTRL_ENABLE_m (1 << 30)
138 #define MDIO_CTRL_CLKDIV_m (0xff)
139 #define MDIO_HIGHEST_USER_CHANNEL_m (0xf)
140 #define MDIO_HIGHEST_USER_CHANNEL_sh 24
142 void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,
143 unsigned int mdioOutputFreq)
145 //HWREG(baseAddr + MDIO_CONTROL) = 0x41000020u;
147 HWREG(baseAddr + MDIO_CONTROL) = (1 << MDIO_HIGHEST_USER_CHANNEL_sh) |
148 MDIO_CTRL_ENABLE_m | (0x60 & MDIO_CTRL_CLKDIV_m);
151 /***************************** End Of File ***********************************/