spi: Fix/add comments

diff --git a/rpp/include/drv/spi_tms570.h b/rpp/include/drv/spi_tms570.h
index 84361e5327a23d4c818dc6d79a4af0ae1020a7e6..e6281d1330a09978b5425091a860d251fde739bb 100644 (file)
--- a/rpp/include/drv/spi_tms570.h
+++ b/rpp/include/drv/spi_tms570.h
@@ -200,6 +200,7 @@ typedef struct spi_tms570_iface {
        unsigned rxcnt; /* No. of received bytes for msg_act */
        spi_dev_t *spi_devs;    /* Pointer to table holding information about SPI devices bound to the interface */
        uint32_t transfer_ctrl; /* Transfer configuration -- upper 16 bits of SPIDAT1 register */
+       /* TODO: Add FMT description here if we need different formats */
 } spi_tms570_iface_t;
 
 //extern spi_tms570_iface_t spi_tms570_ifcs[4];

diff --git a/rpp/src/drv/spi_tms570.c b/rpp/src/drv/spi_tms570.c
index a4e5a42ae657acb4049248faa5ab8be7b1623db8..8a17d5aeb5708855f0140bc11c0d6c17734be0d6 100644 (file)
--- a/rpp/src/drv/spi_tms570.c
+++ b/rpp/src/drv/spi_tms570.c
@@ -28,7 +28,7 @@ static int spi_tms570_ctrl_fnc(spi_drv_t *ifc, int ctrl, void *p);
    ENA register is set even on SPI devices which do not have it --
    this should not be an issue
  */
-void spiInit(spiBASE_compat_t *spiREG)
+static void spiInit(spiBASE_compat_t *spiREG)
 {
        /** bring SPI out of reset */
        spiREG->GCR0 = 1U;
@@ -47,6 +47,7 @@ void spiInit(spiBASE_compat_t *spiREG)
                                        | 0; /* C2EDELAY */
 
        /** - Data Format 0 */
+       /* TODO: Set the formats from spi_tms570_iface_t if we need different formats */
        spiREG->FMT0 = (0 << 24)    /* wdelay */
                                   | (0 << 23) /* parity Polarity */
                                   | (0 << 22) /* parity enable */
@@ -338,10 +339,10 @@ void spi_tms570_isr(int spi_ifc, uint32_t flags)
                                while (iface->reg->FLG & SPI_FLG_RXINT_m) {
                                        rx_data = iface->reg->BUF;
 
-                                       if (msg->rx_buf && (rxcnt < rq_len))
+                                       if (msg->rx_buf && (rxcnt < rq_len)) {
+                                               /* This relies on all FMTs having 8 bit CHARLEN */
                                                msg->rx_buf[rxcnt++] = rx_data & 0xFF;
-                                       //FIXME how to make sure we got only 8 bits
-                                       else
+                                       } else
                                                rxcnt++;
                                }
 
@@ -355,14 +356,15 @@ void spi_tms570_isr(int spi_ifc, uint32_t flags)
                                                break;
                                        /* Make it possible to write "empty data"
                                           for "read transfers" */
-                                       if (msg->tx_buf)
+                                       if (msg->tx_buf) {
+                                               /* This relies on all FMTs having 8 bit CHARLEN */
                                                val_to_wr = msg->tx_buf[txcnt++];
-                                       else {
+                                       } else {
                                                val_to_wr = 0x00;
                                                txcnt++;
                                        }
 
-                                       if (txcnt == rq_len) /* Disable CS for the last byte of the transfer */
+                                       if (txcnt == rq_len) /* Disable CS after last byte of the transfer */
                                                iface->transfer_ctrl &= ~SPI_DAT1_CSHOLD_m;
 
                                        iface->reg->DAT1 =