Add support for GIO port on SPI5

diff --git a/rpp/include/drv/_tms570_hydctr/gio_def.h b/rpp/include/drv/_tms570_hydctr/gio_def.h
index 9c5421e0ea9a3f41e69206df283f8c4cd59ad17c..70511c3e134ef6403b67921a978cabae6df32e30 100644 (file)
--- a/rpp/include/drv/_tms570_hydctr/gio_def.h
+++ b/rpp/include/drv/_tms570_hydctr/gio_def.h
@@ -79,6 +79,22 @@ GIO_PIN_DEF_GEN(NHET129,       HET1, 29, GIO_PIN_CONF_GPIO_IN_LO_PD_PDIS_ODOFF)
 GIO_PIN_DEF_GEN(NHET130,       HET1, 30, GIO_PIN_CONF_GPIO_IN_LO_PD_PDIS_ODOFF)
 GIO_PIN_DEF_GEN(NHET131,       HET1, 31, GIO_PIN_CONF_GPIO_IN_LO_PD_PDIS_ODOFF)
 
+/* Pin numbers correspond to bits in SPIPCx registers */
+GIO_PIN_DEF_GEN(SPI5CS0,      SPI5,  0, GIO_PIN_CONF_FNC_SPI)
+GIO_PIN_DEF_GEN(SPI5CS1,      SPI5,  1, GIO_PIN_CONF_FNC_SPI)
+GIO_PIN_DEF_GEN(SPI5CS2,      SPI5,  2, GIO_PIN_CONF_FNC_SPI)
+GIO_PIN_DEF_GEN(SPI5CS3,      SPI5,  3, GIO_PIN_CONF_FNC_SPI)
+GIO_PIN_DEF_GEN(SPI5ENA,      SPI5,  8, GIO_PIN_CONF_FNC_SPI)
+GIO_PIN_DEF_GEN(SPI5CLK,      SPI5,  9, GIO_PIN_CONF_FNC_SPI)
+GIO_PIN_DEF_GEN(SPI5SIMO0,    SPI5, 16, GIO_PIN_CONF_FNC_SPI)
+GIO_PIN_DEF_GEN(SPI5SIMO1,    SPI5, 17, GIO_PIN_CONF_FNC_SPI)
+GIO_PIN_DEF_GEN(MCU_ENDRV /* SPI5SIMO2 */,    SPI5, 18, GIO_PIN_CONF_GPIO_IN_LO_PD_PDIS_ODOFF)
+GIO_PIN_DEF_GEN(TEMP_ALERT/* SPI5SIMO3 */,    SPI5, 19, GIO_PIN_CONF_GPIO_IN_LO_PD_PDIS_ODOFF)
+GIO_PIN_DEF_GEN(SPI5SOMI0,    SPI5, 24, GIO_PIN_CONF_FNC_SPI)
+GIO_PIN_DEF_GEN(SLEEP     /* SPI5SOMI1 */,    SPI5, 25, GIO_PIN_CONF_GPIO_IN_LO_PD_PDIS_ODOFF)
+GIO_PIN_DEF_GEN(SPI5SOMI2,    SPI5, 26, GIO_PIN_CONF_FNC_SPI)
+GIO_PIN_DEF_GEN(SPI5SOMI3,    SPI5, 27, GIO_PIN_CONF_FNC_SPI)
+
 #undef GIO_PIN_CONF_GPIO_OUT_HI_PD_PEN_ODOFF
 #undef GIO_PIN_CONF_GPIO_OUT_LO_PD_PEN_ODOFF
 #undef GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF

diff --git a/rpp/include/drv/_tms570_hydctr/port_def.h b/rpp/include/drv/_tms570_hydctr/port_def.h
index c08554c1441a5d62fdd2def4f94f6ddeffd58253..0160075cb2ac59fd3e007ac1e6e56edb1379ebe4 100644 (file)
--- a/rpp/include/drv/_tms570_hydctr/port_def.h
+++ b/rpp/include/drv/_tms570_hydctr/port_def.h
@@ -28,6 +28,7 @@ enum port_id {
        PORT_ID_POWER_SUPPLY,
        PORT_ID_SENSOR_SUPPLY,
        PORT_ID_DAC_ADC_LOOPBACK,
+       PORT_ID_GIO_SPI5,
        _PORT_COUNT,
 };
 

diff --git a/rpp/include/drv/gio.h b/rpp/include/drv/gio.h
index e2d01870495fcb21768d4c6998c6209a3ec8bfbd..bc769cf333c1f7e944c8319ca626fdf32be0e3e5 100644 (file)
--- a/rpp/include/drv/gio.h
+++ b/rpp/include/drv/gio.h
@@ -40,6 +40,7 @@
 
 #define GIO_PIN_CONF_FNC_MASK  0xc0000000
 #define GIO_PIN_CONF_FNC_GPIO  0x00000000
+#define GIO_PIN_CONF_FNC_SPI   0x40000000
 #define GIO_PIN_CONF_FNC_0     0x00000000
 #define GIO_PIN_CONF_FNC_1     0x40000000
 #define GIO_PIN_CONF_FNC_2     0x80000000
@@ -52,6 +53,7 @@ enum gio_port {
        GIO_PORT_GIOB,
        GIO_PORT_HET1,
        GIO_PORT_HET2,
+       GIO_PORT_SPI5,
 };
 
 #define GIO_PORT_SHIFT 5

diff --git a/rpp/include/rpp/gio.h b/rpp/include/rpp/gio.h
index 9b00364089276f655a40652d6c4dc2eef0cc8fa1..620be8d6e6edddf3ecca54bc44e15d4e4af29b76 100644 (file)
--- a/rpp/include/rpp/gio.h
+++ b/rpp/include/rpp/gio.h
@@ -21,7 +21,8 @@
 #define RPP_GIO_PORT_GIOA   0x2
 #define RPP_GIO_PORT_GIOB   0x4
 #define RPP_GIO_PORT_NHET1  0x8
-#define RPP_GIO_PORT_ALL    (RPP_GIO_PORT_GIOA|RPP_GIO_PORT_GIOB|RPP_GIO_PORT_NHET1)
+#define RPP_GIO_PORT_SPI5   0x20
+#define RPP_GIO_PORT_ALL    (RPP_GIO_PORT_GIOA|RPP_GIO_PORT_GIOB|RPP_GIO_PORT_NHET1|RPP_GIO_PORT_SPI5)
 
 /**
  * Intialize GIO ports.

diff --git a/rpp/src/drv/_tms570_hydctr/port_def.c b/rpp/src/drv/_tms570_hydctr/port_def.c
index 532577f1455e27bfa42816ea3230388012f606f3..927f45cff7887a90e5865113afbbbba92be33bf8 100644 (file)
--- a/rpp/src/drv/_tms570_hydctr/port_def.c
+++ b/rpp/src/drv/_tms570_hydctr/port_def.c
@@ -40,6 +40,13 @@ static enum pin_name pins_nhet1[] = {
        PIN_NHET129, PIN_NHET130, PIN_NHET131
 };
 
+static enum pin_name pins_spi5[] = {
+       PIN_SPI5CS0, PIN_SPI5CS1, PIN_SPI5CS2, PIN_SPI5CS3,
+       PIN_SPI5ENA, PIN_SPI5CLK,
+       PIN_SPI5SIMO0, PIN_SPI5SIMO1, PIN_MCU_ENDRV, PIN_TEMP_ALERT,
+       PIN_SPI5SOMI0, PIN_SLEEP, PIN_SPI5SOMI2, PIN_SPI5SOMI3,
+};
+
 // Port descriptors
 const struct port_desc port_desc[] = {
        [PORT_ID_GIOA] = {
@@ -122,4 +129,12 @@ const struct port_desc port_desc[] = {
                .set = port_spi_set,
                .cfg = { .spi = { .dev = SPIDEV_MCP6S93_DAC, .chip = "MCP6S93" }, },
        },
+       [PORT_ID_GIO_SPI5] = {
+               .name = "GIOSPI5",
+               .cfg = { .gioset = { .pins = pins_spi5 } },
+               .numchn = ARRAY_SIZE(pins_spi5),
+               .bpch = 1,
+               .get = port_gioset_get,
+               .set = port_gioset_set,
+       },
 };

diff --git a/rpp/src/drv/gio.c b/rpp/src/drv/gio.c
index 060a893c907bf231a8cc503d1640efe1bbd99447..d819ae2d9553aaa63bdd4faf504d76e22d3a67e7 100644 (file)
--- a/rpp/src/drv/gio.c
+++ b/rpp/src/drv/gio.c
@@ -6,6 +6,7 @@
  */
 
 #include "drv/gio.h"
+#include "sys/ti_drv_mibspi.h"
 
 static gioPORT_t *gio_reg[] = {
 #ifdef TARGET_HAS_DMM
@@ -15,6 +16,7 @@ static gioPORT_t *gio_reg[] = {
        [GIO_PORT_GIOB] = gioPORTB,
        [GIO_PORT_HET1] = hetPORT1,
        [GIO_PORT_HET2] = hetPORT2,
+       [GIO_PORT_SPI5] = mibspiPORT5,
 };
 
 void gio_set(uint32_t pin_dsc, boolean_t value)
@@ -35,6 +37,12 @@ void gio_setup(uint32_t pin_dsc)
        gioPORT_t *gioPort = gio_reg[gio_port(pin_dsc)];
        uint32_t pin_bit = 1 << (pin_dsc & GIO_PIN_NUM_MASK);
 
+       if (gioPort >= mibspiPORT1 && gioPort <= mibspiPORT5) {
+               volatile uint32_t *fun_reg = ((uint32_t*)gioPort) - 1;
+               if ((pin_dsc & GIO_PIN_CONF_FNC_MASK) == GIO_PIN_CONF_FNC_GPIO)
+                       *fun_reg &= ~pin_bit;   /* Configure SPI pin as GIO */
+       }
+
        if (pin_dsc & GIO_PIN_CONF_OD_MASK)
                gioPort->PDR |= pin_bit;
        else

diff --git a/rpp/src/rpp/gio.c b/rpp/src/rpp/gio.c
index 8c83c484e1462e28a28ab6328c6e3d2d93fea238..e4612c594bf599754c705d66f407fc912de49d7c 100644 (file)
--- a/rpp/src/rpp/gio.c
+++ b/rpp/src/rpp/gio.c
@@ -22,7 +22,9 @@ static uint32_t ports_initialized = 0;
 /* Configuration consistency check */
 STATIC_ASSERT(RPP_GIO_PORT_GIOA == (1 << GIO_PORT_GIOA) &&
                          RPP_GIO_PORT_GIOB == (1 << GIO_PORT_GIOB) &&
-                         RPP_GIO_PORT_NHET1 == (1 << GIO_PORT_HET1),
+                         RPP_GIO_PORT_NHET1 == (1 << GIO_PORT_HET1) &&
+                         RPP_GIO_PORT_SPI5 == (1 << GIO_PORT_SPI5) &&
+                         1,
                          Port_configuration_is_not_consistent);
 
 int8_t rpp_gio_init(uint32_t init_ports)