Set MDIO initial sequence

Initial sequence taken from Texas Instruments connectivity test.
Created for kit TMS570.
http://processors.wiki.ti.com/index.php/TMS570LS31x_HDK_Kit#Example_Programs

[MS: Added #else and fixed indentation]

diff --git a/rpp/src/sys/ti_drv_mdio.c b/rpp/src/sys/ti_drv_mdio.c
index f5dc69f88867765538f6af3335ff131df6476382..e1a65555716c4d7273d4c92fbab4a559507bd61b 100644 (file)
--- a/rpp/src/sys/ti_drv_mdio.c
+++ b/rpp/src/sys/ti_drv_mdio.c
@@ -144,8 +144,52 @@ void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,
 {
    //HWREG(baseAddr + MDIO_CONTROL) = 0x41000020u;
 
+#ifdef TARGET_TMS570_RPP
     HWREG(baseAddr + MDIO_CONTROL) = (1 << MDIO_HIGHEST_USER_CHANNEL_sh) |
             MDIO_CTRL_ENABLE_m | (0x60 & MDIO_CTRL_CLKDIV_m);
+#else
+    /*Unlock the IOMM Register*/
+    *(int *) 0xFFFFEA38  = 0x83E70B13;  /* kicker 0 register, unlock CPU write access to PINMMR registers */
+    *(int *) 0xFFFFEA3C  = 0x95A4F1E0;  /* kicker 1 register, */
+
+    *(int *) 0xFFFFEB2C  = 0x00000400;
+    *(int *) 0xFFFFEB30  = 0x00000400;
+
+    *(int *) 0xFFFFEB38  &= 0xFFFFFF00; //P10[1]  //Mux 10 Rx_ER
+    *(int *) 0xFFFFEB38  |= (1 << 1);   //P10[1]  //Mux 10 Rx_ER
+
+    *(int *) 0xFFFFEB3C  &= 0x00FFFFFF; //P11[26]   //Mux 11 Rx[0]
+    *(int *) 0xFFFFEB3C  |= (1 << 26);  //P11[26]   //Mux 11 Rx[0]
+
+    *(int *) 0xFFFFEB40  &= 0x0000FF00;//P12[1,18,26]    //Mux 12 Rx[3],Rx[2],Rx[1]
+    *(int *) 0xFFFFEB40  |= ((1<<26) | (1<<18) | (1<<1));//P12[1,18,26]    //Mux 12 Rx[3],Rx[2],Rx[1]
+
+    *(int *) 0xFFFFEB44  &= 0x00000000;//P13[2, 10, 26,18]   //Mux 13 Tx[2],TxEn,Tx[1],Tx[0]
+    *(int *) 0xFFFFEB44  |= ((1<<26)|(1<<18)|(1<<10)|(1<<2)); //P13[2, 10, 26,18]   //Mux 13 Tx[2],TxEn,Tx[1],Tx[0]
+
+    *(int *) 0xFFFFEB48  &= 0xFFFF0000; //P14[9,2,11]   //Mux 14 Tx[3],RxClk
+    *(int *) 0xFFFFEB48  |= ((1<<9)|(1<<2));    //P14[9,2]   //Mux 14 Tx[3],RxClk
+
+    *(int *) 0xFFFFEB54  &= 0xFF00FF00      ;//P17[17,1,3]   //Mux 17 CRS,TxClk
+    *(int *) 0xFFFFEB54  |= ((1<<17)|(1<<1));          //P17[17,1]   //Mux 17 CRS,TxClk
+
+    *(int *) 0xFFFFEB5C  &= 0xFFFF00FF;  //P19[9]   //Mux 19 RxDV
+    *(int *) 0xFFFFEB5C  |= (1<<9);      //P19[9]   //Mux 19 RxDV
+
+    *(int *) 0xFFFFEB60  &= 0xFF00FFFF;  //P20[18]   //Mux 20 COL
+    *(int *) 0xFFFFEB60  |= (1<<18);     //P20[18]   //Mux 20 COL
+
+
+    *(int *) 0xFFFFEB84  &= 0x00FFFFFF;//P29[24]  //Mux 29 MII Select pin (24 bit - 0(MII),1(RMII))
+    *(int *) 0xFFFFEB84  |= (0<<24);   //P29[24]  //Mux 29 MII Select pin (24 bit - 0(MII),1(RMII))
+
+
+    /*lock the IOMM Register*/
+    *(int *) 0xFFFFEA38  = 0x00000000;  /* kicker 0 register, lock CPU write access to PINMMR registers */
+    *(int *) 0xFFFFEA3C  = 0x00000000;  /* kicker 1 register, */
+
+    HWREG(baseAddr + MDIO_CONTROL) = 0x41000020u;
+#endif
 }
 
 /***************************** End Of File ***********************************/