-/** @file sys_phantom.c \r
-* @brief Phantom Interrupt Source File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-* This file contains:\r
-* - Phantom Interrupt Handler\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-\r
-/* Phantom Interrupt Handler */\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(phantomInterrupt, IRQ)\r
-\r
-void phantomInterrupt(void)\r
-{\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
+/** @file sys_phantom.c
+* @brief Phantom Interrupt Source File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+* This file contains:
+* - Phantom Interrupt Handler
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* Phantom Interrupt Handler */
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#pragma INTERRUPT(phantomInterrupt, IRQ)
+
+void phantomInterrupt(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
-/** @file pinmux.c \r
-* @brief PINMUX Driver Implementation File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* Include Files */\r
-\r
-#include "sys_pinmux.h"\r
-\r
-#define PINMUX_SET(REG, BALLID, MUX) \\r
- pinMuxReg->PINMUX##REG## = (pinMuxReg->PINMUX##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX##)\r
-\r
-#define PINMUX_GATE_EMIF_CLK_ENABLE \\r
- pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GATE_EMIF_CLK_MASK) | PINMUX_GATE_EMIF_CLK\r
-\r
-#define PINMUX_GIOB_DISABLE_HET2_ENABLE \\r
- pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GIOB_DISABLE_HET2_MASK) | PINMUX_GIOB_DISABLE_HET2\r
- \r
-#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \\r
- pinMuxReg->PINMUX30 = (pinMuxReg->PINMUX30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num##)\r
- \r
-#define PINMUX_ETHERNET_SELECT(interface) \\r
- pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface##)\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-void muxInit(void){\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
- /* Enable Pin Muxing */\r
- kickerReg->KICKER0 = 0x83E70B13;\r
- kickerReg->KICKER1 = 0x95A4F1E0;\r
- \r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
- pinMuxReg->PINMUX0 = PINMUX_BALL_C3_I2C_SCL | PINMUX_BALL_B2_I2C_SDA;\r
- \r
- pinMuxReg->PINMUX1 = PINMUX_BALL_E3_MIBSPI3NCS_4 | PINMUX_BALL_E5_EMIF_DATA_4 | PINMUX_BALL_F5_EMIF_DATA_5;\r
- \r
- pinMuxReg->PINMUX2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_EMIF_DATA_6 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;\r
- \r
- pinMuxReg->PINMUX3 = PINMUX_BALL_K5_EMIF_DATA_7 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_EMIF_DATA_8;\r
- \r
- pinMuxReg->PINMUX4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_EMIF_DATA_9 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_SPI4NCS_0;\r
- \r
- pinMuxReg->PINMUX5 = PINMUX_BALL_K18_SPI4CLK | PINMUX_BALL_W5_SPI4SIMO | PINMUX_BALL_V6_SPI4SOMI | PINMUX_BALL_N5_EMIF_DATA_10;\r
- \r
- pinMuxReg->PINMUX6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_EMIF_DATA_11 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_EMIF_DATA_12;\r
- \r
- pinMuxReg->PINMUX7 = PINMUX_BALL_R6_EMIF_DATA_13 | PINMUX_BALL_V5_MDCLK | PINMUX_BALL_W3_SCIRX | PINMUX_BALL_R7_EMIF_DATA_14;\r
- \r
- pinMuxReg->PINMUX8 = PINMUX_BALL_N2_SCITX | PINMUX_BALL_G3_MDIO | PINMUX_BALL_N1_MIBSPI1NCS_4 | PINMUX_BALL_R8_EMIF_DATA_15;\r
- \r
- pinMuxReg->PINMUX9 = PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NCS_5 | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;\r
- \r
- pinMuxReg->PINMUX10 = PINMUX_BALL_N19_MII_RX_ER | PINMUX_BALL_N15_EMIF_DATA_3 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_EMIF_DATA_2;\r
- \r
- pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_MII_RXD_0;\r
- \r
- pinMuxReg->PINMUX12 = PINMUX_BALL_A14_MII_RXD_1 | PINMUX_BALL_K15_EMIF_DATA_0 | PINMUX_BALL_G19_MII_RXD_2 | PINMUX_BALL_H18_MII_RXD_3;\r
- \r
- pinMuxReg->PINMUX13 = PINMUX_BALL_J18_MII_TXD_0 | PINMUX_BALL_J19_MII_TXD_1 | PINMUX_BALL_H19_MII_TXEN | PINMUX_BALL_R2_MII_TXD_2;\r
- \r
- pinMuxReg->PINMUX14 = PINMUX_BALL_E18_MII_TXD_3 | PINMUX_BALL_K19_MII_RXCLK | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;\r
- \r
- pinMuxReg->PINMUX15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;\r
- \r
- pinMuxReg->PINMUX16 = PINMUX_BALL_E13_EMIF_BA_0 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_EMIF_nOE;\r
- \r
- pinMuxReg->PINMUX17 = PINMUX_BALL_D19_MII_TX_CLK | PINMUX_BALL_E11_EMIF_nDQM_1 | PINMUX_BALL_B4_MII_CRS | PINMUX_BALL_E9_EMIF_ADDR_5;\r
- \r
- pinMuxReg->PINMUX18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;\r
- \r
- pinMuxReg->PINMUX19 = PINMUX_BALL_E8_EMIF_ADDR_4 | PINMUX_BALL_B11_MII_RX_DV | PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_E7_EMIF_ADDR_3;\r
- \r
- pinMuxReg->PINMUX20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MII_COL | PINMUX_BALL_C9_EMIF_ADDR_11;\r
- \r
- pinMuxReg->PINMUX21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;\r
- \r
- pinMuxReg->PINMUX22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_EMIF_ADDR_2;\r
- \r
- pinMuxReg->PINMUX23 = 0x00010100| /* SPI4SOMI is on ball W6 */\r
- PINMUX_BALL_C6_EMIF_ADDR_8;\r
- \r
- pinMuxReg->PINMUX24 = 0x01010101;\r
- \r
- pinMuxReg->PINMUX25 = 0x01010101;\r
-\r
- /* Halcogen fix enabling N2HET1[29], N2HET1[31] */\r
- pinMuxReg->PINMUX26 = 0x0101 | PINMUX_BALL_W6_DMM_DATA_2 | PINMUX_BALL_T12_DMM_DATA_3;\r
- \r
- pinMuxReg->PINMUX27 = PINMUX_BALL_E19_DMM_DATA_5 | PINMUX_BALL_B6_DMM_DATA_6 | PINMUX_BALL_E16_DMM_DATA_9 | PINMUX_BALL_H17_DMM_DATA_10;\r
- \r
- pinMuxReg->PINMUX28 = PINMUX_BALL_G17_DMM_DATA_11 | PINMUX_BALL_E17_DMM_DATA_13 | PINMUX_BALL_H16_DMM_DATA_14 | PINMUX_BALL_G16_DMM_DATA_15;\r
- \r
- pinMuxReg->PINMUX29 = PINMUX_BALL_D3_SPI2NCS_1;\r
- \r
-\r
- \r
- \r
- PINMUX_ALT_ADC_TRIGGER_SELECT(1);\r
- PINMUX_ETHERNET_SELECT(MII);\r
- \r
- PINMUX_SET(0,A5,GIOA_0);\r
- PINMUX_SET(18,A11,HET1_14);\r
- PINMUX_SET(3,B3,HET1_22);\r
- PINMUX_SET(1,C2,GIOA_1);\r
- PINMUX_SET(21,K2,GIOB_1);\r
- PINMUX_SET(0,W10,GIOB_3);\r
- \r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
- \r
- /* Disable Pin Muxing */\r
- kickerReg->KICKER0 = 0x00000000;\r
- kickerReg->KICKER1 = 0x00000000;\r
- \r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
+/** @file pinmux.c
+* @brief PINMUX Driver Implementation File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* Include Files */
+
+#include "sys_pinmux.h"
+
+#define PINMUX_SET(REG, BALLID, MUX) \
+ pinMuxReg->PINMUX##REG## = (pinMuxReg->PINMUX##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX##)
+
+#define PINMUX_GATE_EMIF_CLK_ENABLE \
+ pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GATE_EMIF_CLK_MASK) | PINMUX_GATE_EMIF_CLK
+
+#define PINMUX_GIOB_DISABLE_HET2_ENABLE \
+ pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GIOB_DISABLE_HET2_MASK) | PINMUX_GIOB_DISABLE_HET2
+
+#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \
+ pinMuxReg->PINMUX30 = (pinMuxReg->PINMUX30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num##)
+
+#define PINMUX_ETHERNET_SELECT(interface) \
+ pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface##)
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+void muxInit(void){
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+ /* Enable Pin Muxing */
+ kickerReg->KICKER0 = 0x83E70B13;
+ kickerReg->KICKER1 = 0x95A4F1E0;
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+ pinMuxReg->PINMUX0 = PINMUX_BALL_C3_I2C_SCL | PINMUX_BALL_B2_I2C_SDA;
+
+ pinMuxReg->PINMUX1 = PINMUX_BALL_E3_MIBSPI3NCS_4 | PINMUX_BALL_E5_EMIF_DATA_4 | PINMUX_BALL_F5_EMIF_DATA_5;
+
+ pinMuxReg->PINMUX2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_EMIF_DATA_6 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
+
+ pinMuxReg->PINMUX3 = PINMUX_BALL_K5_EMIF_DATA_7 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_EMIF_DATA_8;
+
+ pinMuxReg->PINMUX4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_EMIF_DATA_9 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_SPI4NCS_0;
+
+ pinMuxReg->PINMUX5 = PINMUX_BALL_K18_SPI4CLK | PINMUX_BALL_W5_SPI4SIMO | PINMUX_BALL_V6_SPI4SOMI | PINMUX_BALL_N5_EMIF_DATA_10;
+
+ pinMuxReg->PINMUX6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_EMIF_DATA_11 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_EMIF_DATA_12;
+
+ pinMuxReg->PINMUX7 = PINMUX_BALL_R6_EMIF_DATA_13 | PINMUX_BALL_V5_MDCLK | PINMUX_BALL_W3_SCIRX | PINMUX_BALL_R7_EMIF_DATA_14;
+
+ pinMuxReg->PINMUX8 = PINMUX_BALL_N2_SCITX | PINMUX_BALL_G3_MDIO | PINMUX_BALL_N1_MIBSPI1NCS_4 | PINMUX_BALL_R8_EMIF_DATA_15;
+
+ pinMuxReg->PINMUX9 = PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NCS_5 | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;
+
+ pinMuxReg->PINMUX10 = PINMUX_BALL_N19_MII_RX_ER | PINMUX_BALL_N15_EMIF_DATA_3 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_EMIF_DATA_2;
+
+ pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_MII_RXD_0;
+
+ pinMuxReg->PINMUX12 = PINMUX_BALL_A14_MII_RXD_1 | PINMUX_BALL_K15_EMIF_DATA_0 | PINMUX_BALL_G19_MII_RXD_2 | PINMUX_BALL_H18_MII_RXD_3;
+
+ pinMuxReg->PINMUX13 = PINMUX_BALL_J18_MII_TXD_0 | PINMUX_BALL_J19_MII_TXD_1 | PINMUX_BALL_H19_MII_TXEN | PINMUX_BALL_R2_MII_TXD_2;
+
+ pinMuxReg->PINMUX14 = PINMUX_BALL_E18_MII_TXD_3 | PINMUX_BALL_K19_MII_RXCLK | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
+
+ pinMuxReg->PINMUX15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
+
+ pinMuxReg->PINMUX16 = PINMUX_BALL_E13_EMIF_BA_0 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_EMIF_nOE;
+
+ pinMuxReg->PINMUX17 = PINMUX_BALL_D19_MII_TX_CLK | PINMUX_BALL_E11_EMIF_nDQM_1 | PINMUX_BALL_B4_MII_CRS | PINMUX_BALL_E9_EMIF_ADDR_5;
+
+ pinMuxReg->PINMUX18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
+
+ pinMuxReg->PINMUX19 = PINMUX_BALL_E8_EMIF_ADDR_4 | PINMUX_BALL_B11_MII_RX_DV | PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_E7_EMIF_ADDR_3;
+
+ pinMuxReg->PINMUX20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MII_COL | PINMUX_BALL_C9_EMIF_ADDR_11;
+
+ pinMuxReg->PINMUX21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
+
+ pinMuxReg->PINMUX22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_EMIF_ADDR_2;
+
+ pinMuxReg->PINMUX23 = 0x00010100| /* SPI4SOMI is on ball W6 */
+ PINMUX_BALL_C6_EMIF_ADDR_8;
+
+ pinMuxReg->PINMUX24 = 0x01010101;
+
+ pinMuxReg->PINMUX25 = 0x01010101;
+
+ /* Halcogen fix enabling N2HET1[29], N2HET1[31] */
+ pinMuxReg->PINMUX26 = 0x0101 | PINMUX_BALL_W6_DMM_DATA_2 | PINMUX_BALL_T12_DMM_DATA_3;
+
+ pinMuxReg->PINMUX27 = PINMUX_BALL_E19_DMM_DATA_5 | PINMUX_BALL_B6_DMM_DATA_6 | PINMUX_BALL_E16_DMM_DATA_9 | PINMUX_BALL_H17_DMM_DATA_10;
+
+ pinMuxReg->PINMUX28 = PINMUX_BALL_G17_DMM_DATA_11 | PINMUX_BALL_E17_DMM_DATA_13 | PINMUX_BALL_H16_DMM_DATA_14 | PINMUX_BALL_G16_DMM_DATA_15;
+
+ pinMuxReg->PINMUX29 = PINMUX_BALL_D3_SPI2NCS_1;
+
+
+
+
+ PINMUX_ALT_ADC_TRIGGER_SELECT(1);
+ PINMUX_ETHERNET_SELECT(MII);
+
+ PINMUX_SET(0,A5,GIOA_0);
+ PINMUX_SET(18,A11,HET1_14);
+ PINMUX_SET(3,B3,HET1_22);
+ PINMUX_SET(1,C2,GIOA_1);
+ PINMUX_SET(21,K2,GIOB_1);
+ PINMUX_SET(0,W10,GIOB_3);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+ /* Disable Pin Muxing */
+ kickerReg->KICKER0 = 0x00000000;
+ kickerReg->KICKER1 = 0x00000000;
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
-/** @file sys_selftest.c \r
-* @brief Selftest Source File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-* This file contains:\r
-* - Selftest API's\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-#include "sys_selftest.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-/** @fn void ccmSelfCheck(void)\r
-* @brief CCM module self check Driver\r
-*\r
-* This function self checks the CCM module.\r
-*/\r
-void ccmSelfCheck(void)\r
-{\r
- /* Run a diagnostic check on the CCM-R4F module */\r
- /* This step ensures that the CCM-R4F can actually indicate an error */\r
-\r
- /* Configure CCM in self-test mode */\r
- CCMKEYR = 0x6; \r
- /* Wait for CCM self-test to complete */\r
- while ((CCMSR & 0x100) != 0x100);\r
-\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
- \r
- /* Check if there was an error during the self-test */\r
- if ((CCMSR & 0x1) == 0x1)\r
- {\r
- /* STE is set */\r
- ccmFail(0); \r
- }\r
- else\r
- {\r
- /* Check CCM-R4 self-test error flag by itself (without compare error) */\r
- \r
- /* Configure CCM in self-test error-forcing mode */\r
- CCMKEYR = 0xF; \r
- if ((esmREG->ESTATUS1[0] & 0x80000000) != 0x80000000)\r
- {\r
- /* ESM flag is not set */\r
- ccmFail(1); \r
- }\r
- else\r
- {\r
- /* clear ESM group1 channel 31 flag */\r
- esmREG->ESTATUS1[0] = 0x80000000; \r
- \r
- /* Configure CCM in error-forcing mode */\r
- CCMKEYR = 0x9;\r
- \r
- /* check if compare error flag is set */\r
- if ((esmREG->ESTATUS1[1] & 0x4) != 0x4)\r
- {\r
- /* ESM flag is not set */\r
- ccmFail(2);\r
- }\r
- else\r
- {\r
- /* clear ESM group2 channel 2 flag */ \r
- esmREG->ESTATUS1[1] = 0x4;\r
- \r
- /* clear ESM group2 shadow status flag */\r
- esmREG->ESTATUS5EMU = 0x4; \r
- \r
- /* ESM self-test error needs to also be cleared */\r
- esmREG->ESTATUS1[0] = 0x80000000; \r
- \r
- /* Clear CCM-R4 CMPE flag */\r
- CCMSR = 0x00010000;\r
-\r
- /* Return CCM-R4 to lock-step mode */\r
- CCMKEYR = 0x0;\r
- \r
- /* The nERROR pin will become inactive once the LTC counter expires */\r
- esmREG->KEY = 0x5; \r
- }\r
- }\r
- }\r
-}\r
-\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-\r
-/** @fn void ccmFail(unsigned int x)\r
-* @brief CCM module fail service routine\r
-*\r
-* This function is called if CCM module selftest fail.\r
-*/\r
-void ccmFail(unsigned int x)\r
-{\r
- if (x == 0)\r
- {\r
- /* CCM-R4 is not able to flag a compare error in self-test mode.\r
- * Lock-step operation cannot be verified.\r
- */\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
- }\r
- else if (x == 1)\r
- {\r
- /* CCM-R4 self-test error flag is not set in ESM register.\r
- * Could be due to a connection issue inside the part.\r
- */\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
- }\r
- else if (x == 2)\r
- {\r
- /* CCM-R4 compare error flag is not set in ESM.\r
- * Lock-step operation cannot be verified.\r
- */\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
- }\r
-}\r
-\r
-/** @fn void _memoryInit_(unsigned int ram)\r
-* @brief Memory Initialization Driver\r
-*\r
-* This function is called to perform Memory initialization of selected RAM's.\r
-*/\r
-void _memoryInit_(unsigned int ram)\r
-{\r
- /* Enable Memory Hardware Initialization */\r
- systemREG1->MINITGCR = 0xA; \r
- \r
- /* Enable Memory Hardware Initialization for selected RAM's */\r
- systemREG1->MSINENA = ram;\r
- \r
- /* Wait until Memory Hardware Initialization complete */\r
- while( systemREG1->MSTCGSTAT & 0x00000100 != 1);\r
- \r
- /* Disable Memory Hardware Initialization */\r
- systemREG1->MINITGCR = 0xA; \r
-}\r
-\r
-/** @fn void stcSelfCheck(void)\r
-* @brief STC module self check Driver\r
-*\r
-* This function is called to perform STC module self check.\r
-*/\r
-void stcSelfCheck(void)\r
-{\r
- volatile int i = 0;\r
-\r
- /* Run a diagnostic check on the CPU self-test controller */\r
- /* First set up the STC clock divider as STC is only supported up to 90MHz */\r
- \r
- /* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */\r
- systemREG2->STCCLKDIV = 0x01000000; \r
- \r
- /* Select one test interval, restart self-test next time, 0x00010001 */\r
- stcREG->STCGCR0 = 0x00010001; \r
- \r
- /* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */\r
- stcREG->STCSCSCR = 0x1A; \r
- \r
- /* Maximum time-out period */\r
- stcREG->STCTPR = 0xFFFFFFFF; \r
-\r
- /* wait for 16 VBUS clock cycles at least */\r
- for (i=0; i<16; i++); \r
-\r
- /* Enable self-test */\r
- stcREG->STCGCR1 = 0xA; \r
- \r
- /* wait for 16 VBUS clock cycles at least */\r
- for (i=0; i<16; i++); \r
-\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
- \r
- /* Idle the CPU so that the self-test can start */\r
- _gotoCPUIdle_();\r
-\r
-}\r
-\r
-/** @fn void cpuSelfTest(unsigned int no_of_intervals, unsigned int max_timeout, boolean_t restart_test)\r
-* @brief CPU self test Driver\r
-* @param[in] no_of_intervals - Number of Test Intervals to be \r
-* @param[in] max_timeout - Maximun Timeout to complete selected test Intervals\r
-* @param[in] restart_test - Restart the test from Interval 0 or Continue from where it stopped.\r
-*\r
-* This function is called to perfrom CPU self test using STC module.\r
-*/\r
-void cpuSelfTest(unsigned int no_of_intervals, unsigned int max_timeout, boolean_t restart_test)\r
-{\r
- volatile int i = 0;\r
-\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
- \r
- /* Run specified no of test intervals starting from interval 0 */\r
- /* Start test from interval 0 or continue the test. */ \r
- stcREG->STCGCR0 = no_of_intervals << 16 \r
- | (unsigned int) restart_test; \r
- \r
- /* Configure Maximum time-out period */\r
- stcREG->STCTPR = max_timeout; \r
- \r
- /* wait for 16 VBUS clock cycles at least */\r
- for (i=0; i<16; i++); \r
-\r
- /* Enable self-test */\r
- stcREG->STCGCR1 = 0xA; \r
-\r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
- /* Idle the CPU so that the self-test can start */\r
- \r
- _gotoCPUIdle_();\r
- \r
-}\r
-\r
-/** @fn void pbistSelfCheck(void)\r
-* @brief PBIST self test Driver\r
-*\r
-* This function is called to perfrom PBIST self test.\r
-*/\r
-void pbistSelfCheck(void)\r
-{\r
- int i = 0;\r
- /* Run a diagnostic check on the memory self-test controller */\r
- /* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */\r
- \r
- /* PBIST ROM clock frequency = HCLK frequency /2 */\r
- systemREG1->MSTGCR |= 0x00000100; \r
- \r
- /* Enable PBIST controller */\r
- systemREG1->MSINENA = 0x1; \r
- \r
- /* clear MSTGENA field */\r
- systemREG1->MSTGCR &= ~(0xF); \r
- \r
- /* Enable PBIST self-test */\r
- systemREG1->MSTGCR |= 0xA; \r
- \r
- /* software loop to wait at least 32 VCLK cycles */\r
- for (i = 0; i < 32; i++); \r
-\r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
- \r
- /* Enable PBIST clocks and ROM clock */\r
- pbistREG->PACT = 0x3; \r
- \r
- /* Select algo#3, march13n to be run */\r
- pbistREG->ALGO = 0x00000004; \r
- \r
- /* Select RAM Group 1, which is actually the PBIST ROM */\r
- pbistREG->RINFOL = 0x1; \r
- \r
- /* ROM contents will not override ALGO and RINFOx settings */\r
- pbistREG->OVER = 0x0; \r
- \r
- /* Algorithm code is loaded from ROM */\r
- pbistREG->ROM = 0x3; \r
- \r
- /* Start PBIST */\r
- pbistREG->DLR = 0x14; \r
- \r
- /* wait until memory self-test done is indicated */\r
- while ((systemREG1->MSTCGSTAT & 0x1) != 0x1); \r
- \r
- /* Check for the failure */\r
- if (((pbistREG->FSRF0 & 0x1) != 0x1) & ((pbistREG->FSRF1 & 0x1) != 0x1))\r
- {\r
- /* no failure was indicated even if the march13n algorithm was run on a ROM */\r
- pbistSelfCheckFail();\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
- }\r
- else \r
- {\r
- /* PBIST self-check has passed */\r
- \r
- /* Disable PBIST clocks and ROM clock */\r
- pbistREG->PACT = 0x0; \r
- \r
- /* Disable PBIST */\r
- systemREG1->MSTGCR &= ~(0xF); \r
- systemREG1->MSTGCR |= 0x5;\r
- \r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
- }\r
-}\r
-\r
-/** @fn void pbistSelfCheckFail(void)\r
-* @brief PBIST self test Driver failure service routine\r
-*\r
-* This function is called on PBIST self test failure.\r
-*/\r
-void pbistSelfCheckFail(void)\r
-{\r
- /* The PBIST controller is not capable of reporting a failure.\r
- * PBIST cannot be used to verify memory integrity.\r
- * Need custom handler here.\r
- */\r
-}\r
-\r
-/** @fn void pbistRun(unsigned int raminfoL, unsigned int algomask)\r
-* @brief CPU self test Driver\r
-* @param[in] raminfoL - Select the list of RAM to be tested.\r
-* @param[in] algomask - Select the list of Algorithm to be run.\r
-*\r
-* This function performs Memory Built-in Self test using PBIST module.\r
-*/\r
-void pbistRun(unsigned int raminfoL, unsigned int algomask)\r
-{\r
- int i = 0;\r
- \r
- /* PBIST ROM clock frequency = HCLK frequency /2 */\r
- systemREG1->MSTGCR |= 0x00000100; \r
- \r
- /* Enable PBIST controller */\r
- systemREG1->MSINENA = 0x1; \r
- \r
- /* clear MSTGENA field */\r
- systemREG1->MSTGCR &= ~(0xF); \r
- \r
- /* Enable PBIST self-test */\r
- systemREG1->MSTGCR |= 0xA; \r
- \r
- /* software loop to wait at least 32 VCLK cycles */\r
- for (i = 0; i < 32; i++); \r
-\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
- \r
- /* Enable PBIST clocks and ROM clock */\r
- pbistREG->PACT = 0x3; \r
- \r
- /* Select all algorithms to be tested */\r
- pbistREG->ALGO = algomask; \r
- \r
- /* Select RAM groups */\r
- pbistREG->RINFOL = raminfoL; \r
- \r
- /* Select all RAM groups */\r
- pbistREG->RINFOU = 0x00000000; \r
- \r
- /* ROM contents will not override RINFOx settings */\r
- pbistREG->OVER = 0x0; \r
- \r
- /* Algorithm code is loaded from ROM */\r
- pbistREG->ROM = 0x3; \r
- \r
- /* Start PBIST */\r
- pbistREG->DLR = 0x14; \r
-}\r
-\r
-/** @fn void pbistStop(void)\r
-* @brief Routine to stop PBIST test enabled.\r
-*\r
-* This function is called to stop PBIST after test is performed.\r
-*/\r
-void pbistStop(void)\r
-{\r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
- /* disable pbist clocks and ROM clock */\r
- pbistREG->PACT = 0x0; \r
- systemREG1->MSTGCR &= ~(0xF);\r
- systemREG1->MSTGCR |= 0x5;\r
-}\r
-\r
-/** @fn boolean_t pbistIsTestCompleted(void)\r
-* @brief Checks to see if the PBIST test is completed.\r
-* @return 1 if PBIST test completed, otherwise 0.\r
-*\r
-* Checks to see if the PBIST test is completed.\r
-*/\r
-boolean_t pbistIsTestCompleted(void)\r
-{\r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
-\r
- return ((systemREG1->MSTCGSTAT & 0x1) != 0);\r
-}\r
-\r
-/** @fn boolean_t pbistIsTestPassed(void)\r
-* @brief Checks to see if the PBIST test is completed sucessfully.\r
-* @return 1 if PBIST test passed, otherwise 0.\r
-*\r
-* Checks to see if the PBIST test is completed sucessfully.\r
-*/\r
-boolean_t pbistIsTestPassed(void)\r
-{\r
-/* USER CODE BEGIN (16) */\r
-/* USER CODE END */\r
-\r
- return ((pbistREG->FSRF0 || pbistREG->FSRF1) == 0);\r
-}\r
-\r
-/** @fn boolean_t pbistPortTestStatus(uint32_t port)\r
-* @brief Checks to see if the PBIST Port test is completed sucessfully.\r
-* @param[in] port - Select the port to get the status.\r
-* @return 1 if PBIST Port test completed sucessfully, otherwise 0.\r
-*\r
-* Checks to see if the selected PBIST Port test is completed sucessfully.\r
-*/\r
-boolean_t pbistPortTestStatus(uint32_t port)\r
-{\r
- boolean_t status;\r
-/* USER CODE BEGIN (17) */\r
-/* USER CODE END */\r
-\r
- if(port == PBIST_PORT0)\r
- {\r
- status = (pbistREG->FSRF0 == 0);\r
- }\r
- else\r
- {\r
- status = (pbistREG->FSRF1 == 0); \r
- }\r
- \r
- return status;\r
-}\r
-\r
-/** @fn void efcCheck(void)\r
-* @brief EFUSE module self check Driver\r
-*\r
-* This function self checks the EFSUE module.\r
-*/\r
-void efcCheck(void)\r
-{\r
- unsigned int efcStatus = 0;\r
-\r
-/* USER CODE BEGIN (18) */\r
-/* USER CODE END */\r
- \r
- /* read the EFC Error Status Register */\r
- efcStatus = efcREG->ERROR; \r
-\r
-/* USER CODE BEGIN (19) */\r
-/* USER CODE END */\r
- \r
- if (efcStatus == 0x0)\r
- {\r
- /* run stuck-at-zero test and check if it passed */\r
- if (efcStuckZeroTest()) \r
- {\r
- /* start EFC ECC logic self-test */\r
- efcSelfTest(); \r
- }\r
- else\r
- {\r
- /* EFC output is stuck-at-zero, device operation unreliable */\r
- efcClass2Error(); \r
- }\r
- }\r
- /* EFC Error Register is not zero */\r
- else \r
- {\r
- /* one-bit error detected during autoload */\r
- if (efcStatus == 0x15) \r
- {\r
- /* start EFC ECC logic self-test */\r
- efcSelfTest(); \r
- }\r
- else\r
- {\r
- /* Some other EFC error was detected */\r
- efcClass2Error(); \r
- }\r
- }\r
-}\r
-\r
-/** @fn boolean_t efcStuckZeroTest(void)\r
-* @brief Checks to see if the EFUSE Stuck at zero test is completed sucessfully.\r
-* @return 1 if EFUSE Stuck at zero test completed, otherwise 0.\r
-*\r
-* Checks to see if the EFUSE Stuck at zero test is completed sucessfully.\r
-*/\r
-boolean_t efcStuckZeroTest(void)\r
-{\r
- boolean_t result = FALSE;\r
- unsigned int error_checks = EFC_INSTRUCTION_INFO_EN | \r
- EFC_INSTRUCTION_ERROR_EN | \r
- EFC_AUTOLOAD_ERROR_EN | \r
- EFC_SELF_TEST_ERROR_EN ;\r
- \r
- /* configure the output enable for auto load error , instruction info,\r
- instruction error, and self test error using boundary register \r
- and drive values one across all the errors */\r
- efcREG->BOUNDARY = (OUTPUT_ENABLE | error_checks);\r
- \r
- /* Read from the pin register. This register holds the current values \r
- of above errors. This value should be 0x5c00.If not at least one of\r
- the above errors is stuck at 0. */\r
- if ((efcREG->PINS & 0x5C00) == 0x5C00)\r
- {\r
- /* check if the ESM group1 channels 40 is set and group3 channel 2 is set */\r
- if (((esmREG->ESTATUS4[0] & 0x200) == 0x200) & ((esmREG->ESTATUS1[2] & 0x2) == 0x2))\r
- {\r
- /* stuck-at-zero test passed */\r
- result = TRUE; \r
- }\r
- }\r
- \r
- /* put the pins back low */\r
- efcREG->BOUNDARY = OUTPUT_ENABLE;\r
- \r
- /* clear group1 flags */\r
- esmREG->ESTATUS4[0] = 0x300;\r
- \r
- /* clear group3 flag */\r
- esmREG->ESTATUS1[2] = 0x2; \r
- \r
- /* The nERROR pin will become inactive once the LTC counter expires */\r
- esmREG->KEY = 0x5; \r
-\r
- return result;\r
-}\r
-\r
-/** @fn void efcSelfTest(void)\r
-* @brief EFUSE module self check Driver\r
-*\r
-* This function self checks the EFSUE module.\r
-*/\r
-void efcSelfTest(void)\r
-{\r
- /* configure self-test cycles */\r
- efcREG->SELF_TEST_CYCLES = 0x258;\r
- \r
- /* configure self-test signature */\r
- efcREG->SELF_TEST_SIGN = 0x5362F97F;\r
- \r
- /* configure boundary register to start ECC self-test */\r
- efcREG->BOUNDARY = 0x0000200F;\r
-}\r
-\r
-/** @fn boolean_t checkefcSelfTest(void)\r
-* @brief EFUSE module self check Driver\r
-*\r
-* This function self checks the EFSUE module.\r
-*/\r
-boolean_t checkefcSelfTest(void)\r
-{\r
- boolean_t result = FALSE;\r
- \r
- /* wait until EFC self-test is done */\r
- while(!(efcREG->PINS & EFC_SELF_TEST_DONE));\r
- \r
- /* check if EFC self-test error occurred */\r
- if (!(efcREG->PINS & EFC_SELF_TEST_ERROR) & !(efcREG->ERROR & SELF_TEST_ERROR))\r
- {\r
- /* check if EFC self-test error is set */\r
- if ((esmREG->ESTATUS4[0] & 0x100) != 0x100) \r
- {\r
- result = TRUE;\r
- }\r
- }\r
- return result;\r
-}\r
-\r
-/** @fn void efcClass1Error(void)\r
-* @brief EFUSE Class1 Error service routine\r
-*\r
-* This function is called if EFC ECC logic self-test.\r
-*/\r
-void efcClass1Error(void)\r
-{\r
- /* Autoload error was detected during device power-up, and device operation is not reliable. */\r
- while(1);\r
-}\r
-\r
-/** @fn void efcClass2Error(void)\r
-* @brief EFUSE Class2 Error service routine\r
-*\r
-* This function is called if EFC output is stuck-at-zero.\r
-*/\r
-void efcClass2Error(void)\r
-{\r
- /* The ECC logic inside the eFuse controller is not operational. Device operation is not reliable. */\r
- while(1);\r
-}\r
-\r
-/** @fn void fmcBus2Check(void)\r
-* @brief Self Check Flash Bus2 Interface\r
-*\r
-* This function self checks Flash Bus2 Interface\r
-*/\r
-void fmcBus2Check(void)\r
-{\r
- /* enable ECC logic inside FMC */\r
- flashWREG->FEDACCTRL1 = 0x000A060A; \r
-\r
- if (esmREG->ESTATUS1[0] & 0x40)\r
- {\r
- /* a 1-bit error was detected during flash OTP read by flash module\r
- run a self-check on ECC logic inside FMC */\r
- \r
- /* clear ESM group1 channel 6 flag */\r
- esmREG->ESTATUS1[0] = 0x40; \r
- \r
- fmcECCcheck();\r
- }\r
- \r
- /* no 2-bit or 1-bit error detected during power-up */\r
- else \r
- {\r
- fmcECCcheck();\r
- }\r
-}\r
-\r
-/** @fn void fmcECCcheck(void)\r
-* @brief Check Flash ECC Single Bit and multi Bit errors detection logic.\r
-*\r
-* This function Checks Flash ECC Single Bit and multi Bit errors detection logic.\r
-*/\r
-void fmcECCcheck(void)\r
-{\r
- volatile unsigned int otpread;\r
- volatile unsigned int temp;\r
-\r
- /* read location with deliberate 1-bit error */\r
- otpread = flash1bitError; \r
- if (esmREG->ESTATUS1[0] & 0x40)\r
- {\r
- /* 1-bit failure was indicated and corrected */\r
- flashWREG->FEDACSTATUS = 0x00010006;\r
- \r
- /* clear ESM group1 channel 6 flag */\r
- esmREG->ESTATUS1[0] = 0x40; \r
- \r
- /* read location with deliberate 2-bit error */\r
- otpread = flash2bitError; \r
- if (esmREG->ESTATUS1[2] & 0x80)\r
- {\r
- /* 2-bit failure was detected correctly */\r
- temp = flashWREG->FUNCERRADD;\r
- flashWREG->FEDACSTATUS = 0x00020100;\r
- \r
- /* clear ESM group3 channel 7 */\r
- esmREG->ESTATUS1[2] = 0x80; \r
- \r
- /* The nERROR pin will become inactive once the LTC counter expires */\r
- esmREG->KEY = 0x5; \r
-\r
- }\r
- else\r
- {\r
- /* ECC logic inside FMC cannot detect 2-bit error */\r
- fmcClass2Error(); \r
- }\r
- }\r
- else\r
- {\r
- /* ECC logic inside FMC cannot detect 1-bit error */\r
- fmcClass2Error(); \r
- }\r
-}\r
-\r
-/** @fn void fmcClass1Error(void)\r
-* @brief Flash Multi bit ECC error service routine detected during reset configuration.\r
-*\r
-* This function is called if Flash Multi bit ECC error detected during reset configuration.\r
-*/\r
-void fmcClass1Error(void)\r
-{\r
- /* there was a multi-bit error detected during the reset configuration word read from the OTP */\r
- /* This affects the device power domains, endianness, and exception handling ISA */\r
- /* Device operation is not reliable. */\r
- while(1);\r
-}\r
-\r
-/** @fn void fmcClass2Error(void)\r
-* @brief Flash OTP or EEPROM read Multi bit ECC error service routine\r
-*\r
-* This function is called if Flash OTP or EEPROM read Multi bit ECC error detected.\r
-*/\r
-void fmcClass2Error(void)\r
-{\r
- /* The ECC logic inside FMC used to protect against 1-bit and 2-bit errors in OTP and EEPROM banks */\r
- /* is not operational. Device operation is not reliable. */\r
- while(1);\r
-}\r
-\r
-/** @fn void checkB0RAMECC(void)\r
-* @brief Check TCRAM1 ECC error detection logic.\r
-*\r
-* This function checks TCRAM1 ECC error detection logic.\r
-*/\r
-void checkB0RAMECC(void)\r
-{\r
- volatile unsigned int ramread = 0;\r
-\r
- /* enable writes to ECC RAM, enable ECC error response */\r
- tcram1REG->RAMCTRL = 0x0005010A; \r
- tcram2REG->RAMCTRL = 0x0005010A;\r
-\r
- /* the first 1-bit error will cause an error response */\r
- tcram1REG->RAMTHRESHOLD = 0x1; \r
- tcram2REG->RAMTHRESHOLD = 0x1;\r
-\r
- /* allow SERR to be reported to ESM */\r
- tcram1REG->RAMINTCTRL = 0x1; \r
- tcram2REG->RAMINTCTRL = 0x1;\r
- \r
- /* cause a 1-bit ECC error */\r
- tcramA1bitError ^= 0x1; \r
- \r
- /* disable writes to ECC RAM */\r
- tcram1REG->RAMCTRL = 0x0005000A; \r
- tcram2REG->RAMCTRL = 0x0005000A;\r
-\r
- /* read from location with 1-bit ECC error */\r
- ramread = tcramA1bit; \r
- \r
- /* SERR not set in TCRAM1 or TCRAM2 modules */\r
- if (!((tcram1REG->RAMERRSTATUS & 1) || (tcram2REG->RAMERRSTATUS & 1))) \r
- {\r
- /* TCRAM module does not reflect 1-bit error reported by CPU */\r
- tcramClass2Error(); \r
- }\r
- else\r
- {\r
- /* clear SERR flag */\r
- tcram1REG->RAMERRSTATUS = 0x1; \r
- tcram2REG->RAMERRSTATUS = 0x1;\r
- \r
- /* clear status flags for ESM group1 channels 26 and 28 */\r
- esmREG->ESTATUS1[0] = 0x14000000; \r
- }\r
-\r
- /* enable writes to ECC RAM, enable ECC error response */\r
- tcram1REG->RAMCTRL = 0x0005010A; \r
- tcram2REG->RAMCTRL = 0x0005010A;\r
-\r
- /* cause a 2-bit ECC error */\r
- tcramA2bitError ^= 0x3; \r
- ramread = tcram1REG->RAMCTRL;\r
- ramread = tcram2REG->RAMCTRL;\r
-\r
- /* read from location with 2-bit ECC error this will cause a data abort to be generated */\r
- ramread = tcramA2bit; \r
-}\r
-\r
-/** @fn void checkB1RAMECC(void)\r
-* @brief Check TCRAM2 ECC error detection logic.\r
-*\r
-* This function checks TCRAM2 ECC error detection logic.\r
-*/\r
-void checkB1RAMECC(void)\r
-{\r
- volatile unsigned int ramread = 0;\r
-\r
- /* enable writes to ECC RAM, enable ECC error response */\r
- tcram1REG->RAMCTRL = 0x0005010A; \r
- tcram2REG->RAMCTRL = 0x0005010A;\r
- \r
- /* the first 1-bit error will cause an error response */\r
- tcram1REG->RAMTHRESHOLD = 0x1; \r
- tcram2REG->RAMTHRESHOLD = 0x1;\r
-\r
- /* allow SERR to be reported to ESM */\r
- tcram1REG->RAMINTCTRL = 0x1; \r
- tcram2REG->RAMINTCTRL = 0x1;\r
-\r
- /* cause a 1-bit ECC error */\r
- tcramB1bitError ^= 0x1; \r
- \r
- /* disable writes to ECC RAM */\r
- tcram1REG->RAMCTRL = 0x0005000A; \r
- tcram2REG->RAMCTRL = 0x0005000A;\r
-\r
- /* read from location with 1-bit ECC error */\r
- ramread = tcramB1bit; \r
- \r
- /* SERR not set in TCRAM1 or TCRAM2 modules */\r
- if (!((tcram1REG->RAMERRSTATUS & 1) || (tcram2REG->RAMERRSTATUS & 1))) \r
- {\r
- /* TCRAM module does not reflect 1-bit error reported by CPU */\r
- tcramClass2Error(); \r
- }\r
- else\r
- {\r
- /* clear SERR flag */\r
- tcram1REG->RAMERRSTATUS = 0x1; \r
- tcram2REG->RAMERRSTATUS = 0x1;\r
- \r
- /* clear status flags for ESM group1 channels 26 and 28 */\r
- esmREG->ESTATUS1[0] = 0x14000000; \r
- }\r
-\r
- /* enable writes to ECC RAM, enable ECC error response */\r
- tcram1REG->RAMCTRL = 0x0005010A; \r
- tcram2REG->RAMCTRL = 0x0005010A;\r
- \r
- /* cause a 2-bit ECC error */\r
- tcramB2bitError ^= 0x3; \r
- \r
- /* disable writes to ECC RAM */\r
- tcram1REG->RAMCTRL = 0x0005000A; \r
- tcram2REG->RAMCTRL = 0x0005000A;\r
-}\r
-\r
-/** @fn void tcramClass1Error(void)\r
-* @brief Error service routine called if TCRAM module cannot capture 2-bit error.\r
-*\r
-* Error service routine called if TCRAM module cannot respond to 2-bit error.\r
-*/\r
-void tcramClass1Error(void)\r
-{\r
- /* TCRAM module is not capable of responding to 2-bit error indicated by CPU.\r
- * Device operation is not reliable and not recommended.\r
- */\r
- while(1);\r
-}\r
-\r
-/** @fn void tcramClass2Error(void)\r
-* @brief Error service routine called if TCRAM module cannot capture 1-bit error.\r
-*\r
-* Error service routine called if TCRAM module cannot respond to 1-bit error.\r
-*/\r
-void tcramClass2Error(void)\r
-{\r
- /* TCRAM module is not capable of responding to 1-bit error indicated by CPU.\r
- * Device operation is possible, but is prone to future multi-bit errors not being detected.\r
- * Need custom handler here instead of the infinite loop.\r
- */\r
- while(1);\r
-}\r
-\r
-/** @fn void checkFlashECC(void)\r
-* @brief Check Flash ECC error detection logic.\r
-*\r
-* This function checks Flash ECC error detection logic.\r
-*/\r
-void checkFlashECC(void)\r
-{\r
- /* Routine to check operation of ECC logic inside CPU for accesses to program flash */\r
- volatile unsigned int flashread = 0;\r
-\r
- /* Flash Module ECC Response enabled */\r
- flashWREG->FEDACCTRL1 = 0x000A060A; \r
- \r
- /* Enable diagnostic mode and select diag mode 7 */\r
- flashWREG->FDIAGCTRL = 0x00050007; \r
- \r
- /* Select ECC diagnostic mode, single-bit to be corrupted */\r
- flashWREG->FPAROVR = 0x00005401; \r
- \r
- /* Set the trigger for the diagnostic mode */\r
- flashWREG->FDIAGCTRL |= 0x01000000; \r
- \r
- /* read a flash location from the mirrored memory map */\r
- flashread = flashBadECC; \r
- \r
- /* disable diagnostic mode */\r
- flashWREG->FDIAGCTRL = 0x000A0007; \r
-\r
- /* this will have caused a single-bit error to be generated and corrected by CPU */\r
- /* single-bit error not captured in flash module */\r
- if (!(flashWREG->FEDACSTATUS & 0x2)) \r
- {\r
- flashClass2Error();\r
- }\r
- else\r
- {\r
- /* clear single-bit error flag */\r
- flashWREG->FEDACSTATUS = 0x2; \r
-\r
- /* clear ESM flag */\r
- esmREG->ESTATUS1[0] = 0x40; \r
-\r
- /* Enable diagnostic mode and select diag mode 7 */\r
- flashWREG->FDIAGCTRL = 0x00050007; \r
- \r
- /* Select ECC diagnostic mode, two bits of ECC to be corrupted */\r
- flashWREG->FPAROVR = 0x00005A03; \r
- \r
- /* Set the trigger for the diagnostic mode */\r
- flashWREG->FDIAGCTRL |= 0x01000000; \r
-\r
- /* read from flash location from mirrored memory map this will cause a data abort */\r
- flashread = flashBadECC; \r
- }\r
-\r
-}\r
-\r
-/** @fn void flashClass1Error(void)\r
-* @brief Error service routine called if Flash module cannot capture 2-bit error.\r
-*\r
-* Error service routine called if Flash module cannot capture 2-bit error.\r
-*/\r
-void flashClass1Error(void)\r
-{\r
- /* Flash module not able to capture 2-bit error from CPU.\r
- * Device operation not reliable.\r
- */\r
- while(1);\r
-\r
-}\r
-\r
-/** @fn void flashClass2Error(void)\r
-* @brief Error service routine called if Flash module cannot capture 1-bit error.\r
-*\r
-* Error service routine called if Flash module cannot capture 1-bit error.\r
-*/\r
-void flashClass2Error(void)\r
-{\r
- /* Flash module not able to capture 1-bit error from CPU.\r
- * Device operation possible if this weakness in diagnostic is okay.\r
- */\r
-}\r
-\r
-/** @fn void custom_dabort(void)\r
-* @brief Custom Data abort routine for the application.\r
-*\r
-* Custom Data abort routine for the application.\r
-*/\r
-void custom_dabort(void)\r
-{\r
- /* Need custom data abort handler here.\r
- * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC logic.\r
- */\r
-}\r
-\r
-/** @fn void stcSelfCheckFail(void)\r
-* @brief STC Self test check fail service routine\r
-*\r
-* This function is called if STC Self test check fail.\r
-*/\r
-void stcSelfCheckFail(void)\r
-{\r
- /* CPU self-test controller's own self-test failed.\r
- * It is not possible to verify that STC is capable of indicating a CPU self-test error.\r
- * It is not recommended to continue operation.\r
- */\r
- while(1);\r
-}\r
-\r
-/** @fn void cpuSelfTestFail(void)\r
-* @brief CPU Self test check fail service routine\r
-*\r
-* This function is called if CPU Self test check fail.\r
-*/\r
-void cpuSelfTestFail(void)\r
-{\r
- /* CPU self-test has failed.\r
- * CPU operation is not reliable.\r
- */\r
- while(1);\r
-}\r
-\r
-\r
-/** @fn void vimParityCheck(void)\r
-* @brief Routine to check VIM RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check VIM RAM parity error detection and signaling mechanism\r
-*/\r
-void vimParityCheck(void)\r
-{\r
- volatile unsigned int vimramread = 0;\r
-\r
- /* Enable parity checking and parity test mode */\r
- VIM_PARCTL = 0x0000010A;\r
- \r
- /* flip a bit in the VIM RAM parity location */\r
- VIMRAMPARLOC ^= 0x1; \r
- \r
- /* disable parity test mode */\r
- VIM_PARCTL = 0x0000000A; \r
-\r
- /* cause parity error */\r
- vimramread = VIMRAMLOC; \r
- \r
- /* check if ESM group1 channel 15 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x8000)) \r
- {\r
- /* VIM RAM parity error was not flagged to ESM. */\r
- /* Need custom routine to handle this failure instead of the infinite loop. */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear VIM RAM parity error flag in VIM */\r
- VIM_PARFLG = 0x1; \r
- \r
- /* clear ESM group1 channel 15 flag */\r
- esmREG->ESTATUS1[0] = 0x8000; \r
- }\r
-}\r
-\r
-/** @fn void dmaParityCheck(void)\r
-* @brief Routine to check DMA control packet RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check DMA control packet RAM parity error detection and signaling mechanism\r
-*/\r
-void dmaParityCheck(void)\r
-{\r
- volatile unsigned int dmaread = 0;\r
-\r
- /* Enable parity checking and parity test mode */\r
- DMA_PARCR = 0x0000010A; \r
- \r
- /* Flip a bit in DMA RAM parity location */\r
- DMARAMPARLOC ^= 0x1; \r
- \r
- /* Disable parity test mode */\r
- DMA_PARCR = 0x0000000A; \r
- \r
- /* Cause parity error */\r
- dmaread = DMARAMLOC; \r
- \r
- /* Check if ESM group1 channel 3 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x8)) \r
- {\r
- /* DMA RAM parity error was not flagged to ESM. */\r
- /* Need custom routine to handle this failure instead of the infinite loop. */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear DMA parity error flag in DMA */\r
- DMA_PARADDR = 0x01000000; \r
- \r
- /* clear ESM group1 channel 3 flag */\r
- esmREG->ESTATUS1[0] = 0x8; \r
- }\r
-\r
-}\r
-\r
-/** @fn void het1ParityCheck(void)\r
-* @brief Routine to check HET1 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check HET1 RAM parity error detection and signaling mechanism\r
-*/\r
-void het1ParityCheck(void)\r
-{\r
- volatile unsigned int nhetread = 0;\r
-\r
- /* Set TEST mode and enable parity checking */\r
- hetREG1->PCREG = 0x0000010A; \r
- \r
- /* flip parity bit */\r
- NHET1RAMPARLOC ^= 0x1; \r
- \r
- /* Disable TEST mode */\r
- hetREG1->PCREG = 0x0000000A; \r
-\r
- /* read to cause parity error */\r
- nhetread = NHET1RAMLOC; \r
-\r
- /* check if ESM group1 channel 7 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x80)) \r
- {\r
- /* NHET1 RAM parity error was not flagged to ESM. */\r
- /* Need custom routine to handle this failure instead of the infinite loop. */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear ESM group1 channel 7 flag */\r
- esmREG->ESTATUS1[0] = 0x80; \r
- }\r
-}\r
-\r
-/** @fn void htu1ParityCheck(void)\r
-* @brief Routine to check HTU1 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check HTU1 RAM parity error detection and signaling mechanism\r
-*/\r
-void htu1ParityCheck(void)\r
-{\r
- volatile unsigned int hturead = 0;\r
- /* Enable parity and TEST mode */\r
- htuREG1->PCR = 0x0000010A; \r
- \r
- /* flip parity bit */ \r
- HTU1PARLOC ^= 0x1; \r
- \r
- /* Disable parity RAM test mode */\r
- htuREG1->PCR = 0x0000000A; \r
- \r
- /* read to cause parity error */\r
- hturead = HTU1RAMLOC; \r
- \r
- /* check if ESM group1 channel 8 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x100)) \r
- {\r
- /* HTU1 RAM parity error was not flagged to ESM. */\r
- /* Need custom routine to handle this failure instead of the infinite loop. */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* Clear HTU parity error flag */\r
- htuREG1->PAR = 0x00010000; \r
- esmREG->ESTATUS1[0] = 0x100;\r
- }\r
-}\r
-\r
-/** @fn void het2ParityCheck(void)\r
-* @brief Routine to check HET2 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check HET2 RAM parity error detection and signaling mechanism\r
-*/\r
-void het2ParityCheck(void)\r
-{\r
- volatile unsigned int nhetread = 0;\r
- \r
- /* Set TEST mode and enable parity checking */\r
- hetREG2->PCREG = 0x0000010A; \r
- \r
- /* flip parity bit */\r
- NHET2RAMPARLOC ^= 0x1; \r
- \r
- /* Disable TEST mode */\r
- hetREG2->PCREG = 0x0000000A; \r
-\r
- /* read to cause parity error */\r
- nhetread = NHET2RAMLOC; \r
-\r
- /* check if ESM group1 channel 7 or 34 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x80) && !(esmREG->ESTATUS4[0] & 0x4)) \r
- {\r
- /* NHET2 RAM parity error was not flagged to ESM. */\r
- /* Need custom routine to handle this failure instead of the infinite loop. */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear ESM group1 channel 7 flag */\r
- esmREG->ESTATUS1[0] = 0x80; \r
- \r
- /* clear ESM group1 channel 34 flag */\r
- esmREG->ESTATUS4[0] = 0x4; \r
- }\r
-}\r
-\r
-/** @fn void htu2ParityCheck(void)\r
-* @brief Routine to check HTU2 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check HTU2 RAM parity error detection and signaling mechanism\r
-*/\r
-void htu2ParityCheck(void)\r
-{\r
- volatile unsigned int hturead = 0;\r
-\r
- /* Enable parity and TEST mode */\r
- htuREG2->PCR = 0x0000010A; \r
- \r
- /* flip parity bit */\r
- HTU2PARLOC ^= 0x1; \r
- \r
- /* Disable parity RAM test mode */\r
- htuREG2->PCR = 0x0000000A; \r
-\r
- /* read to cause parity error */\r
- hturead = HTU2RAMLOC; \r
-\r
- /* check if ESM group1 channel 8 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x100)) \r
- {\r
- /* HTU2 RAM parity error was not flagged to ESM. */\r
- /* Need custom routine to handle this failure instead of the infinite loop. */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* Clear HTU parity error flag */\r
- htuREG2->PAR = 0x00010000; \r
- esmREG->ESTATUS1[0] = 0x100;\r
- }\r
-}\r
-\r
-/** @fn void adc1ParityCheck(void)\r
-* @brief Routine to check ADC1 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check ADC1 RAM parity error detection and signaling mechanism\r
-*/\r
-void adc1ParityCheck(void)\r
-{\r
- volatile unsigned int adcramread = 0;\r
-\r
- /* Set the TEST bit in the PARCR and enable parity checking */\r
- adcREG1->PARCR = 0x10A; \r
- \r
- /* Invert the parity bits inside the ADC1 RAM's first location */\r
- adcPARRAM1 = ~(adcPARRAM1); \r
-\r
- /* clear the TEST bit */\r
- adcREG1->PARCR = 0x00A; \r
-\r
- /* This read is expected to trigger a parity error */\r
- adcramread = adcRAM1; \r
-\r
- /* Check for ESM group1 channel 19 to be flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x80000)) \r
- {\r
- /* no ADC1 RAM parity error was flagged to ESM */\r
- /* Need custom routine to handle this failure instead of the infinite loop */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear ADC1 RAM parity error flag */\r
- esmREG->ESTATUS1[0] = 0x80000; \r
- }\r
-}\r
-\r
-/** @fn void adc2ParityCheck(void)\r
-* @brief Routine to check ADC2 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check ADC2 RAM parity error detection and signaling mechanism\r
-*/\r
-void adc2ParityCheck(void)\r
-{\r
- volatile unsigned int adcramread = 0;\r
-\r
- /* Set the TEST bit in the PARCR and enable parity checking */\r
- adcREG2->PARCR = 0x10A; \r
- \r
- /* Invert the parity bits inside the ADC2 RAM's first location */\r
- adcPARRAM2 = ~(adcPARRAM2); \r
-\r
- /* clear the TEST bit */\r
- adcREG2->PARCR = 0x00A; \r
-\r
- /* This read is expected to trigger a parity error */\r
- adcramread = adcRAM2; \r
-\r
- /* Check for ESM group1 channel 1 to be flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x2)) \r
- {\r
- /* no ADC2 RAM parity error was flagged to ESM */\r
- /* Need custom routine to handle this failure instead of the infinite loop */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear ADC2 RAM parity error flag */ \r
- esmREG->ESTATUS1[0] = 0x2; \r
- }\r
-}\r
-\r
-/** @fn void can1ParityCheck(void)\r
-* @brief Routine to check CAN1 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check CAN1 RAM parity error detection and signaling mechanism\r
-*/\r
-void can1ParityCheck(void)\r
-{\r
- volatile unsigned int canread = 0;\r
-\r
- /* Disable parity, init mode, TEST mode */\r
- canREG1->CTL = 0x00001481; \r
- \r
- /* Enable RAM Direct Access mode */\r
- canREG1->TEST = 0x00000200; \r
-\r
- /* flip the parity bit */\r
- canPARRAM1 ^= 0x00001000; \r
-\r
- /* Enable parity, disable init, still TEST mode */\r
- canREG1->CTL = 0x00002880; \r
-\r
- /* Read location with parity error */\r
- canread = canRAM1; \r
-\r
- /* check if ESM group1 channel 21 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x00200000)) \r
- {\r
- /* No DCAN1 RAM parity error was flagged to ESM */\r
- /* Need custom routine to handle this failure instead of the infinite loop */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear ESM group1 channel 21 flag */\r
- esmREG->ESTATUS1[0] = 0x00200000; \r
- \r
- /* disable TEST mode */\r
- canREG1->CTL = 0x00002800; \r
- }\r
-}\r
-\r
-/** @fn void can2ParityCheck(void)\r
-* @brief Routine to check CAN2 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check CAN2 RAM parity error detection and signaling mechanism\r
-*/\r
-void can2ParityCheck(void)\r
-{\r
- volatile unsigned int canread = 0;\r
-\r
- /* Disable parity, init mode, TEST mode */\r
- canREG2->CTL = 0x00001481; \r
-\r
- /* Enable RAM Direct Access mode */ \r
- canREG2->TEST = 0x00000200; \r
-\r
- /* flip the parity bit */\r
- canPARRAM2 ^= 0x00001000; \r
-\r
- /* Enable parity, disable init, still TEST mode */\r
- canREG2->CTL = 0x00002880; \r
-\r
- /* Read location with parity error */\r
- canread = canRAM2; \r
- \r
- /* check if ESM group1 channel 23 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x00800000)) \r
- {\r
- /* No DCAN2 RAM parity error was flagged to ESM */\r
- /* Need custom routine to handle this failure instead of the infinite loop */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear ESM group1 channel 23 flag */\r
- esmREG->ESTATUS1[0] = 0x00800000; \r
- \r
- /* disable TEST mode */\r
- canREG2->CTL = 0x00002800; \r
- }\r
-}\r
-\r
-/** @fn void can3ParityCheck(void)\r
-* @brief Routine to check CAN3 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check CAN3 RAM parity error detection and signaling mechanism\r
-*/\r
-void can3ParityCheck(void)\r
-{\r
- volatile unsigned int canread = 0;\r
-\r
- /* Disable parity, init mode, TEST mode */\r
- canREG3->CTL = 0x00001481; \r
-\r
- /* Enable RAM Direct Access mode */ \r
- canREG3->TEST = 0x00000200; \r
-\r
- /* flip the parity bit */\r
- canPARRAM3 ^= 0x00001000; \r
-\r
- /* Enable parity, disable init, still TEST mode */\r
- canREG3->CTL = 0x00002880; \r
-\r
- /* Read location with parity error */\r
- canread = canRAM3; \r
-\r
- /* check if ESM group1 channel 22 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x00400000)) \r
- {\r
- /* No DCAN3 RAM parity error was flagged to ESM */\r
- /* Need custom routine to handle this failure instead of the infinite loop */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear ESM group1 channel 22 flag */\r
- esmREG->ESTATUS1[0] = 0x00400000; \r
- \r
- /* disable TEST mode */\r
- canREG3->CTL = 0x00002800; \r
- }\r
-}\r
-\r
-/** @fn void mibspi1ParityCheck(void)\r
-* @brief Routine to check MIBSPI1 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check MIBSPI1 RAM parity error detection and signaling mechanism\r
-*/\r
-void mibspi1ParityCheck(void)\r
-{\r
- volatile unsigned int spiread = 0;\r
-\r
- /* enable multi-buffered mode */\r
- mibspiREG1->MIBSPIE = 0x1; \r
-\r
- /* enable parity error detection */\r
- mibspiREG1->EDEN = 0xA; \r
- \r
- /* enable parity test mode */\r
- mibspiREG1->PTESTEN = 1; \r
- \r
- /* flip bit 0 of the parity location */\r
- mibspiPARRAM1 ^= 0x1; \r
-\r
- /* disable parity test mode */\r
- mibspiREG1->PTESTEN = 0; \r
-\r
- /* read from MibSPI1 RAM to cause parity error */\r
- spiread = *(unsigned int *) mibspiRAM1; \r
-\r
- /* check if ESM group1 channel 17 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x20000)) \r
- {\r
- /* No MibSPI1 RAM parity error was flagged to ESM. */\r
- /* Need custom routine to handle this failure instead of the infinite loop */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear parity error flags */\r
- mibspiREG1->UERRSTAT = 0x3; \r
- \r
- /* clear ESM group1 channel 17 flag */\r
- esmREG->ESTATUS1[0] = 0x20000; \r
- \r
- /* enable parity test mode */\r
- mibspiREG1->PTESTEN = 1; \r
- \r
- /* Revert back to correct data, flip bit 0 of the parity location */\r
- mibspiPARRAM1 ^= 0x1; \r
- \r
- /* disable parity test mode */\r
- mibspiREG1->PTESTEN = 0; \r
- }\r
-}\r
-\r
-/** @fn void mibspi3ParityCheck(void)\r
-* @brief Routine to check MIBSPI3 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check MIBSPI3 RAM parity error detection and signaling mechanism\r
-*/\r
-void mibspi3ParityCheck(void)\r
-{\r
- volatile unsigned int spiread = 0;\r
-\r
- /* enable multi-buffered mode */\r
- mibspiREG3->MIBSPIE = 0x1; \r
-\r
- /* enable parity test mode */\r
- mibspiREG3->PTESTEN = 1; \r
- \r
- /* flip bit 0 of the parity location */\r
- mibspiPARRAM3 ^= 0x1; \r
-\r
- /* enable parity error detection */\r
- mibspiREG3->EDEN = 0xA; \r
- \r
- /* disable parity test mode */\r
- mibspiREG3->PTESTEN = 0; \r
-\r
- /* read from MibSPI3 RAM to cause parity error */\r
- spiread = *(unsigned int *) mibspiRAM3; \r
-\r
- /* check if ESM group1 channel 18 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x40000)) \r
- {\r
- /* No MibSPI3 RAM parity error was flagged to ESM. */\r
- /* Need custom routine to handle this failure instead of the infinite loop */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear parity error flags */\r
- mibspiREG3->UERRSTAT = 0x3; \r
- \r
- /* clear ESM group1 channel 18 flag */\r
- esmREG->ESTATUS1[0] = 0x40000; \r
- \r
- /* enable parity test mode */\r
- mibspiREG3->PTESTEN = 1; \r
- \r
- /* Revert back to correct data, flip bit 0 of the parity location */\r
- mibspiPARRAM3 ^= 0x1; \r
- \r
- /* disable parity test mode */\r
- mibspiREG3->PTESTEN = 0; \r
- }\r
-}\r
-\r
-/** @fn void mibspi5ParityCheck(void)\r
-* @brief Routine to check MIBSPI5 RAM parity error detection and signaling mechanism\r
-*\r
-* Routine to check MIBSPI5 RAM parity error detection and signaling mechanism\r
-*/\r
-void mibspi5ParityCheck(void)\r
-{\r
- volatile unsigned int spiread = 0;\r
-\r
- /* enable multi-buffered mode */\r
- mibspiREG5->MIBSPIE = 0x1; \r
-\r
- /* enable parity test mode */\r
- mibspiREG5->PTESTEN = 1; \r
- \r
- /* flip bit 0 of the parity location */ \r
- mibspiPARRAM5 ^= 0x1; \r
-\r
- /* enable parity error detection */\r
- mibspiREG5->EDEN = 0xA; \r
- \r
- /* disable parity test mode */\r
- mibspiREG5->PTESTEN = 0; \r
-\r
- /* read from MibSPI5 RAM to cause parity error */\r
- spiread = *(unsigned int *) mibspiRAM5; \r
-\r
- /* check if ESM group1 channel 24 is flagged */\r
- if (!(esmREG->ESTATUS1[0] & 0x01000000))\r
- {\r
- /* No MibSPI5 RAM parity error was flagged to ESM. */\r
- /* Need custom routine to handle this failure instead of the infinite loop */\r
- while(1);\r
- }\r
- else\r
- {\r
- /* clear parity error flags */\r
- mibspiREG5->UERRSTAT = 0x3; \r
- \r
- /* clear ESM group1 channel 24 flag */\r
- esmREG->ESTATUS1[0] = 0x01000000; \r
- \r
- /* enable parity test mode */\r
- mibspiREG5->PTESTEN = 1; \r
- \r
- /* Revert back to correct data, flip bit 0 of the parity location */\r
- mibspiPARRAM5 ^= 0x1; \r
- \r
- /* disable parity test mode */\r
- mibspiREG5->PTESTEN = 0; \r
- }\r
-}\r
+/** @file sys_selftest.c
+* @brief Selftest Source File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+* This file contains:
+* - Selftest API's
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_selftest.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void ccmSelfCheck(void)
+* @brief CCM module self check Driver
+*
+* This function self checks the CCM module.
+*/
+void ccmSelfCheck(void)
+{
+ /* Run a diagnostic check on the CCM-R4F module */
+ /* This step ensures that the CCM-R4F can actually indicate an error */
+
+ /* Configure CCM in self-test mode */
+ CCMKEYR = 0x6;
+ /* Wait for CCM self-test to complete */
+ while ((CCMSR & 0x100) != 0x100);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+ /* Check if there was an error during the self-test */
+ if ((CCMSR & 0x1) == 0x1)
+ {
+ /* STE is set */
+ ccmFail(0);
+ }
+ else
+ {
+ /* Check CCM-R4 self-test error flag by itself (without compare error) */
+
+ /* Configure CCM in self-test error-forcing mode */
+ CCMKEYR = 0xF;
+ if ((esmREG->ESTATUS1[0] & 0x80000000) != 0x80000000)
+ {
+ /* ESM flag is not set */
+ ccmFail(1);
+ }
+ else
+ {
+ /* clear ESM group1 channel 31 flag */
+ esmREG->ESTATUS1[0] = 0x80000000;
+
+ /* Configure CCM in error-forcing mode */
+ CCMKEYR = 0x9;
+
+ /* check if compare error flag is set */
+ if ((esmREG->ESTATUS1[1] & 0x4) != 0x4)
+ {
+ /* ESM flag is not set */
+ ccmFail(2);
+ }
+ else
+ {
+ /* clear ESM group2 channel 2 flag */
+ esmREG->ESTATUS1[1] = 0x4;
+
+ /* clear ESM group2 shadow status flag */
+ esmREG->ESTATUS5EMU = 0x4;
+
+ /* ESM self-test error needs to also be cleared */
+ esmREG->ESTATUS1[0] = 0x80000000;
+
+ /* Clear CCM-R4 CMPE flag */
+ CCMSR = 0x00010000;
+
+ /* Return CCM-R4 to lock-step mode */
+ CCMKEYR = 0x0;
+
+ /* The nERROR pin will become inactive once the LTC counter expires */
+ esmREG->KEY = 0x5;
+ }
+ }
+ }
+}
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+/** @fn void ccmFail(unsigned int x)
+* @brief CCM module fail service routine
+*
+* This function is called if CCM module selftest fail.
+*/
+void ccmFail(unsigned int x)
+{
+ if (x == 0)
+ {
+ /* CCM-R4 is not able to flag a compare error in self-test mode.
+ * Lock-step operation cannot be verified.
+ */
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+ }
+ else if (x == 1)
+ {
+ /* CCM-R4 self-test error flag is not set in ESM register.
+ * Could be due to a connection issue inside the part.
+ */
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+ }
+ else if (x == 2)
+ {
+ /* CCM-R4 compare error flag is not set in ESM.
+ * Lock-step operation cannot be verified.
+ */
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+ }
+}
+
+/** @fn void _memoryInit_(unsigned int ram)
+* @brief Memory Initialization Driver
+*
+* This function is called to perform Memory initialization of selected RAM's.
+*/
+void _memoryInit_(unsigned int ram)
+{
+ /* Enable Memory Hardware Initialization */
+ systemREG1->MINITGCR = 0xA;
+
+ /* Enable Memory Hardware Initialization for selected RAM's */
+ systemREG1->MSINENA = ram;
+
+ /* Wait until Memory Hardware Initialization complete */
+ while( systemREG1->MSTCGSTAT & 0x00000100 != 1);
+
+ /* Disable Memory Hardware Initialization */
+ systemREG1->MINITGCR = 0xA;
+}
+
+/** @fn void stcSelfCheck(void)
+* @brief STC module self check Driver
+*
+* This function is called to perform STC module self check.
+*/
+void stcSelfCheck(void)
+{
+ volatile int i = 0;
+
+ /* Run a diagnostic check on the CPU self-test controller */
+ /* First set up the STC clock divider as STC is only supported up to 90MHz */
+
+ /* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */
+ systemREG2->STCCLKDIV = 0x01000000;
+
+ /* Select one test interval, restart self-test next time, 0x00010001 */
+ stcREG->STCGCR0 = 0x00010001;
+
+ /* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */
+ stcREG->STCSCSCR = 0x1A;
+
+ /* Maximum time-out period */
+ stcREG->STCTPR = 0xFFFFFFFF;
+
+ /* wait for 16 VBUS clock cycles at least */
+ for (i=0; i<16; i++);
+
+ /* Enable self-test */
+ stcREG->STCGCR1 = 0xA;
+
+ /* wait for 16 VBUS clock cycles at least */
+ for (i=0; i<16; i++);
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+ /* Idle the CPU so that the self-test can start */
+ _gotoCPUIdle_();
+
+}
+
+/** @fn void cpuSelfTest(unsigned int no_of_intervals, unsigned int max_timeout, boolean_t restart_test)
+* @brief CPU self test Driver
+* @param[in] no_of_intervals - Number of Test Intervals to be
+* @param[in] max_timeout - Maximun Timeout to complete selected test Intervals
+* @param[in] restart_test - Restart the test from Interval 0 or Continue from where it stopped.
+*
+* This function is called to perfrom CPU self test using STC module.
+*/
+void cpuSelfTest(unsigned int no_of_intervals, unsigned int max_timeout, boolean_t restart_test)
+{
+ volatile int i = 0;
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ /* Run specified no of test intervals starting from interval 0 */
+ /* Start test from interval 0 or continue the test. */
+ stcREG->STCGCR0 = no_of_intervals << 16
+ | (unsigned int) restart_test;
+
+ /* Configure Maximum time-out period */
+ stcREG->STCTPR = max_timeout;
+
+ /* wait for 16 VBUS clock cycles at least */
+ for (i=0; i<16; i++);
+
+ /* Enable self-test */
+ stcREG->STCGCR1 = 0xA;
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+ /* Idle the CPU so that the self-test can start */
+
+ _gotoCPUIdle_();
+
+}
+
+/** @fn void pbistSelfCheck(void)
+* @brief PBIST self test Driver
+*
+* This function is called to perfrom PBIST self test.
+*/
+void pbistSelfCheck(void)
+{
+ int i = 0;
+ /* Run a diagnostic check on the memory self-test controller */
+ /* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */
+
+ /* PBIST ROM clock frequency = HCLK frequency /2 */
+ systemREG1->MSTGCR |= 0x00000100;
+
+ /* Enable PBIST controller */
+ systemREG1->MSINENA = 0x1;
+
+ /* clear MSTGENA field */
+ systemREG1->MSTGCR &= ~(0xF);
+
+ /* Enable PBIST self-test */
+ systemREG1->MSTGCR |= 0xA;
+
+ /* software loop to wait at least 32 VCLK cycles */
+ for (i = 0; i < 32; i++);
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+ /* Enable PBIST clocks and ROM clock */
+ pbistREG->PACT = 0x3;
+
+ /* Select algo#3, march13n to be run */
+ pbistREG->ALGO = 0x00000004;
+
+ /* Select RAM Group 1, which is actually the PBIST ROM */
+ pbistREG->RINFOL = 0x1;
+
+ /* ROM contents will not override ALGO and RINFOx settings */
+ pbistREG->OVER = 0x0;
+
+ /* Algorithm code is loaded from ROM */
+ pbistREG->ROM = 0x3;
+
+ /* Start PBIST */
+ pbistREG->DLR = 0x14;
+
+ /* wait until memory self-test done is indicated */
+ while ((systemREG1->MSTCGSTAT & 0x1) != 0x1);
+
+ /* Check for the failure */
+ if (((pbistREG->FSRF0 & 0x1) != 0x1) & ((pbistREG->FSRF1 & 0x1) != 0x1))
+ {
+ /* no failure was indicated even if the march13n algorithm was run on a ROM */
+ pbistSelfCheckFail();
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+ }
+ else
+ {
+ /* PBIST self-check has passed */
+
+ /* Disable PBIST clocks and ROM clock */
+ pbistREG->PACT = 0x0;
+
+ /* Disable PBIST */
+ systemREG1->MSTGCR &= ~(0xF);
+ systemREG1->MSTGCR |= 0x5;
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+ }
+}
+
+/** @fn void pbistSelfCheckFail(void)
+* @brief PBIST self test Driver failure service routine
+*
+* This function is called on PBIST self test failure.
+*/
+void pbistSelfCheckFail(void)
+{
+ /* The PBIST controller is not capable of reporting a failure.
+ * PBIST cannot be used to verify memory integrity.
+ * Need custom handler here.
+ */
+}
+
+/** @fn void pbistRun(unsigned int raminfoL, unsigned int algomask)
+* @brief CPU self test Driver
+* @param[in] raminfoL - Select the list of RAM to be tested.
+* @param[in] algomask - Select the list of Algorithm to be run.
+*
+* This function performs Memory Built-in Self test using PBIST module.
+*/
+void pbistRun(unsigned int raminfoL, unsigned int algomask)
+{
+ int i = 0;
+
+ /* PBIST ROM clock frequency = HCLK frequency /2 */
+ systemREG1->MSTGCR |= 0x00000100;
+
+ /* Enable PBIST controller */
+ systemREG1->MSINENA = 0x1;
+
+ /* clear MSTGENA field */
+ systemREG1->MSTGCR &= ~(0xF);
+
+ /* Enable PBIST self-test */
+ systemREG1->MSTGCR |= 0xA;
+
+ /* software loop to wait at least 32 VCLK cycles */
+ for (i = 0; i < 32; i++);
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ /* Enable PBIST clocks and ROM clock */
+ pbistREG->PACT = 0x3;
+
+ /* Select all algorithms to be tested */
+ pbistREG->ALGO = algomask;
+
+ /* Select RAM groups */
+ pbistREG->RINFOL = raminfoL;
+
+ /* Select all RAM groups */
+ pbistREG->RINFOU = 0x00000000;
+
+ /* ROM contents will not override RINFOx settings */
+ pbistREG->OVER = 0x0;
+
+ /* Algorithm code is loaded from ROM */
+ pbistREG->ROM = 0x3;
+
+ /* Start PBIST */
+ pbistREG->DLR = 0x14;
+}
+
+/** @fn void pbistStop(void)
+* @brief Routine to stop PBIST test enabled.
+*
+* This function is called to stop PBIST after test is performed.
+*/
+void pbistStop(void)
+{
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+ /* disable pbist clocks and ROM clock */
+ pbistREG->PACT = 0x0;
+ systemREG1->MSTGCR &= ~(0xF);
+ systemREG1->MSTGCR |= 0x5;
+}
+
+/** @fn boolean_t pbistIsTestCompleted(void)
+* @brief Checks to see if the PBIST test is completed.
+* @return 1 if PBIST test completed, otherwise 0.
+*
+* Checks to see if the PBIST test is completed.
+*/
+boolean_t pbistIsTestCompleted(void)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ return ((systemREG1->MSTCGSTAT & 0x1) != 0);
+}
+
+/** @fn boolean_t pbistIsTestPassed(void)
+* @brief Checks to see if the PBIST test is completed sucessfully.
+* @return 1 if PBIST test passed, otherwise 0.
+*
+* Checks to see if the PBIST test is completed sucessfully.
+*/
+boolean_t pbistIsTestPassed(void)
+{
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+ return ((pbistREG->FSRF0 || pbistREG->FSRF1) == 0);
+}
+
+/** @fn boolean_t pbistPortTestStatus(uint32_t port)
+* @brief Checks to see if the PBIST Port test is completed sucessfully.
+* @param[in] port - Select the port to get the status.
+* @return 1 if PBIST Port test completed sucessfully, otherwise 0.
+*
+* Checks to see if the selected PBIST Port test is completed sucessfully.
+*/
+boolean_t pbistPortTestStatus(uint32_t port)
+{
+ boolean_t status;
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ if(port == PBIST_PORT0)
+ {
+ status = (pbistREG->FSRF0 == 0);
+ }
+ else
+ {
+ status = (pbistREG->FSRF1 == 0);
+ }
+
+ return status;
+}
+
+/** @fn void efcCheck(void)
+* @brief EFUSE module self check Driver
+*
+* This function self checks the EFSUE module.
+*/
+void efcCheck(void)
+{
+ unsigned int efcStatus = 0;
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+ /* read the EFC Error Status Register */
+ efcStatus = efcREG->ERROR;
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ if (efcStatus == 0x0)
+ {
+ /* run stuck-at-zero test and check if it passed */
+ if (efcStuckZeroTest())
+ {
+ /* start EFC ECC logic self-test */
+ efcSelfTest();
+ }
+ else
+ {
+ /* EFC output is stuck-at-zero, device operation unreliable */
+ efcClass2Error();
+ }
+ }
+ /* EFC Error Register is not zero */
+ else
+ {
+ /* one-bit error detected during autoload */
+ if (efcStatus == 0x15)
+ {
+ /* start EFC ECC logic self-test */
+ efcSelfTest();
+ }
+ else
+ {
+ /* Some other EFC error was detected */
+ efcClass2Error();
+ }
+ }
+}
+
+/** @fn boolean_t efcStuckZeroTest(void)
+* @brief Checks to see if the EFUSE Stuck at zero test is completed sucessfully.
+* @return 1 if EFUSE Stuck at zero test completed, otherwise 0.
+*
+* Checks to see if the EFUSE Stuck at zero test is completed sucessfully.
+*/
+boolean_t efcStuckZeroTest(void)
+{
+ boolean_t result = FALSE;
+ unsigned int error_checks = EFC_INSTRUCTION_INFO_EN |
+ EFC_INSTRUCTION_ERROR_EN |
+ EFC_AUTOLOAD_ERROR_EN |
+ EFC_SELF_TEST_ERROR_EN ;
+
+ /* configure the output enable for auto load error , instruction info,
+ instruction error, and self test error using boundary register
+ and drive values one across all the errors */
+ efcREG->BOUNDARY = (OUTPUT_ENABLE | error_checks);
+
+ /* Read from the pin register. This register holds the current values
+ of above errors. This value should be 0x5c00.If not at least one of
+ the above errors is stuck at 0. */
+ if ((efcREG->PINS & 0x5C00) == 0x5C00)
+ {
+ /* check if the ESM group1 channels 40 is set and group3 channel 2 is set */
+ if (((esmREG->ESTATUS4[0] & 0x200) == 0x200) & ((esmREG->ESTATUS1[2] & 0x2) == 0x2))
+ {
+ /* stuck-at-zero test passed */
+ result = TRUE;
+ }
+ }
+
+ /* put the pins back low */
+ efcREG->BOUNDARY = OUTPUT_ENABLE;
+
+ /* clear group1 flags */
+ esmREG->ESTATUS4[0] = 0x300;
+
+ /* clear group3 flag */
+ esmREG->ESTATUS1[2] = 0x2;
+
+ /* The nERROR pin will become inactive once the LTC counter expires */
+ esmREG->KEY = 0x5;
+
+ return result;
+}
+
+/** @fn void efcSelfTest(void)
+* @brief EFUSE module self check Driver
+*
+* This function self checks the EFSUE module.
+*/
+void efcSelfTest(void)
+{
+ /* configure self-test cycles */
+ efcREG->SELF_TEST_CYCLES = 0x258;
+
+ /* configure self-test signature */
+ efcREG->SELF_TEST_SIGN = 0x5362F97F;
+
+ /* configure boundary register to start ECC self-test */
+ efcREG->BOUNDARY = 0x0000200F;
+}
+
+/** @fn boolean_t checkefcSelfTest(void)
+* @brief EFUSE module self check Driver
+*
+* This function self checks the EFSUE module.
+*/
+boolean_t checkefcSelfTest(void)
+{
+ boolean_t result = FALSE;
+
+ /* wait until EFC self-test is done */
+ while(!(efcREG->PINS & EFC_SELF_TEST_DONE));
+
+ /* check if EFC self-test error occurred */
+ if (!(efcREG->PINS & EFC_SELF_TEST_ERROR) & !(efcREG->ERROR & SELF_TEST_ERROR))
+ {
+ /* check if EFC self-test error is set */
+ if ((esmREG->ESTATUS4[0] & 0x100) != 0x100)
+ {
+ result = TRUE;
+ }
+ }
+ return result;
+}
+
+/** @fn void efcClass1Error(void)
+* @brief EFUSE Class1 Error service routine
+*
+* This function is called if EFC ECC logic self-test.
+*/
+void efcClass1Error(void)
+{
+ /* Autoload error was detected during device power-up, and device operation is not reliable. */
+ while(1);
+}
+
+/** @fn void efcClass2Error(void)
+* @brief EFUSE Class2 Error service routine
+*
+* This function is called if EFC output is stuck-at-zero.
+*/
+void efcClass2Error(void)
+{
+ /* The ECC logic inside the eFuse controller is not operational. Device operation is not reliable. */
+ while(1);
+}
+
+/** @fn void fmcBus2Check(void)
+* @brief Self Check Flash Bus2 Interface
+*
+* This function self checks Flash Bus2 Interface
+*/
+void fmcBus2Check(void)
+{
+ /* enable ECC logic inside FMC */
+ flashWREG->FEDACCTRL1 = 0x000A060A;
+
+ if (esmREG->ESTATUS1[0] & 0x40)
+ {
+ /* a 1-bit error was detected during flash OTP read by flash module
+ run a self-check on ECC logic inside FMC */
+
+ /* clear ESM group1 channel 6 flag */
+ esmREG->ESTATUS1[0] = 0x40;
+
+ fmcECCcheck();
+ }
+
+ /* no 2-bit or 1-bit error detected during power-up */
+ else
+ {
+ fmcECCcheck();
+ }
+}
+
+/** @fn void fmcECCcheck(void)
+* @brief Check Flash ECC Single Bit and multi Bit errors detection logic.
+*
+* This function Checks Flash ECC Single Bit and multi Bit errors detection logic.
+*/
+void fmcECCcheck(void)
+{
+ volatile unsigned int otpread;
+ volatile unsigned int temp;
+
+ /* read location with deliberate 1-bit error */
+ otpread = flash1bitError;
+ if (esmREG->ESTATUS1[0] & 0x40)
+ {
+ /* 1-bit failure was indicated and corrected */
+ flashWREG->FEDACSTATUS = 0x00010006;
+
+ /* clear ESM group1 channel 6 flag */
+ esmREG->ESTATUS1[0] = 0x40;
+
+ /* read location with deliberate 2-bit error */
+ otpread = flash2bitError;
+ if (esmREG->ESTATUS1[2] & 0x80)
+ {
+ /* 2-bit failure was detected correctly */
+ temp = flashWREG->FUNCERRADD;
+ flashWREG->FEDACSTATUS = 0x00020100;
+
+ /* clear ESM group3 channel 7 */
+ esmREG->ESTATUS1[2] = 0x80;
+
+ /* The nERROR pin will become inactive once the LTC counter expires */
+ esmREG->KEY = 0x5;
+
+ }
+ else
+ {
+ /* ECC logic inside FMC cannot detect 2-bit error */
+ fmcClass2Error();
+ }
+ }
+ else
+ {
+ /* ECC logic inside FMC cannot detect 1-bit error */
+ fmcClass2Error();
+ }
+}
+
+/** @fn void fmcClass1Error(void)
+* @brief Flash Multi bit ECC error service routine detected during reset configuration.
+*
+* This function is called if Flash Multi bit ECC error detected during reset configuration.
+*/
+void fmcClass1Error(void)
+{
+ /* there was a multi-bit error detected during the reset configuration word read from the OTP */
+ /* This affects the device power domains, endianness, and exception handling ISA */
+ /* Device operation is not reliable. */
+ while(1);
+}
+
+/** @fn void fmcClass2Error(void)
+* @brief Flash OTP or EEPROM read Multi bit ECC error service routine
+*
+* This function is called if Flash OTP or EEPROM read Multi bit ECC error detected.
+*/
+void fmcClass2Error(void)
+{
+ /* The ECC logic inside FMC used to protect against 1-bit and 2-bit errors in OTP and EEPROM banks */
+ /* is not operational. Device operation is not reliable. */
+ while(1);
+}
+
+/** @fn void checkB0RAMECC(void)
+* @brief Check TCRAM1 ECC error detection logic.
+*
+* This function checks TCRAM1 ECC error detection logic.
+*/
+void checkB0RAMECC(void)
+{
+ volatile unsigned int ramread = 0;
+
+ /* enable writes to ECC RAM, enable ECC error response */
+ tcram1REG->RAMCTRL = 0x0005010A;
+ tcram2REG->RAMCTRL = 0x0005010A;
+
+ /* the first 1-bit error will cause an error response */
+ tcram1REG->RAMTHRESHOLD = 0x1;
+ tcram2REG->RAMTHRESHOLD = 0x1;
+
+ /* allow SERR to be reported to ESM */
+ tcram1REG->RAMINTCTRL = 0x1;
+ tcram2REG->RAMINTCTRL = 0x1;
+
+ /* cause a 1-bit ECC error */
+ tcramA1bitError ^= 0x1;
+
+ /* disable writes to ECC RAM */
+ tcram1REG->RAMCTRL = 0x0005000A;
+ tcram2REG->RAMCTRL = 0x0005000A;
+
+ /* read from location with 1-bit ECC error */
+ ramread = tcramA1bit;
+
+ /* SERR not set in TCRAM1 or TCRAM2 modules */
+ if (!((tcram1REG->RAMERRSTATUS & 1) || (tcram2REG->RAMERRSTATUS & 1)))
+ {
+ /* TCRAM module does not reflect 1-bit error reported by CPU */
+ tcramClass2Error();
+ }
+ else
+ {
+ /* clear SERR flag */
+ tcram1REG->RAMERRSTATUS = 0x1;
+ tcram2REG->RAMERRSTATUS = 0x1;
+
+ /* clear status flags for ESM group1 channels 26 and 28 */
+ esmREG->ESTATUS1[0] = 0x14000000;
+ }
+
+ /* enable writes to ECC RAM, enable ECC error response */
+ tcram1REG->RAMCTRL = 0x0005010A;
+ tcram2REG->RAMCTRL = 0x0005010A;
+
+ /* cause a 2-bit ECC error */
+ tcramA2bitError ^= 0x3;
+ ramread = tcram1REG->RAMCTRL;
+ ramread = tcram2REG->RAMCTRL;
+
+ /* read from location with 2-bit ECC error this will cause a data abort to be generated */
+ ramread = tcramA2bit;
+}
+
+/** @fn void checkB1RAMECC(void)
+* @brief Check TCRAM2 ECC error detection logic.
+*
+* This function checks TCRAM2 ECC error detection logic.
+*/
+void checkB1RAMECC(void)
+{
+ volatile unsigned int ramread = 0;
+
+ /* enable writes to ECC RAM, enable ECC error response */
+ tcram1REG->RAMCTRL = 0x0005010A;
+ tcram2REG->RAMCTRL = 0x0005010A;
+
+ /* the first 1-bit error will cause an error response */
+ tcram1REG->RAMTHRESHOLD = 0x1;
+ tcram2REG->RAMTHRESHOLD = 0x1;
+
+ /* allow SERR to be reported to ESM */
+ tcram1REG->RAMINTCTRL = 0x1;
+ tcram2REG->RAMINTCTRL = 0x1;
+
+ /* cause a 1-bit ECC error */
+ tcramB1bitError ^= 0x1;
+
+ /* disable writes to ECC RAM */
+ tcram1REG->RAMCTRL = 0x0005000A;
+ tcram2REG->RAMCTRL = 0x0005000A;
+
+ /* read from location with 1-bit ECC error */
+ ramread = tcramB1bit;
+
+ /* SERR not set in TCRAM1 or TCRAM2 modules */
+ if (!((tcram1REG->RAMERRSTATUS & 1) || (tcram2REG->RAMERRSTATUS & 1)))
+ {
+ /* TCRAM module does not reflect 1-bit error reported by CPU */
+ tcramClass2Error();
+ }
+ else
+ {
+ /* clear SERR flag */
+ tcram1REG->RAMERRSTATUS = 0x1;
+ tcram2REG->RAMERRSTATUS = 0x1;
+
+ /* clear status flags for ESM group1 channels 26 and 28 */
+ esmREG->ESTATUS1[0] = 0x14000000;
+ }
+
+ /* enable writes to ECC RAM, enable ECC error response */
+ tcram1REG->RAMCTRL = 0x0005010A;
+ tcram2REG->RAMCTRL = 0x0005010A;
+
+ /* cause a 2-bit ECC error */
+ tcramB2bitError ^= 0x3;
+
+ /* disable writes to ECC RAM */
+ tcram1REG->RAMCTRL = 0x0005000A;
+ tcram2REG->RAMCTRL = 0x0005000A;
+}
+
+/** @fn void tcramClass1Error(void)
+* @brief Error service routine called if TCRAM module cannot capture 2-bit error.
+*
+* Error service routine called if TCRAM module cannot respond to 2-bit error.
+*/
+void tcramClass1Error(void)
+{
+ /* TCRAM module is not capable of responding to 2-bit error indicated by CPU.
+ * Device operation is not reliable and not recommended.
+ */
+ while(1);
+}
+
+/** @fn void tcramClass2Error(void)
+* @brief Error service routine called if TCRAM module cannot capture 1-bit error.
+*
+* Error service routine called if TCRAM module cannot respond to 1-bit error.
+*/
+void tcramClass2Error(void)
+{
+ /* TCRAM module is not capable of responding to 1-bit error indicated by CPU.
+ * Device operation is possible, but is prone to future multi-bit errors not being detected.
+ * Need custom handler here instead of the infinite loop.
+ */
+ while(1);
+}
+
+/** @fn void checkFlashECC(void)
+* @brief Check Flash ECC error detection logic.
+*
+* This function checks Flash ECC error detection logic.
+*/
+void checkFlashECC(void)
+{
+ /* Routine to check operation of ECC logic inside CPU for accesses to program flash */
+ volatile unsigned int flashread = 0;
+
+ /* Flash Module ECC Response enabled */
+ flashWREG->FEDACCTRL1 = 0x000A060A;
+
+ /* Enable diagnostic mode and select diag mode 7 */
+ flashWREG->FDIAGCTRL = 0x00050007;
+
+ /* Select ECC diagnostic mode, single-bit to be corrupted */
+ flashWREG->FPAROVR = 0x00005401;
+
+ /* Set the trigger for the diagnostic mode */
+ flashWREG->FDIAGCTRL |= 0x01000000;
+
+ /* read a flash location from the mirrored memory map */
+ flashread = flashBadECC;
+
+ /* disable diagnostic mode */
+ flashWREG->FDIAGCTRL = 0x000A0007;
+
+ /* this will have caused a single-bit error to be generated and corrected by CPU */
+ /* single-bit error not captured in flash module */
+ if (!(flashWREG->FEDACSTATUS & 0x2))
+ {
+ flashClass2Error();
+ }
+ else
+ {
+ /* clear single-bit error flag */
+ flashWREG->FEDACSTATUS = 0x2;
+
+ /* clear ESM flag */
+ esmREG->ESTATUS1[0] = 0x40;
+
+ /* Enable diagnostic mode and select diag mode 7 */
+ flashWREG->FDIAGCTRL = 0x00050007;
+
+ /* Select ECC diagnostic mode, two bits of ECC to be corrupted */
+ flashWREG->FPAROVR = 0x00005A03;
+
+ /* Set the trigger for the diagnostic mode */
+ flashWREG->FDIAGCTRL |= 0x01000000;
+
+ /* read from flash location from mirrored memory map this will cause a data abort */
+ flashread = flashBadECC;
+ }
+
+}
+
+/** @fn void flashClass1Error(void)
+* @brief Error service routine called if Flash module cannot capture 2-bit error.
+*
+* Error service routine called if Flash module cannot capture 2-bit error.
+*/
+void flashClass1Error(void)
+{
+ /* Flash module not able to capture 2-bit error from CPU.
+ * Device operation not reliable.
+ */
+ while(1);
+
+}
+
+/** @fn void flashClass2Error(void)
+* @brief Error service routine called if Flash module cannot capture 1-bit error.
+*
+* Error service routine called if Flash module cannot capture 1-bit error.
+*/
+void flashClass2Error(void)
+{
+ /* Flash module not able to capture 1-bit error from CPU.
+ * Device operation possible if this weakness in diagnostic is okay.
+ */
+}
+
+/** @fn void custom_dabort(void)
+* @brief Custom Data abort routine for the application.
+*
+* Custom Data abort routine for the application.
+*/
+void custom_dabort(void)
+{
+ /* Need custom data abort handler here.
+ * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC logic.
+ */
+}
+
+/** @fn void stcSelfCheckFail(void)
+* @brief STC Self test check fail service routine
+*
+* This function is called if STC Self test check fail.
+*/
+void stcSelfCheckFail(void)
+{
+ /* CPU self-test controller's own self-test failed.
+ * It is not possible to verify that STC is capable of indicating a CPU self-test error.
+ * It is not recommended to continue operation.
+ */
+ while(1);
+}
+
+/** @fn void cpuSelfTestFail(void)
+* @brief CPU Self test check fail service routine
+*
+* This function is called if CPU Self test check fail.
+*/
+void cpuSelfTestFail(void)
+{
+ /* CPU self-test has failed.
+ * CPU operation is not reliable.
+ */
+ while(1);
+}
+
+
+/** @fn void vimParityCheck(void)
+* @brief Routine to check VIM RAM parity error detection and signaling mechanism
+*
+* Routine to check VIM RAM parity error detection and signaling mechanism
+*/
+void vimParityCheck(void)
+{
+ volatile unsigned int vimramread = 0;
+
+ /* Enable parity checking and parity test mode */
+ VIM_PARCTL = 0x0000010A;
+
+ /* flip a bit in the VIM RAM parity location */
+ VIMRAMPARLOC ^= 0x1;
+
+ /* disable parity test mode */
+ VIM_PARCTL = 0x0000000A;
+
+ /* cause parity error */
+ vimramread = VIMRAMLOC;
+
+ /* check if ESM group1 channel 15 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x8000))
+ {
+ /* VIM RAM parity error was not flagged to ESM. */
+ /* Need custom routine to handle this failure instead of the infinite loop. */
+ while(1);
+ }
+ else
+ {
+ /* clear VIM RAM parity error flag in VIM */
+ VIM_PARFLG = 0x1;
+
+ /* clear ESM group1 channel 15 flag */
+ esmREG->ESTATUS1[0] = 0x8000;
+ }
+}
+
+/** @fn void dmaParityCheck(void)
+* @brief Routine to check DMA control packet RAM parity error detection and signaling mechanism
+*
+* Routine to check DMA control packet RAM parity error detection and signaling mechanism
+*/
+void dmaParityCheck(void)
+{
+ volatile unsigned int dmaread = 0;
+
+ /* Enable parity checking and parity test mode */
+ DMA_PARCR = 0x0000010A;
+
+ /* Flip a bit in DMA RAM parity location */
+ DMARAMPARLOC ^= 0x1;
+
+ /* Disable parity test mode */
+ DMA_PARCR = 0x0000000A;
+
+ /* Cause parity error */
+ dmaread = DMARAMLOC;
+
+ /* Check if ESM group1 channel 3 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x8))
+ {
+ /* DMA RAM parity error was not flagged to ESM. */
+ /* Need custom routine to handle this failure instead of the infinite loop. */
+ while(1);
+ }
+ else
+ {
+ /* clear DMA parity error flag in DMA */
+ DMA_PARADDR = 0x01000000;
+
+ /* clear ESM group1 channel 3 flag */
+ esmREG->ESTATUS1[0] = 0x8;
+ }
+
+}
+
+/** @fn void het1ParityCheck(void)
+* @brief Routine to check HET1 RAM parity error detection and signaling mechanism
+*
+* Routine to check HET1 RAM parity error detection and signaling mechanism
+*/
+void het1ParityCheck(void)
+{
+ volatile unsigned int nhetread = 0;
+
+ /* Set TEST mode and enable parity checking */
+ hetREG1->PCREG = 0x0000010A;
+
+ /* flip parity bit */
+ NHET1RAMPARLOC ^= 0x1;
+
+ /* Disable TEST mode */
+ hetREG1->PCREG = 0x0000000A;
+
+ /* read to cause parity error */
+ nhetread = NHET1RAMLOC;
+
+ /* check if ESM group1 channel 7 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x80))
+ {
+ /* NHET1 RAM parity error was not flagged to ESM. */
+ /* Need custom routine to handle this failure instead of the infinite loop. */
+ while(1);
+ }
+ else
+ {
+ /* clear ESM group1 channel 7 flag */
+ esmREG->ESTATUS1[0] = 0x80;
+ }
+}
+
+/** @fn void htu1ParityCheck(void)
+* @brief Routine to check HTU1 RAM parity error detection and signaling mechanism
+*
+* Routine to check HTU1 RAM parity error detection and signaling mechanism
+*/
+void htu1ParityCheck(void)
+{
+ volatile unsigned int hturead = 0;
+ /* Enable parity and TEST mode */
+ htuREG1->PCR = 0x0000010A;
+
+ /* flip parity bit */
+ HTU1PARLOC ^= 0x1;
+
+ /* Disable parity RAM test mode */
+ htuREG1->PCR = 0x0000000A;
+
+ /* read to cause parity error */
+ hturead = HTU1RAMLOC;
+
+ /* check if ESM group1 channel 8 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x100))
+ {
+ /* HTU1 RAM parity error was not flagged to ESM. */
+ /* Need custom routine to handle this failure instead of the infinite loop. */
+ while(1);
+ }
+ else
+ {
+ /* Clear HTU parity error flag */
+ htuREG1->PAR = 0x00010000;
+ esmREG->ESTATUS1[0] = 0x100;
+ }
+}
+
+/** @fn void het2ParityCheck(void)
+* @brief Routine to check HET2 RAM parity error detection and signaling mechanism
+*
+* Routine to check HET2 RAM parity error detection and signaling mechanism
+*/
+void het2ParityCheck(void)
+{
+ volatile unsigned int nhetread = 0;
+
+ /* Set TEST mode and enable parity checking */
+ hetREG2->PCREG = 0x0000010A;
+
+ /* flip parity bit */
+ NHET2RAMPARLOC ^= 0x1;
+
+ /* Disable TEST mode */
+ hetREG2->PCREG = 0x0000000A;
+
+ /* read to cause parity error */
+ nhetread = NHET2RAMLOC;
+
+ /* check if ESM group1 channel 7 or 34 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x80) && !(esmREG->ESTATUS4[0] & 0x4))
+ {
+ /* NHET2 RAM parity error was not flagged to ESM. */
+ /* Need custom routine to handle this failure instead of the infinite loop. */
+ while(1);
+ }
+ else
+ {
+ /* clear ESM group1 channel 7 flag */
+ esmREG->ESTATUS1[0] = 0x80;
+
+ /* clear ESM group1 channel 34 flag */
+ esmREG->ESTATUS4[0] = 0x4;
+ }
+}
+
+/** @fn void htu2ParityCheck(void)
+* @brief Routine to check HTU2 RAM parity error detection and signaling mechanism
+*
+* Routine to check HTU2 RAM parity error detection and signaling mechanism
+*/
+void htu2ParityCheck(void)
+{
+ volatile unsigned int hturead = 0;
+
+ /* Enable parity and TEST mode */
+ htuREG2->PCR = 0x0000010A;
+
+ /* flip parity bit */
+ HTU2PARLOC ^= 0x1;
+
+ /* Disable parity RAM test mode */
+ htuREG2->PCR = 0x0000000A;
+
+ /* read to cause parity error */
+ hturead = HTU2RAMLOC;
+
+ /* check if ESM group1 channel 8 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x100))
+ {
+ /* HTU2 RAM parity error was not flagged to ESM. */
+ /* Need custom routine to handle this failure instead of the infinite loop. */
+ while(1);
+ }
+ else
+ {
+ /* Clear HTU parity error flag */
+ htuREG2->PAR = 0x00010000;
+ esmREG->ESTATUS1[0] = 0x100;
+ }
+}
+
+/** @fn void adc1ParityCheck(void)
+* @brief Routine to check ADC1 RAM parity error detection and signaling mechanism
+*
+* Routine to check ADC1 RAM parity error detection and signaling mechanism
+*/
+void adc1ParityCheck(void)
+{
+ volatile unsigned int adcramread = 0;
+
+ /* Set the TEST bit in the PARCR and enable parity checking */
+ adcREG1->PARCR = 0x10A;
+
+ /* Invert the parity bits inside the ADC1 RAM's first location */
+ adcPARRAM1 = ~(adcPARRAM1);
+
+ /* clear the TEST bit */
+ adcREG1->PARCR = 0x00A;
+
+ /* This read is expected to trigger a parity error */
+ adcramread = adcRAM1;
+
+ /* Check for ESM group1 channel 19 to be flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x80000))
+ {
+ /* no ADC1 RAM parity error was flagged to ESM */
+ /* Need custom routine to handle this failure instead of the infinite loop */
+ while(1);
+ }
+ else
+ {
+ /* clear ADC1 RAM parity error flag */
+ esmREG->ESTATUS1[0] = 0x80000;
+ }
+}
+
+/** @fn void adc2ParityCheck(void)
+* @brief Routine to check ADC2 RAM parity error detection and signaling mechanism
+*
+* Routine to check ADC2 RAM parity error detection and signaling mechanism
+*/
+void adc2ParityCheck(void)
+{
+ volatile unsigned int adcramread = 0;
+
+ /* Set the TEST bit in the PARCR and enable parity checking */
+ adcREG2->PARCR = 0x10A;
+
+ /* Invert the parity bits inside the ADC2 RAM's first location */
+ adcPARRAM2 = ~(adcPARRAM2);
+
+ /* clear the TEST bit */
+ adcREG2->PARCR = 0x00A;
+
+ /* This read is expected to trigger a parity error */
+ adcramread = adcRAM2;
+
+ /* Check for ESM group1 channel 1 to be flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x2))
+ {
+ /* no ADC2 RAM parity error was flagged to ESM */
+ /* Need custom routine to handle this failure instead of the infinite loop */
+ while(1);
+ }
+ else
+ {
+ /* clear ADC2 RAM parity error flag */
+ esmREG->ESTATUS1[0] = 0x2;
+ }
+}
+
+/** @fn void can1ParityCheck(void)
+* @brief Routine to check CAN1 RAM parity error detection and signaling mechanism
+*
+* Routine to check CAN1 RAM parity error detection and signaling mechanism
+*/
+void can1ParityCheck(void)
+{
+ volatile unsigned int canread = 0;
+
+ /* Disable parity, init mode, TEST mode */
+ canREG1->CTL = 0x00001481;
+
+ /* Enable RAM Direct Access mode */
+ canREG1->TEST = 0x00000200;
+
+ /* flip the parity bit */
+ canPARRAM1 ^= 0x00001000;
+
+ /* Enable parity, disable init, still TEST mode */
+ canREG1->CTL = 0x00002880;
+
+ /* Read location with parity error */
+ canread = canRAM1;
+
+ /* check if ESM group1 channel 21 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x00200000))
+ {
+ /* No DCAN1 RAM parity error was flagged to ESM */
+ /* Need custom routine to handle this failure instead of the infinite loop */
+ while(1);
+ }
+ else
+ {
+ /* clear ESM group1 channel 21 flag */
+ esmREG->ESTATUS1[0] = 0x00200000;
+
+ /* disable TEST mode */
+ canREG1->CTL = 0x00002800;
+ }
+}
+
+/** @fn void can2ParityCheck(void)
+* @brief Routine to check CAN2 RAM parity error detection and signaling mechanism
+*
+* Routine to check CAN2 RAM parity error detection and signaling mechanism
+*/
+void can2ParityCheck(void)
+{
+ volatile unsigned int canread = 0;
+
+ /* Disable parity, init mode, TEST mode */
+ canREG2->CTL = 0x00001481;
+
+ /* Enable RAM Direct Access mode */
+ canREG2->TEST = 0x00000200;
+
+ /* flip the parity bit */
+ canPARRAM2 ^= 0x00001000;
+
+ /* Enable parity, disable init, still TEST mode */
+ canREG2->CTL = 0x00002880;
+
+ /* Read location with parity error */
+ canread = canRAM2;
+
+ /* check if ESM group1 channel 23 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x00800000))
+ {
+ /* No DCAN2 RAM parity error was flagged to ESM */
+ /* Need custom routine to handle this failure instead of the infinite loop */
+ while(1);
+ }
+ else
+ {
+ /* clear ESM group1 channel 23 flag */
+ esmREG->ESTATUS1[0] = 0x00800000;
+
+ /* disable TEST mode */
+ canREG2->CTL = 0x00002800;
+ }
+}
+
+/** @fn void can3ParityCheck(void)
+* @brief Routine to check CAN3 RAM parity error detection and signaling mechanism
+*
+* Routine to check CAN3 RAM parity error detection and signaling mechanism
+*/
+void can3ParityCheck(void)
+{
+ volatile unsigned int canread = 0;
+
+ /* Disable parity, init mode, TEST mode */
+ canREG3->CTL = 0x00001481;
+
+ /* Enable RAM Direct Access mode */
+ canREG3->TEST = 0x00000200;
+
+ /* flip the parity bit */
+ canPARRAM3 ^= 0x00001000;
+
+ /* Enable parity, disable init, still TEST mode */
+ canREG3->CTL = 0x00002880;
+
+ /* Read location with parity error */
+ canread = canRAM3;
+
+ /* check if ESM group1 channel 22 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x00400000))
+ {
+ /* No DCAN3 RAM parity error was flagged to ESM */
+ /* Need custom routine to handle this failure instead of the infinite loop */
+ while(1);
+ }
+ else
+ {
+ /* clear ESM group1 channel 22 flag */
+ esmREG->ESTATUS1[0] = 0x00400000;
+
+ /* disable TEST mode */
+ canREG3->CTL = 0x00002800;
+ }
+}
+
+/** @fn void mibspi1ParityCheck(void)
+* @brief Routine to check MIBSPI1 RAM parity error detection and signaling mechanism
+*
+* Routine to check MIBSPI1 RAM parity error detection and signaling mechanism
+*/
+void mibspi1ParityCheck(void)
+{
+ volatile unsigned int spiread = 0;
+
+ /* enable multi-buffered mode */
+ mibspiREG1->MIBSPIE = 0x1;
+
+ /* enable parity error detection */
+ mibspiREG1->EDEN = 0xA;
+
+ /* enable parity test mode */
+ mibspiREG1->PTESTEN = 1;
+
+ /* flip bit 0 of the parity location */
+ mibspiPARRAM1 ^= 0x1;
+
+ /* disable parity test mode */
+ mibspiREG1->PTESTEN = 0;
+
+ /* read from MibSPI1 RAM to cause parity error */
+ spiread = *(unsigned int *) mibspiRAM1;
+
+ /* check if ESM group1 channel 17 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x20000))
+ {
+ /* No MibSPI1 RAM parity error was flagged to ESM. */
+ /* Need custom routine to handle this failure instead of the infinite loop */
+ while(1);
+ }
+ else
+ {
+ /* clear parity error flags */
+ mibspiREG1->UERRSTAT = 0x3;
+
+ /* clear ESM group1 channel 17 flag */
+ esmREG->ESTATUS1[0] = 0x20000;
+
+ /* enable parity test mode */
+ mibspiREG1->PTESTEN = 1;
+
+ /* Revert back to correct data, flip bit 0 of the parity location */
+ mibspiPARRAM1 ^= 0x1;
+
+ /* disable parity test mode */
+ mibspiREG1->PTESTEN = 0;
+ }
+}
+
+/** @fn void mibspi3ParityCheck(void)
+* @brief Routine to check MIBSPI3 RAM parity error detection and signaling mechanism
+*
+* Routine to check MIBSPI3 RAM parity error detection and signaling mechanism
+*/
+void mibspi3ParityCheck(void)
+{
+ volatile unsigned int spiread = 0;
+
+ /* enable multi-buffered mode */
+ mibspiREG3->MIBSPIE = 0x1;
+
+ /* enable parity test mode */
+ mibspiREG3->PTESTEN = 1;
+
+ /* flip bit 0 of the parity location */
+ mibspiPARRAM3 ^= 0x1;
+
+ /* enable parity error detection */
+ mibspiREG3->EDEN = 0xA;
+
+ /* disable parity test mode */
+ mibspiREG3->PTESTEN = 0;
+
+ /* read from MibSPI3 RAM to cause parity error */
+ spiread = *(unsigned int *) mibspiRAM3;
+
+ /* check if ESM group1 channel 18 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x40000))
+ {
+ /* No MibSPI3 RAM parity error was flagged to ESM. */
+ /* Need custom routine to handle this failure instead of the infinite loop */
+ while(1);
+ }
+ else
+ {
+ /* clear parity error flags */
+ mibspiREG3->UERRSTAT = 0x3;
+
+ /* clear ESM group1 channel 18 flag */
+ esmREG->ESTATUS1[0] = 0x40000;
+
+ /* enable parity test mode */
+ mibspiREG3->PTESTEN = 1;
+
+ /* Revert back to correct data, flip bit 0 of the parity location */
+ mibspiPARRAM3 ^= 0x1;
+
+ /* disable parity test mode */
+ mibspiREG3->PTESTEN = 0;
+ }
+}
+
+/** @fn void mibspi5ParityCheck(void)
+* @brief Routine to check MIBSPI5 RAM parity error detection and signaling mechanism
+*
+* Routine to check MIBSPI5 RAM parity error detection and signaling mechanism
+*/
+void mibspi5ParityCheck(void)
+{
+ volatile unsigned int spiread = 0;
+
+ /* enable multi-buffered mode */
+ mibspiREG5->MIBSPIE = 0x1;
+
+ /* enable parity test mode */
+ mibspiREG5->PTESTEN = 1;
+
+ /* flip bit 0 of the parity location */
+ mibspiPARRAM5 ^= 0x1;
+
+ /* enable parity error detection */
+ mibspiREG5->EDEN = 0xA;
+
+ /* disable parity test mode */
+ mibspiREG5->PTESTEN = 0;
+
+ /* read from MibSPI5 RAM to cause parity error */
+ spiread = *(unsigned int *) mibspiRAM5;
+
+ /* check if ESM group1 channel 24 is flagged */
+ if (!(esmREG->ESTATUS1[0] & 0x01000000))
+ {
+ /* No MibSPI5 RAM parity error was flagged to ESM. */
+ /* Need custom routine to handle this failure instead of the infinite loop */
+ while(1);
+ }
+ else
+ {
+ /* clear parity error flags */
+ mibspiREG5->UERRSTAT = 0x3;
+
+ /* clear ESM group1 channel 24 flag */
+ esmREG->ESTATUS1[0] = 0x01000000;
+
+ /* enable parity test mode */
+ mibspiREG5->PTESTEN = 1;
+
+ /* Revert back to correct data, flip bit 0 of the parity location */
+ mibspiPARRAM5 ^= 0x1;
+
+ /* disable parity test mode */
+ mibspiREG5->PTESTEN = 0;
+ }
+}
-/** @file sys_startup.c\r
-* @brief Startup Source File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-* This file contains:\r
-* - Include Files\r
-* - Type Definitions\r
-* - External Functions\r
-* - VIM RAM Setup\r
-* - Startup Routine\r
-* .\r
-* which are relevant for the Startup.\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-\r
-/* Include Files */\r
-\r
-#include "sys_common.h"\r
-#include "system.h"\r
-#include "sys_vim.h"\r
-#include "sys_core.h"\r
-#include "sys_selftest.h"\r
-#include "ti_drv_esm.h"\r
-\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-\r
-/* Type Definitions */\r
-\r
-typedef void (*handler_fptr)(const uint8_t *in, uint8_t *out);\r
-\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
-\r
-/* External Functions */\r
-\r
-#pragma WEAK(__TI_Handler_Table_Base)\r
-#pragma WEAK(__TI_Handler_Table_Limit)\r
-#pragma WEAK(__TI_CINIT_Base)\r
-#pragma WEAK(__TI_CINIT_Limit)\r
-\r
-extern uint32_t __TI_Handler_Table_Base;\r
-extern uint32_t __TI_Handler_Table_Limit;\r
-extern uint32_t __TI_CINIT_Base;\r
-extern uint32_t __TI_CINIT_Limit;\r
-extern uint32_t __TI_PINIT_Base;\r
-extern uint32_t __TI_PINIT_Limit;\r
-extern uint32_t * __binit__;\r
-\r
-extern void main(void);\r
-extern void exit(void);\r
-\r
-extern void muxInit(void);\r
-\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-\r
-\r
-/* Vim Ram Definition */\r
-/** @struct vimRam\r
-* @brief Vim Ram Definition\r
-*\r
-* This type is used to access the Vim Ram.\r
-*/\r
-/** @typedef vimRAM_t\r
-* @brief Vim Ram Type Definition\r
-*\r
-* This type is used to access the Vim Ram.\r
-*/\r
-typedef volatile struct vimRam\r
-{\r
- t_isrFuncPTR ISR[VIM_CHANNELS + 1];\r
-} vimRAM_t;\r
-\r
-#define vimRAM ((vimRAM_t *)0xFFF82000U)\r
-\r
-static const t_isrFuncPTR s_vim_init[] =\r
-{\r
- &phantomInterrupt,\r
- &esmHighInterrupt, // 0\r
- &phantomInterrupt,\r
- &vPreemptiveTick,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 5\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 10\r
- &phantomInterrupt,\r
- &mibspi1HighLevelInterrupt,\r
- &linHighLevelInterrupt,\r
- &phantomInterrupt,\r
- &adc1Group1Interrupt, // 15\r
- &can1HighLevelInterrupt,\r
- &spi2HighLevelInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 20\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 25\r
- &mibspi1LowLevelInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &spi2LowLevelInterrupt, // 30\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &can2HighLevelInterrupt, // 35\r
- &phantomInterrupt,\r
- &mibspi3HighInterruptLevel,\r
- &mibspi3LowLevelInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 40\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &can3HighLevelInterrupt, // 45\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &spi4HighLevelInterrupt,\r
- &phantomInterrupt, // 50\r
- &adc2Group1Interrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &spi4LowLevelInterrupt,\r
- &phantomInterrupt, // 55\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 60\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &sciHighLevelInterrupt,\r
- &phantomInterrupt, // 65\r
- &i2cInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 70\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 75\r
- &phantomInterrupt,\r
- &EMACCore0TxIsr,\r
- &phantomInterrupt,\r
- &EMACCore0RxIsr,\r
- &phantomInterrupt, // 80\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 85\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 90\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 95\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt, // 100\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
- &phantomInterrupt,\r
-};\r
-\r
-\r
-/* Startup Routine */\r
-\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(_c_int00, RESET)\r
-\r
-void _c_int00()\r
-{\r
-\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
-\r
- /* Initialize Core Registers to avoid CCM Error */\r
- _coreInitRegisters_();\r
-\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
-\r
- /* Initialize Stack Pointers */\r
- _coreInitStackPointer_();\r
-\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
-\r
- /* Implement work-around for CCM-R4 issue on silicon revision A */\r
- if (DEVICE_ID_REV == 0x802AAD05)\r
- {\r
- _esmCcmErrorsClear_();\r
- }\r
-\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
-\r
- /* Enable response to ECC errors indicated by CPU for accesses to flash */\r
- flashWREG->FEDACCTRL1 = 0x000A060A;\r
-\r
- /* Enable CPU Event Export */\r
- /* This allows the CPU to signal any single-bit or double-bit errors detected\r
- * by its ECC logic for accesses to program flash or data RAM.\r
- */\r
- _coreEnableEventBusExport_();\r
-\r
- /* Enable CPU ECC checking for ATCM (flash accesses) */\r
- _coreEnableFlashEcc_();\r
-\r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
-\r
- /* Reset handler: the following instructions read from the system exception status register\r
- * to identify the cause of the CPU reset.\r
- */\r
-\r
- /* check for power-on reset condition */\r
- if ((SYS_EXCEPTION & POWERON_RESET) != 0)\r
- {\r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
-\r
- /* clear all reset status flags */\r
- SYS_EXCEPTION = 0xFFFF;\r
-\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
-\r
- /* continue with normal start-up sequence */\r
- }\r
- else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0)\r
- {\r
- /* Reset caused due to oscillator failure.\r
- Add user code here to handle oscillator failure */\r
-\r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
- }\r
- else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0 )\r
- {\r
- /* Reset caused due\r
- * 1) windowed watchdog violation - Add user code here to handle watchdog violation.\r
- * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS\r
- */\r
- /* Check the WatchDog Status register */\r
- if(WATCHDOG_STATUS != 0U)\r
- {\r
- /* Add user code here to handle watchdog violation. */\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
-\r
- /* Clear the Watchdog reset flag in Exception Status register */\r
- SYS_EXCEPTION = WATCHDOG_RESET;\r
-\r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
- }\r
- else\r
- {\r
- /* Clear the ICEPICK reset flag in Exception Status register */\r
- SYS_EXCEPTION = ICEPICK_RESET;\r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
- }\r
- }\r
- else if ((SYS_EXCEPTION & CPU_RESET) !=0 )\r
- {\r
- /* Reset caused due to CPU reset.\r
- CPU reset can be caused by CPU self-test completion, or\r
- by toggling the "CPU RESET" bit of the CPU Reset Control Register. */\r
-\r
-/* USER CODE BEGIN (16) */\r
-/* USER CODE END */\r
-\r
- /* clear all reset status flags */\r
- SYS_EXCEPTION = CPU_RESET;\r
-\r
-/* USER CODE BEGIN (17) */\r
-/* USER CODE END */\r
-\r
- }\r
- else if ((SYS_EXCEPTION & SW_RESET) != 0)\r
- {\r
- /* Reset caused due to software reset.\r
- Add user code to handle software reset. */\r
-\r
-/* USER CODE BEGIN (18) */\r
-/* USER CODE END */\r
- }\r
- else\r
- {\r
- /* Reset caused by nRST being driven low externally.\r
- Add user code to handle external reset. */\r
-\r
-/* USER CODE BEGIN (19) */\r
-/* USER CODE END */\r
- }\r
-\r
- /* Check if there were ESM group3 errors during power-up.\r
- * These could occur during eFuse auto-load or during reads from flash OTP\r
- * during power-up. Device operation is not reliable and not recommended\r
- * in this case.\r
- * An ESM group3 error only drives the nERROR pin low. An external circuit\r
- * that monitors the nERROR pin must take the appropriate action to ensure that\r
- * the system is placed in a safe state, as determined by the application.\r
- */\r
- if (esmREG->ESTATUS1[2])\r
- {\r
-/* USER CODE BEGIN (20) */\r
-/* USER CODE END */\r
- while(1);\r
- }\r
-\r
-/* USER CODE BEGIN (21) */\r
-/* USER CODE END */\r
-\r
- /* Initialize System - Clock, Flash settings with Efuse self check */\r
- systemInit();\r
-\r
-\r
-/* USER CODE BEGIN (24) */\r
-/* USER CODE END */\r
-\r
- /* Run a diagnostic check on the memory self-test controller.\r
- * This function chooses a RAM test algorithm and runs it on an on-chip ROM.\r
- * The memory self-test is expected to fail. The function ensures that the PBIST controller\r
- * is capable of detecting and indicating a memory self-test failure.\r
- */\r
- pbistSelfCheck();\r
-\r
-/* USER CODE BEGIN (26) */\r
-/* USER CODE END */\r
-\r
-\r
- /* Run PBIST on CPU RAM.\r
- * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.\r
- * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the\r
- * device datasheet.\r
- */\r
- pbistRun(0x08300020, /* ESRAM Single Port PBIST */\r
- PBIST_March13N_SP);\r
-\r
-/* USER CODE BEGIN (27) */\r
-/* USER CODE END */\r
-\r
- /* Wait for PBIST for CPU RAM to be completed */\r
- while(!pbistIsTestCompleted());\r
-\r
-/* USER CODE BEGIN (28) */\r
-/* USER CODE END */\r
-\r
- /* Check if CPU RAM passed the self-test */\r
- if( pbistIsTestPassed() != TRUE)\r
- {\r
- /* CPU RAM failed the self-test.\r
- * Need custom handler to check the memory failure\r
- * and to take the appropriate next step.\r
- */\r
- if(pbistPortTestStatus(PBIST_PORT0) != TRUE)\r
- {\r
- memoryPort0TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA0, pbistREG->FSRDL0);\r
- }\r
- else if(pbistPortTestStatus(PBIST_PORT1) != TRUE)\r
- {\r
- memoryPort1TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA1, pbistREG->FSRDL1);\r
- }\r
- else\r
- {\r
- while(1);\r
- }\r
- }\r
-\r
-/* USER CODE BEGIN (29) */\r
-/* USER CODE END */\r
-\r
- /* Disable PBIST clocks and disable memory self-test mode */\r
- pbistStop();\r
-\r
-/* USER CODE BEGIN (30) */\r
-/* USER CODE END */\r
-\r
- /* Initialize CPU RAM.\r
- * This function uses the system module's hardware for auto-initialization of memories and their\r
- * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.\r
- * Hence the value 0x1 passed to the function.\r
- * This function will initialize the entire CPU RAM and the corresponding ECC locations.\r
- */\r
- _memoryInit_(0x1);\r
-\r
-/* USER CODE BEGIN (31) */\r
-/* USER CODE END */\r
-\r
- /* Enable ECC checking for TCRAM accesses.\r
- * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.\r
- */\r
- _coreEnableRamEcc_();\r
-\r
-/* USER CODE BEGIN (32) */\r
-/* USER CODE END */\r
-\r
- /* Start PBIST on all dual-port memories */\r
- pbistRun( 0x00000000 /* EMAC Dual Port PBIST */\r
- | 0x00000000 /* USB Dual Port PBIST for RMx / Reserved for TMS570x */\r
- | 0x00000800 /* DMA Dual Port PBIST */\r
- | 0x00000200 /* VIM Dual Port PBIST */\r
- | 0x00000040 /* MIBSPI1 Dual Port PBIST */\r
- | 0x00000080 /* MIBSPI3 Dual Port PBIST */\r
- | 0x00000100 /* MIBSPI5 Dual Port PBIST */\r
- | 0x00000004 /* CAN1 Dual Port PBIST */\r
- | 0x00000008 /* CAN2 Dual Port PBIST */\r
- | 0x00000010 /* CAN3 Dual Port PBIST */\r
- | 0x00000400 /* ADC1 Dual Port PBIST */\r
- | 0x00020000 /* ADC2 Dual Port PBIST */\r
- | 0x00001000 /* HET1 Dual Port PBIST */\r
- | 0x00040000 /* HET2 Dual Port PBIST */\r
- | 0x00002000 /* HTU1 Dual Port PBIST */\r
- | 0x00080000 /* HTU2 Dual Port PBIST */\r
- | 0x00004000 /* RTP Dual Port PBIST */\r
- | 0x00000000 /* FTU Dual Port PBIST for TMS570x / Reserved for RMx */\r
- | 0x00008000 /* FRAY Dual Port PBIST for TMS570x / Reserved for RMx */\r
- , PBIST_March13N_DP);\r
-\r
-/* USER CODE BEGIN (33) */\r
-/* USER CODE END */\r
-\r
-\r
- /* Test the CPU ECC mechanism for RAM accesses.\r
- * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses\r
- * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error\r
- * in the ECC causes a data abort exception. The data abort handler is written to look for\r
- * deliberately caused exception and to return the code execution to the instruction\r
- * following the one that caused the abort.\r
- */\r
- checkB0RAMECC();\r
- tcram1REG->RAMCTRL &= ~(0x00000100); /* disable writes to ECC RAM */\r
- tcram2REG->RAMCTRL &= ~(0x00000100);\r
-\r
- checkB1RAMECC();\r
- tcram1REG->RAMCTRL &= ~(0x00000100); /* disable writes to ECC RAM */\r
- tcram2REG->RAMCTRL &= ~(0x00000100);\r
-\r
-/* USER CODE BEGIN (34) */\r
-/* USER CODE END */\r
-\r
-\r
- /* Test the CPU ECC mechanism for Flash accesses.\r
- * The checkFlashECC function uses the flash interface module's diagnostic mode 7\r
- * to create single-bit and double-bit errors in CPU accesses to the flash. A double-bit\r
- * error on reading from flash causes a data abort exception.\r
- * The data abort handler is written to look for deliberately caused exception and\r
- * to return the code execution to the instruction following the one that was aborted.\r
- *\r
- */\r
- checkFlashECC();\r
- flashWREG->FDIAGCTRL = 0x000A0007; /* disable flash diagnostic mode */\r
-\r
-/* USER CODE BEGIN (35) */\r
-/* USER CODE END */\r
-\r
-/* USER CODE BEGIN (36) */\r
-/* USER CODE END */\r
-\r
- /* Wait for PBIST for CPU RAM to be completed */\r
- while(!pbistIsTestCompleted());\r
-\r
-/* USER CODE BEGIN (37) */\r
-/* USER CODE END */\r
-\r
- /* Check if CPU RAM passed the self-test */\r
- if( pbistIsTestPassed() != TRUE)\r
- {\r
-\r
-/* USER CODE BEGIN (38) */\r
-/* USER CODE END */\r
-\r
- /* CPU RAM failed the self-test.\r
- * Need custom handler to check the memory failure\r
- * and to take the appropriate next step.\r
- */\r
- if(pbistPortTestStatus(PBIST_PORT0) != TRUE)\r
- {\r
- memoryPort0TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA0, pbistREG->FSRDL0);\r
- }\r
- else if(pbistPortTestStatus(PBIST_PORT1) != TRUE)\r
- {\r
- memoryPort1TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA1, pbistREG->FSRDL1);\r
- }\r
- else\r
- {\r
- while(1);\r
- }\r
- }\r
-\r
-/* USER CODE BEGIN (39) */\r
-/* USER CODE END */\r
-\r
- /* Disable PBIST clocks and disable memory self-test mode */\r
- pbistStop();\r
-\r
-\r
-/* USER CODE BEGIN (45) */\r
-/* USER CODE END */\r
-\r
- /* Release the MibSPI1 modules from local reset.\r
- * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.\r
- */\r
- mibspiREG1->GCR0 = 0x1;\r
-\r
- /* Release the MibSPI3 modules from local reset.\r
- * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.\r
- */\r
- mibspiREG3->GCR0 = 0x1;\r
-\r
- /* Release the MibSPI5 modules from local reset.\r
- * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.\r
- */\r
- mibspiREG5->GCR0 = 0x1;\r
-\r
-/* USER CODE BEGIN (46) */\r
-/* USER CODE END */\r
-\r
- /* Initialize all on-chip SRAMs except for MibSPIx RAMs\r
- * The MibSPIx modules have their own auto-initialization mechanism which is triggered\r
- * as soon as the modules are brought out of local reset.\r
- */\r
- /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.\r
- */\r
- _memoryInit_( 1 << 1 /* DMA Memory Init */\r
- | 1 << 2 /* VIM Memory Init */\r
- | 1 << 5 /* CAN1 Memory Init */\r
- | 1 << 6 /* CAN2 Memory Init */\r
- | 1 << 10 /* CAN3 Memory Init */\r
- | 1 << 8 /* ADC1 Memory Init */\r
- | 1 << 14 /* ADC2 Memory Init */\r
- | 1 << 3 /* HET1 Memory Init */\r
- | 1 << 4 /* HTU1 Memory Init */\r
- | 1 << 15 /* HET2 Memory Init */\r
- | 1 << 16 /* HTU2 Memory Init */\r
- | 1 << 13); /* Reserved for RMx Family / FTU Memory Init for TMS570x Family */\r
-\r
- /* Test the parity protection mechanism for peripheral RAMs\r
- * The following memories have parity protection that needs to be checked:\r
- * VIM, DMA, ADC1, ADC2, NHET1, NHET2, HTU1, HTU2, FlexRay, FTU,\r
- * MibSPI1, MibSPI3, MibSPI5, DCAN1, DCAN2, DCAN3 based on user selection\r
- */\r
-\r
-/* USER CODE BEGIN (47) */\r
-/* USER CODE END */\r
-\r
- het1ParityCheck();\r
-\r
-/* USER CODE BEGIN (48) */\r
-/* USER CODE END */\r
-\r
- htu1ParityCheck();\r
-\r
-/* USER CODE BEGIN (49) */\r
-/* USER CODE END */\r
-\r
- het2ParityCheck();\r
-\r
-/* USER CODE BEGIN (50) */\r
-/* USER CODE END */\r
-\r
- htu2ParityCheck();\r
-\r
-/* USER CODE BEGIN (51) */\r
-/* USER CODE END */\r
-\r
- adc1ParityCheck();\r
-\r
-/* USER CODE BEGIN (52) */\r
-/* USER CODE END */\r
-\r
- adc2ParityCheck();\r
-\r
-/* USER CODE BEGIN (53) */\r
-/* USER CODE END */\r
-\r
- can1ParityCheck();\r
-\r
-/* USER CODE BEGIN (54) */\r
-/* USER CODE END */\r
-\r
- can2ParityCheck();\r
-\r
-/* USER CODE BEGIN (55) */\r
-/* USER CODE END */\r
-\r
- can3ParityCheck();\r
-\r
-/* USER CODE BEGIN (56) */\r
-/* USER CODE END */\r
-\r
- vimParityCheck();\r
-\r
-/* USER CODE BEGIN (57) */\r
-/* USER CODE END */\r
-\r
- dmaParityCheck();\r
-\r
-\r
-/* USER CODE BEGIN (58) */\r
-/* USER CODE END */\r
-\r
- while (mibspiREG1->BUFINIT); /* wait for MibSPI1 RAM to complete initialization */\r
- while (mibspiREG3->BUFINIT); /* wait for MibSPI3 RAM to complete initialization */\r
- while (mibspiREG5->BUFINIT); /* wait for MibSPI5 RAM to complete initialization */\r
-\r
-/* USER CODE BEGIN (59) */\r
-/* USER CODE END */\r
-\r
- mibspi1ParityCheck();\r
-\r
-/* USER CODE BEGIN (60) */\r
-/* USER CODE END */\r
-\r
- mibspi3ParityCheck();\r
-\r
-/* USER CODE BEGIN (61) */\r
-/* USER CODE END */\r
-\r
- mibspi5ParityCheck();\r
-\r
-\r
-/* USER CODE BEGIN (62) */\r
-/* USER CODE END */\r
-\r
-\r
-/* USER CODE BEGIN (63) */\r
-/* USER CODE END */\r
-\r
-\r
- /* Initialize VIM table */\r
- {\r
- uint32_t i;\r
-\r
- for (i = 0; i < (VIM_CHANNELS + 1); i++)\r
- {\r
- vimRAM->ISR[i] = s_vim_init[i];\r
- }\r
- }\r
-\r
- /* set IRQ/FIQ priorities */\r
- vimREG->FIRQPR0 = SYS_FIQ\r
- | (SYS_FIQ << 1U)\r
- | (SYS_IRQ << 2U)\r
- | (SYS_IRQ << 3U)\r
- | (SYS_IRQ << 4U)\r
- | (SYS_IRQ << 5U)\r
- | (SYS_IRQ << 6U)\r
- | (SYS_IRQ << 7U)\r
- | (SYS_IRQ << 8U)\r
- | (SYS_IRQ << 9U)\r
- | (SYS_IRQ << 10U)\r
- | (SYS_IRQ << 11U)\r
- | (SYS_IRQ << 12U)\r
- | (SYS_IRQ << 13U)\r
- | (SYS_IRQ << 14U)\r
- | (SYS_IRQ << 15U)\r
- | (SYS_IRQ << 16U)\r
- | (SYS_IRQ << 17U)\r
- | (SYS_IRQ << 18U)\r
- | (SYS_IRQ << 19U)\r
- | (SYS_IRQ << 20U)\r
- | (SYS_IRQ << 21U)\r
- | (SYS_IRQ << 22U)\r
- | (SYS_IRQ << 23U)\r
- | (SYS_IRQ << 24U)\r
- | (SYS_IRQ << 25U)\r
- | (SYS_IRQ << 26U)\r
- | (SYS_IRQ << 27U)\r
- | (SYS_IRQ << 28U)\r
- | (SYS_IRQ << 29U)\r
- | (SYS_IRQ << 30U)\r
- | (SYS_IRQ << 31U);\r
-\r
- vimREG->FIRQPR1 = SYS_IRQ\r
- | (SYS_IRQ << 1U)\r
- | (SYS_IRQ << 2U)\r
- | (SYS_IRQ << 3U)\r
- | (SYS_IRQ << 4U)\r
- | (SYS_IRQ << 5U)\r
- | (SYS_IRQ << 6U)\r
- | (SYS_IRQ << 7U)\r
- | (SYS_IRQ << 8U)\r
- | (SYS_IRQ << 9U)\r
- | (SYS_IRQ << 10U)\r
- | (SYS_IRQ << 11U)\r
- | (SYS_IRQ << 12U)\r
- | (SYS_IRQ << 13U)\r
- | (SYS_IRQ << 14U)\r
- | (SYS_IRQ << 15U)\r
- | (SYS_IRQ << 16U)\r
- | (SYS_IRQ << 17U)\r
- | (SYS_IRQ << 18U)\r
- | (SYS_IRQ << 19U)\r
- | (SYS_IRQ << 20U)\r
- | (SYS_IRQ << 21U)\r
- | (SYS_IRQ << 22U)\r
- | (SYS_IRQ << 23U)\r
- | (SYS_IRQ << 24U)\r
- | (SYS_IRQ << 25U)\r
- | (SYS_IRQ << 26U)\r
- | (SYS_IRQ << 27U)\r
- | (SYS_IRQ << 28U)\r
- | (SYS_IRQ << 29U)\r
- | (SYS_IRQ << 30U)\r
- | (SYS_IRQ << 31U);\r
-\r
-\r
- vimREG->FIRQPR2 = SYS_IRQ\r
- | (SYS_IRQ << 1U)\r
- | (SYS_IRQ << 2U)\r
- | (SYS_IRQ << 3U)\r
- | (SYS_IRQ << 4U)\r
- | (SYS_IRQ << 5U)\r
- | (SYS_IRQ << 6U)\r
- | (SYS_IRQ << 7U)\r
- | (SYS_IRQ << 8U)\r
- | (SYS_IRQ << 9U)\r
- | (SYS_IRQ << 10U)\r
- | (SYS_IRQ << 11U)\r
- | (SYS_IRQ << 12U)\r
- | (SYS_FIQ << 13U) // EMAC\r
- | (SYS_IRQ << 14U)\r
- | (SYS_FIQ << 15U) // EMAC\r
- | (SYS_IRQ << 16U)\r
- | (SYS_IRQ << 17U)\r
- | (SYS_IRQ << 18U)\r
- | (SYS_IRQ << 19U)\r
- | (SYS_IRQ << 20U)\r
- | (SYS_IRQ << 21U)\r
- | (SYS_IRQ << 22U)\r
- | (SYS_IRQ << 23U)\r
- | (SYS_IRQ << 24U)\r
- | (SYS_IRQ << 25U)\r
- | (SYS_IRQ << 26U)\r
- | (SYS_IRQ << 27U)\r
- | (SYS_IRQ << 28U)\r
- | (SYS_IRQ << 29U)\r
- | (SYS_IRQ << 30U)\r
- | (SYS_IRQ << 31U);\r
-\r
- vimREG->FIRQPR3 = SYS_IRQ\r
- | (SYS_IRQ << 1U)\r
- | (SYS_IRQ << 2U)\r
- | (SYS_IRQ << 3U)\r
- | (SYS_IRQ << 4U)\r
- | (SYS_IRQ << 5U)\r
- | (SYS_IRQ << 6U)\r
- | (SYS_IRQ << 7U)\r
- | (SYS_IRQ << 8U)\r
- | (SYS_IRQ << 9U)\r
- | (SYS_IRQ << 10U)\r
- | (SYS_IRQ << 11U)\r
- | (SYS_IRQ << 12U)\r
- | (SYS_IRQ << 13U)\r
- | (SYS_IRQ << 14U)\r
- | (SYS_IRQ << 15U)\r
- | (SYS_IRQ << 16U)\r
- | (SYS_IRQ << 17U)\r
- | (SYS_IRQ << 18U)\r
- | (SYS_IRQ << 19U)\r
- | (SYS_IRQ << 20U)\r
- | (SYS_IRQ << 21U)\r
- | (SYS_IRQ << 22U)\r
- | (SYS_IRQ << 23U)\r
- | (SYS_IRQ << 24U)\r
- | (SYS_IRQ << 25U)\r
- | (SYS_IRQ << 26U)\r
- | (SYS_IRQ << 27U)\r
- | (SYS_IRQ << 28U)\r
- | (SYS_IRQ << 29U)\r
- | (SYS_IRQ << 30U)\r
- | (SYS_IRQ << 31U);\r
-\r
-\r
- /* enable interrupts */\r
- vimREG->REQMASKSET0 = 1U\r
- | (1U << 1U)\r
- | (1U << 2U)\r
- | (0U << 3U)\r
- | (0U << 4U)\r
- | (0U << 5U)\r
- | (0U << 6U)\r
- | (0U << 7U)\r
- | (0U << 8U)\r
- | (0U << 9U)\r
- | (0U << 10U)\r
- | (0U << 11U)\r
- | (1U << 12U)\r
- | (1U << 13U)\r
- | (0U << 14U)\r
- | (1U << 15U)\r
- | (1U << 16U)\r
- | (1U << 17U)\r
- | (0U << 18U)\r
- | (0U << 19U)\r
- | (0U << 20U)\r
- | (0U << 21U)\r
- | (0U << 22U)\r
- | (0U << 23U)\r
- | (0U << 24U)\r
- | (0U << 25U)\r
- | (1U << 26U)\r
- | (0U << 27U)\r
- | (0U << 28U)\r
- | (0U << 29U)\r
- | (1U << 30U)\r
- | (0U << 31U);\r
-\r
- vimREG->REQMASKSET1 = 0U\r
- | (0U << 1U)\r
- | (0U << 2U)\r
- | (1U << 3U)\r
- | (0U << 4U)\r
- | (1U << 5U)\r
- | (1U << 6U)\r
- | (0U << 7U)\r
- | (0U << 8U)\r
- | (0U << 9U)\r
- | (0U << 10U)\r
- | (0U << 11U)\r
- | (0U << 12U)\r
- | (1U << 13U)\r
- | (0U << 14U)\r
- | (0U << 15U)\r
- | (0U << 16U)\r
- | (1U << 17U)\r
- | (0U << 18U)\r
- | (1U << 19U)\r
- | (0U << 20U)\r
- | (0U << 21U)\r
- | (1U << 22U)\r
- | (0U << 23U)\r
- | (0U << 24U)\r
- | (0U << 25U)\r
- | (0U << 26U)\r
- | (0U << 27U)\r
- | (0U << 28U)\r
- | (0U << 29U)\r
- | (0U << 30U)\r
- | (0U << 31U);\r
-\r
- vimREG->REQMASKSET2 = 1U\r
- | (0U << 1U)\r
- | (0U << 2U)\r
- | (0U << 3U)\r
- | (0U << 4U)\r
- | (0U << 5U)\r
- | (0U << 6U)\r
- | (0U << 7U)\r
- | (0U << 8U)\r
- | (0U << 9U)\r
- | (0U << 10U)\r
- | (0U << 11U)\r
- | (0U << 12U)\r
- | (1U << 13U) // EMACCore0TxIsr\r
- | (0U << 14U)\r
- | (1U << 15U) // EMACCore0RxIsr\r
- | (0U << 16U)\r
- | (0U << 17U)\r
- | (0U << 18U)\r
- | (0U << 19U)\r
- | (0U << 20U)\r
- | (0U << 21U)\r
- | (0U << 22U)\r
- | (0U << 23U)\r
- | (0U << 24U)\r
- | (0U << 25U)\r
- | (0U << 26U)\r
- | (0U << 27U)\r
- | (0U << 28U)\r
- | (0U << 29U)\r
- | (0U << 30U)\r
- | (0U << 31U);\r
-\r
- vimREG->REQMASKSET3 = 0U\r
- | (0U << 1U)\r
- | (0U << 2U)\r
- | (0U << 3U)\r
- | (0U << 4U)\r
- | (0U << 5U)\r
- | (0U << 6U)\r
- | (0U << 7U)\r
- | (0U << 8U)\r
- | (0U << 9U)\r
- | (0U << 10U)\r
- | (0U << 11U)\r
- | (0U << 12U)\r
- | (0U << 13U)\r
- | (0U << 14U)\r
- | (0U << 15U)\r
- | (0U << 16U)\r
- | (0U << 17U)\r
- | (0U << 18U)\r
- | (0U << 19U)\r
- | (0U << 20U)\r
- | (0U << 21U)\r
- | (0U << 22U)\r
- | (0U << 23U)\r
- | (0U << 24U)\r
- | (0U << 25U)\r
- | (0U << 26U)\r
- | (0U << 27U)\r
- | (0U << 28U)\r
- | (0U << 29U)\r
- | (0U << 30U)\r
- | (0U << 31U);\r
-\r
-/* USER CODE BEGIN (64) */\r
-/* USER CODE END */\r
-\r
- /* Configure system response to error conditions signaled to the ESM group1 */\r
- /* This function can be configured from the ESM tab of HALCoGen */\r
- esmInit();\r
-\r
- /* initalise copy table */\r
- if ((uint32_t *)&__binit__ != (uint32_t *)0xFFFFFFFFU)\r
- {\r
- extern void copy_in(void *binit);\r
- copy_in((void *)&__binit__);\r
- }\r
-\r
- /* initalise the C global variables */\r
- if (&__TI_Handler_Table_Base < &__TI_Handler_Table_Limit)\r
- {\r
- uint8_t **tablePtr = (uint8_t **)&__TI_CINIT_Base;\r
- uint8_t **tableLimit = (uint8_t **)&__TI_CINIT_Limit;\r
-\r
- while (tablePtr < tableLimit)\r
- {\r
- uint8_t *loadAdr = *tablePtr++;\r
- uint8_t *runAdr = *tablePtr++;\r
- uint8_t idx = *loadAdr++;\r
- handler_fptr handler = (handler_fptr)(&__TI_Handler_Table_Base)[idx];\r
-\r
- (*handler)((const uint8_t *)loadAdr, runAdr);\r
- }\r
- }\r
-\r
- /* initalise contructors */\r
- if (__TI_PINIT_Base < __TI_PINIT_Limit)\r
- {\r
- void (**p0)() = (void *)__TI_PINIT_Base;\r
-\r
- while ((uint32_t)p0 < __TI_PINIT_Limit)\r
- {\r
- void (*p)() = *p0++;\r
- p();\r
- }\r
- }\r
-\r
-/* USER CODE BEGIN (65) */\r
-/* USER CODE END */\r
-\r
- /* call the application */\r
- main();\r
-\r
-/* USER CODE BEGIN (66) */\r
-/* USER CODE END */\r
-\r
- exit();\r
-/* USER CODE BEGIN (67) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (68) */\r
-/* USER CODE END */\r
+/** @file sys_startup.c
+* @brief Startup Source File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+* This file contains:
+* - Include Files
+* - Type Definitions
+* - External Functions
+* - VIM RAM Setup
+* - Startup Routine
+* .
+* which are relevant for the Startup.
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* Include Files */
+
+#include "sys_common.h"
+#include "system.h"
+#include "sys_vim.h"
+#include "sys_core.h"
+#include "sys_selftest.h"
+#include "ti_drv_esm.h"
+
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/* Type Definitions */
+
+typedef void (*handler_fptr)(const uint8_t *in, uint8_t *out);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+/* External Functions */
+
+#pragma WEAK(__TI_Handler_Table_Base)
+#pragma WEAK(__TI_Handler_Table_Limit)
+#pragma WEAK(__TI_CINIT_Base)
+#pragma WEAK(__TI_CINIT_Limit)
+
+extern uint32_t __TI_Handler_Table_Base;
+extern uint32_t __TI_Handler_Table_Limit;
+extern uint32_t __TI_CINIT_Base;
+extern uint32_t __TI_CINIT_Limit;
+extern uint32_t __TI_PINIT_Base;
+extern uint32_t __TI_PINIT_Limit;
+extern uint32_t * __binit__;
+
+extern void main(void);
+extern void exit(void);
+
+extern void muxInit(void);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+
+/* Vim Ram Definition */
+/** @struct vimRam
+* @brief Vim Ram Definition
+*
+* This type is used to access the Vim Ram.
+*/
+/** @typedef vimRAM_t
+* @brief Vim Ram Type Definition
+*
+* This type is used to access the Vim Ram.
+*/
+typedef volatile struct vimRam
+{
+ t_isrFuncPTR ISR[VIM_CHANNELS + 1];
+} vimRAM_t;
+
+#define vimRAM ((vimRAM_t *)0xFFF82000U)
+
+static const t_isrFuncPTR s_vim_init[] =
+{
+ &phantomInterrupt,
+ &esmHighInterrupt, // 0
+ &phantomInterrupt,
+ &vPreemptiveTick,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 5
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 10
+ &phantomInterrupt,
+ &mibspi1HighLevelInterrupt,
+ &linHighLevelInterrupt,
+ &phantomInterrupt,
+ &adc1Group1Interrupt, // 15
+ &can1HighLevelInterrupt,
+ &spi2HighLevelInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 20
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 25
+ &mibspi1LowLevelInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &spi2LowLevelInterrupt, // 30
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &can2HighLevelInterrupt, // 35
+ &phantomInterrupt,
+ &mibspi3HighInterruptLevel,
+ &mibspi3LowLevelInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 40
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &can3HighLevelInterrupt, // 45
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &spi4HighLevelInterrupt,
+ &phantomInterrupt, // 50
+ &adc2Group1Interrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &spi4LowLevelInterrupt,
+ &phantomInterrupt, // 55
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 60
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &sciHighLevelInterrupt,
+ &phantomInterrupt, // 65
+ &i2cInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 70
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 75
+ &phantomInterrupt,
+ &EMACCore0TxIsr,
+ &phantomInterrupt,
+ &EMACCore0RxIsr,
+ &phantomInterrupt, // 80
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 85
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 90
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 95
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt, // 100
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+ &phantomInterrupt,
+};
+
+
+/* Startup Routine */
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+#pragma INTERRUPT(_c_int00, RESET)
+
+void _c_int00()
+{
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+ /* Initialize Core Registers to avoid CCM Error */
+ _coreInitRegisters_();
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+ /* Initialize Stack Pointers */
+ _coreInitStackPointer_();
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+ /* Implement work-around for CCM-R4 issue on silicon revision A */
+ if (DEVICE_ID_REV == 0x802AAD05)
+ {
+ _esmCcmErrorsClear_();
+ }
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ /* Enable response to ECC errors indicated by CPU for accesses to flash */
+ flashWREG->FEDACCTRL1 = 0x000A060A;
+
+ /* Enable CPU Event Export */
+ /* This allows the CPU to signal any single-bit or double-bit errors detected
+ * by its ECC logic for accesses to program flash or data RAM.
+ */
+ _coreEnableEventBusExport_();
+
+ /* Enable CPU ECC checking for ATCM (flash accesses) */
+ _coreEnableFlashEcc_();
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+ /* Reset handler: the following instructions read from the system exception status register
+ * to identify the cause of the CPU reset.
+ */
+
+ /* check for power-on reset condition */
+ if ((SYS_EXCEPTION & POWERON_RESET) != 0)
+ {
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+ /* clear all reset status flags */
+ SYS_EXCEPTION = 0xFFFF;
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ /* continue with normal start-up sequence */
+ }
+ else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0)
+ {
+ /* Reset caused due to oscillator failure.
+ Add user code here to handle oscillator failure */
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+ }
+ else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0 )
+ {
+ /* Reset caused due
+ * 1) windowed watchdog violation - Add user code here to handle watchdog violation.
+ * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
+ */
+ /* Check the WatchDog Status register */
+ if(WATCHDOG_STATUS != 0U)
+ {
+ /* Add user code here to handle watchdog violation. */
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ /* Clear the Watchdog reset flag in Exception Status register */
+ SYS_EXCEPTION = WATCHDOG_RESET;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+ }
+ else
+ {
+ /* Clear the ICEPICK reset flag in Exception Status register */
+ SYS_EXCEPTION = ICEPICK_RESET;
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+ }
+ }
+ else if ((SYS_EXCEPTION & CPU_RESET) !=0 )
+ {
+ /* Reset caused due to CPU reset.
+ CPU reset can be caused by CPU self-test completion, or
+ by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+ /* clear all reset status flags */
+ SYS_EXCEPTION = CPU_RESET;
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ }
+ else if ((SYS_EXCEPTION & SW_RESET) != 0)
+ {
+ /* Reset caused due to software reset.
+ Add user code to handle software reset. */
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+ }
+ else
+ {
+ /* Reset caused by nRST being driven low externally.
+ Add user code to handle external reset. */
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+ }
+
+ /* Check if there were ESM group3 errors during power-up.
+ * These could occur during eFuse auto-load or during reads from flash OTP
+ * during power-up. Device operation is not reliable and not recommended
+ * in this case.
+ * An ESM group3 error only drives the nERROR pin low. An external circuit
+ * that monitors the nERROR pin must take the appropriate action to ensure that
+ * the system is placed in a safe state, as determined by the application.
+ */
+ if (esmREG->ESTATUS1[2])
+ {
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+ while(1);
+ }
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+ /* Initialize System - Clock, Flash settings with Efuse self check */
+ systemInit();
+
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+ /* Run a diagnostic check on the memory self-test controller.
+ * This function chooses a RAM test algorithm and runs it on an on-chip ROM.
+ * The memory self-test is expected to fail. The function ensures that the PBIST controller
+ * is capable of detecting and indicating a memory self-test failure.
+ */
+ pbistSelfCheck();
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+
+ /* Run PBIST on CPU RAM.
+ * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
+ * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
+ * device datasheet.
+ */
+ pbistRun(0x08300020, /* ESRAM Single Port PBIST */
+ PBIST_March13N_SP);
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+ /* Wait for PBIST for CPU RAM to be completed */
+ while(!pbistIsTestCompleted());
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ /* Check if CPU RAM passed the self-test */
+ if( pbistIsTestPassed() != TRUE)
+ {
+ /* CPU RAM failed the self-test.
+ * Need custom handler to check the memory failure
+ * and to take the appropriate next step.
+ */
+ if(pbistPortTestStatus(PBIST_PORT0) != TRUE)
+ {
+ memoryPort0TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA0, pbistREG->FSRDL0);
+ }
+ else if(pbistPortTestStatus(PBIST_PORT1) != TRUE)
+ {
+ memoryPort1TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA1, pbistREG->FSRDL1);
+ }
+ else
+ {
+ while(1);
+ }
+ }
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+ /* Disable PBIST clocks and disable memory self-test mode */
+ pbistStop();
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+ /* Initialize CPU RAM.
+ * This function uses the system module's hardware for auto-initialization of memories and their
+ * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
+ * Hence the value 0x1 passed to the function.
+ * This function will initialize the entire CPU RAM and the corresponding ECC locations.
+ */
+ _memoryInit_(0x1);
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+ /* Enable ECC checking for TCRAM accesses.
+ * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
+ */
+ _coreEnableRamEcc_();
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+ /* Start PBIST on all dual-port memories */
+ pbistRun( 0x00000000 /* EMAC Dual Port PBIST */
+ | 0x00000000 /* USB Dual Port PBIST for RMx / Reserved for TMS570x */
+ | 0x00000800 /* DMA Dual Port PBIST */
+ | 0x00000200 /* VIM Dual Port PBIST */
+ | 0x00000040 /* MIBSPI1 Dual Port PBIST */
+ | 0x00000080 /* MIBSPI3 Dual Port PBIST */
+ | 0x00000100 /* MIBSPI5 Dual Port PBIST */
+ | 0x00000004 /* CAN1 Dual Port PBIST */
+ | 0x00000008 /* CAN2 Dual Port PBIST */
+ | 0x00000010 /* CAN3 Dual Port PBIST */
+ | 0x00000400 /* ADC1 Dual Port PBIST */
+ | 0x00020000 /* ADC2 Dual Port PBIST */
+ | 0x00001000 /* HET1 Dual Port PBIST */
+ | 0x00040000 /* HET2 Dual Port PBIST */
+ | 0x00002000 /* HTU1 Dual Port PBIST */
+ | 0x00080000 /* HTU2 Dual Port PBIST */
+ | 0x00004000 /* RTP Dual Port PBIST */
+ | 0x00000000 /* FTU Dual Port PBIST for TMS570x / Reserved for RMx */
+ | 0x00008000 /* FRAY Dual Port PBIST for TMS570x / Reserved for RMx */
+ , PBIST_March13N_DP);
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+
+ /* Test the CPU ECC mechanism for RAM accesses.
+ * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
+ * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
+ * in the ECC causes a data abort exception. The data abort handler is written to look for
+ * deliberately caused exception and to return the code execution to the instruction
+ * following the one that caused the abort.
+ */
+ checkB0RAMECC();
+ tcram1REG->RAMCTRL &= ~(0x00000100); /* disable writes to ECC RAM */
+ tcram2REG->RAMCTRL &= ~(0x00000100);
+
+ checkB1RAMECC();
+ tcram1REG->RAMCTRL &= ~(0x00000100); /* disable writes to ECC RAM */
+ tcram2REG->RAMCTRL &= ~(0x00000100);
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+
+ /* Test the CPU ECC mechanism for Flash accesses.
+ * The checkFlashECC function uses the flash interface module's diagnostic mode 7
+ * to create single-bit and double-bit errors in CPU accesses to the flash. A double-bit
+ * error on reading from flash causes a data abort exception.
+ * The data abort handler is written to look for deliberately caused exception and
+ * to return the code execution to the instruction following the one that was aborted.
+ *
+ */
+ checkFlashECC();
+ flashWREG->FDIAGCTRL = 0x000A0007; /* disable flash diagnostic mode */
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+ /* Wait for PBIST for CPU RAM to be completed */
+ while(!pbistIsTestCompleted());
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+
+ /* Check if CPU RAM passed the self-test */
+ if( pbistIsTestPassed() != TRUE)
+ {
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+
+ /* CPU RAM failed the self-test.
+ * Need custom handler to check the memory failure
+ * and to take the appropriate next step.
+ */
+ if(pbistPortTestStatus(PBIST_PORT0) != TRUE)
+ {
+ memoryPort0TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA0, pbistREG->FSRDL0);
+ }
+ else if(pbistPortTestStatus(PBIST_PORT1) != TRUE)
+ {
+ memoryPort1TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA1, pbistREG->FSRDL1);
+ }
+ else
+ {
+ while(1);
+ }
+ }
+
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+
+ /* Disable PBIST clocks and disable memory self-test mode */
+ pbistStop();
+
+
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+
+ /* Release the MibSPI1 modules from local reset.
+ * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
+ */
+ mibspiREG1->GCR0 = 0x1;
+
+ /* Release the MibSPI3 modules from local reset.
+ * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
+ */
+ mibspiREG3->GCR0 = 0x1;
+
+ /* Release the MibSPI5 modules from local reset.
+ * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
+ */
+ mibspiREG5->GCR0 = 0x1;
+
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+
+ /* Initialize all on-chip SRAMs except for MibSPIx RAMs
+ * The MibSPIx modules have their own auto-initialization mechanism which is triggered
+ * as soon as the modules are brought out of local reset.
+ */
+ /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
+ */
+ _memoryInit_( 1 << 1 /* DMA Memory Init */
+ | 1 << 2 /* VIM Memory Init */
+ | 1 << 5 /* CAN1 Memory Init */
+ | 1 << 6 /* CAN2 Memory Init */
+ | 1 << 10 /* CAN3 Memory Init */
+ | 1 << 8 /* ADC1 Memory Init */
+ | 1 << 14 /* ADC2 Memory Init */
+ | 1 << 3 /* HET1 Memory Init */
+ | 1 << 4 /* HTU1 Memory Init */
+ | 1 << 15 /* HET2 Memory Init */
+ | 1 << 16 /* HTU2 Memory Init */
+ | 1 << 13); /* Reserved for RMx Family / FTU Memory Init for TMS570x Family */
+
+ /* Test the parity protection mechanism for peripheral RAMs
+ * The following memories have parity protection that needs to be checked:
+ * VIM, DMA, ADC1, ADC2, NHET1, NHET2, HTU1, HTU2, FlexRay, FTU,
+ * MibSPI1, MibSPI3, MibSPI5, DCAN1, DCAN2, DCAN3 based on user selection
+ */
+
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+
+ het1ParityCheck();
+
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+
+ htu1ParityCheck();
+
+/* USER CODE BEGIN (49) */
+/* USER CODE END */
+
+ het2ParityCheck();
+
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+
+ htu2ParityCheck();
+
+/* USER CODE BEGIN (51) */
+/* USER CODE END */
+
+ adc1ParityCheck();
+
+/* USER CODE BEGIN (52) */
+/* USER CODE END */
+
+ adc2ParityCheck();
+
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+
+ can1ParityCheck();
+
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+
+ can2ParityCheck();
+
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+
+ can3ParityCheck();
+
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+
+ vimParityCheck();
+
+/* USER CODE BEGIN (57) */
+/* USER CODE END */
+
+ dmaParityCheck();
+
+
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+
+ while (mibspiREG1->BUFINIT); /* wait for MibSPI1 RAM to complete initialization */
+ while (mibspiREG3->BUFINIT); /* wait for MibSPI3 RAM to complete initialization */
+ while (mibspiREG5->BUFINIT); /* wait for MibSPI5 RAM to complete initialization */
+
+/* USER CODE BEGIN (59) */
+/* USER CODE END */
+
+ mibspi1ParityCheck();
+
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
+
+ mibspi3ParityCheck();
+
+/* USER CODE BEGIN (61) */
+/* USER CODE END */
+
+ mibspi5ParityCheck();
+
+
+/* USER CODE BEGIN (62) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (63) */
+/* USER CODE END */
+
+
+ /* Initialize VIM table */
+ {
+ uint32_t i;
+
+ for (i = 0; i < (VIM_CHANNELS + 1); i++)
+ {
+ vimRAM->ISR[i] = s_vim_init[i];
+ }
+ }
+
+ /* set IRQ/FIQ priorities */
+ vimREG->FIRQPR0 = SYS_FIQ
+ | (SYS_FIQ << 1U)
+ | (SYS_IRQ << 2U)
+ | (SYS_IRQ << 3U)
+ | (SYS_IRQ << 4U)
+ | (SYS_IRQ << 5U)
+ | (SYS_IRQ << 6U)
+ | (SYS_IRQ << 7U)
+ | (SYS_IRQ << 8U)
+ | (SYS_IRQ << 9U)
+ | (SYS_IRQ << 10U)
+ | (SYS_IRQ << 11U)
+ | (SYS_IRQ << 12U)
+ | (SYS_IRQ << 13U)
+ | (SYS_IRQ << 14U)
+ | (SYS_IRQ << 15U)
+ | (SYS_IRQ << 16U)
+ | (SYS_IRQ << 17U)
+ | (SYS_IRQ << 18U)
+ | (SYS_IRQ << 19U)
+ | (SYS_IRQ << 20U)
+ | (SYS_IRQ << 21U)
+ | (SYS_IRQ << 22U)
+ | (SYS_IRQ << 23U)
+ | (SYS_IRQ << 24U)
+ | (SYS_IRQ << 25U)
+ | (SYS_IRQ << 26U)
+ | (SYS_IRQ << 27U)
+ | (SYS_IRQ << 28U)
+ | (SYS_IRQ << 29U)
+ | (SYS_IRQ << 30U)
+ | (SYS_IRQ << 31U);
+
+ vimREG->FIRQPR1 = SYS_IRQ
+ | (SYS_IRQ << 1U)
+ | (SYS_IRQ << 2U)
+ | (SYS_IRQ << 3U)
+ | (SYS_IRQ << 4U)
+ | (SYS_IRQ << 5U)
+ | (SYS_IRQ << 6U)
+ | (SYS_IRQ << 7U)
+ | (SYS_IRQ << 8U)
+ | (SYS_IRQ << 9U)
+ | (SYS_IRQ << 10U)
+ | (SYS_IRQ << 11U)
+ | (SYS_IRQ << 12U)
+ | (SYS_IRQ << 13U)
+ | (SYS_IRQ << 14U)
+ | (SYS_IRQ << 15U)
+ | (SYS_IRQ << 16U)
+ | (SYS_IRQ << 17U)
+ | (SYS_IRQ << 18U)
+ | (SYS_IRQ << 19U)
+ | (SYS_IRQ << 20U)
+ | (SYS_IRQ << 21U)
+ | (SYS_IRQ << 22U)
+ | (SYS_IRQ << 23U)
+ | (SYS_IRQ << 24U)
+ | (SYS_IRQ << 25U)
+ | (SYS_IRQ << 26U)
+ | (SYS_IRQ << 27U)
+ | (SYS_IRQ << 28U)
+ | (SYS_IRQ << 29U)
+ | (SYS_IRQ << 30U)
+ | (SYS_IRQ << 31U);
+
+
+ vimREG->FIRQPR2 = SYS_IRQ
+ | (SYS_IRQ << 1U)
+ | (SYS_IRQ << 2U)
+ | (SYS_IRQ << 3U)
+ | (SYS_IRQ << 4U)
+ | (SYS_IRQ << 5U)
+ | (SYS_IRQ << 6U)
+ | (SYS_IRQ << 7U)
+ | (SYS_IRQ << 8U)
+ | (SYS_IRQ << 9U)
+ | (SYS_IRQ << 10U)
+ | (SYS_IRQ << 11U)
+ | (SYS_IRQ << 12U)
+ | (SYS_FIQ << 13U) // EMAC
+ | (SYS_IRQ << 14U)
+ | (SYS_FIQ << 15U) // EMAC
+ | (SYS_IRQ << 16U)
+ | (SYS_IRQ << 17U)
+ | (SYS_IRQ << 18U)
+ | (SYS_IRQ << 19U)
+ | (SYS_IRQ << 20U)
+ | (SYS_IRQ << 21U)
+ | (SYS_IRQ << 22U)
+ | (SYS_IRQ << 23U)
+ | (SYS_IRQ << 24U)
+ | (SYS_IRQ << 25U)
+ | (SYS_IRQ << 26U)
+ | (SYS_IRQ << 27U)
+ | (SYS_IRQ << 28U)
+ | (SYS_IRQ << 29U)
+ | (SYS_IRQ << 30U)
+ | (SYS_IRQ << 31U);
+
+ vimREG->FIRQPR3 = SYS_IRQ
+ | (SYS_IRQ << 1U)
+ | (SYS_IRQ << 2U)
+ | (SYS_IRQ << 3U)
+ | (SYS_IRQ << 4U)
+ | (SYS_IRQ << 5U)
+ | (SYS_IRQ << 6U)
+ | (SYS_IRQ << 7U)
+ | (SYS_IRQ << 8U)
+ | (SYS_IRQ << 9U)
+ | (SYS_IRQ << 10U)
+ | (SYS_IRQ << 11U)
+ | (SYS_IRQ << 12U)
+ | (SYS_IRQ << 13U)
+ | (SYS_IRQ << 14U)
+ | (SYS_IRQ << 15U)
+ | (SYS_IRQ << 16U)
+ | (SYS_IRQ << 17U)
+ | (SYS_IRQ << 18U)
+ | (SYS_IRQ << 19U)
+ | (SYS_IRQ << 20U)
+ | (SYS_IRQ << 21U)
+ | (SYS_IRQ << 22U)
+ | (SYS_IRQ << 23U)
+ | (SYS_IRQ << 24U)
+ | (SYS_IRQ << 25U)
+ | (SYS_IRQ << 26U)
+ | (SYS_IRQ << 27U)
+ | (SYS_IRQ << 28U)
+ | (SYS_IRQ << 29U)
+ | (SYS_IRQ << 30U)
+ | (SYS_IRQ << 31U);
+
+
+ /* enable interrupts */
+ vimREG->REQMASKSET0 = 1U
+ | (1U << 1U)
+ | (1U << 2U)
+ | (0U << 3U)
+ | (0U << 4U)
+ | (0U << 5U)
+ | (0U << 6U)
+ | (0U << 7U)
+ | (0U << 8U)
+ | (0U << 9U)
+ | (0U << 10U)
+ | (0U << 11U)
+ | (1U << 12U)
+ | (1U << 13U)
+ | (0U << 14U)
+ | (1U << 15U)
+ | (1U << 16U)
+ | (1U << 17U)
+ | (0U << 18U)
+ | (0U << 19U)
+ | (0U << 20U)
+ | (0U << 21U)
+ | (0U << 22U)
+ | (0U << 23U)
+ | (0U << 24U)
+ | (0U << 25U)
+ | (1U << 26U)
+ | (0U << 27U)
+ | (0U << 28U)
+ | (0U << 29U)
+ | (1U << 30U)
+ | (0U << 31U);
+
+ vimREG->REQMASKSET1 = 0U
+ | (0U << 1U)
+ | (0U << 2U)
+ | (1U << 3U)
+ | (0U << 4U)
+ | (1U << 5U)
+ | (1U << 6U)
+ | (0U << 7U)
+ | (0U << 8U)
+ | (0U << 9U)
+ | (0U << 10U)
+ | (0U << 11U)
+ | (0U << 12U)
+ | (1U << 13U)
+ | (0U << 14U)
+ | (0U << 15U)
+ | (0U << 16U)
+ | (1U << 17U)
+ | (0U << 18U)
+ | (1U << 19U)
+ | (0U << 20U)
+ | (0U << 21U)
+ | (1U << 22U)
+ | (0U << 23U)
+ | (0U << 24U)
+ | (0U << 25U)
+ | (0U << 26U)
+ | (0U << 27U)
+ | (0U << 28U)
+ | (0U << 29U)
+ | (0U << 30U)
+ | (0U << 31U);
+
+ vimREG->REQMASKSET2 = 1U
+ | (0U << 1U)
+ | (0U << 2U)
+ | (0U << 3U)
+ | (0U << 4U)
+ | (0U << 5U)
+ | (0U << 6U)
+ | (0U << 7U)
+ | (0U << 8U)
+ | (0U << 9U)
+ | (0U << 10U)
+ | (0U << 11U)
+ | (0U << 12U)
+ | (1U << 13U) // EMACCore0TxIsr
+ | (0U << 14U)
+ | (1U << 15U) // EMACCore0RxIsr
+ | (0U << 16U)
+ | (0U << 17U)
+ | (0U << 18U)
+ | (0U << 19U)
+ | (0U << 20U)
+ | (0U << 21U)
+ | (0U << 22U)
+ | (0U << 23U)
+ | (0U << 24U)
+ | (0U << 25U)
+ | (0U << 26U)
+ | (0U << 27U)
+ | (0U << 28U)
+ | (0U << 29U)
+ | (0U << 30U)
+ | (0U << 31U);
+
+ vimREG->REQMASKSET3 = 0U
+ | (0U << 1U)
+ | (0U << 2U)
+ | (0U << 3U)
+ | (0U << 4U)
+ | (0U << 5U)
+ | (0U << 6U)
+ | (0U << 7U)
+ | (0U << 8U)
+ | (0U << 9U)
+ | (0U << 10U)
+ | (0U << 11U)
+ | (0U << 12U)
+ | (0U << 13U)
+ | (0U << 14U)
+ | (0U << 15U)
+ | (0U << 16U)
+ | (0U << 17U)
+ | (0U << 18U)
+ | (0U << 19U)
+ | (0U << 20U)
+ | (0U << 21U)
+ | (0U << 22U)
+ | (0U << 23U)
+ | (0U << 24U)
+ | (0U << 25U)
+ | (0U << 26U)
+ | (0U << 27U)
+ | (0U << 28U)
+ | (0U << 29U)
+ | (0U << 30U)
+ | (0U << 31U);
+
+/* USER CODE BEGIN (64) */
+/* USER CODE END */
+
+ /* Configure system response to error conditions signaled to the ESM group1 */
+ /* This function can be configured from the ESM tab of HALCoGen */
+ esmInit();
+
+ /* initalise copy table */
+ if ((uint32_t *)&__binit__ != (uint32_t *)0xFFFFFFFFU)
+ {
+ extern void copy_in(void *binit);
+ copy_in((void *)&__binit__);
+ }
+
+ /* initalise the C global variables */
+ if (&__TI_Handler_Table_Base < &__TI_Handler_Table_Limit)
+ {
+ uint8_t **tablePtr = (uint8_t **)&__TI_CINIT_Base;
+ uint8_t **tableLimit = (uint8_t **)&__TI_CINIT_Limit;
+
+ while (tablePtr < tableLimit)
+ {
+ uint8_t *loadAdr = *tablePtr++;
+ uint8_t *runAdr = *tablePtr++;
+ uint8_t idx = *loadAdr++;
+ handler_fptr handler = (handler_fptr)(&__TI_Handler_Table_Base)[idx];
+
+ (*handler)((const uint8_t *)loadAdr, runAdr);
+ }
+ }
+
+ /* initalise contructors */
+ if (__TI_PINIT_Base < __TI_PINIT_Limit)
+ {
+ void (**p0)() = (void *)__TI_PINIT_Base;
+
+ while ((uint32_t)p0 < __TI_PINIT_Limit)
+ {
+ void (*p)() = *p0++;
+ p();
+ }
+ }
+
+/* USER CODE BEGIN (65) */
+/* USER CODE END */
+
+ /* call the application */
+ main();
+
+/* USER CODE BEGIN (66) */
+/* USER CODE END */
+
+ exit();
+/* USER CODE BEGIN (67) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (68) */
+/* USER CODE END */
-/** @file system.c \r
-* @brief System Driver Source File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-* This file contains:\r
-* - API Funcions\r
-* .\r
-* which are relevant for the System driver.\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-\r
-/* Include Files */\r
-\r
-#include "system.h"\r
-#include "sys_selftest.h"\r
-#include "sys_pinmux.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-/** @fn void systemInit(void)\r
-* @brief Initializes System Driver\r
-*\r
-* This function initializes the System driver.\r
-*\r
-*/\r
-\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
-void setupPLL(void)\r
-{\r
-\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-\r
- /** - Configure PLL control registers */\r
- /** @b Initialize @b Pll1: */\r
-\r
- /** - Setup pll control register 1:\r
- * - Setup reset on oscillator slip \r
- * - Setup bypass on pll slip\r
- * - setup Pll output clock divider to max before Lock\r
- * - Setup reset on oscillator fail\r
- * - Setup reference clock divider \r
- * - Setup Pll multiplier \r
- */\r
- systemREG1->PLLCTL1 = 0x00000000U \r
- | 0x20000000U \r
- | ((0x1F)<< 24U) \r
- | 0x00000000U \r
- | ((6U - 1U)<< 16U) \r
- | ((120U - 1U)<< 8U);\r
-\r
- /** - Setup pll control register 2\r
- * - Enable/Disable frequency modulation\r
- * - Setup spreading rate\r
- * - Setup bandwidth adjustment\r
- * - Setup internal Pll output divider\r
- * - Setup spreading amount\r
- */\r
- systemREG1->PLLCTL2 = 0x00000000U\r
- | (255U << 22U)\r
- | (7U << 12U)\r
- | ((2U - 1U)<< 9U)\r
- | 61U;\r
-\r
- /** @b Initialize @b Pll2: */\r
-\r
- /** - Setup pll2 control register :\r
- * - setup Pll output clock divider to max before Lock\r
- * - Setup reference clock divider \r
- * - Setup internal Pll output divider\r
- * - Setup Pll multiplier \r
- */\r
- systemREG2->PLLCTL3 = ((2U - 1U) << 29U)\r
- | ((0x1F)<< 24U) \r
- | ((6U - 1U)<< 16U) \r
- | ((120U - 1U) << 8U);\r
- \r
- /** - Enable PLL(s) to start up or Lock */\r
- systemREG1->CSDIS = 0x00000000U \r
- | 0x00000000U \r
- | 0x00000008U \r
- | 0x00000080U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U;\r
-}\r
-\r
-void trimLPO(void)\r
-{\r
-\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-\r
- /** @b Initialize Lpo: */\r
- /** Load TRIM values from OTP if present else load user defined values */\r
- if(LPO_TRIM_VALUE != 0xFFFF)\r
- {\r
- \r
- systemREG1->LPOMONCTL = (1U << 24U)\r
- | LPO_TRIM_VALUE;\r
- }\r
- else\r
- {\r
-\r
- systemREG1->LPOMONCTL = (1U << 24U)\r
- | (16U << 8U)\r
- | 8U;\r
- }\r
-\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-void setupFlash(void)\r
-{\r
-\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
-\r
- /** - Setup flash read mode, address wait states and data wait states */\r
- flashWREG->FRDCNTL = 0x00000000U \r
- | (3U << 8U) \r
- | (1U << 4U) \r
- | 1U;\r
-\r
- /** - Setup flash access wait states for bank 7 */\r
- FSM_WR_ENA = 0x5;\r
- EEPROM_CONFIG = 0x00030002;\r
-\r
- /** - Disable write access to flash state machine registers */\r
- FSM_WR_ENA = 0xA;\r
-\r
- /** - Setup flash bank power modes */\r
- flashWREG->FBFALLBACK = 0x00000000\r
- | (SYS_ACTIVE << 14U) \r
- | (SYS_SLEEP << 12U) \r
- | (SYS_SLEEP << 10U) \r
- | (SYS_SLEEP << 8U) \r
- | (SYS_SLEEP << 6U) \r
- | (SYS_SLEEP << 4U) \r
- | (SYS_ACTIVE << 2U) \r
- | SYS_ACTIVE;\r
-\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-void periphInit(void)\r
-{\r
-\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
-\r
- /** - Disable Peripherals before peripheral powerup*/\r
- systemREG1->PENA = 0U;\r
-\r
- /** - Release peripherals from reset and enable clocks to all peripherals */\r
- /** - Power-up all peripharals */\r
- pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;\r
- pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;\r
- pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;\r
- pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;\r
-\r
- /** - Enable Peripherals */\r
- systemREG1->PENA = 1U;\r
- \r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-void mapClocks(void)\r
-{\r
- \r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
-\r
- /** @b Initialize @b Clock @b Tree: */\r
- /** - Diable / Enable clock domain */\r
- systemREG1->CDDIS= (FALSE << 4 ) /* AVCLK 1 OFF */\r
- |(FALSE << 5 ) /* AVCLK 2 OFF */\r
- |(FALSE << 8 ) /* VCLK3 OFF */\r
- |(FALSE << 10) /* AVCLK 3 OFF */\r
- |(FALSE << 11); /* AVCLK 4 OFF */\r
-\r
- /** - Wait for until clocks are locked */\r
- while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF))\r
- {\r
- }\r
-\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
-\r
- /* Now the PLLs are locked and the PLL outputs can be sped up */\r
- /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */\r
- systemREG1->PLLCTL1 = (systemREG1->PLLCTL1 & 0xE0FFFFFF)|((1U - 1U)<< 24U);\r
- systemREG2->PLLCTL3 = (systemREG2->PLLCTL3 & 0xE0FFFFFF)|((1U - 1U)<< 24U);\r
- \r
- /** - Map device clock domains to desired sources and configure top-level dividers */\r
- /** - All clock domains are working off the default clock sources until now */\r
- /** - The below assignments can be easily modified using the HALCoGen GUI */\r
- \r
- /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */\r
- systemREG1->GHVSRC = (SYS_PLL1 << 24U) \r
- | (SYS_PLL1 << 16U) \r
- | SYS_PLL1;\r
- \r
- /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */\r
- systemREG1->VCLKR = 1U;\r
- systemREG1->VCLK2R = 1U;\r
- systemREG2->VCLK3R = 1U;\r
-\r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
- \r
- /** - Setup RTICLK1 and RTICLK2 clocks */\r
- systemREG1->RCLKSRC = (1U << 24U)\r
- | (SYS_VCLK << 16U) \r
- | (1U << 8U) \r
- | SYS_VCLK;\r
-\r
- /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */\r
- systemREG1->VCLKASRC = (SYS_VCLK << 8U)\r
- | SYS_VCLK;\r
-\r
- systemREG2->VCLKACON1 = (1U << 24) \r
- | 1 << 20U \r
- | (SYS_VCLK << 16)\r
- | (1U << 8)\r
- | 1 << 4U \r
- | SYS_VCLK;\r
-\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-void systemInit(void)\r
-{\r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
-\r
- /* Configure PLL control registers and enable PLLs.\r
- * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.\r
- * This initialization sequence performs all the tasks that are not\r
- * required to be done at full application speed while the PLL locks.\r
- */\r
- setupPLL();\r
- \r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
-\r
- /* Run eFuse controller start-up checks and start eFuse controller ECC self-test.\r
- * This includes a check for the eFuse controller error outputs to be stuck-at-zero.\r
- */\r
- efcCheck();\r
- \r
-/* USER CODE BEGIN (16) */\r
-/* USER CODE END */\r
- \r
- /* Enable clocks to peripherals and release peripheral reset */\r
- periphInit();\r
-\r
-/* USER CODE BEGIN (17) */\r
-/* USER CODE END */\r
-\r
- /* Configure device-level multiplexing and I/O multiplexing */\r
- muxInit();\r
- \r
-/* USER CODE BEGIN (18) */\r
-/* USER CODE END */\r
-\r
- /* Wait for eFuse controller self-test to complete and check results */\r
- if (!checkefcSelfTest()) /* eFuse controller ECC logic self-test failed */\r
- {\r
- efcClass2Error(); /* device operation is not reliable */\r
- }\r
- \r
-/* USER CODE BEGIN (19) */\r
-/* USER CODE END */\r
-\r
- /** - Set up flash address and data wait states based on the target CPU clock frequency\r
- * The number of address and data wait states for the target CPU clock frequency are specified\r
- * in the specific part's datasheet.\r
- */\r
- setupFlash();\r
-\r
-/* USER CODE BEGIN (20) */\r
-/* USER CODE END */\r
-\r
- /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */\r
- trimLPO();\r
-\r
-/* USER CODE BEGIN (21) */\r
-/* USER CODE END */\r
-\r
- /** - Check if there was an ESM error from FMC OTP read during power-up */\r
- fmcBus2Check();\r
- \r
-/* USER CODE BEGIN (22) */\r
-/* USER CODE END */\r
-\r
- /** - Wait for PLLs to start up and map clock domains to desired clock sources */\r
- mapClocks();\r
-\r
-/* USER CODE BEGIN (23) */\r
-/* USER CODE END */\r
-\r
- /** - set ECLK pins functional mode */\r
- systemREG1->SYSPC1 = 0U;\r
-\r
- /** - set ECLK pins default output value */\r
- systemREG1->SYSPC4 = 0U;\r
-\r
- /** - set ECLK pins output direction */\r
- systemREG1->SYSPC2 = 1U;\r
-\r
- /** - set ECLK pins open drain enable */\r
- systemREG1->SYSPC7 = 0U;\r
-\r
- /** - set ECLK pins pullup/pulldown enable */\r
- systemREG1->SYSPC8 = 0U; \r
-\r
- /** - set ECLK pins pullup/pulldown select */\r
- systemREG1->SYSPC9 = 1U;\r
-\r
- /** - Setup ECLK */\r
- systemREG1->ECPCNTL = (0U << 24U)\r
- | (0U << 23U)\r
- | ((8U - 1U) & 0xFFFFU);\r
-\r
-/* USER CODE BEGIN (24) */\r
-/* USER CODE END */\r
-}\r
-\r
-void systemPowerDown(uint32_t mode)\r
-{\r
-\r
-/* USER CODE BEGIN (25) */\r
-/* USER CODE END */\r
-\r
- /* Disable clock sources */\r
- systemREG1->CSDISSET = mode & 0x000000FFU;\r
-\r
- /* Disable clock domains */\r
- systemREG1->CDDIS = (mode >> 8U) & 0x00000FFFU;\r
-\r
- /* Idle CPU */\r
- asm(" wfi");\r
-\r
-/* USER CODE BEGIN (26) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-/* USER CODE BEGIN (27) */\r
-/* USER CODE END */\r
+/** @file system.c
+* @brief System Driver Source File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+* This file contains:
+* - API Funcions
+* .
+* which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* Include Files */
+
+#include "system.h"
+#include "sys_selftest.h"
+#include "sys_pinmux.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void systemInit(void)
+* @brief Initializes System Driver
+*
+* This function initializes the System driver.
+*
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+void setupPLL(void)
+{
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+ /** - Configure PLL control registers */
+ /** @b Initialize @b Pll1: */
+
+ /** - Setup pll control register 1:
+ * - Setup reset on oscillator slip
+ * - Setup bypass on pll slip
+ * - setup Pll output clock divider to max before Lock
+ * - Setup reset on oscillator fail
+ * - Setup reference clock divider
+ * - Setup Pll multiplier
+ */
+ systemREG1->PLLCTL1 = 0x00000000U
+ | 0x20000000U
+ | ((0x1F)<< 24U)
+ | 0x00000000U
+ | ((6U - 1U)<< 16U)
+ | ((120U - 1U)<< 8U);
+
+ /** - Setup pll control register 2
+ * - Enable/Disable frequency modulation
+ * - Setup spreading rate
+ * - Setup bandwidth adjustment
+ * - Setup internal Pll output divider
+ * - Setup spreading amount
+ */
+ systemREG1->PLLCTL2 = 0x00000000U
+ | (255U << 22U)
+ | (7U << 12U)
+ | ((2U - 1U)<< 9U)
+ | 61U;
+
+ /** @b Initialize @b Pll2: */
+
+ /** - Setup pll2 control register :
+ * - setup Pll output clock divider to max before Lock
+ * - Setup reference clock divider
+ * - Setup internal Pll output divider
+ * - Setup Pll multiplier
+ */
+ systemREG2->PLLCTL3 = ((2U - 1U) << 29U)
+ | ((0x1F)<< 24U)
+ | ((6U - 1U)<< 16U)
+ | ((120U - 1U) << 8U);
+
+ /** - Enable PLL(s) to start up or Lock */
+ systemREG1->CSDIS = 0x00000000U
+ | 0x00000000U
+ | 0x00000008U
+ | 0x00000080U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+}
+
+void trimLPO(void)
+{
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+ /** @b Initialize Lpo: */
+ /** Load TRIM values from OTP if present else load user defined values */
+ if(LPO_TRIM_VALUE != 0xFFFF)
+ {
+
+ systemREG1->LPOMONCTL = (1U << 24U)
+ | LPO_TRIM_VALUE;
+ }
+ else
+ {
+
+ systemREG1->LPOMONCTL = (1U << 24U)
+ | (16U << 8U)
+ | 8U;
+ }
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+}
+
+void setupFlash(void)
+{
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+ /** - Setup flash read mode, address wait states and data wait states */
+ flashWREG->FRDCNTL = 0x00000000U
+ | (3U << 8U)
+ | (1U << 4U)
+ | 1U;
+
+ /** - Setup flash access wait states for bank 7 */
+ FSM_WR_ENA = 0x5;
+ EEPROM_CONFIG = 0x00030002;
+
+ /** - Disable write access to flash state machine registers */
+ FSM_WR_ENA = 0xA;
+
+ /** - Setup flash bank power modes */
+ flashWREG->FBFALLBACK = 0x00000000
+ | (SYS_ACTIVE << 14U)
+ | (SYS_SLEEP << 12U)
+ | (SYS_SLEEP << 10U)
+ | (SYS_SLEEP << 8U)
+ | (SYS_SLEEP << 6U)
+ | (SYS_SLEEP << 4U)
+ | (SYS_ACTIVE << 2U)
+ | SYS_ACTIVE;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+}
+
+void periphInit(void)
+{
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ /** - Disable Peripherals before peripheral powerup*/
+ systemREG1->PENA = 0U;
+
+ /** - Release peripherals from reset and enable clocks to all peripherals */
+ /** - Power-up all peripharals */
+ pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;
+ pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;
+ pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;
+ pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;
+
+ /** - Enable Peripherals */
+ systemREG1->PENA = 1U;
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+}
+
+void mapClocks(void)
+{
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+ /** @b Initialize @b Clock @b Tree: */
+ /** - Diable / Enable clock domain */
+ systemREG1->CDDIS= (FALSE << 4 ) /* AVCLK 1 OFF */
+ |(FALSE << 5 ) /* AVCLK 2 OFF */
+ |(FALSE << 8 ) /* VCLK3 OFF */
+ |(FALSE << 10) /* AVCLK 3 OFF */
+ |(FALSE << 11); /* AVCLK 4 OFF */
+
+ /** - Wait for until clocks are locked */
+ while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF))
+ {
+ }
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ /* Now the PLLs are locked and the PLL outputs can be sped up */
+ /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
+ systemREG1->PLLCTL1 = (systemREG1->PLLCTL1 & 0xE0FFFFFF)|((1U - 1U)<< 24U);
+ systemREG2->PLLCTL3 = (systemREG2->PLLCTL3 & 0xE0FFFFFF)|((1U - 1U)<< 24U);
+
+ /** - Map device clock domains to desired sources and configure top-level dividers */
+ /** - All clock domains are working off the default clock sources until now */
+ /** - The below assignments can be easily modified using the HALCoGen GUI */
+
+ /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
+ systemREG1->GHVSRC = (SYS_PLL1 << 24U)
+ | (SYS_PLL1 << 16U)
+ | SYS_PLL1;
+
+ /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
+ systemREG1->VCLKR = 1U;
+ systemREG1->VCLK2R = 1U;
+ systemREG2->VCLK3R = 1U;
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+ /** - Setup RTICLK1 and RTICLK2 clocks */
+ systemREG1->RCLKSRC = (1U << 24U)
+ | (SYS_VCLK << 16U)
+ | (1U << 8U)
+ | SYS_VCLK;
+
+ /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
+ systemREG1->VCLKASRC = (SYS_VCLK << 8U)
+ | SYS_VCLK;
+
+ systemREG2->VCLKACON1 = (1U << 24)
+ | 1 << 20U
+ | (SYS_VCLK << 16)
+ | (1U << 8)
+ | 1 << 4U
+ | SYS_VCLK;
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+}
+
+void systemInit(void)
+{
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+ /* Configure PLL control registers and enable PLLs.
+ * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
+ * This initialization sequence performs all the tasks that are not
+ * required to be done at full application speed while the PLL locks.
+ */
+ setupPLL();
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ /* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
+ * This includes a check for the eFuse controller error outputs to be stuck-at-zero.
+ */
+ efcCheck();
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+ /* Enable clocks to peripherals and release peripheral reset */
+ periphInit();
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ /* Configure device-level multiplexing and I/O multiplexing */
+ muxInit();
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+ /* Wait for eFuse controller self-test to complete and check results */
+ if (!checkefcSelfTest()) /* eFuse controller ECC logic self-test failed */
+ {
+ efcClass2Error(); /* device operation is not reliable */
+ }
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ /** - Set up flash address and data wait states based on the target CPU clock frequency
+ * The number of address and data wait states for the target CPU clock frequency are specified
+ * in the specific part's datasheet.
+ */
+ setupFlash();
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+ /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
+ trimLPO();
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+ /** - Check if there was an ESM error from FMC OTP read during power-up */
+ fmcBus2Check();
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+ /** - Wait for PLLs to start up and map clock domains to desired clock sources */
+ mapClocks();
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+ /** - set ECLK pins functional mode */
+ systemREG1->SYSPC1 = 0U;
+
+ /** - set ECLK pins default output value */
+ systemREG1->SYSPC4 = 0U;
+
+ /** - set ECLK pins output direction */
+ systemREG1->SYSPC2 = 1U;
+
+ /** - set ECLK pins open drain enable */
+ systemREG1->SYSPC7 = 0U;
+
+ /** - set ECLK pins pullup/pulldown enable */
+ systemREG1->SYSPC8 = 0U;
+
+ /** - set ECLK pins pullup/pulldown select */
+ systemREG1->SYSPC9 = 1U;
+
+ /** - Setup ECLK */
+ systemREG1->ECPCNTL = (0U << 24U)
+ | (0U << 23U)
+ | ((8U - 1U) & 0xFFFFU);
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+void systemPowerDown(uint32_t mode)
+{
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+ /* Disable clock sources */
+ systemREG1->CSDISSET = mode & 0x000000FFU;
+
+ /* Disable clock domains */
+ systemREG1->CDDIS = (mode >> 8U) & 0x00000FFFU;
+
+ /* Idle CPU */
+ asm(" wfi");
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+}
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
-/** @file adc.c \r
-* @brief ADC Driver Source File\r
-* @date 04.January.2012\r
-* @version 03.01.00\r
-*\r
-* This file contains:\r
-* - API Funcions\r
-* - Interrupt Handlers\r
-* .\r
-* which are relevant for the ADC driver.\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-/* Include Files */\r
-\r
-#include "ti_drv_adc.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adcInit(void)\r
-* @brief Initializes ADC Driver\r
-*\r
-* This function initializes the ADC driver.\r
-*\r
-*/\r
-\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
-void adcInit(void)\r
-{\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-\r
-\r
-\r
- /** @b Initialize @b ADC1: */\r
-\r
- /** - Reset ADC module */\r
- adcREG1->RSTCR = 1U;\r
- adcREG1->RSTCR = 0U;\r
-\r
- /** - Enable 12-BIT ADC */\r
- adcREG1->OPMODECR |= 0x80000000U;\r
- \r
- /** - Setup prescaler */\r
- adcREG1->CLOCKCR = 7U;\r
- \r
- /** - Setup memory boundaries */\r
- adcREG1->BNDCR =(8U << 16U)|(8U + 8U);\r
- adcREG1->BNDEND = 2U;\r
- \r
- /** - Setup event group conversion mode\r
- * - Setup data format\r
- * - Enable/Disable channel id in conversion result\r
- * - Enable/Disable continuous conversion\r
- */\r
- adcREG1->GxMODECR[0U] = ADC_12_BIT\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Setup event group hardware trigger\r
- * - Setup hardware trigger edge\r
- * - Setup hardware trigger source\r
- */\r
- adcREG1->G0SRC = 0x00000000U\r
- | ADC1_EVENT;\r
-\r
- /** - Setup event group sample window */\r
- adcREG1->G0SAMP = 0U;\r
-\r
- /** - Setup event group sample discharge \r
- * - Setup discharge prescaler\r
- * - Enable/Disable discharge\r
- */\r
- adcREG1->G0SAMPDISEN = 0U << 8U\r
- | 0x00000000U;\r
-\r
- /** - Setup group 1 conversion mode\r
- * - Setup data format\r
- * - Enable/Disable channel id in conversion result\r
- * - Enable/Disable continuous conversion\r
- */\r
- adcREG1->GxMODECR[1U] = ADC_12_BIT\r
- | 0x00000020U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Setup group 1 hardware trigger\r
- * - Setup hardware trigger edge\r
- * - Setup hardware trigger source\r
- */\r
- adcREG1->G1SRC = 0x00000000U\r
- | ADC1_EVENT;\r
-\r
- /** - Setup group 1 sample window */\r
- adcREG1->G1SAMP = 0U;\r
-\r
- /** - Setup group 1 sample discharge \r
- * - Setup discharge prescaler\r
- * - Enable/Disable discharge\r
- */\r
- adcREG1->G1SAMPDISEN = 0U << 8U\r
- | 0x00000000U;\r
-\r
- /** - Setup group 2 conversion mode\r
- * - Setup data format\r
- * - Enable/Disable channel id in conversion result\r
- * - Enable/Disable continuous conversion\r
- */\r
- adcREG1->GxMODECR[2U] = ADC_12_BIT\r
- | 0x00000020U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Setup group 2 hardware trigger\r
- * - Setup hardware trigger edge\r
- * - Setup hardware trigger source\r
- */\r
- adcREG1->G2SRC = 0x00000000U\r
- | ADC1_EVENT;\r
-\r
- /** - Setup group 2 sample window */\r
- adcREG1->G2SAMP = 0U;\r
-\r
- /** - Setup group 2 sample discharge \r
- * - Setup discharge prescaler\r
- * - Enable/Disable discharge\r
- */\r
- adcREG1->G2SAMPDISEN = 0U << 8U\r
- | 0x00000000U;\r
-\r
- /** - Enable ADC module */\r
- adcREG1->OPMODECR |= 0x80140001U;\r
-\r
- /** - Wait for buffer inialisation complete */\r
- while ((adcREG1->BUFINIT) != 0) { /* Wait */ } \r
- \r
- /** - Setup parity */\r
- adcREG1->PARCR = 0x00000005U;\r
-\r
-\r
-\r
- /** @b Initialize @b ADC2: */\r
-\r
- /** - Reset ADC module */\r
- adcREG2->RSTCR = 1U;\r
- adcREG2->RSTCR = 0U;\r
- \r
- /** - Enable 12-BIT ADC */\r
- adcREG2->OPMODECR |= 0x80000000U;\r
- \r
- /** - Setup prescaler */\r
- adcREG2->CLOCKCR = 7U;\r
- \r
- /** - Setup memory boundaries */\r
- adcREG2->BNDCR =(8U << 16U)|(8U + 8U);\r
- adcREG2->BNDEND = 2U;\r
- \r
- /** - Setup event group conversion mode\r
- * - Setup data format\r
- * - Enable/Disable channel id in conversion result\r
- * - Enable/Disable continuous conversion\r
- */\r
- adcREG2->GxMODECR[0U] = ADC_12_BIT\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Setup event group hardware trigger\r
- * - Setup hardware trigger edge\r
- * - Setup hardware trigger source\r
- */\r
- adcREG2->G0SRC = 0x00000000U\r
- | ADC2_EVENT;\r
-\r
- /** - Setup event group sample window */\r
- adcREG2->G0SAMP = 0U;\r
-\r
- /** - Setup event group sample discharge \r
- * - Setup discharge prescaler\r
- * - Enable/Disable discharge\r
- */\r
- adcREG2->G0SAMPDISEN = 0U << 8U\r
- | 0x00000000U;\r
-\r
- /** - Setup group 1 conversion mode\r
- * - Setup data format\r
- * - Enable/Disable channel id in conversion result\r
- * - Enable/Disable continuous conversion\r
- */\r
- adcREG2->GxMODECR[1U] = ADC_12_BIT\r
- | 0x00000020U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Setup group 1 hardware trigger\r
- * - Setup hardware trigger edge\r
- * - Setup hardware trigger source\r
- */\r
- adcREG2->G1SRC = 0x00000000U\r
- | ADC2_EVENT;\r
-\r
-\r
- /** - Setup group 1 sample window */\r
- adcREG2->G1SAMP = 0U;\r
-\r
- /** - Setup group 1 sample discharge \r
- * - Setup discharge prescaler\r
- * - Enable/Disable discharge\r
- */\r
- adcREG2->G1SAMPDISEN = 0U << 8U\r
- | 0x00000000U;\r
-\r
- /** - Setup group 2 conversion mode\r
- * - Setup data format\r
- * - Enable/Disable channel id in conversion result\r
- * - Enable/Disable continuous conversion\r
- */\r
- adcREG2->GxMODECR[2U] = ADC_12_BIT\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Setup group 2 hardware trigger\r
- * - Setup hardware trigger edge\r
- * - Setup hardware trigger source\r
- */\r
- adcREG2->G2SRC = 0x00000000U\r
- | ADC2_EVENT;\r
-\r
- /** - Setup group 2 sample window */\r
- adcREG2->G2SAMP = 0U;\r
-\r
- /** - Setup group 2 sample discharge \r
- * - Setup discharge prescaler\r
- * - Enable/Disable discharge\r
- */\r
- adcREG2->G2SAMPDISEN = 0U << 8U\r
- | 0x00000000U;\r
-\r
- /** - Enable ADC module */\r
- adcREG2->OPMODECR |= 0x80140001U;\r
-\r
- /** - Wait for buffer inialisation complete */\r
- while ((adcREG2->BUFINIT) != 0) { /* Wait */ } \r
- \r
- /** - Setup parity */\r
- adcREG2->PARCR = 0x00000005U;\r
-\r
- /** @note This function has to be called before the driver can be used.\n\r
- * This function has to be executed in priviledged mode.\n\r
- */\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adcStartConversion(adcBASE_t *adc, uint32_t group)\r
-* @brief Starts an ADC conversion\r
-* @param[in] adc Pointer to ADC module:\r
-* - adcREG1: ADC1 module pointer\r
-* - adcREG2: ADC2 module pointer\r
-* @param[in] group Hardware group of ADC module:\r
-* - adcGROUP0: ADC event group\r
-* - adcGROUP1: ADC group 1\r
-* - adcGROUP2: ADC group 2\r
-*\r
-* This function starts a convesion of the ADC hardware group.\r
-*\r
-*/\r
-\r
-/** - s_adcSelect is used as constant table for channel selection */\r
-static const uint32_t s_adcSelect[2U][3U] =\r
-{\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U,\r
- 0x00000001U |\r
- 0x00000002U |\r
- 0x00000004U |\r
- 0x00000008U |\r
- 0x00000010U |\r
- 0x00000020U |\r
- 0x00000040U |\r
- 0x00000080U |\r
- 0x00000100U |\r
- 0x00000200U |\r
- 0x00000400U |\r
- 0x00000800U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U,\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U,\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U ,\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000004U |\r
- 0x00000008U |\r
- 0x00000010U |\r
- 0x00000020U |\r
- 0x00000040U |\r
- 0x00000080U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U,\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U |\r
- 0x00000000U,\r
-};\r
-\r
-/** - s_adcSelect is used as constant table for channel selection */\r
-static const uint32_t s_adcFiFoSize[2U][3U] =\r
-{\r
- 16U,\r
- 16U,\r
- 16U,\r
- 16U,\r
- 16U,\r
- 16U,\r
-};\r
-\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
-\r
-void adcStartConversion(adcBASE_t *adc, uint32_t group)\r
-{\r
- uint32_t index = adc == adcREG1 ? 0U : 1U;\r
-\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
-\r
- /** - Setup FiFo size */\r
- adc->GxINTCR[group] = s_adcFiFoSize[index][group];\r
-\r
- /** - Start Conversion */\r
- adc->GxSEL[group] = s_adcSelect[index][group];\r
-\r
- /** @note The function adcInit has to be called before this function can be used. */\r
-\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adcStopConversion(adcBASE_t *adc, uint32_t group)\r
-* @brief Stops an ADC conversion\r
-* @param[in] adc Pointer to ADC module:\r
-* - adcREG1: ADC1 module pointer\r
-* - adcREG2: ADC2 module pointer\r
-* @param[in] group Hardware group of ADC module:\r
-* - adcGROUP0: ADC event group\r
-* - adcGROUP1: ADC group 1\r
-* - adcGROUP2: ADC group 2\r
-*\r
-* This function stops a convesion of the ADC hardware group.\r
-*\r
-*/\r
-\r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
-\r
-void adcStopConversion(adcBASE_t *adc, uint32_t group)\r
-{\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
-\r
- /** - Stop Conversion */\r
- adc->GxSEL[group] = 0U;\r
-\r
- /** @note The function adcInit has to be called before this function can be used. */\r
-\r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adcResetFiFo(adcBASE_t *adc, uint32_t group)\r
-* @brief Resets FiFo read and write pointer.\r
-* @param[in] adc Pointer to ADC module:\r
-* - adcREG1: ADC1 module pointer\r
-* - adcREG2: ADC2 module pointer\r
-* @param[in] group Hardware group of ADC module:\r
-* - adcGROUP0: ADC event group\r
-* - adcGROUP1: ADC group 1\r
-* - adcGROUP2: ADC group 2\r
-*\r
-* This function resets the FiFo read and write pointrs.\r
-*\r
-*/\r
-\r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
-\r
-void adcResetFiFo(adcBASE_t *adc, uint32_t group)\r
-{\r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
-\r
- /** - Reset FiFo */\r
- adc->GxFIFORESETCR[group] = 1U;\r
-\r
- /** @note The function adcInit has to be called before this function can be used.\n\r
- * the conversion should be stopped before calling this function. \r
- */\r
-\r
-/* USER CODE BEGIN (16) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (17) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn uint32_t adcGetData(adcBASE_t *adc, uint32_t group, adcData_t *data)\r
-* @brief Gets converted a ADC values\r
-* @param[in] adc Pointer to ADC module:\r
-* - adcREG1: ADC1 module pointer\r
-* - adcREG2: ADC2 module pointer\r
-* - adcREG3: ADC3 module pointer\r
-* @param[in] group Hardware group of ADC module:\r
-* - adcGROUP0: ADC event group\r
-* - adcGROUP1: ADC group 1\r
-* - adcGROUP2: ADC group 2\r
-* @param[out] data Pointer to store ADC converted data\r
-* @return The function will return the number of converted values copied into data buffer:\r
-*\r
-* This function writes a ADC message into a ADC message box.\r
-*\r
-*/\r
-\r
-\r
-/* USER CODE BEGIN (18) */\r
-/* USER CODE END */\r
-\r
-uint32_t adcGetData(adcBASE_t *adc, uint32_t group, adcData_t *data)\r
-{\r
- uint32_t i;\r
- uint32_t buf;\r
- uint32_t mode; \r
- uint32_t index = adc == adcREG1 ? 0U : 1U;\r
- uint32_t count = adc->GxINTCR[group] >= 256U ? s_adcFiFoSize[index][group] : s_adcFiFoSize[index][group] - (uint32_t)(adc->GxINTCR[group] & 0xFF);\r
- adcData_t *ptr = data; \r
-\r
-/* USER CODE BEGIN (19) */\r
-/* USER CODE END */\r
-\r
- mode = ((adc->GxMODECR[group]) & 0x00000300U);\r
-\r
- if(mode == ADC_12_BIT)\r
- {\r
- /** - Get conversion data and channel/pin id */\r
- for (i = 0; i < count; i++)\r
- {\r
- buf = adc->GxBUF[group].BUF0;\r
- ptr->value = (uint16_t)(buf & 0xFFFU);\r
- ptr->id = (uint32_t)((buf >> 16U) & 0x1FU);\r
- ptr++;\r
- }\r
- }\r
- else\r
- {\r
- /** - Get conversion data and channel/pin id */\r
- for (i = 0; i < count; i++)\r
- {\r
- buf = adc->GxBUF[group].BUF0;\r
- ptr->value = (uint16_t)(buf & 0x3FFU);\r
- ptr->id = (uint32_t)((buf >> 10U) & 0x1FU);\r
- ptr++;\r
- }\r
- }\r
-\r
-\r
- adc->GxINTFLG[group] = 9U;\r
-\r
- /** @note The function adcInit has to be called before this function can be used.\n\r
- * The user is responsible to initialize the message box.\r
- */\r
-\r
-/* USER CODE BEGIN (20) */\r
-/* USER CODE END */\r
-\r
- return count;\r
-}\r
-\r
-/* USER CODE BEGIN (21) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn uint32_t adcIsFifoFull(adcBASE_t *adc, uint32_t group)\r
-* @brief Checks if FiFo buffer is full\r
-* @param[in] adc Pointer to ADC module:\r
-* - adcREG1: ADC1 module pointer\r
-* - adcREG2: ADC2 module pointer\r
-* - adcREG3: ADC3 module pointer\r
-* @param[in] group Hardware group of ADC module:\r
-* - adcGROUP0: ADC event group\r
-* - adcGROUP1: ADC group 1\r
-* - adcGROUP2: ADC group 2\r
-* @return The function will return:\r
-* - 0: When FiFo buffer is not full \r
-* - 1: When FiFo buffer is full \r
-* - 3: When FiFo buffer overflow occured \r
-*\r
-* This function checks FiFo buffer status.\r
-*\r
-*/\r
-\r
-\r
-/* USER CODE BEGIN (22) */\r
-/* USER CODE END */\r
-\r
-uint32_t adcIsFifoFull(adcBASE_t *adc, uint32_t group)\r
-{\r
- uint32_t flags;\r
-\r
-/* USER CODE BEGIN (23) */\r
-/* USER CODE END */\r
-\r
- /** - Read FiFo flags */\r
- flags = adc->GxINTFLG[group] & 3U;\r
-\r
- /** @note The function adcInit has to be called before this function can be used. */\r
-\r
-/* USER CODE BEGIN (24) */\r
-/* USER CODE END */\r
-\r
- return flags;\r
-}\r
-\r
-/* USER CODE BEGIN (25) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn uint32_t adcIsConversionComplete(adcBASE_t *adc, uint32_t group)\r
-* @brief Checks if Conversion is complete\r
-* @param[in] adc Pointer to ADC module:\r
-* - adcREG1: ADC1 module pointer\r
-* - adcREG2: ADC2 module pointer\r
-* - adcREG3: ADC3 module pointer\r
-* @param[in] group Hardware group of ADC module:\r
-* - adcGROUP0: ADC event group\r
-* - adcGROUP1: ADC group 1\r
-* - adcGROUP2: ADC group 2\r
-* @return The function will return:\r
-* - 0: When is not finished \r
-* - 8: When conversion is complete \r
-*\r
-* This function checks if conversion is complete.\r
-*\r
-*/\r
-\r
-\r
-/* USER CODE BEGIN (26) */\r
-/* USER CODE END */\r
-\r
-uint32_t adcIsConversionComplete(adcBASE_t *adc, uint32_t group)\r
-{\r
- uint32_t flags;\r
-\r
-/* USER CODE BEGIN (27) */\r
-/* USER CODE END */\r
-\r
- /** - Read conversion flags */\r
- flags = adc->GxINTFLG[group] & 8U;\r
-\r
- /** @note The function adcInit has to be called before this function can be used. */\r
-\r
-/* USER CODE BEGIN (28) */\r
-/* USER CODE END */\r
-\r
- return flags;\r
-}\r
-\r
-/* USER CODE BEGIN (29) */\r
-/* USER CODE END */\r
-\r
-/** @fn void adcCalibration(adcBASE_t *adc)\r
-* @brief Computes offset error using Calibration mode\r
-* @param[in] adc Pointer to ADC module:\r
-* - adcREG1: ADC1 module pointer\r
-* - adcREG2: ADC2 module pointer\r
-* - adcREG3: ADC3 module pointer\r
-* This function computes offset error using Calibration mode\r
-*\r
-*/\r
-void adcCalibration(adcBASE_t *adc)\r
-{\r
-/* USER CODE BEGIN (30) */\r
-/* USER CODE END */\r
- \r
- uint32_t conv_val[5]={0,0,0,0,0},loop_index=0;\r
- uint32_t offset_error=0;\r
- uint32_t backup_mode;\r
- \r
- /** - Backup Mode before Calibration */\r
- backup_mode = adc->OPMODECR;\r
- \r
- /** - Enable 12-BIT ADC */\r
- adcREG1->OPMODECR |= 0x80000000U;\r
-\r
- /* Disable all channels for conversion */\r
- adc->GxSEL[0]=0x00;\r
- adc->GxSEL[1]=0x00;\r
- adc->GxSEL[2]=0x00;\r
-\r
- for(loop_index=0;loop_index<4;loop_index++)\r
- {\r
- /* Disable Self Test and Calibration mode */\r
- adc->CALCR=0x0;\r
- \r
- switch(loop_index)\r
- {\r
- case 0 : /* Test 1 : Bride En = 0 , HiLo =0 */\r
- adc->CALCR=0x0;\r
- break;\r
-\r
- case 1 : /* Test 1 : Bride En = 0 , HiLo =1 */\r
- adc->CALCR=0x0100;\r
- break;\r
-\r
- case 2 : /* Test 1 : Bride En = 1 , HiLo =0 */\r
- adc->CALCR=0x0200;\r
- break;\r
- \r
- case 3 : /* Test 1 : Bride En = 1 , HiLo =1 */\r
- adc->CALCR=0x0300;\r
- break;\r
- }\r
- \r
- /* Enable Calibration mode */\r
- adc->CALCR|=0x1;\r
- \r
- /* Start calibration conversion */\r
- adc->CALCR|=0x00010000;\r
-\r
- /* Wait for calibration conversion to complete */\r
- while((adc->CALCR & 0x00010000)==0x00010000);\r
-\r
- /* Read converted value */\r
- conv_val[loop_index]= adc->CALR;\r
- }\r
-\r
- /* Disable Self Test and Calibration mode */\r
- adc->CALCR=0x0;\r
-\r
- /* Compute the Offset error correction value */\r
- conv_val[4]=conv_val[0]+ conv_val[1] + conv_val[2] + conv_val[3];\r
-\r
- conv_val[4]=(conv_val[4]/4);\r
-\r
- offset_error=conv_val[4]-0x7FF;\r
-\r
- /*Write the offset error to the Calibration register */\r
- /* Load 2;s complement of the computed value to ADCALR register */\r
- offset_error=~offset_error;\r
- offset_error=offset_error & 0xFFF;\r
- offset_error=offset_error+1;\r
-\r
- adc->CALR = offset_error;\r
-\r
- /** - Restore Mode after Calibration */\r
- adc->OPMODECR = backup_mode;\r
- \r
- /** @note The function adcInit has to be called before using this function. */\r
-\r
-/* USER CODE BEGIN (31) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void adcMidPointCalibration(adcBASE_t *adc)\r
-* @brief Computes offset error using Mid Point Calibration mode\r
-* @param[in] adc Pointer to ADC module:\r
-* - adcREG1: ADC1 module pointer\r
-* - adcREG2: ADC2 module pointer\r
-* - adcREG3: ADC3 module pointer\r
-* This function computes offset error using Mid Point Calibration mode\r
-*\r
-*/\r
-\r
-/* USER CODE BEGIN (32) */\r
-/* USER CODE END */\r
-\r
-uint32_t adcMidPointCalibration(adcBASE_t *adc)\r
-{\r
-/* USER CODE BEGIN (33) */\r
-/* USER CODE END */\r
- \r
- uint32_t conv_val[3]={0,0,0},loop_index=0;\r
- uint32_t offset_error=0;\r
- uint32_t backup_mode;\r
- \r
- /** - Backup Mode before Calibration */\r
- backup_mode = adc->OPMODECR;\r
- \r
- /** - Enable 12-BIT ADC */\r
- adcREG1->OPMODECR |= 0x80000000U;\r
-\r
- /* Disable all channels for conversion */\r
- adc->GxSEL[0]=0x00;\r
- adc->GxSEL[1]=0x00;\r
- adc->GxSEL[2]=0x00;\r
-\r
- for(loop_index=0;loop_index<2;loop_index++)\r
- {\r
- /* Disable Self Test and Calibration mode */\r
- adc->CALCR=0x0;\r
- \r
- switch(loop_index)\r
- {\r
- case 0 : /* Test 1 : Bride En = 0 , HiLo =0 */\r
- adc->CALCR=0x0;\r
- break;\r
-\r
- case 1 : /* Test 1 : Bride En = 0 , HiLo =1 */\r
- adc->CALCR=0x0100;\r
- break;\r
-\r
- }\r
- \r
- /* Enable Calibration mode */\r
- adc->CALCR|=0x1;\r
- \r
- /* Start calibration conversion */\r
- adc->CALCR|=0x00010000;\r
-\r
- /* Wait for calibration conversion to complete */\r
- while((adc->CALCR & 0x00010000)==0x00010000);\r
-\r
- /* Read converted value */\r
- conv_val[loop_index]= adc->CALR;\r
- }\r
-\r
- /* Disable Self Test and Calibration mode */\r
- adc->CALCR=0x0;\r
-\r
- /* Compute the Offset error correction value */\r
- conv_val[2]=(conv_val[0])+ (conv_val[1]);\r
-\r
- conv_val[2]=(conv_val[2]/2);\r
-\r
- offset_error=conv_val[2]-0x7FF;\r
-\r
- /* Write the offset error to the Calibration register */\r
- /* Load 2's complement of the computed value to ADCALR register */\r
- offset_error=~offset_error;\r
- offset_error=offset_error & 0xFFF;\r
- offset_error=offset_error+1;\r
-\r
- adc->CALR = offset_error;\r
-\r
- /** - Restore Mode after Calibration */\r
- adc->OPMODECR = backup_mode;\r
- \r
- return(offset_error);\r
-\r
- /** @note The function adcInit has to be called before this function can be used. */\r
-\r
-/* USER CODE BEGIN (34) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (35) */\r
-/* USER CODE END */\r
-\r
-/** @fn void adcEnableNotification(adcBASE_t *adc, uint32_t group)\r
-* @brief Enable notification\r
-* @param[in] adc Pointer to ADC module:\r
-* - adcREG1: ADC1 module pointer\r
-* - adcREG2: ADC2 module pointer\r
-* - adcREG3: ADC3 module pointer\r
-* @param[in] group Hardware group of ADC module:\r
-* - adcGROUP0: ADC event group\r
-* - adcGROUP1: ADC group 1\r
-* - adcGROUP2: ADC group 2\r
-*\r
-* This function will enable the notification of a conversion.\r
-* In single conversion mode for conversion complete and\r
-* in continuous conversion mode when the FiFo buffer is full.\r
-*\r
-*/\r
-\r
-/* USER CODE BEGIN (36) */\r
-/* USER CODE END */\r
-\r
-void adcEnableNotification(adcBASE_t *adc, uint32_t group)\r
-{\r
- uint32_t notif = adc->GxMODECR[group] & 2U ? 1U : 8U;\r
-\r
-/* USER CODE BEGIN (37) */\r
-/* USER CODE END */\r
-\r
- adc->GxINTENA[group] = notif;\r
-\r
- /** @note The function adcInit has to be called before this function can be used.\n\r
- * This function should be called before the conversion is started\r
- */\r
-\r
-/* USER CODE BEGIN (38) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (39) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adcDisableNotification(adcBASE_t *adc, uint32_t group)\r
-* @brief Disable notification\r
-* @param[in] adc Pointer to ADC module:\r
-* - adcREG1: ADC1 module pointer\r
-* - adcREG2: ADC2 module pointer\r
-* - adcREG3: ADC3 module pointer\r
-* @param[in] group Hardware group of ADC module:\r
-* - adcGROUP0: ADC event group\r
-* - adcGROUP1: ADC group 1\r
-* - adcGROUP2: ADC group 2\r
-*\r
-* This function will disable the notification of a conversion.\r
-*/\r
-\r
-/* USER CODE BEGIN (40) */\r
-/* USER CODE END */\r
-\r
-void adcDisableNotification(adcBASE_t *adc, uint32_t group)\r
-{\r
-/* USER CODE BEGIN (41) */\r
-/* USER CODE END */\r
-\r
- adc->GxINTENA[group] = 0U;\r
-\r
- /** @note The function adcInit has to be called before this function can be used. */\r
-\r
-/* USER CODE BEGIN (42) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (43) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adc1Group0Interrupt(void)\r
-* @brief ADC1 Event Group Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (44) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(adc1Group0Interrupt, IRQ)\r
-\r
-void adc1Group0Interrupt(void)\r
-{\r
-/* USER CODE BEGIN (45) */\r
-/* USER CODE END */\r
- \r
- adcREG1->GxINTFLG[0U] = 9U;\r
-\r
- adcNotification(adcREG1, adcGROUP0);\r
-\r
-/* USER CODE BEGIN (46) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (47) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adc1Group1Interrupt(void)\r
-* @brief ADC1 Group 1 Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (48) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(adc1Group1Interrupt, IRQ)\r
-\r
-void adc1Group1Interrupt(void)\r
-{\r
-/* USER CODE BEGIN (49) */\r
- // Delete generated content after user code block!!!\r
- adcNotification(adcREG1, adcGROUP1);\r
-/* USER CODE END */\r
-/* USER CODE BEGIN (50) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (51) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adc1Group2Interrupt(void)\r
-* @brief ADC1 Group 2 Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (52) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(adc1Group2Interrupt, IRQ)\r
-\r
-void adc1Group2Interrupt(void)\r
-{\r
-/* USER CODE BEGIN (53) */\r
-/* USER CODE END */\r
- \r
- adcREG1->GxINTFLG[2U] = 9U;\r
-\r
- adcNotification(adcREG1, adcGROUP2);\r
-\r
-/* USER CODE BEGIN (54) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (55) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adc2Group0Interrupt(void)\r
-* @brief ADC2 Event Group Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (56) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(adc2Group0Interrupt, IRQ)\r
-\r
-void adc2Group0Interrupt(void)\r
-{\r
-/* USER CODE BEGIN (57) */\r
-/* USER CODE END */\r
- \r
- adcREG2->GxINTFLG[0U] = 9U;\r
-\r
- adcNotification(adcREG2, adcGROUP0);\r
-\r
-/* USER CODE BEGIN (58) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (59) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adc2Group1Interrupt(void)\r
-* @brief ADC2 Group 1 Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (60) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(adc2Group1Interrupt, IRQ)\r
-\r
-void adc2Group1Interrupt(void)\r
-{\r
-/* USER CODE BEGIN (61) */\r
- // Delete generated content after user code block!!!\r
- adcNotification(adcREG2, adcGROUP1);\r
-/* USER CODE END */\r
-/* USER CODE BEGIN (62) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (63) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void adc2Group2Interrupt(void)\r
-* @brief ADC2 Group 2 Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (64) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(adc2Group2Interrupt, IRQ)\r
-\r
-void adc2Group2Interrupt(void)\r
-{\r
-/* USER CODE BEGIN (65) */\r
-/* USER CODE END */\r
- \r
- adcREG2->GxINTFLG[2U] = 9U;\r
-\r
- adcNotification(adcREG2, adcGROUP2);\r
-\r
-/* USER CODE BEGIN (66) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (67) */\r
-/* USER CODE END */\r
-\r
-\r
+/** @file adc.c
+* @brief ADC Driver Source File
+* @date 04.January.2012
+* @version 03.01.00
+*
+* This file contains:
+* - API Funcions
+* - Interrupt Handlers
+* .
+* which are relevant for the ADC driver.
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "ti_drv_adc.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @fn void adcInit(void)
+* @brief Initializes ADC Driver
+*
+* This function initializes the ADC driver.
+*
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+void adcInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+
+
+ /** @b Initialize @b ADC1: */
+
+ /** - Reset ADC module */
+ adcREG1->RSTCR = 1U;
+ adcREG1->RSTCR = 0U;
+
+ /** - Enable 12-BIT ADC */
+ adcREG1->OPMODECR |= 0x80000000U;
+
+ /** - Setup prescaler */
+ adcREG1->CLOCKCR = 7U;
+
+ /** - Setup memory boundaries */
+ adcREG1->BNDCR =(8U << 16U)|(8U + 8U);
+ adcREG1->BNDEND = 2U;
+
+ /** - Setup event group conversion mode
+ * - Setup data format
+ * - Enable/Disable channel id in conversion result
+ * - Enable/Disable continuous conversion
+ */
+ adcREG1->GxMODECR[0U] = ADC_12_BIT
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Setup event group hardware trigger
+ * - Setup hardware trigger edge
+ * - Setup hardware trigger source
+ */
+ adcREG1->G0SRC = 0x00000000U
+ | ADC1_EVENT;
+
+ /** - Setup event group sample window */
+ adcREG1->G0SAMP = 0U;
+
+ /** - Setup event group sample discharge
+ * - Setup discharge prescaler
+ * - Enable/Disable discharge
+ */
+ adcREG1->G0SAMPDISEN = 0U << 8U
+ | 0x00000000U;
+
+ /** - Setup group 1 conversion mode
+ * - Setup data format
+ * - Enable/Disable channel id in conversion result
+ * - Enable/Disable continuous conversion
+ */
+ adcREG1->GxMODECR[1U] = ADC_12_BIT
+ | 0x00000020U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Setup group 1 hardware trigger
+ * - Setup hardware trigger edge
+ * - Setup hardware trigger source
+ */
+ adcREG1->G1SRC = 0x00000000U
+ | ADC1_EVENT;
+
+ /** - Setup group 1 sample window */
+ adcREG1->G1SAMP = 0U;
+
+ /** - Setup group 1 sample discharge
+ * - Setup discharge prescaler
+ * - Enable/Disable discharge
+ */
+ adcREG1->G1SAMPDISEN = 0U << 8U
+ | 0x00000000U;
+
+ /** - Setup group 2 conversion mode
+ * - Setup data format
+ * - Enable/Disable channel id in conversion result
+ * - Enable/Disable continuous conversion
+ */
+ adcREG1->GxMODECR[2U] = ADC_12_BIT
+ | 0x00000020U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Setup group 2 hardware trigger
+ * - Setup hardware trigger edge
+ * - Setup hardware trigger source
+ */
+ adcREG1->G2SRC = 0x00000000U
+ | ADC1_EVENT;
+
+ /** - Setup group 2 sample window */
+ adcREG1->G2SAMP = 0U;
+
+ /** - Setup group 2 sample discharge
+ * - Setup discharge prescaler
+ * - Enable/Disable discharge
+ */
+ adcREG1->G2SAMPDISEN = 0U << 8U
+ | 0x00000000U;
+
+ /** - Enable ADC module */
+ adcREG1->OPMODECR |= 0x80140001U;
+
+ /** - Wait for buffer inialisation complete */
+ while ((adcREG1->BUFINIT) != 0) { /* Wait */ }
+
+ /** - Setup parity */
+ adcREG1->PARCR = 0x00000005U;
+
+
+
+ /** @b Initialize @b ADC2: */
+
+ /** - Reset ADC module */
+ adcREG2->RSTCR = 1U;
+ adcREG2->RSTCR = 0U;
+
+ /** - Enable 12-BIT ADC */
+ adcREG2->OPMODECR |= 0x80000000U;
+
+ /** - Setup prescaler */
+ adcREG2->CLOCKCR = 7U;
+
+ /** - Setup memory boundaries */
+ adcREG2->BNDCR =(8U << 16U)|(8U + 8U);
+ adcREG2->BNDEND = 2U;
+
+ /** - Setup event group conversion mode
+ * - Setup data format
+ * - Enable/Disable channel id in conversion result
+ * - Enable/Disable continuous conversion
+ */
+ adcREG2->GxMODECR[0U] = ADC_12_BIT
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Setup event group hardware trigger
+ * - Setup hardware trigger edge
+ * - Setup hardware trigger source
+ */
+ adcREG2->G0SRC = 0x00000000U
+ | ADC2_EVENT;
+
+ /** - Setup event group sample window */
+ adcREG2->G0SAMP = 0U;
+
+ /** - Setup event group sample discharge
+ * - Setup discharge prescaler
+ * - Enable/Disable discharge
+ */
+ adcREG2->G0SAMPDISEN = 0U << 8U
+ | 0x00000000U;
+
+ /** - Setup group 1 conversion mode
+ * - Setup data format
+ * - Enable/Disable channel id in conversion result
+ * - Enable/Disable continuous conversion
+ */
+ adcREG2->GxMODECR[1U] = ADC_12_BIT
+ | 0x00000020U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Setup group 1 hardware trigger
+ * - Setup hardware trigger edge
+ * - Setup hardware trigger source
+ */
+ adcREG2->G1SRC = 0x00000000U
+ | ADC2_EVENT;
+
+
+ /** - Setup group 1 sample window */
+ adcREG2->G1SAMP = 0U;
+
+ /** - Setup group 1 sample discharge
+ * - Setup discharge prescaler
+ * - Enable/Disable discharge
+ */
+ adcREG2->G1SAMPDISEN = 0U << 8U
+ | 0x00000000U;
+
+ /** - Setup group 2 conversion mode
+ * - Setup data format
+ * - Enable/Disable channel id in conversion result
+ * - Enable/Disable continuous conversion
+ */
+ adcREG2->GxMODECR[2U] = ADC_12_BIT
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Setup group 2 hardware trigger
+ * - Setup hardware trigger edge
+ * - Setup hardware trigger source
+ */
+ adcREG2->G2SRC = 0x00000000U
+ | ADC2_EVENT;
+
+ /** - Setup group 2 sample window */
+ adcREG2->G2SAMP = 0U;
+
+ /** - Setup group 2 sample discharge
+ * - Setup discharge prescaler
+ * - Enable/Disable discharge
+ */
+ adcREG2->G2SAMPDISEN = 0U << 8U
+ | 0x00000000U;
+
+ /** - Enable ADC module */
+ adcREG2->OPMODECR |= 0x80140001U;
+
+ /** - Wait for buffer inialisation complete */
+ while ((adcREG2->BUFINIT) != 0) { /* Wait */ }
+
+ /** - Setup parity */
+ adcREG2->PARCR = 0x00000005U;
+
+ /** @note This function has to be called before the driver can be used.\n
+ * This function has to be executed in priviledged mode.\n
+ */
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+
+/** @fn void adcStartConversion(adcBASE_t *adc, uint32_t group)
+* @brief Starts an ADC conversion
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* This function starts a convesion of the ADC hardware group.
+*
+*/
+
+/** - s_adcSelect is used as constant table for channel selection */
+static const uint32_t s_adcSelect[2U][3U] =
+{
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U,
+ 0x00000001U |
+ 0x00000002U |
+ 0x00000004U |
+ 0x00000008U |
+ 0x00000010U |
+ 0x00000020U |
+ 0x00000040U |
+ 0x00000080U |
+ 0x00000100U |
+ 0x00000200U |
+ 0x00000400U |
+ 0x00000800U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U,
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U,
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U ,
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000004U |
+ 0x00000008U |
+ 0x00000010U |
+ 0x00000020U |
+ 0x00000040U |
+ 0x00000080U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U,
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U,
+};
+
+/** - s_adcSelect is used as constant table for channel selection */
+static const uint32_t s_adcFiFoSize[2U][3U] =
+{
+ 16U,
+ 16U,
+ 16U,
+ 16U,
+ 16U,
+ 16U,
+};
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+void adcStartConversion(adcBASE_t *adc, uint32_t group)
+{
+ uint32_t index = adc == adcREG1 ? 0U : 1U;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+ /** - Setup FiFo size */
+ adc->GxINTCR[group] = s_adcFiFoSize[index][group];
+
+ /** - Start Conversion */
+ adc->GxSEL[group] = s_adcSelect[index][group];
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+
+/** @fn void adcStopConversion(adcBASE_t *adc, uint32_t group)
+* @brief Stops an ADC conversion
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* This function stops a convesion of the ADC hardware group.
+*
+*/
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+void adcStopConversion(adcBASE_t *adc, uint32_t group)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ /** - Stop Conversion */
+ adc->GxSEL[group] = 0U;
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+
+/** @fn void adcResetFiFo(adcBASE_t *adc, uint32_t group)
+* @brief Resets FiFo read and write pointer.
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* This function resets the FiFo read and write pointrs.
+*
+*/
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+void adcResetFiFo(adcBASE_t *adc, uint32_t group)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ /** - Reset FiFo */
+ adc->GxFIFORESETCR[group] = 1U;
+
+ /** @note The function adcInit has to be called before this function can be used.\n
+ * the conversion should be stopped before calling this function.
+ */
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+
+/** @fn uint32_t adcGetData(adcBASE_t *adc, uint32_t group, adcData_t *data)
+* @brief Gets converted a ADC values
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* - adcREG3: ADC3 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+* @param[out] data Pointer to store ADC converted data
+* @return The function will return the number of converted values copied into data buffer:
+*
+* This function writes a ADC message into a ADC message box.
+*
+*/
+
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+uint32_t adcGetData(adcBASE_t *adc, uint32_t group, adcData_t *data)
+{
+ uint32_t i;
+ uint32_t buf;
+ uint32_t mode;
+ uint32_t index = adc == adcREG1 ? 0U : 1U;
+ uint32_t count = adc->GxINTCR[group] >= 256U ? s_adcFiFoSize[index][group] : s_adcFiFoSize[index][group] - (uint32_t)(adc->GxINTCR[group] & 0xFF);
+ adcData_t *ptr = data;
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ mode = ((adc->GxMODECR[group]) & 0x00000300U);
+
+ if(mode == ADC_12_BIT)
+ {
+ /** - Get conversion data and channel/pin id */
+ for (i = 0; i < count; i++)
+ {
+ buf = adc->GxBUF[group].BUF0;
+ ptr->value = (uint16_t)(buf & 0xFFFU);
+ ptr->id = (uint32_t)((buf >> 16U) & 0x1FU);
+ ptr++;
+ }
+ }
+ else
+ {
+ /** - Get conversion data and channel/pin id */
+ for (i = 0; i < count; i++)
+ {
+ buf = adc->GxBUF[group].BUF0;
+ ptr->value = (uint16_t)(buf & 0x3FFU);
+ ptr->id = (uint32_t)((buf >> 10U) & 0x1FU);
+ ptr++;
+ }
+ }
+
+
+ adc->GxINTFLG[group] = 9U;
+
+ /** @note The function adcInit has to be called before this function can be used.\n
+ * The user is responsible to initialize the message box.
+ */
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+ return count;
+}
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+
+/** @fn uint32_t adcIsFifoFull(adcBASE_t *adc, uint32_t group)
+* @brief Checks if FiFo buffer is full
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* - adcREG3: ADC3 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+* @return The function will return:
+* - 0: When FiFo buffer is not full
+* - 1: When FiFo buffer is full
+* - 3: When FiFo buffer overflow occured
+*
+* This function checks FiFo buffer status.
+*
+*/
+
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+uint32_t adcIsFifoFull(adcBASE_t *adc, uint32_t group)
+{
+ uint32_t flags;
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+ /** - Read FiFo flags */
+ flags = adc->GxINTFLG[group] & 3U;
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+ return flags;
+}
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+
+/** @fn uint32_t adcIsConversionComplete(adcBASE_t *adc, uint32_t group)
+* @brief Checks if Conversion is complete
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* - adcREG3: ADC3 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+* @return The function will return:
+* - 0: When is not finished
+* - 8: When conversion is complete
+*
+* This function checks if conversion is complete.
+*
+*/
+
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+uint32_t adcIsConversionComplete(adcBASE_t *adc, uint32_t group)
+{
+ uint32_t flags;
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+ /** - Read conversion flags */
+ flags = adc->GxINTFLG[group] & 8U;
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ return flags;
+}
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+/** @fn void adcCalibration(adcBASE_t *adc)
+* @brief Computes offset error using Calibration mode
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* - adcREG3: ADC3 module pointer
+* This function computes offset error using Calibration mode
+*
+*/
+void adcCalibration(adcBASE_t *adc)
+{
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+ uint32_t conv_val[5]={0,0,0,0,0},loop_index=0;
+ uint32_t offset_error=0;
+ uint32_t backup_mode;
+
+ /** - Backup Mode before Calibration */
+ backup_mode = adc->OPMODECR;
+
+ /** - Enable 12-BIT ADC */
+ adcREG1->OPMODECR |= 0x80000000U;
+
+ /* Disable all channels for conversion */
+ adc->GxSEL[0]=0x00;
+ adc->GxSEL[1]=0x00;
+ adc->GxSEL[2]=0x00;
+
+ for(loop_index=0;loop_index<4;loop_index++)
+ {
+ /* Disable Self Test and Calibration mode */
+ adc->CALCR=0x0;
+
+ switch(loop_index)
+ {
+ case 0 : /* Test 1 : Bride En = 0 , HiLo =0 */
+ adc->CALCR=0x0;
+ break;
+
+ case 1 : /* Test 1 : Bride En = 0 , HiLo =1 */
+ adc->CALCR=0x0100;
+ break;
+
+ case 2 : /* Test 1 : Bride En = 1 , HiLo =0 */
+ adc->CALCR=0x0200;
+ break;
+
+ case 3 : /* Test 1 : Bride En = 1 , HiLo =1 */
+ adc->CALCR=0x0300;
+ break;
+ }
+
+ /* Enable Calibration mode */
+ adc->CALCR|=0x1;
+
+ /* Start calibration conversion */
+ adc->CALCR|=0x00010000;
+
+ /* Wait for calibration conversion to complete */
+ while((adc->CALCR & 0x00010000)==0x00010000);
+
+ /* Read converted value */
+ conv_val[loop_index]= adc->CALR;
+ }
+
+ /* Disable Self Test and Calibration mode */
+ adc->CALCR=0x0;
+
+ /* Compute the Offset error correction value */
+ conv_val[4]=conv_val[0]+ conv_val[1] + conv_val[2] + conv_val[3];
+
+ conv_val[4]=(conv_val[4]/4);
+
+ offset_error=conv_val[4]-0x7FF;
+
+ /*Write the offset error to the Calibration register */
+ /* Load 2;s complement of the computed value to ADCALR register */
+ offset_error=~offset_error;
+ offset_error=offset_error & 0xFFF;
+ offset_error=offset_error+1;
+
+ adc->CALR = offset_error;
+
+ /** - Restore Mode after Calibration */
+ adc->OPMODECR = backup_mode;
+
+ /** @note The function adcInit has to be called before using this function. */
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+
+/** @fn void adcMidPointCalibration(adcBASE_t *adc)
+* @brief Computes offset error using Mid Point Calibration mode
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* - adcREG3: ADC3 module pointer
+* This function computes offset error using Mid Point Calibration mode
+*
+*/
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+uint32_t adcMidPointCalibration(adcBASE_t *adc)
+{
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+ uint32_t conv_val[3]={0,0,0},loop_index=0;
+ uint32_t offset_error=0;
+ uint32_t backup_mode;
+
+ /** - Backup Mode before Calibration */
+ backup_mode = adc->OPMODECR;
+
+ /** - Enable 12-BIT ADC */
+ adcREG1->OPMODECR |= 0x80000000U;
+
+ /* Disable all channels for conversion */
+ adc->GxSEL[0]=0x00;
+ adc->GxSEL[1]=0x00;
+ adc->GxSEL[2]=0x00;
+
+ for(loop_index=0;loop_index<2;loop_index++)
+ {
+ /* Disable Self Test and Calibration mode */
+ adc->CALCR=0x0;
+
+ switch(loop_index)
+ {
+ case 0 : /* Test 1 : Bride En = 0 , HiLo =0 */
+ adc->CALCR=0x0;
+ break;
+
+ case 1 : /* Test 1 : Bride En = 0 , HiLo =1 */
+ adc->CALCR=0x0100;
+ break;
+
+ }
+
+ /* Enable Calibration mode */
+ adc->CALCR|=0x1;
+
+ /* Start calibration conversion */
+ adc->CALCR|=0x00010000;
+
+ /* Wait for calibration conversion to complete */
+ while((adc->CALCR & 0x00010000)==0x00010000);
+
+ /* Read converted value */
+ conv_val[loop_index]= adc->CALR;
+ }
+
+ /* Disable Self Test and Calibration mode */
+ adc->CALCR=0x0;
+
+ /* Compute the Offset error correction value */
+ conv_val[2]=(conv_val[0])+ (conv_val[1]);
+
+ conv_val[2]=(conv_val[2]/2);
+
+ offset_error=conv_val[2]-0x7FF;
+
+ /* Write the offset error to the Calibration register */
+ /* Load 2's complement of the computed value to ADCALR register */
+ offset_error=~offset_error;
+ offset_error=offset_error & 0xFFF;
+ offset_error=offset_error+1;
+
+ adc->CALR = offset_error;
+
+ /** - Restore Mode after Calibration */
+ adc->OPMODECR = backup_mode;
+
+ return(offset_error);
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+/** @fn void adcEnableNotification(adcBASE_t *adc, uint32_t group)
+* @brief Enable notification
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* - adcREG3: ADC3 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* This function will enable the notification of a conversion.
+* In single conversion mode for conversion complete and
+* in continuous conversion mode when the FiFo buffer is full.
+*
+*/
+
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+void adcEnableNotification(adcBASE_t *adc, uint32_t group)
+{
+ uint32_t notif = adc->GxMODECR[group] & 2U ? 1U : 8U;
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+
+ adc->GxINTENA[group] = notif;
+
+ /** @note The function adcInit has to be called before this function can be used.\n
+ * This function should be called before the conversion is started
+ */
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+
+
+/** @fn void adcDisableNotification(adcBASE_t *adc, uint32_t group)
+* @brief Disable notification
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* - adcREG3: ADC3 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* This function will disable the notification of a conversion.
+*/
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+
+void adcDisableNotification(adcBASE_t *adc, uint32_t group)
+{
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+
+ adc->GxINTENA[group] = 0U;
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+
+
+/** @fn void adc1Group0Interrupt(void)
+* @brief ADC1 Event Group Interrupt Handler
+*/
+
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+
+#pragma INTERRUPT(adc1Group0Interrupt, IRQ)
+
+void adc1Group0Interrupt(void)
+{
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+
+ adcREG1->GxINTFLG[0U] = 9U;
+
+ adcNotification(adcREG1, adcGROUP0);
+
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+
+
+/** @fn void adc1Group1Interrupt(void)
+* @brief ADC1 Group 1 Interrupt Handler
+*/
+
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+
+#pragma INTERRUPT(adc1Group1Interrupt, IRQ)
+
+void adc1Group1Interrupt(void)
+{
+/* USER CODE BEGIN (49) */
+ // Delete generated content after user code block!!!
+ adcNotification(adcREG1, adcGROUP1);
+/* USER CODE END */
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (51) */
+/* USER CODE END */
+
+
+/** @fn void adc1Group2Interrupt(void)
+* @brief ADC1 Group 2 Interrupt Handler
+*/
+
+/* USER CODE BEGIN (52) */
+/* USER CODE END */
+
+#pragma INTERRUPT(adc1Group2Interrupt, IRQ)
+
+void adc1Group2Interrupt(void)
+{
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+
+ adcREG1->GxINTFLG[2U] = 9U;
+
+ adcNotification(adcREG1, adcGROUP2);
+
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (55) */
+/* USER CODE END */
+
+
+/** @fn void adc2Group0Interrupt(void)
+* @brief ADC2 Event Group Interrupt Handler
+*/
+
+/* USER CODE BEGIN (56) */
+/* USER CODE END */
+
+#pragma INTERRUPT(adc2Group0Interrupt, IRQ)
+
+void adc2Group0Interrupt(void)
+{
+/* USER CODE BEGIN (57) */
+/* USER CODE END */
+
+ adcREG2->GxINTFLG[0U] = 9U;
+
+ adcNotification(adcREG2, adcGROUP0);
+
+/* USER CODE BEGIN (58) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (59) */
+/* USER CODE END */
+
+
+/** @fn void adc2Group1Interrupt(void)
+* @brief ADC2 Group 1 Interrupt Handler
+*/
+
+/* USER CODE BEGIN (60) */
+/* USER CODE END */
+
+#pragma INTERRUPT(adc2Group1Interrupt, IRQ)
+
+void adc2Group1Interrupt(void)
+{
+/* USER CODE BEGIN (61) */
+ // Delete generated content after user code block!!!
+ adcNotification(adcREG2, adcGROUP1);
+/* USER CODE END */
+/* USER CODE BEGIN (62) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (63) */
+/* USER CODE END */
+
+
+/** @fn void adc2Group2Interrupt(void)
+* @brief ADC2 Group 2 Interrupt Handler
+*/
+
+/* USER CODE BEGIN (64) */
+/* USER CODE END */
+
+#pragma INTERRUPT(adc2Group2Interrupt, IRQ)
+
+void adc2Group2Interrupt(void)
+{
+/* USER CODE BEGIN (65) */
+/* USER CODE END */
+
+ adcREG2->GxINTFLG[2U] = 9U;
+
+ adcNotification(adcREG2, adcGROUP2);
+
+/* USER CODE BEGIN (66) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (67) */
+/* USER CODE END */
+
+
-/** @file can.c \r
-* @brief CAN Driver Source File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-* This file contains:\r
-* - API Funcions\r
-* - Interrupt Handlers\r
-* .\r
-* which are relevant for the CAN driver.\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-\r
-/* Include Files */\r
-\r
-#include "ti_drv_can.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-\r
-/* Global and Static Variables */\r
-\r
-#ifndef __little_endian__\r
- static const uint32_t s_canByteOrder[] = {3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U};\r
-#endif\r
-\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void canInit(void)\r
-* @brief Initializes CAN Driver\r
-*\r
-* This function initializes the CAN driver.\r
-*\r
-*/\r
-\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-\r
-void canInit(void)\r
-{\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
- /** @b Initialize @b CAN1: */\r
-\r
- /** - Setup control register\r
- * - Disable automatic wakeup on bus activity\r
- * - Local power down mode disabled\r
- * - Disable DMA request lines\r
- * - Enable global Interrupt Line 0 and 1\r
- * - Disable debug mode\r
- * - Release from software reset\r
- * - Enable/Disable parity or ECC\r
- * - Enable/Disable auto bus on timer\r
- * - Setup message completion before entering debug state\r
- * - Setup normal operation mode\r
- * - Request write access to the configuration registers\r
- * - Setup automatic retransmission of messages\r
- * - Disable error interrups\r
- * - Disable status interrupts\r
- * - Enter initialization mode\r
- */\r
- canREG1->CTL = 0x00000000U \r
- | 0x00000000U \r
- | 0x00000005U \r
- | 0x000200043U;\r
-\r
- /** - Clear all pending error flags and reset current status */\r
- canREG1->ES = 0x0000031FU;\r
-\r
- /** - Assign interrupt level for messages */\r
- canREG1->INTMUXx[0U] = 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- canREG1->INTMUXx[1U] = 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Setup auto bus on timer pewriod */\r
- canREG1->ABOTR = 0U;\r
-\r
- /** - Initialize message 1 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x80000000U | 0x40000000U | 0x20000000U | ((1U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 1;\r
-\r
- /** - Initialize message 2 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((2U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000C00U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 2;\r
-\r
- /** - Initialize message 3 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((3U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 3;\r
-\r
- /** - Initialize message 4 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 4;\r
-\r
- /** - Initialize message 5 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 5;\r
-\r
- /** - Initialize message 6 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 6;\r
-\r
- /** - Initialize message 7 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 7;\r
-\r
- /** - Initialize message 8 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 8;\r
-\r
- /** - Initialize message 9 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 9;\r
-\r
- /** - Initialize message 10 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 10;\r
-\r
- /** - Initialize message 11 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 11;\r
-\r
- /** - Initialize message 12 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 12;\r
-\r
- /** - Initialize message 13 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 13;\r
-\r
- /** - Initialize message 14 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 14;\r
-\r
- /** - Initialize message 15 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 15;\r
-\r
- /** - Initialize message 16 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 16;\r
-\r
- /** - Initialize message 17 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 17;\r
-\r
- /** - Initialize message 18 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 18;\r
-\r
- /** - Initialize message 19 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 19;\r
-\r
- /** - Initialize message 20 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 20;\r
-\r
- /** - Initialize message 21 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 21;\r
-\r
- /** - Initialize message 22 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 22;\r
-\r
- /** - Initialize message 23 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 23;\r
-\r
- /** - Initialize message 24 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 24;\r
-\r
- /** - Initialize message 25 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 25;\r
-\r
- /** - Initialize message 26 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 26;\r
-\r
- /** - Initialize message 27 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 27;\r
-\r
- /** - Initialize message 28 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 28;\r
-\r
- /** - Initialize message 29 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 29;\r
-\r
- /** - Initialize message 30 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 30;\r
-\r
- /** - Initialize message 31 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 31;\r
-\r
- /** - Initialize message 32 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 32;\r
-\r
- /** - Initialize message 33 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((33U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 33;\r
-\r
- /** - Initialize message 34 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((34U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 34;\r
-\r
- /** - Initialize message 35 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((35U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 35;\r
-\r
- /** - Initialize message 36 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((36U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 36;\r
-\r
- /** - Initialize message 37 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((37U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 37;\r
-\r
- /** - Initialize message 38 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((38U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 38;\r
-\r
- /** - Initialize message 39 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((39U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 39;\r
-\r
- /** - Initialize message 40 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((40U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 40;\r
-\r
- /** - Initialize message 41 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((41U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 41;\r
-\r
- /** - Initialize message 42 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((42U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 42;\r
-\r
- /** - Initialize message 43 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((43U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 43;\r
-\r
- /** - Initialize message 44 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((44U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 44;\r
-\r
- /** - Initialize message 45 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((45U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 45;\r
-\r
- /** - Initialize message 46 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((46U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 46;\r
-\r
- /** - Initialize message 47 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((47U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 47;\r
-\r
- /** - Initialize message 48 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((48U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 48;\r
-\r
- /** - Initialize message 49 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((49U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 49;\r
-\r
- /** - Initialize message 50 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((50U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 50;\r
-\r
- /** - Initialize message 51 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((51U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 51;\r
-\r
- /** - Initialize message 52 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((52U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 52;\r
-\r
- /** - Initialize message 53 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((53U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 53;\r
-\r
- /** - Initialize message 54 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((54U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 54;\r
-\r
- /** - Initialize message 55 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((55U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 55;\r
-\r
- /** - Initialize message 56 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((56U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 56;\r
-\r
- /** - Initialize message 57 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((57U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 57;\r
-\r
- /** - Initialize message 58 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((58U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 58;\r
-\r
- /** - Initialize message 59 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((59U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 59;\r
-\r
- /** - Initialize message 60 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((60U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 60;\r
-\r
- /** - Initialize message 61 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((61U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 61;\r
-\r
- /** - Initialize message 62 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((62U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 62;\r
-\r
- /** - Initialize message 63 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((63U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF1CMD = 0xF8;\r
- canREG1->IF1NO = 63;\r
-\r
- /** - Initialize message 64 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((64U & 0x1FFFFFFFU) << 0U);\r
- canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG1->IF2CMD = 0xF8;\r
- canREG1->IF2NO = 64;\r
-\r
- /** - Setup IF1 for data transmission \r
- * - Wait until IF1 is ready for use \r
- * - Set IF1 control byte\r
- */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1CMD = 0x87;\r
-\r
- /** - Setup IF2 for reading data\r
- * - Wait until IF1 is ready for use \r
- * - Set IF1 control byte\r
- */\r
- while (canREG1->IF2STAT & 0x80);\r
-\r
- canREG1->IF2CMD = 0x17;\r
- /** - Setup bit timing \r
- * - Setup baud rate prescaler extension\r
- * - Setup TSeg2\r
- * - Setup TSeg1\r
- * - Setup sample jump width\r
- * - Setup baud rate prescaler\r
- */\r
- canREG1->BTR = (0U << 16U) |\r
- ((2U - 1U) << 12U) |\r
- (((3U + 2U) - 1U) << 8U) |\r
- ((2U - 1U) << 6U) |\r
- 19U;\r
-\r
- /** - CAN1 Port output values */\r
- canREG1->TIOC = (1 << 18 )\r
- | (0 << 17 ) \r
- | (1 << 3 ) \r
- | (0 << 2 ) \r
- | (0 << 1 ) \r
- | (0 ); \r
- canREG1->RIOC = (1 << 18 ) \r
- | (0 << 17 ) \r
- | (1 << 3 ) \r
- | (0 << 2 )\r
- | (0 <<1 ) \r
- | (0 ); \r
-\r
-\r
- /** - Leave configuration and initialization mode */\r
- canREG1->CTL &= ~0x00000041U;\r
-\r
-\r
- /** @b Initialize @b CAN2: */\r
-\r
- /** - Setup control register\r
- * - Disable automatic wakeup on bus activity\r
- * - Local power down mode disabled\r
- * - Disable DMA request lines\r
- * - Enable global Interrupt Line 0 and 1\r
- * - Disable debug mode\r
- * - Release from software reset\r
- * - Enable/Disable parity or ECC\r
- * - Enable/Disable auto bus on timer\r
- * - Setup message completion before entering debug state\r
- * - Setup normal operation mode\r
- * - Request write access to the configuration registers\r
- * - Setup automatic retransmission of messages\r
- * - Disable error interrups\r
- * - Disable status interrupts\r
- * - Enter initialization mode\r
- */\r
- canREG2->CTL = 0x00000000U \r
- | 0x00000000U \r
- | 0x00000005U \r
- | 0x000200043U;\r
-\r
- /** - Clear all pending error flags and reset current status */\r
- canREG2->ES = 0x0000031FU;\r
-\r
-\r
- /** - Assign interrupt level for messages */\r
- canREG2->INTMUXx[0U] = 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- canREG2->INTMUXx[1U] = 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
-\r
- /** - Setup auto bus on timer pewriod */\r
- canREG2->ABOTR = 0U;\r
-\r
- /** - Initialize message 1 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((1U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 1;\r
-\r
- /** - Initialize message 2 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x80000000U | 0x40000000U | 0x20000000U | ((2U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000C00U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 2;\r
-\r
- /** - Initialize message 3 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((3U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 3;\r
-\r
- /** - Initialize message 4 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 4;\r
-\r
- /** - Initialize message 5 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 5;\r
-\r
- /** - Initialize message 6 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 6;\r
-\r
- /** - Initialize message 7 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 7;\r
-\r
- /** - Initialize message 8 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 8;\r
-\r
- /** - Initialize message 9 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 9;\r
-\r
- /** - Initialize message 10 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 10;\r
-\r
- /** - Initialize message 11 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 11;\r
-\r
- /** - Initialize message 12 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 12;\r
-\r
- /** - Initialize message 13 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 13;\r
-\r
- /** - Initialize message 14 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 14;\r
-\r
- /** - Initialize message 15 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 15;\r
-\r
- /** - Initialize message 16 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 16;\r
-\r
- /** - Initialize message 17 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 17;\r
-\r
- /** - Initialize message 18 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 18;\r
-\r
- /** - Initialize message 19 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 19;\r
-\r
- /** - Initialize message 20 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 20;\r
-\r
- /** - Initialize message 21 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 21;\r
-\r
- /** - Initialize message 22 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 22;\r
-\r
- /** - Initialize message 23 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 23;\r
-\r
- /** - Initialize message 24 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 24;\r
-\r
- /** - Initialize message 25 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 25;\r
-\r
- /** - Initialize message 26 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 26;\r
-\r
- /** - Initialize message 27 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 27;\r
-\r
- /** - Initialize message 28 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 28;\r
-\r
- /** - Initialize message 29 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 29;\r
-\r
- /** - Initialize message 30 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 30;\r
-\r
- /** - Initialize message 31 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 31;\r
-\r
- /** - Initialize message 32 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 32;\r
-\r
- /** - Initialize message 33 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((33U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 33;\r
-\r
- /** - Initialize message 34 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((34U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 34;\r
-\r
- /** - Initialize message 35 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((35U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 35;\r
-\r
- /** - Initialize message 36 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((36U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 36;\r
-\r
- /** - Initialize message 37 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((37U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 37;\r
-\r
- /** - Initialize message 38 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((38U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 38;\r
-\r
- /** - Initialize message 39 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((39U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 39;\r
-\r
- /** - Initialize message 40 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((40U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 40;\r
-\r
- /** - Initialize message 41 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((41U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 41;\r
-\r
- /** - Initialize message 42 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((42U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 42;\r
-\r
- /** - Initialize message 43 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((43U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 43;\r
-\r
- /** - Initialize message 44 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((44U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 44;\r
-\r
- /** - Initialize message 45 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((45U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 45;\r
-\r
- /** - Initialize message 46 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((46U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 46;\r
-\r
- /** - Initialize message 47 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((47U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 47;\r
-\r
- /** - Initialize message 48 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((48U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 48;\r
-\r
- /** - Initialize message 49 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((49U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 49;\r
-\r
- /** - Initialize message 50 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((50U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 50;\r
-\r
- /** - Initialize message 51 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((51U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 51;\r
-\r
- /** - Initialize message 52 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((52U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 52;\r
-\r
- /** - Initialize message 53 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((53U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 53;\r
-\r
- /** - Initialize message 54 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((54U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 54;\r
-\r
- /** - Initialize message 55 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((55U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 55;\r
-\r
- /** - Initialize message 56 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((56U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 56;\r
-\r
- /** - Initialize message 57 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((57U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 57;\r
-\r
- /** - Initialize message 58 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((58U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 58;\r
-\r
- /** - Initialize message 59 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((59U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 59;\r
-\r
- /** - Initialize message 60 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((60U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 60;\r
-\r
- /** - Initialize message 61 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((61U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 61;\r
-\r
- /** - Initialize message 62 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((62U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 62;\r
-\r
- /** - Initialize message 63 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((63U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF1CMD = 0xF8;\r
- canREG2->IF1NO = 63;\r
-\r
- /** - Initialize message 64 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((64U & 0x1FFFFFFFU) << 0U);\r
- canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG2->IF2CMD = 0xF8;\r
- canREG2->IF2NO = 64;\r
-\r
- /** - Setup IF1 for data transmission \r
- * - Wait until IF1 is ready for use \r
- * - Set IF1 control byte\r
- */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1CMD = 0x87;\r
-\r
- /** - Setup IF2 for reading data\r
- * - Wait until IF1 is ready for use \r
- * - Set IF1 control byte\r
- */\r
- while (canREG2->IF2STAT & 0x80);\r
-\r
- canREG2->IF2CMD = 0x17;\r
- /** - Setup bit timing \r
- * - Setup baud rate prescaler extension\r
- * - Setup TSeg2\r
- * - Setup TSeg1\r
- * - Setup sample jump width\r
- * - Setup baud rate prescaler\r
- */\r
- canREG2->BTR = (0U << 16U) |\r
- ((2U - 1U) << 12U) |\r
- (((3U + 2U) - 1U) << 8U) |\r
- ((2U - 1U) << 6U) |\r
- 19U;\r
-\r
- /** - CAN2 Port output values */\r
- canREG2->TIOC = (1 << 18 )\r
- | (0 << 17 ) \r
- | (1 << 3 ) \r
- | (0 << 2 ) \r
- | (0 << 1 ) \r
- | (0 ); \r
- canREG2->RIOC = (1 << 18 ) \r
- | (0 << 17 ) \r
- | (1 << 3 ) \r
- | (0 << 2 )\r
- | (0 <<1 ) \r
- | (0 ); \r
-\r
- /** - Leave configuration and initialization mode */\r
- canREG2->CTL &= ~0x00000041U;\r
-\r
- /** @b Initialize @b CAN3: */\r
-\r
- /** - Setup control register\r
- * - Disable automatic wakeup on bus activity\r
- * - Local power down mode disabled\r
- * - Disable DMA request lines\r
- * - Enable global Interrupt Line 0 and 1\r
- * - Disable debug mode\r
- * - Release from software reset\r
- * - Enable/Disable parity or ECC\r
- * - Enable/Disable auto bus on timer\r
- * - Setup message completion before entering debug state\r
- * - Setup normal operation mode\r
- * - Request write access to the configuration registers\r
- * - Setup automatic retransmission of messages\r
- * - Disable error interrups\r
- * - Disable status interrupts\r
- * - Enter initialization mode\r
- */\r
- canREG3->CTL = 0x00000000U \r
- | 0x00000000U \r
- | 0x00000005U \r
- | 0x000200043U;\r
-\r
- /** - Clear all pending error flags and reset current status */\r
- canREG3->ES = 0x0000031FU;\r
-\r
- /** - Assign interrupt level for messages */\r
- canREG3->INTMUXx[0U] = 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Setup auto bus on timer pewriod */\r
- canREG3->ABOTR = 0U;\r
-\r
- /** - Initialize message 1 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((1U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 1;\r
-\r
- /** - Initialize message 2 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((2U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000C00U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 2;\r
-\r
- /** - Initialize message 3 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x80000000U | 0x40000000U | 0x20000000U | ((3U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 3;\r
-\r
- /** - Initialize message 4 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 4;\r
-\r
- /** - Initialize message 5 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 5;\r
-\r
- /** - Initialize message 6 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 6;\r
-\r
- /** - Initialize message 7 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 7;\r
-\r
- /** - Initialize message 8 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 8;\r
-\r
- /** - Initialize message 9 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 9;\r
-\r
- /** - Initialize message 10 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 10;\r
-\r
- /** - Initialize message 11 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 11;\r
-\r
- /** - Initialize message 12 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 12;\r
-\r
- /** - Initialize message 13 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 13;\r
-\r
- /** - Initialize message 14 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 14;\r
-\r
- /** - Initialize message 15 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 15;\r
-\r
- /** - Initialize message 16 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 16;\r
-\r
- /** - Initialize message 17 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 17;\r
-\r
- /** - Initialize message 18 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 18;\r
-\r
- /** - Initialize message 19 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 19;\r
-\r
- /** - Initialize message 20 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 20;\r
-\r
- /** - Initialize message 21 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 21;\r
-\r
- /** - Initialize message 22 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 22;\r
-\r
- /** - Initialize message 23 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 23;\r
-\r
- /** - Initialize message 24 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 24;\r
-\r
- /** - Initialize message 25 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 25;\r
-\r
- /** - Initialize message 26 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 26;\r
-\r
- /** - Initialize message 27 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 27;\r
-\r
- /** - Initialize message 28 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 28;\r
-\r
- /** - Initialize message 29 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 29;\r
-\r
- /** - Initialize message 30 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 30;\r
-\r
- /** - Initialize message 31 \r
- * - Wait until IF1 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF1 control byte\r
- * - Set IF1 message number\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF1CMD = 0xF8;\r
- canREG3->IF1NO = 31;\r
-\r
- /** - Initialize message 32 \r
- * - Wait until IF2 is ready for use \r
- * - Set message mask\r
- * - Set message control word\r
- * - Set message arbitration\r
- * - Set IF2 control byte\r
- * - Set IF2 message number\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);\r
- canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
- canREG3->IF2CMD = 0xF8;\r
- canREG3->IF2NO = 32;\r
-\r
- /** - Setup IF1 for data transmission \r
- * - Wait until IF1 is ready for use \r
- * - Set IF1 control byte\r
- */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1CMD = 0x87;\r
-\r
- /** - Setup IF2 for reading data\r
- * - Wait until IF1 is ready for use \r
- * - Set IF1 control byte\r
- */\r
- while (canREG3->IF2STAT & 0x80);\r
-\r
- canREG3->IF2CMD = 0x17;\r
-\r
- /** - Setup bit timing \r
- * - Setup baud rate prescaler extension\r
- * - Setup TSeg2\r
- * - Setup TSeg1\r
- * - Setup sample jump width\r
- * - Setup baud rate prescaler\r
- */\r
- canREG3->BTR = (0U << 16U) |\r
- ((2U - 1U) << 12U) |\r
- (((3U + 2U) - 1U) << 8U) |\r
- ((2U - 1U) << 6U) |\r
- 19U;\r
-\r
- \r
- /** - CAN3 Port output values */\r
- canREG3->TIOC = (1 << 18 )\r
- | (0 << 17 ) \r
- | (1 << 3 ) \r
- | (0 << 2 ) \r
- | (0 << 1 ) \r
- | (0 ); \r
- canREG3->RIOC = (1 << 18 ) \r
- | (0 << 17 ) \r
- | (1 << 3 ) \r
- | (0 << 2 )\r
- | (0 <<1 ) \r
- | (0 ); \r
-\r
- /** - Leave configuration and initialization mode */\r
- canREG3->CTL &= ~0x00000041U;\r
-\r
- /** @note This function has to be called before the driver can be used.\n\r
- * This function has to be executed in priviledged mode.\n\r
- */\r
-\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn uint32_t canTransmit(canBASE_t *node, uint32_t messageBox, const uint8_t *data)\r
-* @brief Transmits a CAN message\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-* @param[in] messageBox Message box number of CAN node:\r
-* - canMESSAGE_BOX1: CAN message box 1\r
-* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
-* - canMESSAGE_BOX64: CAN message box 64\r
-* @param[in] data Pointer to CAN TX data\r
-* @return The function will return:\r
-* - 0: When the setup of the TX message box wasn't successful \r
-* - 1: When the setup of the TX message box was successful \r
-*\r
-* This function writes a CAN message into a CAN message box.\r
-*\r
-*/\r
-\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
-\r
-uint32_t canTransmit(canBASE_t *node, uint32_t messageBox, const uint8_t *data)\r
-{\r
- uint32_t i;\r
- uint32_t success = 0U;\r
- uint32_t regIndex = (messageBox - 1U) >> 5U;\r
- uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
-\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
-\r
- /** - Check for pending message:\r
- * - pending message, return 0\r
- * - no pending message, start new transmission \r
- */\r
- if (node->TXRQx[regIndex] & bitIndex)\r
- {\r
- return success;\r
- }\r
-\r
- /** - Wait until IF1 is ready for use */\r
- while (node->IF1STAT & 0x80);\r
-\r
- /** - Copy TX data into IF1 */\r
- for (i = 0U; i < 8U; i++)\r
- {\r
-#ifdef __little_endian__\r
- node->IF1DATx[i] = *data++;\r
-#else\r
- node->IF1DATx[s_canByteOrder[i]] = *data++;\r
-#endif\r
- }\r
-\r
- /** - Copy TX data into mesasge box */\r
- node->IF1NO = messageBox;\r
-\r
- success = 1U; \r
-\r
- /** @note The function canInit has to be called before this function can be used.\n\r
- * The user is responsible to initialize the message box.\r
- */\r
-\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
-\r
- return success;\r
-}\r
-\r
-\r
-/** @fn uint32_t canGetData(canBASE_t *node, uint32_t messageBox, uint8_t * const data)\r
-* @brief Gets received a CAN message\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-* @param[in] messageBox Message box number of CAN node:\r
-* - canMESSAGE_BOX1: CAN message box 1\r
-* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
-* - canMESSAGE_BOX64: CAN message box 64\r
-* @param[out] data Pointer to store CAN RX data\r
-* @return The function will return:\r
-* - 0: When RX message box hasn't received new data \r
-* - 1: When RX data are stored in the data buffer \r
-* - 3: When RX data are stored in the data buffer and a message was lost \r
-*\r
-* This function writes a CAN message into a CAN message box.\r
-*\r
-*/\r
-\r
-\r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
-\r
-uint32_t canGetData(canBASE_t *node, uint32_t messageBox, uint8_t * const data)\r
-{\r
- uint32_t i;\r
- uint32_t size;\r
- uint8_t *pData = (uint8_t *)data;\r
- uint32_t success = 0U;\r
- uint32_t regIndex = (messageBox - 1U) >> 5U;\r
- uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
-\r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
-\r
- /** - Check if new data have been arrived:\r
- * - no new data, return 0\r
- * - new data, get received message \r
- */\r
- if (!(node->NWDATx[regIndex] & bitIndex))\r
- {\r
- return success;\r
- }\r
-\r
- /** - Wait until IF2 is ready for use */\r
- while (node->IF2STAT & 0x80);\r
-\r
- /** - Copy data into IF2 */\r
- node->IF2NO = messageBox;\r
-\r
- /** - Wait until data are copied into IF2 */\r
- while (node->IF2STAT & 0x80);\r
-\r
- /** - Get number of received bytes */\r
- size = node->IF2MCTL & 0xFU;\r
-\r
- /** - Copy RX data into destination buffer */\r
- for (i = 0U; i < size; i++)\r
- {\r
-#ifdef __little_endian__\r
- *pData++ = node->IF2DATx[i];\r
-#else\r
- *pData++ = node->IF2DATx[s_canByteOrder[i]];\r
-#endif\r
- }\r
-\r
- success = 1U;\r
-\r
- /** - Check if data have been lost:\r
- * - no data lost, return 1\r
- * - data lost, return 3 \r
- */\r
- if (node->IF2MCTL & 0x4000U)\r
- {\r
- success = 3U;\r
- }\r
-\r
- /** @note The function canInit has to be called before this function can be used.\n\r
- * The user is responsible to initialize the message box.\r
- */\r
-\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
-\r
- return success;\r
-}\r
-\r
-\r
-/** @fn uint32_t canIsTxMessagePending(canBASE_t *node, uint32_t messageBox)\r
-* @brief Gets Tx message box transmission status\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-* @param[in] messageBox Message box number of CAN node:\r
-* - canMESSAGE_BOX1: CAN message box 1\r
-* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
-* - canMESSAGE_BOX64: CAN message box 64\r
-* @return The function will return the tx request flag\r
-*\r
-* Checks to see if the Tx message box has a pending Tx request, returns\r
-* 0 is flag not set otherwise will return the Tx request flag itself.\r
-*/\r
-\r
-\r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
-\r
-uint32_t canIsTxMessagePending(canBASE_t *node, uint32_t messageBox)\r
-{\r
- uint32_t flag;\r
- uint32_t regIndex = (messageBox - 1U) >> 5U;\r
- uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
-\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
-\r
- /** - Read Tx request reigster */\r
- flag = node->TXRQx[regIndex] & bitIndex;\r
-\r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
-\r
- return flag;\r
-}\r
-\r
-\r
-/** @fn uint32_t canIsRxMessageArrived(canBASE_t *node, uint32_t messageBox)\r
-* @brief Gets Rx message box reception status\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-* @param[in] messageBox Message box number of CAN node:\r
-* - canMESSAGE_BOX1: CAN message box 1\r
-* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
-* - canMESSAGE_BOX64: CAN message box 64\r
-* @return The function will return the new data flag\r
-*\r
-* Checks to see if the Rx message box has pending Rx data, returns\r
-* 0 is flag not set otherwise will return the Tx request flag itself.\r
-*/\r
-\r
-\r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
-\r
-uint32_t canIsRxMessageArrived(canBASE_t *node, uint32_t messageBox)\r
-{\r
- uint32_t flag;\r
- uint32_t regIndex = (messageBox - 1U) >> 5U;\r
- uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
-\r
-/* USER CODE BEGIN (16) */\r
-/* USER CODE END */\r
-\r
- /** - Read Tx request register */\r
- flag = node->NWDATx[regIndex] & bitIndex;\r
-\r
-/* USER CODE BEGIN (17) */\r
-/* USER CODE END */\r
-\r
- return flag;\r
-}\r
-\r
-\r
-/** @fn uint32_t canIsMessageBoxValid(canBASE_t *node, uint32_t messageBox)\r
-* @brief Chechs if message box is valid\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-* @param[in] messageBox Message box number of CAN node:\r
-* - canMESSAGE_BOX1: CAN message box 1\r
-* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
-* - canMESSAGE_BOX64: CAN message box 64\r
-* @return The function will return the new data flag\r
-*\r
-* Checks to see if the message box is valid for operation, returns\r
-* 0 is flag not set otherwise will return the validation flag itself.\r
-*/\r
-\r
-\r
-/* USER CODE BEGIN (18) */\r
-/* USER CODE END */\r
-\r
-uint32_t canIsMessageBoxValid(canBASE_t *node, uint32_t messageBox)\r
-{\r
- uint32_t flag;\r
- uint32_t regIndex = (messageBox - 1U) >> 5U;\r
- uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
-\r
-/* USER CODE BEGIN (19) */\r
-/* USER CODE END */\r
-\r
- /** - Read Tx request register */\r
- flag = node->MSGVALx[regIndex] & bitIndex;\r
-\r
-/* USER CODE BEGIN (20) */\r
-/* USER CODE END */\r
-\r
- return flag;\r
-}\r
-\r
-\r
-/** @fn uint32_t canGetLastError(canBASE_t *node)\r
-* @brief Gets last RX/TX-Error of CAN message traffic\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-* @return The function will return:\r
-* - canERROR_OK (0): When no CAN error occured \r
-* - canERROR_STUFF (1): When a stuff error occured on RX message \r
-* - canERROR_FORMAT (2): When a form/format error occured on RX message \r
-* - canERROR_ACKNOWLEDGE (3): When a TX message wasn't acknowledged \r
-* - canERROR_BIT1 (4): When a TX message monitored dominant level where recessive is expected \r
-* - canERROR_BIT0 (5): When a TX message monitored recessive level where dominant is expected \r
-* - canERROR_CRC (6): When a RX message has wrong CRC value \r
-* - canERROR_NO (7): When no error occured since last call of this function \r
-*\r
-* This function returns the last occured error code of an RX or TX message,\r
-* since the last call of this function.\r
-*\r
-*/\r
-\r
-\r
-/* USER CODE BEGIN (21) */\r
-/* USER CODE END */\r
-\r
-uint32_t canGetLastError(canBASE_t *node)\r
-{\r
- uint32_t errorCode;\r
-\r
-/* USER CODE BEGIN (22) */\r
-/* USER CODE END */\r
-\r
- /** - Get last error code */\r
- errorCode = node->ES & 7U;\r
-\r
- /** @note The function canInit has to be called before this function can be used. */\r
-\r
-/* USER CODE BEGIN (23) */\r
-/* USER CODE END */\r
-\r
- return errorCode;\r
-}\r
-\r
-\r
-/** @fn uint32_t canGetErrorLevel(canBASE_t *node)\r
-* @brief Gets error level of a CAN node\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-* @return The function will return:\r
-* - canLEVEL_ACTIVE (0x00): When RX- and TX error counters are below 96 \r
-* - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and 127 \r
-* - canLEVEL_PASSIVE (0x20): When RX- or TX error counter are between 128 and 255 \r
-* - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 \r
-*\r
-* This function returns the current error level of a CAN node.\r
-*\r
-*/\r
-\r
-\r
-/* USER CODE BEGIN (24) */\r
-/* USER CODE END */\r
-\r
-uint32_t canGetErrorLevel(canBASE_t *node)\r
-{\r
- uint32_t errorLevel;\r
-\r
-/* USER CODE BEGIN (25) */\r
-/* USER CODE END */\r
-\r
- /** - Get error level */\r
- errorLevel = node->ES & 0xE0U;\r
-\r
- /** @note The function canInit has to be called before this function can be used. */\r
-\r
-/* USER CODE BEGIN (26) */\r
-/* USER CODE END */\r
-\r
- return errorLevel;\r
-}\r
-\r
-\r
-/** @fn void canEnableErrorNotification(canBASE_t *node)\r
-* @brief Enable error notification\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-*\r
-* This function will enable the notification for the reaching the error levels warning, passive and bus off.\r
-*/\r
-\r
-/* USER CODE BEGIN (27) */\r
-/* USER CODE END */\r
-\r
-void canEnableErrorNotification(canBASE_t *node)\r
-{\r
-/* USER CODE BEGIN (28) */\r
-/* USER CODE END */\r
-\r
- node->CTL |= 8U;\r
-\r
- /** @note The function canInit has to be called before this function can be used. */\r
-\r
-/* USER CODE BEGIN (29) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void canDisableErrorNotification(canBASE_t *node)\r
-* @brief Disable error notification\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-*\r
-* This function will disable the notification for the reaching the error levels warning, passive and bus off.\r
-*/\r
-\r
-/* USER CODE BEGIN (30) */\r
-/* USER CODE END */\r
-\r
-void canDisableErrorNotification(canBASE_t *node)\r
-{\r
-/* USER CODE BEGIN (31) */\r
-/* USER CODE END */\r
-\r
- node->CTL &= ~8U;\r
-\r
- /** @note The function canInit has to be called before this function can be used. */\r
-\r
-/* USER CODE BEGIN (32) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void canIoSetDirection(canBASE_t *node,uint32_t TxDir,uint32_t RxDir)\r
-* @brief Set Port Direction\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-* @param[in] TxDir - TX Pin direction\r
-* @param[in] RxDir - RX Pin direction\r
-*\r
-* Set the direction of CAN pins at runtime when configured as IO pins.\r
-*/\r
-void canIoSetDirection(canBASE_t *node,uint32_t TxDir,uint32_t RxDir)\r
-{\r
- node->TIOC = TxDir << 2;\r
- node->RIOC = RxDir << 2;\r
-}\r
-\r
-/** @fn void canIoSetPort(canBASE_t *node, uint32_t TxValue, uint32_t RxValue)\r
-* @brief Write Port Value\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-* @param[in] TxValue - TX Pin value 0 or 1\r
-* @param[in] RxValue - RX Pin value 0 or 1\r
-*\r
-* Writes a value to TX and RX pin of a given CAN module when configured as IO pins.\r
-*/\r
-void canIoSetPort(canBASE_t *node, uint32_t TxValue, uint32_t RxValue)\r
-{\r
-/* USER CODE BEGIN (33) */\r
-/* USER CODE END */\r
-\r
- node->TIOC = TxValue << 1;\r
- node->RIOC = RxValue << 1;\r
-\r
-/* USER CODE BEGIN (34) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn uint32_t canIoTxGetBit(canBASE_t *node)\r
-* @brief Read TX Bit\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-*\r
-* Reads a the current value from the TX pin of the given CAN port\r
-*/\r
-uint32_t canIoTxGetBit(canBASE_t *node)\r
-{\r
-/* USER CODE BEGIN (35) */\r
-/* USER CODE END */\r
-\r
- return (node->TIOC >> 0) & 1U;\r
-}\r
-\r
-/** @fn uint32_t canIoRxGetBit(canBASE_t *node)\r
-* @brief Read RX Bit\r
-* @param[in] node Pointer to CAN node:\r
-* - canREG1: CAN1 node pointer\r
-* - canREG2: CAN2 node pointer\r
-* - canREG3: CAN3 node pointer\r
-*\r
-* Reads a the current value from the RX pin of the given CAN port\r
-*/\r
-uint32_t canIoRxGetBit(canBASE_t *node)\r
-{\r
-/* USER CODE BEGIN (36) */\r
-/* USER CODE END */\r
-\r
- return (node->RIOC >> 0) & 1U;\r
-}\r
-\r
-/** @fn void can1HighLevelInterrupt(void)\r
-* @brief CAN1 Level 0 Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (37) */\r
-/* USER CODE END */\r
-\r
-\r
-#pragma INTERRUPT(can1HighLevelInterrupt, IRQ)\r
-\r
-void can1HighLevelInterrupt(void)\r
-{\r
- uint32_t value = canREG1->INT;\r
-\r
-/* USER CODE BEGIN (38) */\r
-/* USER CODE END */\r
-\r
- if (value == 0x8000U)\r
- {\r
- canErrorNotification(canREG1, canREG1->ES);\r
- return;\r
- }\r
-\r
- /** - Setup IF1 for clear pending interrupt flag */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1CMD = 0x08;\r
- canREG1->IF1NO = value;\r
-\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1CMD = 0x87;\r
-\r
- canMessageNotification(canREG1, value);\r
-\r
-/* USER CODE BEGIN (39) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void can1LowLevelInterrupt(void)\r
-* @brief CAN1 Level 1 Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (40) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(can1LowLevelInterrupt, IRQ)\r
-\r
-void can1LowLevelInterrupt(void)\r
-{\r
- uint32_t messageBox = canREG1->INT >> 16U;\r
-\r
-/* USER CODE BEGIN (41) */\r
-/* USER CODE END */\r
-\r
- /** - Setup IF1 for clear pending interrupt flag */\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1CMD = 0x08;\r
- canREG1->IF1NO = messageBox;\r
-\r
- while (canREG1->IF1STAT & 0x80);\r
-\r
- canREG1->IF1CMD = 0x87;\r
-\r
- canMessageNotification(canREG1, messageBox);\r
-\r
-/* USER CODE BEGIN (42) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void can2HighLevelInterrupt(void)\r
-* @brief CAN2 Level 0 Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (43) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(can2HighLevelInterrupt, IRQ)\r
-\r
-void can2HighLevelInterrupt(void)\r
-{\r
- uint32_t value = canREG2->INT;\r
-\r
-/* USER CODE BEGIN (44) */\r
-/* USER CODE END */\r
-\r
- if (value == 0x8000U)\r
- {\r
- canErrorNotification(canREG2, canREG2->ES);\r
- return;\r
- }\r
-\r
- /** - Setup IF1 for clear pending interrupt flag */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1CMD = 0x08;\r
- canREG2->IF1NO = value;\r
-\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1CMD = 0x87;\r
-\r
- canMessageNotification(canREG2, value);\r
-\r
-/* USER CODE BEGIN (45) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void can2LowLevelInterrupt(void)\r
-* @brief CAN2 Level 1 Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (46) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(can2LowLevelInterrupt, IRQ)\r
-\r
-void can2LowLevelInterrupt(void)\r
-{\r
- uint32_t messageBox = canREG2->INT >> 16U;\r
-\r
-/* USER CODE BEGIN (47) */\r
-/* USER CODE END */\r
-\r
- /** - Setup IF1 for clear pending interrupt flag */\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1CMD = 0x08;\r
- canREG2->IF1NO = messageBox;\r
-\r
- while (canREG2->IF1STAT & 0x80);\r
-\r
- canREG2->IF1CMD = 0x87;\r
-\r
- canMessageNotification(canREG2, messageBox);\r
-\r
-/* USER CODE BEGIN (48) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void can3HighLevelInterrupt(void)\r
-* @brief CAN3 Level 0 Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (49) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(can3HighLevelInterrupt, IRQ)\r
-\r
-void can3HighLevelInterrupt(void)\r
-{\r
- uint32_t value = canREG3->INT;\r
-\r
-/* USER CODE BEGIN (50) */\r
-/* USER CODE END */\r
-\r
- if (value == 0x8000U)\r
- {\r
- canErrorNotification(canREG3, canREG3->ES);\r
- return;\r
- }\r
-\r
- /** - Setup IF1 for clear pending interrupt flag */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1CMD = 0x08;\r
- canREG3->IF1NO = value;\r
-\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1CMD = 0x87;\r
-\r
- canMessageNotification(canREG3, value);\r
-\r
-/* USER CODE BEGIN (51) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void can3LowLevelInterrupt(void)\r
-* @brief CAN3 Level 1 Interrupt Handler\r
-*/\r
-\r
-/* USER CODE BEGIN (52) */\r
-/* USER CODE END */\r
-\r
-#pragma INTERRUPT(can3LowLevelInterrupt, IRQ)\r
-\r
-void can3LowLevelInterrupt(void)\r
-{\r
- uint32_t messageBox = canREG3->INT >> 16U;\r
-\r
-/* USER CODE BEGIN (53) */\r
-/* USER CODE END */\r
-\r
- /** - Setup IF1 for clear pending interrupt flag */\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1CMD = 0x08;\r
- canREG3->IF1NO = messageBox;\r
-\r
- while (canREG3->IF1STAT & 0x80);\r
-\r
- canREG3->IF1CMD = 0x87;\r
-\r
- canMessageNotification(canREG3, messageBox);\r
-\r
-/* USER CODE BEGIN (54) */\r
-/* USER CODE END */\r
-}\r
-\r
+/** @file can.c
+* @brief CAN Driver Source File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+* This file contains:
+* - API Funcions
+* - Interrupt Handlers
+* .
+* which are relevant for the CAN driver.
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* Include Files */
+
+#include "ti_drv_can.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/* Global and Static Variables */
+
+#ifndef __little_endian__
+ static const uint32_t s_canByteOrder[] = {3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U};
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+/** @fn void canInit(void)
+* @brief Initializes CAN Driver
+*
+* This function initializes the CAN driver.
+*
+*/
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+void canInit(void)
+{
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+ /** @b Initialize @b CAN1: */
+
+ /** - Setup control register
+ * - Disable automatic wakeup on bus activity
+ * - Local power down mode disabled
+ * - Disable DMA request lines
+ * - Enable global Interrupt Line 0 and 1
+ * - Disable debug mode
+ * - Release from software reset
+ * - Enable/Disable parity or ECC
+ * - Enable/Disable auto bus on timer
+ * - Setup message completion before entering debug state
+ * - Setup normal operation mode
+ * - Request write access to the configuration registers
+ * - Setup automatic retransmission of messages
+ * - Disable error interrups
+ * - Disable status interrupts
+ * - Enter initialization mode
+ */
+ canREG1->CTL = 0x00000000U
+ | 0x00000000U
+ | 0x00000005U
+ | 0x000200043U;
+
+ /** - Clear all pending error flags and reset current status */
+ canREG1->ES = 0x0000031FU;
+
+ /** - Assign interrupt level for messages */
+ canREG1->INTMUXx[0U] = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ canREG1->INTMUXx[1U] = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Setup auto bus on timer pewriod */
+ canREG1->ABOTR = 0U;
+
+ /** - Initialize message 1
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x80000000U | 0x40000000U | 0x20000000U | ((1U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 1;
+
+ /** - Initialize message 2
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((2U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000C00U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 2;
+
+ /** - Initialize message 3
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((3U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 3;
+
+ /** - Initialize message 4
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 4;
+
+ /** - Initialize message 5
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 5;
+
+ /** - Initialize message 6
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 6;
+
+ /** - Initialize message 7
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 7;
+
+ /** - Initialize message 8
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 8;
+
+ /** - Initialize message 9
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 9;
+
+ /** - Initialize message 10
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 10;
+
+ /** - Initialize message 11
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 11;
+
+ /** - Initialize message 12
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 12;
+
+ /** - Initialize message 13
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 13;
+
+ /** - Initialize message 14
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 14;
+
+ /** - Initialize message 15
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 15;
+
+ /** - Initialize message 16
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 16;
+
+ /** - Initialize message 17
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 17;
+
+ /** - Initialize message 18
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 18;
+
+ /** - Initialize message 19
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 19;
+
+ /** - Initialize message 20
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 20;
+
+ /** - Initialize message 21
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 21;
+
+ /** - Initialize message 22
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 22;
+
+ /** - Initialize message 23
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 23;
+
+ /** - Initialize message 24
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 24;
+
+ /** - Initialize message 25
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 25;
+
+ /** - Initialize message 26
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 26;
+
+ /** - Initialize message 27
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 27;
+
+ /** - Initialize message 28
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 28;
+
+ /** - Initialize message 29
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 29;
+
+ /** - Initialize message 30
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 30;
+
+ /** - Initialize message 31
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 31;
+
+ /** - Initialize message 32
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 32;
+
+ /** - Initialize message 33
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((33U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 33;
+
+ /** - Initialize message 34
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((34U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 34;
+
+ /** - Initialize message 35
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((35U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 35;
+
+ /** - Initialize message 36
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((36U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 36;
+
+ /** - Initialize message 37
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((37U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 37;
+
+ /** - Initialize message 38
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((38U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 38;
+
+ /** - Initialize message 39
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((39U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 39;
+
+ /** - Initialize message 40
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((40U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 40;
+
+ /** - Initialize message 41
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((41U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 41;
+
+ /** - Initialize message 42
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((42U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 42;
+
+ /** - Initialize message 43
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((43U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 43;
+
+ /** - Initialize message 44
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((44U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 44;
+
+ /** - Initialize message 45
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((45U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 45;
+
+ /** - Initialize message 46
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((46U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 46;
+
+ /** - Initialize message 47
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((47U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 47;
+
+ /** - Initialize message 48
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((48U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 48;
+
+ /** - Initialize message 49
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((49U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 49;
+
+ /** - Initialize message 50
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((50U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 50;
+
+ /** - Initialize message 51
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((51U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 51;
+
+ /** - Initialize message 52
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((52U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 52;
+
+ /** - Initialize message 53
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((53U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 53;
+
+ /** - Initialize message 54
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((54U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 54;
+
+ /** - Initialize message 55
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((55U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 55;
+
+ /** - Initialize message 56
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((56U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 56;
+
+ /** - Initialize message 57
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((57U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 57;
+
+ /** - Initialize message 58
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((58U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 58;
+
+ /** - Initialize message 59
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((59U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 59;
+
+ /** - Initialize message 60
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((60U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 60;
+
+ /** - Initialize message 61
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((61U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 61;
+
+ /** - Initialize message 62
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((62U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 62;
+
+ /** - Initialize message 63
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((63U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF1CMD = 0xF8;
+ canREG1->IF1NO = 63;
+
+ /** - Initialize message 64
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((64U & 0x1FFFFFFFU) << 0U);
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG1->IF2CMD = 0xF8;
+ canREG1->IF2NO = 64;
+
+ /** - Setup IF1 for data transmission
+ * - Wait until IF1 is ready for use
+ * - Set IF1 control byte
+ */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1CMD = 0x87;
+
+ /** - Setup IF2 for reading data
+ * - Wait until IF1 is ready for use
+ * - Set IF1 control byte
+ */
+ while (canREG1->IF2STAT & 0x80);
+
+ canREG1->IF2CMD = 0x17;
+ /** - Setup bit timing
+ * - Setup baud rate prescaler extension
+ * - Setup TSeg2
+ * - Setup TSeg1
+ * - Setup sample jump width
+ * - Setup baud rate prescaler
+ */
+ canREG1->BTR = (0U << 16U) |
+ ((2U - 1U) << 12U) |
+ (((3U + 2U) - 1U) << 8U) |
+ ((2U - 1U) << 6U) |
+ 19U;
+
+ /** - CAN1 Port output values */
+ canREG1->TIOC = (1 << 18 )
+ | (0 << 17 )
+ | (1 << 3 )
+ | (0 << 2 )
+ | (0 << 1 )
+ | (0 );
+ canREG1->RIOC = (1 << 18 )
+ | (0 << 17 )
+ | (1 << 3 )
+ | (0 << 2 )
+ | (0 <<1 )
+ | (0 );
+
+
+ /** - Leave configuration and initialization mode */
+ canREG1->CTL &= ~0x00000041U;
+
+
+ /** @b Initialize @b CAN2: */
+
+ /** - Setup control register
+ * - Disable automatic wakeup on bus activity
+ * - Local power down mode disabled
+ * - Disable DMA request lines
+ * - Enable global Interrupt Line 0 and 1
+ * - Disable debug mode
+ * - Release from software reset
+ * - Enable/Disable parity or ECC
+ * - Enable/Disable auto bus on timer
+ * - Setup message completion before entering debug state
+ * - Setup normal operation mode
+ * - Request write access to the configuration registers
+ * - Setup automatic retransmission of messages
+ * - Disable error interrups
+ * - Disable status interrupts
+ * - Enter initialization mode
+ */
+ canREG2->CTL = 0x00000000U
+ | 0x00000000U
+ | 0x00000005U
+ | 0x000200043U;
+
+ /** - Clear all pending error flags and reset current status */
+ canREG2->ES = 0x0000031FU;
+
+
+ /** - Assign interrupt level for messages */
+ canREG2->INTMUXx[0U] = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ canREG2->INTMUXx[1U] = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+
+ /** - Setup auto bus on timer pewriod */
+ canREG2->ABOTR = 0U;
+
+ /** - Initialize message 1
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((1U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 1;
+
+ /** - Initialize message 2
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x80000000U | 0x40000000U | 0x20000000U | ((2U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000C00U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 2;
+
+ /** - Initialize message 3
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((3U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 3;
+
+ /** - Initialize message 4
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 4;
+
+ /** - Initialize message 5
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 5;
+
+ /** - Initialize message 6
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 6;
+
+ /** - Initialize message 7
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 7;
+
+ /** - Initialize message 8
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 8;
+
+ /** - Initialize message 9
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 9;
+
+ /** - Initialize message 10
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 10;
+
+ /** - Initialize message 11
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 11;
+
+ /** - Initialize message 12
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 12;
+
+ /** - Initialize message 13
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 13;
+
+ /** - Initialize message 14
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 14;
+
+ /** - Initialize message 15
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 15;
+
+ /** - Initialize message 16
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 16;
+
+ /** - Initialize message 17
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 17;
+
+ /** - Initialize message 18
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 18;
+
+ /** - Initialize message 19
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 19;
+
+ /** - Initialize message 20
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 20;
+
+ /** - Initialize message 21
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 21;
+
+ /** - Initialize message 22
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 22;
+
+ /** - Initialize message 23
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 23;
+
+ /** - Initialize message 24
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 24;
+
+ /** - Initialize message 25
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 25;
+
+ /** - Initialize message 26
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 26;
+
+ /** - Initialize message 27
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 27;
+
+ /** - Initialize message 28
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 28;
+
+ /** - Initialize message 29
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 29;
+
+ /** - Initialize message 30
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 30;
+
+ /** - Initialize message 31
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 31;
+
+ /** - Initialize message 32
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 32;
+
+ /** - Initialize message 33
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((33U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 33;
+
+ /** - Initialize message 34
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((34U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 34;
+
+ /** - Initialize message 35
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((35U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 35;
+
+ /** - Initialize message 36
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((36U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 36;
+
+ /** - Initialize message 37
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((37U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 37;
+
+ /** - Initialize message 38
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((38U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 38;
+
+ /** - Initialize message 39
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((39U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 39;
+
+ /** - Initialize message 40
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((40U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 40;
+
+ /** - Initialize message 41
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((41U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 41;
+
+ /** - Initialize message 42
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((42U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 42;
+
+ /** - Initialize message 43
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((43U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 43;
+
+ /** - Initialize message 44
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((44U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 44;
+
+ /** - Initialize message 45
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((45U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 45;
+
+ /** - Initialize message 46
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((46U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 46;
+
+ /** - Initialize message 47
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((47U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 47;
+
+ /** - Initialize message 48
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((48U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 48;
+
+ /** - Initialize message 49
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((49U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 49;
+
+ /** - Initialize message 50
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((50U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 50;
+
+ /** - Initialize message 51
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((51U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 51;
+
+ /** - Initialize message 52
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((52U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 52;
+
+ /** - Initialize message 53
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((53U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 53;
+
+ /** - Initialize message 54
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((54U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 54;
+
+ /** - Initialize message 55
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((55U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 55;
+
+ /** - Initialize message 56
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((56U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 56;
+
+ /** - Initialize message 57
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((57U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 57;
+
+ /** - Initialize message 58
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((58U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 58;
+
+ /** - Initialize message 59
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((59U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 59;
+
+ /** - Initialize message 60
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((60U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 60;
+
+ /** - Initialize message 61
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((61U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 61;
+
+ /** - Initialize message 62
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((62U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 62;
+
+ /** - Initialize message 63
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((63U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF1CMD = 0xF8;
+ canREG2->IF1NO = 63;
+
+ /** - Initialize message 64
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((64U & 0x1FFFFFFFU) << 0U);
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG2->IF2CMD = 0xF8;
+ canREG2->IF2NO = 64;
+
+ /** - Setup IF1 for data transmission
+ * - Wait until IF1 is ready for use
+ * - Set IF1 control byte
+ */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1CMD = 0x87;
+
+ /** - Setup IF2 for reading data
+ * - Wait until IF1 is ready for use
+ * - Set IF1 control byte
+ */
+ while (canREG2->IF2STAT & 0x80);
+
+ canREG2->IF2CMD = 0x17;
+ /** - Setup bit timing
+ * - Setup baud rate prescaler extension
+ * - Setup TSeg2
+ * - Setup TSeg1
+ * - Setup sample jump width
+ * - Setup baud rate prescaler
+ */
+ canREG2->BTR = (0U << 16U) |
+ ((2U - 1U) << 12U) |
+ (((3U + 2U) - 1U) << 8U) |
+ ((2U - 1U) << 6U) |
+ 19U;
+
+ /** - CAN2 Port output values */
+ canREG2->TIOC = (1 << 18 )
+ | (0 << 17 )
+ | (1 << 3 )
+ | (0 << 2 )
+ | (0 << 1 )
+ | (0 );
+ canREG2->RIOC = (1 << 18 )
+ | (0 << 17 )
+ | (1 << 3 )
+ | (0 << 2 )
+ | (0 <<1 )
+ | (0 );
+
+ /** - Leave configuration and initialization mode */
+ canREG2->CTL &= ~0x00000041U;
+
+ /** @b Initialize @b CAN3: */
+
+ /** - Setup control register
+ * - Disable automatic wakeup on bus activity
+ * - Local power down mode disabled
+ * - Disable DMA request lines
+ * - Enable global Interrupt Line 0 and 1
+ * - Disable debug mode
+ * - Release from software reset
+ * - Enable/Disable parity or ECC
+ * - Enable/Disable auto bus on timer
+ * - Setup message completion before entering debug state
+ * - Setup normal operation mode
+ * - Request write access to the configuration registers
+ * - Setup automatic retransmission of messages
+ * - Disable error interrups
+ * - Disable status interrupts
+ * - Enter initialization mode
+ */
+ canREG3->CTL = 0x00000000U
+ | 0x00000000U
+ | 0x00000005U
+ | 0x000200043U;
+
+ /** - Clear all pending error flags and reset current status */
+ canREG3->ES = 0x0000031FU;
+
+ /** - Assign interrupt level for messages */
+ canREG3->INTMUXx[0U] = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Setup auto bus on timer pewriod */
+ canREG3->ABOTR = 0U;
+
+ /** - Initialize message 1
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((1U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 1;
+
+ /** - Initialize message 2
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((2U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000C00U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 2;
+
+ /** - Initialize message 3
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x80000000U | 0x40000000U | 0x20000000U | ((3U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000C00U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 3;
+
+ /** - Initialize message 4
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 4;
+
+ /** - Initialize message 5
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 5;
+
+ /** - Initialize message 6
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 6;
+
+ /** - Initialize message 7
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 7;
+
+ /** - Initialize message 8
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 8;
+
+ /** - Initialize message 9
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 9;
+
+ /** - Initialize message 10
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 10;
+
+ /** - Initialize message 11
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 11;
+
+ /** - Initialize message 12
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 12;
+
+ /** - Initialize message 13
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 13;
+
+ /** - Initialize message 14
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 14;
+
+ /** - Initialize message 15
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 15;
+
+ /** - Initialize message 16
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 16;
+
+ /** - Initialize message 17
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 17;
+
+ /** - Initialize message 18
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 18;
+
+ /** - Initialize message 19
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 19;
+
+ /** - Initialize message 20
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 20;
+
+ /** - Initialize message 21
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 21;
+
+ /** - Initialize message 22
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 22;
+
+ /** - Initialize message 23
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 23;
+
+ /** - Initialize message 24
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 24;
+
+ /** - Initialize message 25
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 25;
+
+ /** - Initialize message 26
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 26;
+
+ /** - Initialize message 27
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 27;
+
+ /** - Initialize message 28
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 28;
+
+ /** - Initialize message 29
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 29;
+
+ /** - Initialize message 30
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 30;
+
+ /** - Initialize message 31
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF1CMD = 0xF8;
+ canREG3->IF1NO = 31;
+
+ /** - Initialize message 32
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;
+ canREG3->IF2CMD = 0xF8;
+ canREG3->IF2NO = 32;
+
+ /** - Setup IF1 for data transmission
+ * - Wait until IF1 is ready for use
+ * - Set IF1 control byte
+ */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1CMD = 0x87;
+
+ /** - Setup IF2 for reading data
+ * - Wait until IF1 is ready for use
+ * - Set IF1 control byte
+ */
+ while (canREG3->IF2STAT & 0x80);
+
+ canREG3->IF2CMD = 0x17;
+
+ /** - Setup bit timing
+ * - Setup baud rate prescaler extension
+ * - Setup TSeg2
+ * - Setup TSeg1
+ * - Setup sample jump width
+ * - Setup baud rate prescaler
+ */
+ canREG3->BTR = (0U << 16U) |
+ ((2U - 1U) << 12U) |
+ (((3U + 2U) - 1U) << 8U) |
+ ((2U - 1U) << 6U) |
+ 19U;
+
+
+ /** - CAN3 Port output values */
+ canREG3->TIOC = (1 << 18 )
+ | (0 << 17 )
+ | (1 << 3 )
+ | (0 << 2 )
+ | (0 << 1 )
+ | (0 );
+ canREG3->RIOC = (1 << 18 )
+ | (0 << 17 )
+ | (1 << 3 )
+ | (0 << 2 )
+ | (0 <<1 )
+ | (0 );
+
+ /** - Leave configuration and initialization mode */
+ canREG3->CTL &= ~0x00000041U;
+
+ /** @note This function has to be called before the driver can be used.\n
+ * This function has to be executed in priviledged mode.\n
+ */
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+}
+
+
+/** @fn uint32_t canTransmit(canBASE_t *node, uint32_t messageBox, const uint8_t *data)
+* @brief Transmits a CAN message
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @param[in] data Pointer to CAN TX data
+* @return The function will return:
+* - 0: When the setup of the TX message box wasn't successful
+* - 1: When the setup of the TX message box was successful
+*
+* This function writes a CAN message into a CAN message box.
+*
+*/
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+uint32_t canTransmit(canBASE_t *node, uint32_t messageBox, const uint8_t *data)
+{
+ uint32_t i;
+ uint32_t success = 0U;
+ uint32_t regIndex = (messageBox - 1U) >> 5U;
+ uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+ /** - Check for pending message:
+ * - pending message, return 0
+ * - no pending message, start new transmission
+ */
+ if (node->TXRQx[regIndex] & bitIndex)
+ {
+ return success;
+ }
+
+ /** - Wait until IF1 is ready for use */
+ while (node->IF1STAT & 0x80);
+
+ /** - Copy TX data into IF1 */
+ for (i = 0U; i < 8U; i++)
+ {
+#ifdef __little_endian__
+ node->IF1DATx[i] = *data++;
+#else
+ node->IF1DATx[s_canByteOrder[i]] = *data++;
+#endif
+ }
+
+ /** - Copy TX data into mesasge box */
+ node->IF1NO = messageBox;
+
+ success = 1U;
+
+ /** @note The function canInit has to be called before this function can be used.\n
+ * The user is responsible to initialize the message box.
+ */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ return success;
+}
+
+
+/** @fn uint32_t canGetData(canBASE_t *node, uint32_t messageBox, uint8_t * const data)
+* @brief Gets received a CAN message
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @param[out] data Pointer to store CAN RX data
+* @return The function will return:
+* - 0: When RX message box hasn't received new data
+* - 1: When RX data are stored in the data buffer
+* - 3: When RX data are stored in the data buffer and a message was lost
+*
+* This function writes a CAN message into a CAN message box.
+*
+*/
+
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+uint32_t canGetData(canBASE_t *node, uint32_t messageBox, uint8_t * const data)
+{
+ uint32_t i;
+ uint32_t size;
+ uint8_t *pData = (uint8_t *)data;
+ uint32_t success = 0U;
+ uint32_t regIndex = (messageBox - 1U) >> 5U;
+ uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+ /** - Check if new data have been arrived:
+ * - no new data, return 0
+ * - new data, get received message
+ */
+ if (!(node->NWDATx[regIndex] & bitIndex))
+ {
+ return success;
+ }
+
+ /** - Wait until IF2 is ready for use */
+ while (node->IF2STAT & 0x80);
+
+ /** - Copy data into IF2 */
+ node->IF2NO = messageBox;
+
+ /** - Wait until data are copied into IF2 */
+ while (node->IF2STAT & 0x80);
+
+ /** - Get number of received bytes */
+ size = node->IF2MCTL & 0xFU;
+
+ /** - Copy RX data into destination buffer */
+ for (i = 0U; i < size; i++)
+ {
+#ifdef __little_endian__
+ *pData++ = node->IF2DATx[i];
+#else
+ *pData++ = node->IF2DATx[s_canByteOrder[i]];
+#endif
+ }
+
+ success = 1U;
+
+ /** - Check if data have been lost:
+ * - no data lost, return 1
+ * - data lost, return 3
+ */
+ if (node->IF2MCTL & 0x4000U)
+ {
+ success = 3U;
+ }
+
+ /** @note The function canInit has to be called before this function can be used.\n
+ * The user is responsible to initialize the message box.
+ */
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ return success;
+}
+
+
+/** @fn uint32_t canIsTxMessagePending(canBASE_t *node, uint32_t messageBox)
+* @brief Gets Tx message box transmission status
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @return The function will return the tx request flag
+*
+* Checks to see if the Tx message box has a pending Tx request, returns
+* 0 is flag not set otherwise will return the Tx request flag itself.
+*/
+
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+uint32_t canIsTxMessagePending(canBASE_t *node, uint32_t messageBox)
+{
+ uint32_t flag;
+ uint32_t regIndex = (messageBox - 1U) >> 5U;
+ uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ /** - Read Tx request reigster */
+ flag = node->TXRQx[regIndex] & bitIndex;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+ return flag;
+}
+
+
+/** @fn uint32_t canIsRxMessageArrived(canBASE_t *node, uint32_t messageBox)
+* @brief Gets Rx message box reception status
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @return The function will return the new data flag
+*
+* Checks to see if the Rx message box has pending Rx data, returns
+* 0 is flag not set otherwise will return the Tx request flag itself.
+*/
+
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+uint32_t canIsRxMessageArrived(canBASE_t *node, uint32_t messageBox)
+{
+ uint32_t flag;
+ uint32_t regIndex = (messageBox - 1U) >> 5U;
+ uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+ /** - Read Tx request register */
+ flag = node->NWDATx[regIndex] & bitIndex;
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ return flag;
+}
+
+
+/** @fn uint32_t canIsMessageBoxValid(canBASE_t *node, uint32_t messageBox)
+* @brief Chechs if message box is valid
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @return The function will return the new data flag
+*
+* Checks to see if the message box is valid for operation, returns
+* 0 is flag not set otherwise will return the validation flag itself.
+*/
+
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+uint32_t canIsMessageBoxValid(canBASE_t *node, uint32_t messageBox)
+{
+ uint32_t flag;
+ uint32_t regIndex = (messageBox - 1U) >> 5U;
+ uint32_t bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ /** - Read Tx request register */
+ flag = node->MSGVALx[regIndex] & bitIndex;
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+ return flag;
+}
+
+
+/** @fn uint32_t canGetLastError(canBASE_t *node)
+* @brief Gets last RX/TX-Error of CAN message traffic
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @return The function will return:
+* - canERROR_OK (0): When no CAN error occured
+* - canERROR_STUFF (1): When a stuff error occured on RX message
+* - canERROR_FORMAT (2): When a form/format error occured on RX message
+* - canERROR_ACKNOWLEDGE (3): When a TX message wasn't acknowledged
+* - canERROR_BIT1 (4): When a TX message monitored dominant level where recessive is expected
+* - canERROR_BIT0 (5): When a TX message monitored recessive level where dominant is expected
+* - canERROR_CRC (6): When a RX message has wrong CRC value
+* - canERROR_NO (7): When no error occured since last call of this function
+*
+* This function returns the last occured error code of an RX or TX message,
+* since the last call of this function.
+*
+*/
+
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+uint32_t canGetLastError(canBASE_t *node)
+{
+ uint32_t errorCode;
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+ /** - Get last error code */
+ errorCode = node->ES & 7U;
+
+ /** @note The function canInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+ return errorCode;
+}
+
+
+/** @fn uint32_t canGetErrorLevel(canBASE_t *node)
+* @brief Gets error level of a CAN node
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @return The function will return:
+* - canLEVEL_ACTIVE (0x00): When RX- and TX error counters are below 96
+* - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and 127
+* - canLEVEL_PASSIVE (0x20): When RX- or TX error counter are between 128 and 255
+* - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255
+*
+* This function returns the current error level of a CAN node.
+*
+*/
+
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+uint32_t canGetErrorLevel(canBASE_t *node)
+{
+ uint32_t errorLevel;
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+ /** - Get error level */
+ errorLevel = node->ES & 0xE0U;
+
+ /** @note The function canInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+ return errorLevel;
+}
+
+
+/** @fn void canEnableErrorNotification(canBASE_t *node)
+* @brief Enable error notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* This function will enable the notification for the reaching the error levels warning, passive and bus off.
+*/
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+void canEnableErrorNotification(canBASE_t *node)
+{
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ node->CTL |= 8U;
+
+ /** @note The function canInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+}
+
+
+/** @fn void canDisableErrorNotification(canBASE_t *node)
+* @brief Disable error notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* This function will disable the notification for the reaching the error levels warning, passive and bus off.
+*/
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+void canDisableErrorNotification(canBASE_t *node)
+{
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+ node->CTL &= ~8U;
+
+ /** @note The function canInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+}
+
+/** @fn void canIoSetDirection(canBASE_t *node,uint32_t TxDir,uint32_t RxDir)
+* @brief Set Port Direction
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] TxDir - TX Pin direction
+* @param[in] RxDir - RX Pin direction
+*
+* Set the direction of CAN pins at runtime when configured as IO pins.
+*/
+void canIoSetDirection(canBASE_t *node,uint32_t TxDir,uint32_t RxDir)
+{
+ node->TIOC = TxDir << 2;
+ node->RIOC = RxDir << 2;
+}
+
+/** @fn void canIoSetPort(canBASE_t *node, uint32_t TxValue, uint32_t RxValue)
+* @brief Write Port Value
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] TxValue - TX Pin value 0 or 1
+* @param[in] RxValue - RX Pin value 0 or 1
+*
+* Writes a value to TX and RX pin of a given CAN module when configured as IO pins.
+*/
+void canIoSetPort(canBASE_t *node, uint32_t TxValue, uint32_t RxValue)
+{
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+ node->TIOC = TxValue << 1;
+ node->RIOC = RxValue << 1;
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+}
+
+/** @fn uint32_t canIoTxGetBit(canBASE_t *node)
+* @brief Read TX Bit
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* Reads a the current value from the TX pin of the given CAN port
+*/
+uint32_t canIoTxGetBit(canBASE_t *node)
+{
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+ return (node->TIOC >> 0) & 1U;
+}
+
+/** @fn uint32_t canIoRxGetBit(canBASE_t *node)
+* @brief Read RX Bit
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* Reads a the current value from the RX pin of the given CAN port
+*/
+uint32_t canIoRxGetBit(canBASE_t *node)
+{
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+ return (node->RIOC >> 0) & 1U;
+}
+
+/** @fn void can1HighLevelInterrupt(void)
+* @brief CAN1 Level 0 Interrupt Handler
+*/
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+
+
+#pragma INTERRUPT(can1HighLevelInterrupt, IRQ)
+
+void can1HighLevelInterrupt(void)
+{
+ uint32_t value = canREG1->INT;
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+
+ if (value == 0x8000U)
+ {
+ canErrorNotification(canREG1, canREG1->ES);
+ return;
+ }
+
+ /** - Setup IF1 for clear pending interrupt flag */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1CMD = 0x08;
+ canREG1->IF1NO = value;
+
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1CMD = 0x87;
+
+ canMessageNotification(canREG1, value);
+
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+}
+
+
+/** @fn void can1LowLevelInterrupt(void)
+* @brief CAN1 Level 1 Interrupt Handler
+*/
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+
+#pragma INTERRUPT(can1LowLevelInterrupt, IRQ)
+
+void can1LowLevelInterrupt(void)
+{
+ uint32_t messageBox = canREG1->INT >> 16U;
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+
+ /** - Setup IF1 for clear pending interrupt flag */
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1CMD = 0x08;
+ canREG1->IF1NO = messageBox;
+
+ while (canREG1->IF1STAT & 0x80);
+
+ canREG1->IF1CMD = 0x87;
+
+ canMessageNotification(canREG1, messageBox);
+
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+}
+
+
+/** @fn void can2HighLevelInterrupt(void)
+* @brief CAN2 Level 0 Interrupt Handler
+*/
+
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+
+#pragma INTERRUPT(can2HighLevelInterrupt, IRQ)
+
+void can2HighLevelInterrupt(void)
+{
+ uint32_t value = canREG2->INT;
+
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+
+ if (value == 0x8000U)
+ {
+ canErrorNotification(canREG2, canREG2->ES);
+ return;
+ }
+
+ /** - Setup IF1 for clear pending interrupt flag */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1CMD = 0x08;
+ canREG2->IF1NO = value;
+
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1CMD = 0x87;
+
+ canMessageNotification(canREG2, value);
+
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+}
+
+
+/** @fn void can2LowLevelInterrupt(void)
+* @brief CAN2 Level 1 Interrupt Handler
+*/
+
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+
+#pragma INTERRUPT(can2LowLevelInterrupt, IRQ)
+
+void can2LowLevelInterrupt(void)
+{
+ uint32_t messageBox = canREG2->INT >> 16U;
+
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+
+ /** - Setup IF1 for clear pending interrupt flag */
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1CMD = 0x08;
+ canREG2->IF1NO = messageBox;
+
+ while (canREG2->IF1STAT & 0x80);
+
+ canREG2->IF1CMD = 0x87;
+
+ canMessageNotification(canREG2, messageBox);
+
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+}
+
+
+/** @fn void can3HighLevelInterrupt(void)
+* @brief CAN3 Level 0 Interrupt Handler
+*/
+
+/* USER CODE BEGIN (49) */
+/* USER CODE END */
+
+#pragma INTERRUPT(can3HighLevelInterrupt, IRQ)
+
+void can3HighLevelInterrupt(void)
+{
+ uint32_t value = canREG3->INT;
+
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+
+ if (value == 0x8000U)
+ {
+ canErrorNotification(canREG3, canREG3->ES);
+ return;
+ }
+
+ /** - Setup IF1 for clear pending interrupt flag */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1CMD = 0x08;
+ canREG3->IF1NO = value;
+
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1CMD = 0x87;
+
+ canMessageNotification(canREG3, value);
+
+/* USER CODE BEGIN (51) */
+/* USER CODE END */
+}
+
+
+/** @fn void can3LowLevelInterrupt(void)
+* @brief CAN3 Level 1 Interrupt Handler
+*/
+
+/* USER CODE BEGIN (52) */
+/* USER CODE END */
+
+#pragma INTERRUPT(can3LowLevelInterrupt, IRQ)
+
+void can3LowLevelInterrupt(void)
+{
+ uint32_t messageBox = canREG3->INT >> 16U;
+
+/* USER CODE BEGIN (53) */
+/* USER CODE END */
+
+ /** - Setup IF1 for clear pending interrupt flag */
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1CMD = 0x08;
+ canREG3->IF1NO = messageBox;
+
+ while (canREG3->IF1STAT & 0x80);
+
+ canREG3->IF1CMD = 0x87;
+
+ canMessageNotification(canREG3, messageBox);
+
+/* USER CODE BEGIN (54) */
+/* USER CODE END */
+}
+
-/** @file dma.c \r
-* @brief DMA Driver Inmplmentation File\r
-* @date 22.Aug.2011\r
-* @version 1.01.000\r
-*\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2010, All rights reserved. */\r
-\r
-\r
-#include "ti_drv_dma.h"\r
-\r
-g_dmaCTRL g_dmaCTRLPKT;\r
-\r
-/** @fn void dmaEnable(void)\r
-* @brief enables dma module\r
-*\r
-* This function brings DMA out of reset\r
-*/\r
-\r
-void dmaEnable(void)\r
-{\r
- dmaREG->GCTRL = 0x00000001; /* reset dma */\r
- dmaREG->GCTRL |= 0x00010000; /* enable dma */\r
- dmaREG->GCTRL |= 0x00000300; /* stop at suspend */ \r
-}\r
-\r
-\r
-\r
-/** @fn void dmaReqAssign(uint32_t channel,uint32_t reqline)\r
-* @brief Initializes the DMA Driver\r
-*\r
-* This function assigns dma request lines to channels\r
-*/\r
-\r
-void dmaReqAssign(uint32_t channel,uint32_t reqline)\r
-{\r
- register uint32_t i=0,j=0;\r
-\r
- i = channel >> 2; /* Find the register to configure */\r
- j = channel -(i<<2); /* Find the offset of the type */\r
- j = 3-j; /* reverse the byte order */\r
- j = j<<3; /* find the bit location */\r
-\r
- /* mapping channel 'i' to request line 'j' */\r
- dmaREG->DREQASI[i] &= ~(0xff<<j); \r
- dmaREG->DREQASI[i] |= (reqline<<j);\r
-}\r
-\r
-\r
-\r
-/** @fn void dmaSetCtrlPacket(uint32_t channel)\r
-* @brief Initializes the DMA Driver\r
-*\r
-* This function sets control packet\r
-*/\r
-\r
-void dmaSetCtrlPacket(uint32_t channel)\r
-{\r
- register uint32_t i=0,j=0;\r
- \r
- dmaRAMREG->PCP[channel].ISADDR = g_dmaCTRLPKT.SADD;\r
- \r
- dmaRAMREG->PCP[channel].IDADDR = g_dmaCTRLPKT.DADD;\r
- \r
- dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16) | g_dmaCTRLPKT.ELCNT;\r
- \r
- dmaRAMREG->PCP[channel].CHCTRL = (g_dmaCTRLPKT.RDSIZE << 14) | (g_dmaCTRLPKT.WRSIZE << 12) | (g_dmaCTRLPKT.TTYPE << 8)| \\r
- (g_dmaCTRLPKT.ADDMODERD << 3 ) | (g_dmaCTRLPKT.ADDMODEWR << 1 ) | (g_dmaCTRLPKT.AUTOINIT);\r
-\r
- dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16);\r
-\r
- dmaRAMREG->PCP[channel].EIOFF = (g_dmaCTRLPKT.ELDOFFSET << 16) | (g_dmaCTRLPKT.ELSOFFSET);\r
- \r
- dmaRAMREG->PCP[channel].FIOFF = (g_dmaCTRLPKT.FRDOFFSET << 16) | (g_dmaCTRLPKT.FRSOFFSET);\r
-\r
- i = channel >> 3; /* Find the register to write */\r
- j = channel -(i << 3); /* Find the offset of the 4th bit */\r
- j = 7 -j; /* Reverse the order of the 4th bit offset */\r
- j = j<<2; /* Find the bit location of the 4th bit to write */\r
-\r
- dmaREG->PAR[i] &= ~(0xf<<j);\r
- dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN<<j);\r
-}\r
-\r
-\r
-\r
-/** @fn void dmaSetCtrlPacket(uint32_t channel)\r
-* @brief Initializes the DMA Driver\r
-*\r
-* This function sets control packet\r
-*/\r
-\r
-void dmaSetChEnable(uint32_t channel,uint32_t type)\r
-{\r
- if(type == DMA_HW)\r
- {\r
- dmaREG->HWCHENAS = (1 << channel);\r
- }\r
- else if(type == DMA_SW)\r
- {\r
- dmaREG->SWCHENAS = (1 << channel);\r
- }\r
-}\r
-\r
-\r
-\r
-/**/\r
-\r
+/** @file dma.c
+* @brief DMA Driver Inmplmentation File
+* @date 22.Aug.2011
+* @version 1.01.000
+*
+*/
+
+/* (c) Texas Instruments 2009-2010, All rights reserved. */
+
+
+#include "ti_drv_dma.h"
+
+g_dmaCTRL g_dmaCTRLPKT;
+
+/** @fn void dmaEnable(void)
+* @brief enables dma module
+*
+* This function brings DMA out of reset
+*/
+
+void dmaEnable(void)
+{
+ dmaREG->GCTRL = 0x00000001; /* reset dma */
+ dmaREG->GCTRL |= 0x00010000; /* enable dma */
+ dmaREG->GCTRL |= 0x00000300; /* stop at suspend */
+}
+
+
+
+/** @fn void dmaReqAssign(uint32_t channel,uint32_t reqline)
+* @brief Initializes the DMA Driver
+*
+* This function assigns dma request lines to channels
+*/
+
+void dmaReqAssign(uint32_t channel,uint32_t reqline)
+{
+ register uint32_t i=0,j=0;
+
+ i = channel >> 2; /* Find the register to configure */
+ j = channel -(i<<2); /* Find the offset of the type */
+ j = 3-j; /* reverse the byte order */
+ j = j<<3; /* find the bit location */
+
+ /* mapping channel 'i' to request line 'j' */
+ dmaREG->DREQASI[i] &= ~(0xff<<j);
+ dmaREG->DREQASI[i] |= (reqline<<j);
+}
+
+
+
+/** @fn void dmaSetCtrlPacket(uint32_t channel)
+* @brief Initializes the DMA Driver
+*
+* This function sets control packet
+*/
+
+void dmaSetCtrlPacket(uint32_t channel)
+{
+ register uint32_t i=0,j=0;
+
+ dmaRAMREG->PCP[channel].ISADDR = g_dmaCTRLPKT.SADD;
+
+ dmaRAMREG->PCP[channel].IDADDR = g_dmaCTRLPKT.DADD;
+
+ dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16) | g_dmaCTRLPKT.ELCNT;
+
+ dmaRAMREG->PCP[channel].CHCTRL = (g_dmaCTRLPKT.RDSIZE << 14) | (g_dmaCTRLPKT.WRSIZE << 12) | (g_dmaCTRLPKT.TTYPE << 8)| \
+ (g_dmaCTRLPKT.ADDMODERD << 3 ) | (g_dmaCTRLPKT.ADDMODEWR << 1 ) | (g_dmaCTRLPKT.AUTOINIT);
+
+ dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16);
+
+ dmaRAMREG->PCP[channel].EIOFF = (g_dmaCTRLPKT.ELDOFFSET << 16) | (g_dmaCTRLPKT.ELSOFFSET);
+
+ dmaRAMREG->PCP[channel].FIOFF = (g_dmaCTRLPKT.FRDOFFSET << 16) | (g_dmaCTRLPKT.FRSOFFSET);
+
+ i = channel >> 3; /* Find the register to write */
+ j = channel -(i << 3); /* Find the offset of the 4th bit */
+ j = 7 -j; /* Reverse the order of the 4th bit offset */
+ j = j<<2; /* Find the bit location of the 4th bit to write */
+
+ dmaREG->PAR[i] &= ~(0xf<<j);
+ dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN<<j);
+}
+
+
+
+/** @fn void dmaSetCtrlPacket(uint32_t channel)
+* @brief Initializes the DMA Driver
+*
+* This function sets control packet
+*/
+
+void dmaSetChEnable(uint32_t channel,uint32_t type)
+{
+ if(type == DMA_HW)
+ {
+ dmaREG->HWCHENAS = (1 << channel);
+ }
+ else if(type == DMA_SW)
+ {
+ dmaREG->SWCHENAS = (1 << channel);
+ }
+}
+
+
+
+/**/
+
-/** @file dmm.c \r
-* @brief DMM Driver Implementation File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-#include "ti_drv_dmm.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-/** @fn void dmmInit(void)\r
-* @brief Initializes the DMM Driver\r
-*\r
-* This function initializes the DMM module.\r
-*/\r
-\r
-/* ***************************************************** */\r
-/* Modify only by hand -- do not use Halcogen! */\r
-/* ***************************************************** */\r
-void dmmInit(void)\r
-{\r
- /** - DMM Port default output value */\r
- dmmREG->PC3 = 0 /* DMM SYNC - FAN_CONTROL*/\r
- | (0 << 1) /* DMM CLK - ETH_RESET */\r
- | (0 << 2) /* DMM DATA[0] - VBAT_1_EN */\r
- | (0 << 3) /* DMM DATA[1] - VBAT_2_EN */\r
- | (0 << 4) /* DMM DATA[2] - VBAT_3_EN */\r
- | (0 << 5) /* DMM DATA[3] - VBAT_EN */\r
- | (0 << 6) /* DMM DATA[4] - NOT USED */\r
- | (0 << 7) /* DMM DATA[5] - SPICSA */\r
- | (0 << 8) /* DMM DATA[6] - SPICSB */\r
- | (0 << 9) /* DMM DATA[7] - NOT USED */\r
- | (0 << 10) /* DMM DATA[8] - NOT USED */\r
- | (0 << 11) /* DMM DATA[9] - MOUT1_EN */\r
- | (0 << 12) /* DMM DATA[10] - MOUT2_EN */\r
- | (1 << 13) /* DMM DATA[11] - CAN_NSTB */\r
- | (0 << 14) /* DMM DATA[12] - NOT USED */\r
- | (0 << 15) /* DMM DATA[13] - CAN_EN */\r
- | (1 << 16) /* DMM DATA[14] - LIN2_NSLP */\r
- | (1 << 17) /* DMM DATA[15] - LIN1_NSLP */\r
- | (0 << 18); /* DMM ENA - DIN_INT */\r
-\r
- /** - DMM Port direction 1 - output, 0 - input */\r
- dmmREG->PC1 = 1 /* DMM SYNC - FAN_CONTROL*/\r
- | (1 << 1) /* DMM CLK - ETH_RESET */\r
- | (1 << 2) /* DMM DATA[0] - VBAT_1_EN */\r
- | (1 << 3) /* DMM DATA[1] - VBAT_2_EN */\r
- | (1 << 4) /* DMM DATA[2] - VBAT_3_EN */\r
- | (1 << 5) /* DMM DATA[3] - VBAT_EN */\r
- | (1 << 6) /* DMM DATA[4] - NOT USED */\r
- | (1 << 7) /* DMM DATA[5] - SPICSA */\r
- | (1 << 8) /* DMM DATA[6] - SPICSB */\r
- | (1 << 9) /* DMM DATA[7] - NOT USED */\r
- | (1 << 10) /* DMM DATA[8] - NOT USED */\r
- | (1 << 11) /* DMM DATA[9] - MOUT1_EN */\r
- | (1 << 12) /* DMM DATA[10] - MOUT2_EN */\r
- | (1 << 13) /* DMM DATA[11] - CAN_NSTB */\r
- | (1 << 14) /* DMM DATA[12] - NOT USED */\r
- | (1 << 15) /* DMM DATA[13] - CAN_EN */\r
- | (1 << 16) /* DMM DATA[14] - LIN2_NSLP */\r
- | (1 << 17) /* DMM DATA[15] - LIN1_NSLP */\r
- | (1 << 18); /* DMM ENA - DIN_INT */\r
-\r
- /** - DMM Port open drain enable */\r
- dmmREG->PC6 = 0 /* DMM SYNC - FAN_CONTROL*/\r
- | (0 << 1) /* DMM CLK - ETH_RESET */\r
- | (0 << 2) /* DMM DATA[0] - VBAT_1_EN */\r
- | (0 << 3) /* DMM DATA[1] - VBAT_2_EN */\r
- | (0 << 4) /* DMM DATA[2] - VBAT_3_EN */\r
- | (0 << 5) /* DMM DATA[3] - VBAT_EN */\r
- | (0 << 6) /* DMM DATA[4] - NOT USED */\r
- | (0 << 7) /* DMM DATA[5] - SPICSA */\r
- | (0 << 8) /* DMM DATA[6] - SPICSB */\r
- | (0 << 9) /* DMM DATA[7] - NOT USED */\r
- | (0 << 10) /* DMM DATA[8] - NOT USED */\r
- | (1 << 11) /* DMM DATA[9] - MOUT1_EN */\r
- | (1 << 12) /* DMM DATA[10] - MOUT2_EN */\r
- | (0 << 13) /* DMM DATA[11] - CAN_NSTB */\r
- | (0 << 14) /* DMM DATA[12] - NOT USED */\r
- | (0 << 15) /* DMM DATA[13] - CAN_EN */\r
- | (0 << 16) /* DMM DATA[14] - LIN2_NSLP */\r
- | (0 << 17) /* DMM DATA[15] - LIN1_NSLP */\r
- | (0 << 18); /* DMM ENA - DIN_INT */\r
-\r
-\r
- /** - DMM Port pullup(1) / pulldown(0) selection */\r
- dmmREG->PC8 = 0 /* DMM SYNC - FAN_CONTROL*/\r
- | (0 << 1) /* DMM CLK - ETH_RESET */\r
- | (0 << 2) /* DMM DATA[0] - VBAT_1_EN */\r
- | (0 << 3) /* DMM DATA[1] - VBAT_2_EN */\r
- | (0 << 4) /* DMM DATA[2] - VBAT_3_EN */\r
- | (0 << 5) /* DMM DATA[3] - VBAT_EN */\r
- | (0 << 6) /* DMM DATA[4] - NOT USED */\r
- | (0 << 7) /* DMM DATA[5] - SPICSA */\r
- | (0 << 8) /* DMM DATA[6] - SPICSB */\r
- | (0 << 9) /* DMM DATA[7] - NOT USED */\r
- | (0 << 10) /* DMM DATA[8] - NOT USED */\r
- | (0 << 11) /* DMM DATA[9] - MOUT1_EN */\r
- | (0 << 12) /* DMM DATA[10] - MOUT2_EN */\r
- | (0 << 13) /* DMM DATA[11] - CAN_NSTB */\r
- | (0 << 14) /* DMM DATA[12] - NOT USED */\r
- | (0 << 15) /* DMM DATA[13] - CAN_EN */\r
- | (0 << 16) /* DMM DATA[14] - LIN2_NSLP */\r
- | (0 << 17) /* DMM DATA[15] - LIN1_NSLP */\r
- | (0 << 18); /* DMM ENA - DIN_INT */\r
-\r
-\r
- /** - DMM Port pullup / pulldown enable*/\r
- dmmREG->PC7 = 1 /* DMM SYNC - FAN_CONTROL*/\r
- | (1 << 1) /* DMM CLK - ETH_RESET */\r
- | (1 << 2) /* DMM DATA[0] - VBAT_1_EN */\r
- | (1 << 3) /* DMM DATA[1] - VBAT_2_EN */\r
- | (1 << 4) /* DMM DATA[2] - VBAT_3_EN */\r
- | (1 << 5) /* DMM DATA[3] - VBAT_EN */\r
- | (1 << 6) /* DMM DATA[4] - NOT USED */\r
- | (1 << 7) /* DMM DATA[5] - SPICSA */\r
- | (1 << 8) /* DMM DATA[6] - SPICSB */\r
- | (1 << 9) /* DMM DATA[7] - NOT USED */\r
- | (1 << 10) /* DMM DATA[8] - NOT USED */\r
- | (0 << 11) /* DMM DATA[9] - MOUT1_EN */\r
- | (0 << 12) /* DMM DATA[10] - MOUT2_EN */\r
- | (1 << 13) /* DMM DATA[11] - CAN_NSTB */\r
- | (1 << 14) /* DMM DATA[12] - NOT USED */\r
- | (1 << 15) /* DMM DATA[13] - CAN_EN */\r
- | (1 << 16) /* DMM DATA[14] - LIN2_NSLP */\r
- | (1 << 17) /* DMM DATA[15] - LIN1_NSLP */\r
- | (1 << 18); /* DMM ENA - DIN_INT */\r
-\r
- /* 1 = pin is functional / 0 = pin is in GIO */\r
- dmmREG->PC0 = 0 /* DMM SYNC - FAN_CONTROL*/\r
- | (0 << 1) /* DMM CLK - ETH_RESET */\r
- | (0 << 2) /* DMM DATA[0] - VBAT_1_EN */\r
- | (0 << 3) /* DMM DATA[1] - VBAT_2_EN */\r
- | (0 << 4) /* DMM DATA[2] - VBAT_3_EN */\r
- | (0 << 5) /* DMM DATA[3] - VBAT_EN */\r
- | (0 << 6) /* DMM DATA[4] - NOT USED */\r
- | (0 << 7) /* DMM DATA[5] - SPICSA */\r
- | (0 << 8) /* DMM DATA[6] - SPICSB */\r
- | (0 << 9) /* DMM DATA[7] - NOT USED */\r
- | (0 << 10) /* DMM DATA[8] - NOT USED */\r
- | (0 << 11) /* DMM DATA[9] - MOUT1_EN */\r
- | (0 << 12) /* DMM DATA[10] - MOUT2_EN */\r
- | (0 << 13) /* DMM DATA[11] - CAN_NSTB */\r
- | (0 << 14) /* DMM DATA[12] - NOT USED */\r
- | (0 << 15) /* DMM DATA[13] - CAN_EN */\r
- | (0 << 16) /* DMM DATA[14] - LIN2_NSLP */\r
- | (0 << 17) /* DMM DATA[15] - LIN1_NSLP */\r
- | (0 << 18); /* DMM ENA - DIN_INT */\r
-\r
-}\r
+/** @file dmm.c
+* @brief DMM Driver Implementation File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "ti_drv_dmm.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void dmmInit(void)
+* @brief Initializes the DMM Driver
+*
+* This function initializes the DMM module.
+*/
+
+/* ***************************************************** */
+/* Modify only by hand -- do not use Halcogen! */
+/* ***************************************************** */
+void dmmInit(void)
+{
+ /** - DMM Port default output value */
+ dmmREG->PC3 = 0 /* DMM SYNC - FAN_CONTROL*/
+ | (0 << 1) /* DMM CLK - ETH_RESET */
+ | (0 << 2) /* DMM DATA[0] - VBAT_1_EN */
+ | (0 << 3) /* DMM DATA[1] - VBAT_2_EN */
+ | (0 << 4) /* DMM DATA[2] - VBAT_3_EN */
+ | (0 << 5) /* DMM DATA[3] - VBAT_EN */
+ | (0 << 6) /* DMM DATA[4] - NOT USED */
+ | (0 << 7) /* DMM DATA[5] - SPICSA */
+ | (0 << 8) /* DMM DATA[6] - SPICSB */
+ | (0 << 9) /* DMM DATA[7] - NOT USED */
+ | (0 << 10) /* DMM DATA[8] - NOT USED */
+ | (0 << 11) /* DMM DATA[9] - MOUT1_EN */
+ | (0 << 12) /* DMM DATA[10] - MOUT2_EN */
+ | (1 << 13) /* DMM DATA[11] - CAN_NSTB */
+ | (0 << 14) /* DMM DATA[12] - NOT USED */
+ | (0 << 15) /* DMM DATA[13] - CAN_EN */
+ | (1 << 16) /* DMM DATA[14] - LIN2_NSLP */
+ | (1 << 17) /* DMM DATA[15] - LIN1_NSLP */
+ | (0 << 18); /* DMM ENA - DIN_INT */
+
+ /** - DMM Port direction 1 - output, 0 - input */
+ dmmREG->PC1 = 1 /* DMM SYNC - FAN_CONTROL*/
+ | (1 << 1) /* DMM CLK - ETH_RESET */
+ | (1 << 2) /* DMM DATA[0] - VBAT_1_EN */
+ | (1 << 3) /* DMM DATA[1] - VBAT_2_EN */
+ | (1 << 4) /* DMM DATA[2] - VBAT_3_EN */
+ | (1 << 5) /* DMM DATA[3] - VBAT_EN */
+ | (1 << 6) /* DMM DATA[4] - NOT USED */
+ | (1 << 7) /* DMM DATA[5] - SPICSA */
+ | (1 << 8) /* DMM DATA[6] - SPICSB */
+ | (1 << 9) /* DMM DATA[7] - NOT USED */
+ | (1 << 10) /* DMM DATA[8] - NOT USED */
+ | (1 << 11) /* DMM DATA[9] - MOUT1_EN */
+ | (1 << 12) /* DMM DATA[10] - MOUT2_EN */
+ | (1 << 13) /* DMM DATA[11] - CAN_NSTB */
+ | (1 << 14) /* DMM DATA[12] - NOT USED */
+ | (1 << 15) /* DMM DATA[13] - CAN_EN */
+ | (1 << 16) /* DMM DATA[14] - LIN2_NSLP */
+ | (1 << 17) /* DMM DATA[15] - LIN1_NSLP */
+ | (1 << 18); /* DMM ENA - DIN_INT */
+
+ /** - DMM Port open drain enable */
+ dmmREG->PC6 = 0 /* DMM SYNC - FAN_CONTROL*/
+ | (0 << 1) /* DMM CLK - ETH_RESET */
+ | (0 << 2) /* DMM DATA[0] - VBAT_1_EN */
+ | (0 << 3) /* DMM DATA[1] - VBAT_2_EN */
+ | (0 << 4) /* DMM DATA[2] - VBAT_3_EN */
+ | (0 << 5) /* DMM DATA[3] - VBAT_EN */
+ | (0 << 6) /* DMM DATA[4] - NOT USED */
+ | (0 << 7) /* DMM DATA[5] - SPICSA */
+ | (0 << 8) /* DMM DATA[6] - SPICSB */
+ | (0 << 9) /* DMM DATA[7] - NOT USED */
+ | (0 << 10) /* DMM DATA[8] - NOT USED */
+ | (1 << 11) /* DMM DATA[9] - MOUT1_EN */
+ | (1 << 12) /* DMM DATA[10] - MOUT2_EN */
+ | (0 << 13) /* DMM DATA[11] - CAN_NSTB */
+ | (0 << 14) /* DMM DATA[12] - NOT USED */
+ | (0 << 15) /* DMM DATA[13] - CAN_EN */
+ | (0 << 16) /* DMM DATA[14] - LIN2_NSLP */
+ | (0 << 17) /* DMM DATA[15] - LIN1_NSLP */
+ | (0 << 18); /* DMM ENA - DIN_INT */
+
+
+ /** - DMM Port pullup(1) / pulldown(0) selection */
+ dmmREG->PC8 = 0 /* DMM SYNC - FAN_CONTROL*/
+ | (0 << 1) /* DMM CLK - ETH_RESET */
+ | (0 << 2) /* DMM DATA[0] - VBAT_1_EN */
+ | (0 << 3) /* DMM DATA[1] - VBAT_2_EN */
+ | (0 << 4) /* DMM DATA[2] - VBAT_3_EN */
+ | (0 << 5) /* DMM DATA[3] - VBAT_EN */
+ | (0 << 6) /* DMM DATA[4] - NOT USED */
+ | (0 << 7) /* DMM DATA[5] - SPICSA */
+ | (0 << 8) /* DMM DATA[6] - SPICSB */
+ | (0 << 9) /* DMM DATA[7] - NOT USED */
+ | (0 << 10) /* DMM DATA[8] - NOT USED */
+ | (0 << 11) /* DMM DATA[9] - MOUT1_EN */
+ | (0 << 12) /* DMM DATA[10] - MOUT2_EN */
+ | (0 << 13) /* DMM DATA[11] - CAN_NSTB */
+ | (0 << 14) /* DMM DATA[12] - NOT USED */
+ | (0 << 15) /* DMM DATA[13] - CAN_EN */
+ | (0 << 16) /* DMM DATA[14] - LIN2_NSLP */
+ | (0 << 17) /* DMM DATA[15] - LIN1_NSLP */
+ | (0 << 18); /* DMM ENA - DIN_INT */
+
+
+ /** - DMM Port pullup / pulldown enable*/
+ dmmREG->PC7 = 1 /* DMM SYNC - FAN_CONTROL*/
+ | (1 << 1) /* DMM CLK - ETH_RESET */
+ | (1 << 2) /* DMM DATA[0] - VBAT_1_EN */
+ | (1 << 3) /* DMM DATA[1] - VBAT_2_EN */
+ | (1 << 4) /* DMM DATA[2] - VBAT_3_EN */
+ | (1 << 5) /* DMM DATA[3] - VBAT_EN */
+ | (1 << 6) /* DMM DATA[4] - NOT USED */
+ | (1 << 7) /* DMM DATA[5] - SPICSA */
+ | (1 << 8) /* DMM DATA[6] - SPICSB */
+ | (1 << 9) /* DMM DATA[7] - NOT USED */
+ | (1 << 10) /* DMM DATA[8] - NOT USED */
+ | (0 << 11) /* DMM DATA[9] - MOUT1_EN */
+ | (0 << 12) /* DMM DATA[10] - MOUT2_EN */
+ | (1 << 13) /* DMM DATA[11] - CAN_NSTB */
+ | (1 << 14) /* DMM DATA[12] - NOT USED */
+ | (1 << 15) /* DMM DATA[13] - CAN_EN */
+ | (1 << 16) /* DMM DATA[14] - LIN2_NSLP */
+ | (1 << 17) /* DMM DATA[15] - LIN1_NSLP */
+ | (1 << 18); /* DMM ENA - DIN_INT */
+
+ /* 1 = pin is functional / 0 = pin is in GIO */
+ dmmREG->PC0 = 0 /* DMM SYNC - FAN_CONTROL*/
+ | (0 << 1) /* DMM CLK - ETH_RESET */
+ | (0 << 2) /* DMM DATA[0] - VBAT_1_EN */
+ | (0 << 3) /* DMM DATA[1] - VBAT_2_EN */
+ | (0 << 4) /* DMM DATA[2] - VBAT_3_EN */
+ | (0 << 5) /* DMM DATA[3] - VBAT_EN */
+ | (0 << 6) /* DMM DATA[4] - NOT USED */
+ | (0 << 7) /* DMM DATA[5] - SPICSA */
+ | (0 << 8) /* DMM DATA[6] - SPICSB */
+ | (0 << 9) /* DMM DATA[7] - NOT USED */
+ | (0 << 10) /* DMM DATA[8] - NOT USED */
+ | (0 << 11) /* DMM DATA[9] - MOUT1_EN */
+ | (0 << 12) /* DMM DATA[10] - MOUT2_EN */
+ | (0 << 13) /* DMM DATA[11] - CAN_NSTB */
+ | (0 << 14) /* DMM DATA[12] - NOT USED */
+ | (0 << 15) /* DMM DATA[13] - CAN_EN */
+ | (0 << 16) /* DMM DATA[14] - LIN2_NSLP */
+ | (0 << 17) /* DMM DATA[15] - LIN1_NSLP */
+ | (0 << 18); /* DMM ENA - DIN_INT */
+
+}
-/**\r
- * \file emac.c\r
- *\r
- * \brief EMAC APIs.\r
- *\r
- * This file contains the device abstraction layer APIs for EMAC.\r
- */\r
-\r
-/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
- * ALL RIGHTS RESERVED\r
- */\r
-\r
-#include "sys_common.h"\r
-#include "hw_reg_access.h"\r
-#include "ti_drv_emac.h"\r
-#include "hw_emac.h"\r
-#include "hw_emac_ctrl.h"\r
-\r
-/*******************************************************************************\r
-* INTERNAL MACRO DEFINITIONS\r
-*******************************************************************************/\r
-#define EMAC_CONTROL_RESET (0x01u)\r
-#define EMAC_SOFT_RESET (0x01u)\r
-#define EMAC_MAX_HEADER_DESC (8u)\r
-#define EMAC_UNICAST_DISABLE (0xFFu)\r
-\r
-/*******************************************************************************\r
-* API FUNCTION DEFINITIONS\r
-*******************************************************************************/\r
-/**\r
- * \brief Enables the TXPULSE Interrupt Generation.\r
- *\r
- * \param emacBase Base address of the EMAC Module registers.\r
- * \param emacCtrlBase Base address of the EMAC CONTROL module registers\r
- * \param ctrlCore Control core for which the interrupt to be enabled.\r
- * \param channel Channel number for which interrupt to be enabled\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACTxIntPulseEnable(unsigned int emacBase, unsigned int emacCtrlBase,\r
- unsigned int ctrlCore, unsigned int channel)\r
-{\r
- HWREG(emacBase + EMAC_TXINTMASKSET) |= (1 << channel);\r
-\r
- HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) |= (1 << channel);\r
-}\r
-\r
-/**\r
- * \brief Disables the TXPULSE Interrupt Generation.\r
- *\r
- * \param emacBase Base address of the EMAC Module registers.\r
- * \param emacCtrlBase Base address of the EMAC CONTROL module registers\r
- * \param ctrlCore Control core for which the interrupt to be disabled.\r
- * \param channel Channel number for which interrupt to be disabled\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACTxIntPulseDisable(unsigned int emacBase, unsigned int emacCtrlBase,\r
- unsigned int ctrlCore, unsigned int channel)\r
-{\r
- HWREG(emacBase + EMAC_TXINTMASKCLEAR) |= (1 << channel);\r
-\r
- HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) &= ~(1 << channel);\r
-}\r
-\r
-/**\r
- * \brief Enables the RXPULSE Interrupt Generation.\r
- *\r
- * \param emacBase Base address of the EMAC Module registers.\r
- * \param emacCtrlBase Base address of the EMAC CONTROL module registers\r
- * \param ctrlCore Control core for which the interrupt to be enabled.\r
- * \param channel Channel number for which interrupt to be enabled\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACRxIntPulseEnable(unsigned int emacBase, unsigned int emacCtrlBase,\r
- unsigned int ctrlCore, unsigned int channel)\r
-{\r
- HWREG(emacBase + EMAC_RXINTMASKSET) |= (1 << channel);\r
-\r
- HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) |= (1 << channel);\r
-}\r
-\r
-/**\r
- * \brief Disables the RXPULSE Interrupt Generation.\r
- *\r
- * \param emacBase Base address of the EMAC Module registers.\r
- * \param emacCtrlBase Base address of the EMAC CONTROL module registers\r
- * \param ctrlCore Control core for which the interrupt to be disabled.\r
- * \param channel Channel number for which interrupt to be disabled\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACRxIntPulseDisable(unsigned int emacBase, unsigned int emacCtrlBase,\r
- unsigned int ctrlCore, unsigned int channel)\r
-{\r
- HWREG(emacBase + EMAC_RXINTMASKCLEAR) |= (1 << channel);\r
-\r
- HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) &= ~(1 << channel);\r
-}\r
-/**\r
- * \brief This API sets the RMII speed. The RMII Speed can be 10 Mbps or \r
- * 100 Mbps\r
- *\r
- * \param emacBase Base address of the EMAC Module registers.\r
- * \param speed speed for setting.\r
- * speed can take the following values. \n\r
- * EMAC_RMIISPEED_10MBPS - 10 Mbps \n\r
- * EMAC_RMIISPEED_100MBPS - 100 Mbps. \r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACRMIISpeedSet(unsigned int emacBase, unsigned int speed)\r
-{\r
- HWREG(emacBase + EMAC_MACCONTROL) &= ~EMAC_MACCONTROL_RMIISPEED;\r
- \r
- HWREG(emacBase + EMAC_MACCONTROL) |= speed;\r
-}\r
-\r
-/**\r
- * \brief This API enables the MII control block\r
- *\r
- * \param emacBase Base address of the EMAC Module registers.\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACMIIEnable(unsigned int emacBase)\r
-{\r
- HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_GMIIEN;\r
-}\r
-\r
-/**\r
- * \brief This API sets the duplex mode of operation(full/half) for MAC.\r
- *\r
- * \param emacBase Base address of the EMAC Module registers.\r
- * \param duplexMode duplex mode of operation.\r
- * duplexMode can take the following values. \n\r
- * EMAC_DUPLEX_FULL - Full Duplex \n\r
- * EMAC_DUPLEX_HALF - Half Duplex.\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACDuplexSet(unsigned int emacBase, unsigned int duplexMode)\r
-{\r
- HWREG(emacBase + EMAC_MACCONTROL) &= ~EMAC_MACCONTROL_FULLDUPLEX;\r
- \r
- HWREG(emacBase + EMAC_MACCONTROL) |= duplexMode;\r
-}\r
-\r
-/**\r
- * \brief API to enable the transmit in the TX Control Register\r
- * After the transmit is enabled, any write to TXHDP of\r
- * a channel will start transmission\r
- *\r
- * \param emacBase Base Address of the EMAC Module Registers.\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACTxEnable(unsigned int emacBase)\r
-{\r
- HWREG(emacBase + EMAC_TXCONTROL) = EMAC_TXCONTROL_TXEN;\r
-}\r
-\r
-/**\r
- * \brief API to enable the receive in the RX Control Register\r
- * After the transmit is enabled, and write to RXHDP of\r
- * a channel, the data can be received in the destination\r
- * specified by the corresponding RX buffer descriptor.\r
- *\r
- * \param emacBase Base Address of the EMAC Module Registers.\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACRxEnable(unsigned int emacBase)\r
-{\r
- HWREG(emacBase + EMAC_RXCONTROL) = EMAC_RXCONTROL_RXEN;\r
-}\r
-\r
-/**\r
- * \brief API to write the TX HDP register. If transmit is enabled,\r
- * write to the TX HDP will immediately start transmission.\r
- * The data will be taken from the buffer pointer of the TX buffer\r
- * descriptor written to the TX HDP\r
- *\r
- * \param emacBase Base Address of the EMAC Module Registers.\n\r
- * \param descHdr Address of the TX buffer descriptor\r
- * \param channel Channel Number\r
- *\r
- * \return None\r
- *\r
- **/\r
-volatile unsigned int lastInputdescHdr = 0;\r
-volatile unsigned int valHDPbefWrite = 0;\r
-void EMACTxHdrDescPtrWrite(unsigned int emacBase, unsigned int descHdr,\r
- unsigned int channel)\r
-{\r
- valHDPbefWrite = HWREG(emacBase + EMAC_TXHDP(channel));\r
- HWREG(emacBase + EMAC_TXHDP(channel)) = descHdr;\r
- lastInputdescHdr = descHdr;\r
-}\r
-\r
-/**\r
- * \brief API to write the RX HDP register. If receive is enabled,\r
- * write to the RX HDP will enable data reception to point to\r
- * the corresponding RX buffer descriptor's buffer pointer.\r
- *\r
- * \param emacBase Base Address of the EMAC Module Registers.\n\r
- * \param descHdr Address of the RX buffer descriptor\r
- * \param channel Channel Number\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACRxHdrDescPtrWrite(unsigned int emacBase, unsigned int descHdr,\r
- unsigned int channel)\r
-{\r
- HWREG(emacBase + EMAC_RXHDP(channel)) = descHdr;\r
-}\r
-\r
-/**\r
- * \brief This API Initializes the EMAC and EMAC Control modules. The\r
- * EMAC Control module is reset, the CPPI RAM is cleared. also,\r
- * all the interrupts are disabled. This API doesnot enable any\r
- * interrupt or operation of the EMAC.\r
- *\r
- * \param emacCtrlBase Base Address of the EMAC Control module\r
- * registers.\n\r
- * \param emacBase Base address of the EMAC module registers\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACInit(unsigned int emacCtrlBase, unsigned int emacBase)\r
-{\r
- unsigned int cnt;\r
-\r
- /* Reset the EMAC Control Module. This clears the CPPI RAM also */\r
- HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) = EMAC_CONTROL_RESET;\r
-\r
- while(HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) & EMAC_CONTROL_RESET);\r
-\r
- /* Reset the EMAC Control Module. This clears the CPPI RAM also */\r
- HWREG(emacBase + EMAC_SOFTRESET) = EMAC_SOFT_RESET;\r
-\r
- while(HWREG(emacBase + EMAC_SOFTRESET) & EMAC_SOFT_RESET);\r
-\r
- HWREG(emacBase + EMAC_MACCONTROL)= 0;\r
- HWREG(emacBase + EMAC_RXCONTROL)= 0;\r
- HWREG(emacBase + EMAC_TXCONTROL)= 0;\r
-\r
- /* Initialize all the header descriptor pointer registers */\r
- for(cnt = 0; cnt< EMAC_MAX_HEADER_DESC; cnt++)\r
- {\r
- HWREG(emacBase + EMAC_RXHDP(cnt)) = 0;\r
- HWREG(emacBase + EMAC_TXHDP(cnt)) = 0;\r
- HWREG(emacBase + EMAC_RXCP(cnt)) = 0;\r
- HWREG(emacBase + EMAC_TXCP(cnt)) = 0;\r
- HWREG(emacBase + EMAC_RXFREEBUFFER(cnt)) = 0xFF;\r
- }\r
- /* Clear the interrupt enable for all the channels */\r
- HWREG(emacBase + EMAC_TXINTMASKCLEAR) = 0xFF;\r
- HWREG(emacBase + EMAC_RXINTMASKCLEAR) = 0xFF;\r
-\r
- HWREG(emacBase + EMAC_MACHASH1) = 0;\r
- HWREG(emacBase + EMAC_MACHASH2) = 0;\r
-\r
- HWREG(emacBase + EMAC_RXBUFFEROFFSET) = 0;\r
-}\r
-\r
-/**\r
- * \brief Sets the MAC Address in MACSRCADDR registers.\r
- *\r
- * \param emacBase Base Address of the EMAC module registers.\r
- * \param macAddr Start address of a MAC address array.\r
- * The array[0] shall be the LSB of the MAC address\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACMACSrcAddrSet(unsigned int emacBase, unsigned char *macAddr)\r
-{\r
- HWREG(emacBase + EMAC_MACSRCADDRHI) = macAddr[5] |(macAddr[4] << 8)\r
- |(macAddr[3] << 16) |(macAddr[2] << 24);\r
- HWREG(emacBase + EMAC_MACSRCADDRLO) = macAddr[1] | (macAddr[0] << 8);\r
-}\r
-\r
-/**\r
- * \brief Sets the MAC Address in MACADDR registers.\r
- *\r
- * \param emacBase Base Address of the EMAC module registers.\r
- * \param channel Channel Number\r
- * \param matchFilt Match or Filter\r
- * \param macAddr Start address of a MAC address array.\r
- * The array[0] shall be the LSB of the MAC address\r
- * matchFilt can take the following values \n\r
- * EMAC_MACADDR_NO_MATCH_NO_FILTER - Address is not used to match\r
- * or filter incoming packet. \n\r
- * EMAC_MACADDR_FILTER - Address is used to filter incoming packets \n\r
- * EMAC_MACADDR_MATCH - Address is used to match incoming packets \n\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACMACAddrSet(unsigned int emacBase, unsigned int channel,\r
- unsigned char *macAddr, unsigned int matchFilt)\r
-{\r
- HWREG(emacBase + EMAC_MACINDEX) = channel;\r
-\r
- HWREG(emacBase + EMAC_MACADDRHI) = macAddr[5] |(macAddr[4] << 8)\r
- |(macAddr[3] << 16) |(macAddr[2] << 24);\r
- HWREG(emacBase + EMAC_MACADDRLO) = macAddr[1] | (macAddr[0] << 8)\r
- | matchFilt | (channel << 16);\r
-}\r
-\r
-/**\r
- * \brief Acknowledges an interrupt processed to the EMAC Control Core.\r
- *\r
- * \param emacBase Base Address of the EMAC module registers.\r
- * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control\r
- * module.\r
- * eoiFlag can take the following values \n\r
- * EMAC_INT_CORE0_TX - Core 0 TX Interrupt\r
- * EMAC_INT_CORE1_TX - Core 1 TX Interrupt\r
- * EMAC_INT_CORE2_TX - Core 2 TX Interrupt\r
- * EMAC_INT_CORE0_RX - Core 0 RX Interrupt\r
- * EMAC_INT_CORE1_RX - Core 1 RX Interrupt\r
- * EMAC_INT_CORE2_RX - Core 2 RX Interrupt\r
- * \return None\r
- * \r
- **/\r
-void EMACCoreIntAck(unsigned int emacBase, unsigned int eoiFlag)\r
-{\r
- /* Acknowledge the EMAC Control Core */\r
- HWREG(emacBase + EMAC_MACEOIVECTOR) = eoiFlag;\r
-}\r
-\r
-/**\r
- * \brief Writes the the TX Completion Pointer for a specific channel\r
- *\r
- * \param emacBase Base Address of the EMAC module registers.\r
- * \param channel Channel Number.\r
- * \param comPtr Completion Pointer Value to be written\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACTxCPWrite(unsigned int emacBase, unsigned int channel, unsigned int comPtr)\r
-{\r
- HWREG(emacBase + EMAC_TXCP(channel)) = comPtr;\r
-}\r
-\r
-uint32_t EMACTxCPRead(unsigned int emacBase, unsigned int channel)\r
-{\r
- return (HWREG(emacBase + EMAC_TXCP(channel)));\r
-}\r
-\r
-/**\r
- * \brief Writes the the RX Completion Pointer for a specific channel\r
- *\r
- * \param emacBase Base Address of the EMAC module registers.\r
- * \param channel Channel Number.\r
- * \param comPtr Completion Pointer Value to be written\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACRxCPWrite(unsigned int emacBase, unsigned int channel, unsigned int comPtr)\r
-{\r
- HWREG(emacBase + EMAC_RXCP(channel)) = comPtr;\r
-}\r
-\r
-/**\r
- * \brief Acknowledges an interrupt processed to the EMAC module. After\r
- * processing an interrupt, the last processed buffer descriptor is\r
- * written to the completion pointer. Also this API acknowledges\r
- * the EMAC Control Module that the RX interrupt is processed for\r
- * a specified core\r
- *\r
- * \param emacBase Base Address of the EMAC module registers.\r
- * \param channel Channel Number\r
- * \param comPtr Completion Pointer value. This shall be the buffer\r
- * descriptor address last processed.\r
- * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control\r
- module.\r
- * eoiFlag can take the following values \n\r
- * EMAC_INT_CORE0_RX - Core 0 RX Interrupt\r
- * EMAC_INT_CORE1_RX - Core 1 RX Interrupt\r
- * EMAC_INT_CORE2_RX - Core 2 RX Interrupt\r
- * \return None\r
- *\r
- **/\r
-void EMACRxIntAckToClear(unsigned int emacBase, unsigned int channel,\r
- unsigned int comPtr, unsigned eoiFlag)\r
-{\r
- HWREG(emacBase + EMAC_RXCP(channel)) = comPtr;\r
-\r
- /* Acknowledge the EMAC Control Core */\r
- HWREG(emacBase + EMAC_MACEOIVECTOR) = eoiFlag;\r
-}\r
-\r
-/**\r
- * \brief Enables a specific channel to receive broadcast frames\r
- *\r
- * \param emacBase Base Address of the EMAC module registers.\r
- * \param channel Channel Number.\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACRxBroadCastEnable(unsigned int emacBase, unsigned int channel)\r
-{\r
- HWREG(emacBase + EMAC_RXMBPENABLE) &= ~EMAC_RXMBPENABLE_RXBROADCH;\r
-\r
- HWREG(emacBase + EMAC_RXMBPENABLE) |=\r
- EMAC_RXMBPENABLE_RXBROADEN | \r
- (channel << EMAC_RXMBPENABLE_RXBROADCH_SHIFT);\r
-}\r
-\r
-void EMACRxPromiscEnable(unsigned int emacBase, unsigned int channel)\r
-{\r
- HWREG(emacBase + EMAC_RXMBPENABLE) |= EMAC_RXMBPENABLE_RXCAFEN | EMAC_RXMBPENABLE_RXCEFEN;\r
- HWREG(emacBase + EMAC_RXMBPENABLE) |= (channel << EMAC_RXMBPENABLE_RXPROMCH_SHIFT);\r
-}\r
-/**\r
- * \brief Enables unicast for a specific channel\r
- *\r
- * \param emacBase Base Address of the EMAC module registers.\r
- * \param channel Channel Number.\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACRxUnicastSet(unsigned int emacBase, unsigned int channel)\r
-{\r
- HWREG(emacBase + EMAC_RXUNICASTSET) |= (1 << channel);\r
-}\r
-\r
-/**\r
- * \brief Set the free buffers for a specific channel\r
- *\r
- * \param emacBase Base Address of the EMAC module registers.\r
- * \param channel Channel Number.\r
- * \param nBuf Number of free buffers\r
- *\r
- * \return None\r
- *\r
- **/\r
-void EMACNumFreeBufSet(unsigned int emacBase, unsigned int channel,\r
- unsigned int nBuf)\r
-{\r
- HWREG(emacBase + EMAC_RXFREEBUFFER(channel)) = nBuf;\r
-}\r
-\r
-/**\r
- * \brief Gets the interrupt vectors of EMAC, which are pending\r
- *\r
- * \param emacBase Base Address of the EMAC module registers.\r
- *\r
- * \return Vectors\r
- *\r
- **/\r
-unsigned int EMACIntVectorGet(unsigned int emacBase)\r
-{\r
- return (HWREG(emacBase + EMAC_MACINVECTOR));\r
-}\r
-\r
-unsigned int EMACIntVectorRawGet(unsigned int emacBase)\r
-{\r
- return (HWREG(emacBase + EMAC_RXINTSTATRAW));\r
-}\r
-\r
-/***************************** End Of File ***********************************/\r
+/**
+ * \file emac.c
+ *
+ * \brief EMAC APIs.
+ *
+ * This file contains the device abstraction layer APIs for EMAC.
+ */
+
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * ALL RIGHTS RESERVED
+ */
+
+#include "sys_common.h"
+#include "hw_reg_access.h"
+#include "ti_drv_emac.h"
+#include "hw_emac.h"
+#include "hw_emac_ctrl.h"
+
+/*******************************************************************************
+* INTERNAL MACRO DEFINITIONS
+*******************************************************************************/
+#define EMAC_CONTROL_RESET (0x01u)
+#define EMAC_SOFT_RESET (0x01u)
+#define EMAC_MAX_HEADER_DESC (8u)
+#define EMAC_UNICAST_DISABLE (0xFFu)
+
+/*******************************************************************************
+* API FUNCTION DEFINITIONS
+*******************************************************************************/
+/**
+ * \brief Enables the TXPULSE Interrupt Generation.
+ *
+ * \param emacBase Base address of the EMAC Module registers.
+ * \param emacCtrlBase Base address of the EMAC CONTROL module registers
+ * \param ctrlCore Control core for which the interrupt to be enabled.
+ * \param channel Channel number for which interrupt to be enabled
+ *
+ * \return None
+ *
+ **/
+void EMACTxIntPulseEnable(unsigned int emacBase, unsigned int emacCtrlBase,
+ unsigned int ctrlCore, unsigned int channel)
+{
+ HWREG(emacBase + EMAC_TXINTMASKSET) |= (1 << channel);
+
+ HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) |= (1 << channel);
+}
+
+/**
+ * \brief Disables the TXPULSE Interrupt Generation.
+ *
+ * \param emacBase Base address of the EMAC Module registers.
+ * \param emacCtrlBase Base address of the EMAC CONTROL module registers
+ * \param ctrlCore Control core for which the interrupt to be disabled.
+ * \param channel Channel number for which interrupt to be disabled
+ *
+ * \return None
+ *
+ **/
+void EMACTxIntPulseDisable(unsigned int emacBase, unsigned int emacCtrlBase,
+ unsigned int ctrlCore, unsigned int channel)
+{
+ HWREG(emacBase + EMAC_TXINTMASKCLEAR) |= (1 << channel);
+
+ HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) &= ~(1 << channel);
+}
+
+/**
+ * \brief Enables the RXPULSE Interrupt Generation.
+ *
+ * \param emacBase Base address of the EMAC Module registers.
+ * \param emacCtrlBase Base address of the EMAC CONTROL module registers
+ * \param ctrlCore Control core for which the interrupt to be enabled.
+ * \param channel Channel number for which interrupt to be enabled
+ *
+ * \return None
+ *
+ **/
+void EMACRxIntPulseEnable(unsigned int emacBase, unsigned int emacCtrlBase,
+ unsigned int ctrlCore, unsigned int channel)
+{
+ HWREG(emacBase + EMAC_RXINTMASKSET) |= (1 << channel);
+
+ HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) |= (1 << channel);
+}
+
+/**
+ * \brief Disables the RXPULSE Interrupt Generation.
+ *
+ * \param emacBase Base address of the EMAC Module registers.
+ * \param emacCtrlBase Base address of the EMAC CONTROL module registers
+ * \param ctrlCore Control core for which the interrupt to be disabled.
+ * \param channel Channel number for which interrupt to be disabled
+ *
+ * \return None
+ *
+ **/
+void EMACRxIntPulseDisable(unsigned int emacBase, unsigned int emacCtrlBase,
+ unsigned int ctrlCore, unsigned int channel)
+{
+ HWREG(emacBase + EMAC_RXINTMASKCLEAR) |= (1 << channel);
+
+ HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) &= ~(1 << channel);
+}
+/**
+ * \brief This API sets the RMII speed. The RMII Speed can be 10 Mbps or
+ * 100 Mbps
+ *
+ * \param emacBase Base address of the EMAC Module registers.
+ * \param speed speed for setting.
+ * speed can take the following values. \n
+ * EMAC_RMIISPEED_10MBPS - 10 Mbps \n
+ * EMAC_RMIISPEED_100MBPS - 100 Mbps.
+ *
+ * \return None
+ *
+ **/
+void EMACRMIISpeedSet(unsigned int emacBase, unsigned int speed)
+{
+ HWREG(emacBase + EMAC_MACCONTROL) &= ~EMAC_MACCONTROL_RMIISPEED;
+
+ HWREG(emacBase + EMAC_MACCONTROL) |= speed;
+}
+
+/**
+ * \brief This API enables the MII control block
+ *
+ * \param emacBase Base address of the EMAC Module registers.
+ *
+ * \return None
+ *
+ **/
+void EMACMIIEnable(unsigned int emacBase)
+{
+ HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_GMIIEN;
+}
+
+/**
+ * \brief This API sets the duplex mode of operation(full/half) for MAC.
+ *
+ * \param emacBase Base address of the EMAC Module registers.
+ * \param duplexMode duplex mode of operation.
+ * duplexMode can take the following values. \n
+ * EMAC_DUPLEX_FULL - Full Duplex \n
+ * EMAC_DUPLEX_HALF - Half Duplex.
+ *
+ * \return None
+ *
+ **/
+void EMACDuplexSet(unsigned int emacBase, unsigned int duplexMode)
+{
+ HWREG(emacBase + EMAC_MACCONTROL) &= ~EMAC_MACCONTROL_FULLDUPLEX;
+
+ HWREG(emacBase + EMAC_MACCONTROL) |= duplexMode;
+}
+
+/**
+ * \brief API to enable the transmit in the TX Control Register
+ * After the transmit is enabled, any write to TXHDP of
+ * a channel will start transmission
+ *
+ * \param emacBase Base Address of the EMAC Module Registers.
+ *
+ * \return None
+ *
+ **/
+void EMACTxEnable(unsigned int emacBase)
+{
+ HWREG(emacBase + EMAC_TXCONTROL) = EMAC_TXCONTROL_TXEN;
+}
+
+/**
+ * \brief API to enable the receive in the RX Control Register
+ * After the transmit is enabled, and write to RXHDP of
+ * a channel, the data can be received in the destination
+ * specified by the corresponding RX buffer descriptor.
+ *
+ * \param emacBase Base Address of the EMAC Module Registers.
+ *
+ * \return None
+ *
+ **/
+void EMACRxEnable(unsigned int emacBase)
+{
+ HWREG(emacBase + EMAC_RXCONTROL) = EMAC_RXCONTROL_RXEN;
+}
+
+/**
+ * \brief API to write the TX HDP register. If transmit is enabled,
+ * write to the TX HDP will immediately start transmission.
+ * The data will be taken from the buffer pointer of the TX buffer
+ * descriptor written to the TX HDP
+ *
+ * \param emacBase Base Address of the EMAC Module Registers.\n
+ * \param descHdr Address of the TX buffer descriptor
+ * \param channel Channel Number
+ *
+ * \return None
+ *
+ **/
+volatile unsigned int lastInputdescHdr = 0;
+volatile unsigned int valHDPbefWrite = 0;
+void EMACTxHdrDescPtrWrite(unsigned int emacBase, unsigned int descHdr,
+ unsigned int channel)
+{
+ valHDPbefWrite = HWREG(emacBase + EMAC_TXHDP(channel));
+ HWREG(emacBase + EMAC_TXHDP(channel)) = descHdr;
+ lastInputdescHdr = descHdr;
+}
+
+/**
+ * \brief API to write the RX HDP register. If receive is enabled,
+ * write to the RX HDP will enable data reception to point to
+ * the corresponding RX buffer descriptor's buffer pointer.
+ *
+ * \param emacBase Base Address of the EMAC Module Registers.\n
+ * \param descHdr Address of the RX buffer descriptor
+ * \param channel Channel Number
+ *
+ * \return None
+ *
+ **/
+void EMACRxHdrDescPtrWrite(unsigned int emacBase, unsigned int descHdr,
+ unsigned int channel)
+{
+ HWREG(emacBase + EMAC_RXHDP(channel)) = descHdr;
+}
+
+/**
+ * \brief This API Initializes the EMAC and EMAC Control modules. The
+ * EMAC Control module is reset, the CPPI RAM is cleared. also,
+ * all the interrupts are disabled. This API doesnot enable any
+ * interrupt or operation of the EMAC.
+ *
+ * \param emacCtrlBase Base Address of the EMAC Control module
+ * registers.\n
+ * \param emacBase Base address of the EMAC module registers
+ *
+ * \return None
+ *
+ **/
+void EMACInit(unsigned int emacCtrlBase, unsigned int emacBase)
+{
+ unsigned int cnt;
+
+ /* Reset the EMAC Control Module. This clears the CPPI RAM also */
+ HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) = EMAC_CONTROL_RESET;
+
+ while(HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) & EMAC_CONTROL_RESET);
+
+ /* Reset the EMAC Control Module. This clears the CPPI RAM also */
+ HWREG(emacBase + EMAC_SOFTRESET) = EMAC_SOFT_RESET;
+
+ while(HWREG(emacBase + EMAC_SOFTRESET) & EMAC_SOFT_RESET);
+
+ HWREG(emacBase + EMAC_MACCONTROL)= 0;
+ HWREG(emacBase + EMAC_RXCONTROL)= 0;
+ HWREG(emacBase + EMAC_TXCONTROL)= 0;
+
+ /* Initialize all the header descriptor pointer registers */
+ for(cnt = 0; cnt< EMAC_MAX_HEADER_DESC; cnt++)
+ {
+ HWREG(emacBase + EMAC_RXHDP(cnt)) = 0;
+ HWREG(emacBase + EMAC_TXHDP(cnt)) = 0;
+ HWREG(emacBase + EMAC_RXCP(cnt)) = 0;
+ HWREG(emacBase + EMAC_TXCP(cnt)) = 0;
+ HWREG(emacBase + EMAC_RXFREEBUFFER(cnt)) = 0xFF;
+ }
+ /* Clear the interrupt enable for all the channels */
+ HWREG(emacBase + EMAC_TXINTMASKCLEAR) = 0xFF;
+ HWREG(emacBase + EMAC_RXINTMASKCLEAR) = 0xFF;
+
+ HWREG(emacBase + EMAC_MACHASH1) = 0;
+ HWREG(emacBase + EMAC_MACHASH2) = 0;
+
+ HWREG(emacBase + EMAC_RXBUFFEROFFSET) = 0;
+}
+
+/**
+ * \brief Sets the MAC Address in MACSRCADDR registers.
+ *
+ * \param emacBase Base Address of the EMAC module registers.
+ * \param macAddr Start address of a MAC address array.
+ * The array[0] shall be the LSB of the MAC address
+ *
+ * \return None
+ *
+ **/
+void EMACMACSrcAddrSet(unsigned int emacBase, unsigned char *macAddr)
+{
+ HWREG(emacBase + EMAC_MACSRCADDRHI) = macAddr[5] |(macAddr[4] << 8)
+ |(macAddr[3] << 16) |(macAddr[2] << 24);
+ HWREG(emacBase + EMAC_MACSRCADDRLO) = macAddr[1] | (macAddr[0] << 8);
+}
+
+/**
+ * \brief Sets the MAC Address in MACADDR registers.
+ *
+ * \param emacBase Base Address of the EMAC module registers.
+ * \param channel Channel Number
+ * \param matchFilt Match or Filter
+ * \param macAddr Start address of a MAC address array.
+ * The array[0] shall be the LSB of the MAC address
+ * matchFilt can take the following values \n
+ * EMAC_MACADDR_NO_MATCH_NO_FILTER - Address is not used to match
+ * or filter incoming packet. \n
+ * EMAC_MACADDR_FILTER - Address is used to filter incoming packets \n
+ * EMAC_MACADDR_MATCH - Address is used to match incoming packets \n
+ *
+ * \return None
+ *
+ **/
+void EMACMACAddrSet(unsigned int emacBase, unsigned int channel,
+ unsigned char *macAddr, unsigned int matchFilt)
+{
+ HWREG(emacBase + EMAC_MACINDEX) = channel;
+
+ HWREG(emacBase + EMAC_MACADDRHI) = macAddr[5] |(macAddr[4] << 8)
+ |(macAddr[3] << 16) |(macAddr[2] << 24);
+ HWREG(emacBase + EMAC_MACADDRLO) = macAddr[1] | (macAddr[0] << 8)
+ | matchFilt | (channel << 16);
+}
+
+/**
+ * \brief Acknowledges an interrupt processed to the EMAC Control Core.
+ *
+ * \param emacBase Base Address of the EMAC module registers.
+ * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control
+ * module.
+ * eoiFlag can take the following values \n
+ * EMAC_INT_CORE0_TX - Core 0 TX Interrupt
+ * EMAC_INT_CORE1_TX - Core 1 TX Interrupt
+ * EMAC_INT_CORE2_TX - Core 2 TX Interrupt
+ * EMAC_INT_CORE0_RX - Core 0 RX Interrupt
+ * EMAC_INT_CORE1_RX - Core 1 RX Interrupt
+ * EMAC_INT_CORE2_RX - Core 2 RX Interrupt
+ * \return None
+ *
+ **/
+void EMACCoreIntAck(unsigned int emacBase, unsigned int eoiFlag)
+{
+ /* Acknowledge the EMAC Control Core */
+ HWREG(emacBase + EMAC_MACEOIVECTOR) = eoiFlag;
+}
+
+/**
+ * \brief Writes the the TX Completion Pointer for a specific channel
+ *
+ * \param emacBase Base Address of the EMAC module registers.
+ * \param channel Channel Number.
+ * \param comPtr Completion Pointer Value to be written
+ *
+ * \return None
+ *
+ **/
+void EMACTxCPWrite(unsigned int emacBase, unsigned int channel, unsigned int comPtr)
+{
+ HWREG(emacBase + EMAC_TXCP(channel)) = comPtr;
+}
+
+uint32_t EMACTxCPRead(unsigned int emacBase, unsigned int channel)
+{
+ return (HWREG(emacBase + EMAC_TXCP(channel)));
+}
+
+/**
+ * \brief Writes the the RX Completion Pointer for a specific channel
+ *
+ * \param emacBase Base Address of the EMAC module registers.
+ * \param channel Channel Number.
+ * \param comPtr Completion Pointer Value to be written
+ *
+ * \return None
+ *
+ **/
+void EMACRxCPWrite(unsigned int emacBase, unsigned int channel, unsigned int comPtr)
+{
+ HWREG(emacBase + EMAC_RXCP(channel)) = comPtr;
+}
+
+/**
+ * \brief Acknowledges an interrupt processed to the EMAC module. After
+ * processing an interrupt, the last processed buffer descriptor is
+ * written to the completion pointer. Also this API acknowledges
+ * the EMAC Control Module that the RX interrupt is processed for
+ * a specified core
+ *
+ * \param emacBase Base Address of the EMAC module registers.
+ * \param channel Channel Number
+ * \param comPtr Completion Pointer value. This shall be the buffer
+ * descriptor address last processed.
+ * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control
+ module.
+ * eoiFlag can take the following values \n
+ * EMAC_INT_CORE0_RX - Core 0 RX Interrupt
+ * EMAC_INT_CORE1_RX - Core 1 RX Interrupt
+ * EMAC_INT_CORE2_RX - Core 2 RX Interrupt
+ * \return None
+ *
+ **/
+void EMACRxIntAckToClear(unsigned int emacBase, unsigned int channel,
+ unsigned int comPtr, unsigned eoiFlag)
+{
+ HWREG(emacBase + EMAC_RXCP(channel)) = comPtr;
+
+ /* Acknowledge the EMAC Control Core */
+ HWREG(emacBase + EMAC_MACEOIVECTOR) = eoiFlag;
+}
+
+/**
+ * \brief Enables a specific channel to receive broadcast frames
+ *
+ * \param emacBase Base Address of the EMAC module registers.
+ * \param channel Channel Number.
+ *
+ * \return None
+ *
+ **/
+void EMACRxBroadCastEnable(unsigned int emacBase, unsigned int channel)
+{
+ HWREG(emacBase + EMAC_RXMBPENABLE) &= ~EMAC_RXMBPENABLE_RXBROADCH;
+
+ HWREG(emacBase + EMAC_RXMBPENABLE) |=
+ EMAC_RXMBPENABLE_RXBROADEN |
+ (channel << EMAC_RXMBPENABLE_RXBROADCH_SHIFT);
+}
+
+void EMACRxPromiscEnable(unsigned int emacBase, unsigned int channel)
+{
+ HWREG(emacBase + EMAC_RXMBPENABLE) |= EMAC_RXMBPENABLE_RXCAFEN | EMAC_RXMBPENABLE_RXCEFEN;
+ HWREG(emacBase + EMAC_RXMBPENABLE) |= (channel << EMAC_RXMBPENABLE_RXPROMCH_SHIFT);
+}
+/**
+ * \brief Enables unicast for a specific channel
+ *
+ * \param emacBase Base Address of the EMAC module registers.
+ * \param channel Channel Number.
+ *
+ * \return None
+ *
+ **/
+void EMACRxUnicastSet(unsigned int emacBase, unsigned int channel)
+{
+ HWREG(emacBase + EMAC_RXUNICASTSET) |= (1 << channel);
+}
+
+/**
+ * \brief Set the free buffers for a specific channel
+ *
+ * \param emacBase Base Address of the EMAC module registers.
+ * \param channel Channel Number.
+ * \param nBuf Number of free buffers
+ *
+ * \return None
+ *
+ **/
+void EMACNumFreeBufSet(unsigned int emacBase, unsigned int channel,
+ unsigned int nBuf)
+{
+ HWREG(emacBase + EMAC_RXFREEBUFFER(channel)) = nBuf;
+}
+
+/**
+ * \brief Gets the interrupt vectors of EMAC, which are pending
+ *
+ * \param emacBase Base Address of the EMAC module registers.
+ *
+ * \return Vectors
+ *
+ **/
+unsigned int EMACIntVectorGet(unsigned int emacBase)
+{
+ return (HWREG(emacBase + EMAC_MACINVECTOR));
+}
+
+unsigned int EMACIntVectorRawGet(unsigned int emacBase)
+{
+ return (HWREG(emacBase + EMAC_RXINTSTATRAW));
+}
+
+/***************************** End Of File ***********************************/
-/** @file emif.c\r
-* @brief emif Driver Implementation File\r
-* @date 15.January.2012\r
-* @version 03.01.00\r
-*\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-\r
-#include "system.h"\r
-#include "ti_drv_emif.h"\r
-\r
-/** @fn void emif_SDRAMInit()\r
-* @brief Initializes the emif Driver for SDRAM\r
-*\r
-* This function initializes the emif driver for SDRAM (SDRAM initialization function).\r
-*/\r
-\r
-\r
-void emif_SDRAMInit()\r
-{\r
- uint32_t buffer;\r
- unsigned long saveif;\r
-\r
- /*\r
- * configure for SDRAM 64MB IS45S16320\r
- *\r
- * 4 banks, 1024 rows and 8192 columns\r
- * 2 bits , 10 bits and 13 bits\r
- * CL = 2/3\r
- * full refresh 64 ms\r
- * for 80 degC 16 ms\r
- * self refresh exit time 67 ns\r
- */\r
-\r
- saveif = _disable_IRQ();\r
-\r
- /* \r
- * From UM 4.3.3 Control of Special Multiplexed Options\r
- * Any application that requires the EMIF functionality\r
- * must set GPREG1[31]. This allows these 8 EMIF module\r
- * outputs to be driven on to the assigned balls.\r
- */\r
-\r
- systemREG1->GPREG1 |= 0x80000000;\r
-\r
- emifREG->SDTIMR = ((9-1) << 27)| /* TRF_C REFR to REFR*/\r
- ((3-1) << 24)| /* T_RP PRE to ACTIV or REFR */\r
- (0 << 23)|\r
- ((3-1) << 20)| /* T_RCD ACTIV to RD/WR */\r
- (0 << 19)|\r
- ((2-1) << 16)| /* T_WR WRITE to PRE */\r
- ((6-1) << 12)| /* T_RAS ACTIV to PRE */\r
- ((9-1) << 8)| /* T_RC ACTIV to ACTIV */\r
- (0 << 7)|\r
- ((2-1) << 4)| /* T_RRD ACTIV to ACTIV other bank */\r
- (0 << 3);\r
-\r
- /* configure refresh rate*/\r
- emifREG->SDSRETR = (5+3-1);\r
-\r
- /* 80e6 * 16e-3 / 8192 => less or equal to 156 */\r
- emifREG->SDRCR = 156;\r
-\r
-/** -general clearing of register\r
-* -for NM for setting 16 bit data bus\r
-* -cas latency\r
-* -BIT11_9CLOCK to allow the cl field to be written\r
-* -selecting the banks\r
-* -setting the pagesize\r
-*/\r
- emifREG->SDCR = (0 << 31)| /* SR self refresh mode */\r
- (0 << 30)| /* PD power down */\r
- (0 << 29)| /* PDWR refresh in PD */\r
- (1 << 14)| /* NM narrow mode */\r
- (3 << 9)| /* CAS latency */\r
- (1 << 8)| /* CAS latency lock */\r
- (2 << 4)| /* IBANK .. 4 banks */\r
- (2 << 0); /* PAGESIZE .. 10 bit / 1024ele */\r
-/* wait for a read to happen*/\r
- buffer = *(volatile uint32_t *)PTR;\r
- buffer = buffer;\r
- emifREG->SDRCR = 156;\r
-\r
- _restore_interrupts(saveif); \r
-}\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
+/** @file emif.c
+* @brief emif Driver Implementation File
+* @date 15.January.2012
+* @version 03.01.00
+*
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+
+#include "system.h"
+#include "ti_drv_emif.h"
+
+/** @fn void emif_SDRAMInit()
+* @brief Initializes the emif Driver for SDRAM
+*
+* This function initializes the emif driver for SDRAM (SDRAM initialization function).
+*/
+
+
+void emif_SDRAMInit()
+{
+ uint32_t buffer;
+ unsigned long saveif;
+
+ /*
+ * configure for SDRAM 64MB IS45S16320
+ *
+ * 4 banks, 1024 rows and 8192 columns
+ * 2 bits , 10 bits and 13 bits
+ * CL = 2/3
+ * full refresh 64 ms
+ * for 80 degC 16 ms
+ * self refresh exit time 67 ns
+ */
+
+ saveif = _disable_IRQ();
+
+ /*
+ * From UM 4.3.3 Control of Special Multiplexed Options
+ * Any application that requires the EMIF functionality
+ * must set GPREG1[31]. This allows these 8 EMIF module
+ * outputs to be driven on to the assigned balls.
+ */
+
+ systemREG1->GPREG1 |= 0x80000000;
+
+ emifREG->SDTIMR = ((9-1) << 27)| /* TRF_C REFR to REFR*/
+ ((3-1) << 24)| /* T_RP PRE to ACTIV or REFR */
+ (0 << 23)|
+ ((3-1) << 20)| /* T_RCD ACTIV to RD/WR */
+ (0 << 19)|
+ ((2-1) << 16)| /* T_WR WRITE to PRE */
+ ((6-1) << 12)| /* T_RAS ACTIV to PRE */
+ ((9-1) << 8)| /* T_RC ACTIV to ACTIV */
+ (0 << 7)|
+ ((2-1) << 4)| /* T_RRD ACTIV to ACTIV other bank */
+ (0 << 3);
+
+ /* configure refresh rate*/
+ emifREG->SDSRETR = (5+3-1);
+
+ /* 80e6 * 16e-3 / 8192 => less or equal to 156 */
+ emifREG->SDRCR = 156;
+
+/** -general clearing of register
+* -for NM for setting 16 bit data bus
+* -cas latency
+* -BIT11_9CLOCK to allow the cl field to be written
+* -selecting the banks
+* -setting the pagesize
+*/
+ emifREG->SDCR = (0 << 31)| /* SR self refresh mode */
+ (0 << 30)| /* PD power down */
+ (0 << 29)| /* PDWR refresh in PD */
+ (1 << 14)| /* NM narrow mode */
+ (3 << 9)| /* CAS latency */
+ (1 << 8)| /* CAS latency lock */
+ (2 << 4)| /* IBANK .. 4 banks */
+ (2 << 0); /* PAGESIZE .. 10 bit / 1024ele */
+/* wait for a read to happen*/
+ buffer = *(volatile uint32_t *)PTR;
+ buffer = buffer;
+ emifREG->SDRCR = 156;
+
+ _restore_interrupts(saveif);
+}
+
+
+
+
+
+
+
-/** @file esm.c \r
-* @brief Esm Driver Source File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-* This file contains:\r
-* - API Funcions\r
-* .\r
-* which are relevant for the Esm driver.\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-/* Include Files */\r
-\r
-#include "ti_drv_esm.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-\r
-/** @fn void esmInit(void)\r
-* @brief Initializes Esm Driver\r
-*\r
-* This function initializes the Esm driver.\r
-*\r
-*/\r
-\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
-void esmInit(void)\r
-{\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-\r
- /** - Disable error pin channels */\r
- esmREG->EPENACLR1 = 0xFFFFFFFFU;\r
- esmREG->EPENACLR4 = 0xFFFFFFFFU;\r
-\r
- /** - Disable interrupts */\r
- esmREG->INTENACLR1 = 0xFFFFFFFFU;\r
- esmREG->INTENACLR4 = 0xFFFFFFFFU;\r
-\r
- /** - Clear error status flags */\r
- esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;\r
- esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;\r
- esmREG->ESTATUS2EMU = 0xFFFFFFFFU;\r
- esmREG->ESTATUS1[2U] = 0xFFFFFFFFU;\r
- esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;\r
- esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;\r
- esmREG->ESTATUS5EMU = 0xFFFFFFFFU;\r
- esmREG->ESTATUS4[2U] = 0xFFFFFFFFU;\r
-\r
- /** - Setup LPC preload */\r
- esmREG->LTCPRELOAD = 16384U - 1U;\r
-\r
- /** - Reset error pin */\r
- if (esmREG->EPSTATUS == 0U)\r
- {\r
- esmREG->KEY = 0x00000005U;\r
- }\r
- else\r
- {\r
- esmREG->KEY = 0x00000000U;\r
- }\r
-\r
- /** - Clear interrupt level */\r
- esmREG->INTLVLCLR1 = 0xFFFFFFFFU;\r
- esmREG->INTLVLCLR4 = 0xFFFFFFFFU;\r
-\r
- /** - Set interrupt level */\r
- esmREG->INTLVLSET1 = (0U << 31U)\r
- | (0U << 30U)\r
- | (0U << 29U)\r
- | (0U << 28U)\r
- | (0U << 27U)\r
- | (0U << 26U)\r
- | (0U << 25U)\r
- | (0U << 24U)\r
- | (0U << 23U)\r
- | (0U << 22U)\r
- | (0U << 21U)\r
- | (0U << 20U)\r
- | (0U << 19U)\r
- | (0U << 18U)\r
- | (0U << 17U)\r
- | (0U << 16U)\r
- | (0U << 15U)\r
- | (0U << 14U)\r
- | (0U << 13U)\r
- | (0U << 12U)\r
- | (0U << 11U)\r
- | (0U << 10U)\r
- | (0U << 9U)\r
- | (0U << 8U)\r
- | (0U << 7U)\r
- | (0U << 6U)\r
- | (0U << 5U)\r
- | (0U << 4U)\r
- | (0U << 3U)\r
- | (0U << 2U)\r
- | (0U << 1U)\r
- | (0U);\r
-\r
- esmREG->INTLVLSET4 = (0U << 31U)\r
- | (0U << 30U)\r
- | (0U << 29U)\r
- | (0U << 28U)\r
- | (0U << 27U)\r
- | (0U << 26U)\r
- | (0U << 25U)\r
- | (0U << 24U)\r
- | (0U << 23U)\r
- | (0U << 22U)\r
- | (0U << 21U)\r
- | (0U << 20U)\r
- | (0U << 19U)\r
- | (0U << 18U)\r
- | (0U << 17U)\r
- | (0U << 16U)\r
- | (0U << 15U)\r
- | (0U << 14U)\r
- | (0U << 13U)\r
- | (0U << 12U)\r
- | (0U << 11U)\r
- | (0U << 10U)\r
- | (0U << 9U)\r
- | (0U << 8U)\r
- | (0U << 7U)\r
- | (0U << 6U)\r
- | (0U << 5U)\r
- | (0U << 4U)\r
- | (0U << 3U)\r
- | (0U << 2U)\r
- | (0U << 1U)\r
- | (0U);\r
-\r
- /** - Enable error pin channels */\r
- esmREG->EPENASET1 = (0U << 31U)\r
- | (0U << 30U)\r
- | (0U << 29U)\r
- | (0U << 28U)\r
- | (0U << 27U)\r
- | (0U << 26U)\r
- | (0U << 25U)\r
- | (0U << 24U)\r
- | (0U << 23U)\r
- | (0U << 22U)\r
- | (0U << 21U)\r
- | (0U << 20U)\r
- | (0U << 19U)\r
- | (0U << 18U)\r
- | (0U << 17U)\r
- | (0U << 16U)\r
- | (0U << 15U)\r
- | (0U << 14U)\r
- | (0U << 13U)\r
- | (0U << 12U)\r
- | (0U << 11U)\r
- | (0U << 10U)\r
- | (0U << 9U)\r
- | (0U << 8U)\r
- | (0U << 7U)\r
- | (0U << 6U)\r
- | (0U << 5U)\r
- | (0U << 4U)\r
- | (0U << 3U)\r
- | (0U << 2U)\r
- | (0U << 1U)\r
- | (0U);\r
-\r
- esmREG->EPENASET4 = (0U << 31U)\r
- | (0U << 30U)\r
- | (0U << 29U)\r
- | (0U << 28U)\r
- | (0U << 27U)\r
- | (0U << 26U)\r
- | (0U << 25U)\r
- | (0U << 24U)\r
- | (0U << 23U)\r
- | (0U << 22U)\r
- | (0U << 21U)\r
- | (0U << 20U)\r
- | (0U << 19U)\r
- | (0U << 18U)\r
- | (0U << 17U)\r
- | (0U << 16U)\r
- | (0U << 15U)\r
- | (0U << 14U)\r
- | (0U << 13U)\r
- | (0U << 12U)\r
- | (0U << 11U)\r
- | (0U << 10U)\r
- | (0U << 9U)\r
- | (0U << 8U)\r
- | (0U << 7U)\r
- | (0U << 6U)\r
- | (0U << 5U)\r
- | (0U << 4U)\r
- | (0U << 3U)\r
- | (0U << 2U)\r
- | (0U << 1U)\r
- | (0U);\r
-\r
- /** - Enable interrpts */\r
- esmREG->INTENASET1 = (0U << 31U)\r
- | (0U << 30U)\r
- | (0U << 29U)\r
- | (0U << 28U)\r
- | (0U << 27U)\r
- | (0U << 26U)\r
- | (0U << 25U)\r
- | (0U << 24U)\r
- | (0U << 23U)\r
- | (0U << 22U)\r
- | (0U << 21U)\r
- | (0U << 20U)\r
- | (0U << 19U)\r
- | (0U << 18U)\r
- | (0U << 17U)\r
- | (0U << 16U)\r
- | (0U << 15U)\r
- | (0U << 14U)\r
- | (0U << 13U)\r
- | (0U << 12U)\r
- | (0U << 11U)\r
- | (0U << 10U)\r
- | (0U << 9U)\r
- | (0U << 8U)\r
- | (0U << 7U)\r
- | (0U << 6U)\r
- | (0U << 5U)\r
- | (0U << 4U)\r
- | (0U << 3U)\r
- | (0U << 2U)\r
- | (0U << 1U)\r
- | (0U);\r
-\r
- esmREG->INTENASET4 = (0U << 31U)\r
- | (0U << 30U)\r
- | (0U << 29U)\r
- | (0U << 28U)\r
- | (0U << 27U)\r
- | (0U << 26U)\r
- | (0U << 25U)\r
- | (0U << 24U)\r
- | (0U << 23U)\r
- | (0U << 22U)\r
- | (0U << 21U)\r
- | (0U << 20U)\r
- | (0U << 19U)\r
- | (0U << 18U)\r
- | (0U << 17U)\r
- | (0U << 16U)\r
- | (0U << 15U)\r
- | (0U << 14U)\r
- | (0U << 13U)\r
- | (0U << 12U)\r
- | (0U << 11U)\r
- | (0U << 10U)\r
- | (0U << 9U)\r
- | (0U << 8U)\r
- | (0U << 7U)\r
- | (0U << 6U)\r
- | (0U << 5U)\r
- | (0U << 4U)\r
- | (0U << 3U)\r
- | (0U << 2U)\r
- | (0U << 1U)\r
- | (0U);\r
-\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn uint32_t esmError(void)\r
-* @brief Return Error status\r
-*\r
-* @return The error status\r
-*\r
-* Returns the error status.\r
-*/\r
-uint32_t esmError(void)\r
-{\r
- uint32_t status;\r
-\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
-\r
- status = esmREG->EPSTATUS;\r
-\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
-\r
- return status;\r
-}\r
-\r
-\r
-/** @fn void esmEnableError(uint64_t channels)\r
-* @brief Enable Group 1 Channels Error Signals propagation\r
-*\r
-* @param[in] channels - Channel mask\r
-*\r
-* Enable Group 1 Channels Error Signals propagation to the error pin.\r
-*/\r
-void esmEnableError(uint64_t channels)\r
-{\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
-\r
- esmREG->EPENASET4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
- esmREG->EPENASET1 = (uint32_t)(channels & 0xFFFFFFFF);\r
-\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void esmDisableError(uint64_t channels)\r
-* @brief Disable Group 1 Channels Error Signals propagation\r
-*\r
-* @param[in] channels - Channel mask\r
-*\r
-* Disable Group 1 Channels Error Signals propagation to the error pin.\r
-*/\r
-void esmDisableError(uint64_t channels)\r
-{\r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
-\r
- esmREG->EPENACLR4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
- esmREG->EPENACLR1 = (uint32_t)(channels & 0xFFFFFFFF);\r
-\r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void esmTriggerErrorPinReset(void)\r
-* @brief Trigger error pin reset and switch back to normal operation\r
-*\r
-* Trigger error pin reset and switch back to normal operation.\r
-*/\r
-void esmTriggerErrorPinReset(void)\r
-{\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
-\r
- esmREG->KEY = 5U;\r
-\r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void esmActivateNormalOperation(void)\r
-* @brief Activate normal operation\r
-*\r
-* Activates normal operation mode.\r
-*/\r
-void esmActivateNormalOperation(void)\r
-{\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
-\r
- esmREG->KEY = 0U;\r
-\r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void esmEnableInterrupt(uint64_t channels)\r
-* @brief Enable Group 1 Channels Interrupts\r
-*\r
-* @param[in] channels - Channel mask\r
-*\r
-* Enable Group 1 Channels Interrupts.\r
-*/\r
-void esmEnableInterrupt(uint64_t channels)\r
-{\r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
-\r
- esmREG->INTENASET4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
- esmREG->INTENASET1 = (uint32_t)(channels & 0xFFFFFFFF);\r
-\r
-/* USER CODE BEGIN (16) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void esmDisableInterrupt(uint64_t channels)\r
-* @brief Disable Group 1 Channels Interrupts\r
-*\r
-* @param[in] channels - Channel mask\r
-*\r
-* Disable Group 1 Channels Interrupts.\r
-*/\r
-void esmDisableInterrupt(uint64_t channels)\r
-{\r
-/* USER CODE BEGIN (17) */\r
-/* USER CODE END */\r
-\r
- esmREG->INTENACLR4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
- esmREG->INTENACLR1 = (uint32_t)(channels & 0xFFFFFFFF);\r
-\r
-/* USER CODE BEGIN (18) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void esmSetInterruptLevel(uint64_t channels, uint64_t flags)\r
-* @brief Set Group 1 Channels Interrupt Levels\r
-*\r
-* @param[in] channels - Channel mask\r
-* @param[in] flags - Level mask: - 0: Low priority interrupt\r
-* - 1: High priority interrupt\r
-*\r
-* Set Group 1 Channels Interrupts levels.\r
-*/\r
-void esmSetInterruptLevel(uint64_t channels, uint64_t flags)\r
-{\r
-/* USER CODE BEGIN (19) */\r
-/* USER CODE END */\r
-\r
- esmREG->INTLVLCLR4 = (uint32_t)(((channels & ~flags) >> 32) & 0xFFFFFFF);\r
- esmREG->INTLVLSET4 = (uint32_t)(((channels & flags) >> 32) & 0xFFFFFFFF);\r
- esmREG->INTLVLCLR1 = (uint32_t)(channels & ~flags & 0xFFFFFFF);\r
- esmREG->INTLVLSET1 = (uint32_t)(channels & flags & 0xFFFFFFFF);\r
-\r
-/* USER CODE BEGIN (20) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void esmClearStatus(uint32_t group, uint64_t channels)\r
-* @brief Clear Group error status\r
-*\r
-* @param[in] group - Error group\r
-* @param[in] channels - Channel mask\r
-*\r
-* Clear Group error status.\r
-*/\r
-void esmClearStatus(uint32_t group, uint64_t channels)\r
-{\r
-/* USER CODE BEGIN (21) */\r
-/* USER CODE END */\r
-\r
- esmREG->ESTATUS4[group] = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
- esmREG->ESTATUS1[group] = (uint32_t)(channels & 0xFFFFFFFF);\r
-\r
-/* USER CODE BEGIN (22) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void esmClearStatusBuffer(uint64_t channels)\r
-* @brief Clear Group 2 error status buffer\r
-*\r
-* @param[in] channels - Channel mask\r
-*\r
-* Clear Group 2 error status buffer.\r
-*/\r
-void esmClearStatusBuffer(uint64_t channels)\r
-{\r
-/* USER CODE BEGIN (23) */\r
-/* USER CODE END */\r
-\r
- esmREG->ESTATUS5EMU = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
- esmREG->ESTATUS2EMU = (uint32_t)(channels & 0xFFFFFFFF);\r
-\r
-/* USER CODE BEGIN (24) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void esmSetCounterPreloadValue(uint32_t value)\r
-* @brief Set couter preload value\r
-*\r
-* @param[in] value - Counter preload value\r
-*\r
-* Set counter preload value.\r
-*/\r
-void esmSetCounterPreloadValue(uint32_t value)\r
-{\r
-/* USER CODE BEGIN (25) */\r
-/* USER CODE END */\r
-\r
- esmREG->LTCPRELOAD = value & 0xC000U;\r
-\r
-/* USER CODE BEGIN (26) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn uint64_t esmGetStatus(uint32_t group, uint64_t channels)\r
-* @brief Return Error status\r
-*\r
-* @param[in] group - Error group\r
-* @param[in] channels - Error Channels\r
-*\r
-* @return The channels status of selected group\r
-*\r
-* Returns the channels status of selected group.\r
-*/\r
-uint64_t esmGetStatus(uint32_t group, uint64_t channels)\r
-{\r
- uint64_t status;\r
-\r
-/* USER CODE BEGIN (27) */\r
-/* USER CODE END */\r
-\r
- status = (((uint64_t)esmREG->ESTATUS4[group] << 32) | (uint64_t)esmREG->ESTATUS1[group]) & channels;\r
-\r
-/* USER CODE BEGIN (28) */\r
-/* USER CODE END */\r
-\r
- return status;\r
-}\r
-\r
-\r
-/** @fn uint64_t esmGetStatusBuffer(uint64_t channels)\r
-* @brief Return Group 2 channel x Error status buffer\r
-*\r
-* @param[in] channels - Error Channels\r
-*\r
-* @return The channels status\r
-*\r
-* Returns the group 2 bufferd status of selected channels.\r
-*/\r
-uint64_t esmGetStatusBuffer(uint64_t channels)\r
-{\r
- uint64_t status;\r
-\r
-/* USER CODE BEGIN (29) */\r
-/* USER CODE END */\r
-\r
- status = (((uint64_t)esmREG->ESTATUS5EMU << 32) | (uint64_t)esmREG->ESTATUS2EMU) & channels;\r
-\r
-/* USER CODE BEGIN (30) */\r
-/* USER CODE END */\r
-\r
- return status;\r
-}\r
-\r
-/** @fn void esmHighInterrupt(void)\r
-* @brief High Level Interrupt for ESM\r
-*/\r
-#pragma INTERRUPT(esmHighInterrupt, FIQ)\r
-\r
-\r
-void esmHighInterrupt(void)\r
-{\r
- int vec = esmREG->INTOFFH - 1;\r
-\r
-/* USER CODE BEGIN (31) */\r
-/* USER CODE END */\r
-\r
- if (vec >= 96)\r
- {\r
- esmREG->ESTATUS4[1U] = 1U << (vec-96);\r
- esmGroup2Notification(vec-64);\r
- }\r
- else if (vec >= 64)\r
- {\r
- esmREG->ESTATUS4[0U] = 1U << (vec-64);\r
- esmGroup1Notification(vec-32);\r
- }\r
- else if (vec >= 32)\r
- {\r
- esmREG->ESTATUS1[1U] = 1U << (vec-32);\r
- esmGroup2Notification(vec-32);\r
- }\r
- else if (vec >= 0)\r
- {\r
- esmREG->ESTATUS1[0U] = 1 << vec;\r
- esmGroup1Notification(vec);\r
- }\r
- else\r
- {\r
- esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;\r
- esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;\r
- esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;\r
- esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;\r
- }\r
-\r
-/* USER CODE BEGIN (32) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void esmLowInterrupt(void)\r
-* @brief Low Level Interrupt for ESM\r
-*/\r
-#pragma INTERRUPT(esmLowInterrupt, IRQ)\r
-\r
-void esmLowInterrupt(void)\r
-{\r
-\r
- /* Note : Group 1 Error */\r
- /* 1 to 32 -> channel 0 to 31 */\r
- /* 65 to 96 -> channel 32 to 63 */\r
-\r
- int vec = esmREG->INTOFFL - 1;\r
-\r
-/* USER CODE BEGIN (33) */\r
-/* USER CODE END */\r
-\r
-\r
- if (vec >= 64) /* channel 32 to 63 */\r
- {\r
- esmREG->ESTATUS4[0U] = 1U << (vec-64);\r
- esmGroup1Notification(vec-32);\r
- }\r
- else if (vec >= 0) /* channel 0 to 31 */\r
- {\r
- esmREG->ESTATUS1[0U] = 1U << vec;\r
- esmGroup1Notification(vec);\r
- }\r
- else\r
- {\r
- esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;\r
- esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;\r
- }\r
-\r
-/* USER CODE BEGIN (34) */\r
-/* USER CODE END */\r
-}\r
-\r
-/* USER CODE BEGIN (35) */\r
-/* USER CODE END */\r
+/** @file esm.c
+* @brief Esm Driver Source File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+* This file contains:
+* - API Funcions
+* .
+* which are relevant for the Esm driver.
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "ti_drv_esm.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @fn void esmInit(void)
+* @brief Initializes Esm Driver
+*
+* This function initializes the Esm driver.
+*
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+void esmInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+ /** - Disable error pin channels */
+ esmREG->EPENACLR1 = 0xFFFFFFFFU;
+ esmREG->EPENACLR4 = 0xFFFFFFFFU;
+
+ /** - Disable interrupts */
+ esmREG->INTENACLR1 = 0xFFFFFFFFU;
+ esmREG->INTENACLR4 = 0xFFFFFFFFU;
+
+ /** - Clear error status flags */
+ esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;
+ esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;
+ esmREG->ESTATUS2EMU = 0xFFFFFFFFU;
+ esmREG->ESTATUS1[2U] = 0xFFFFFFFFU;
+ esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;
+ esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;
+ esmREG->ESTATUS5EMU = 0xFFFFFFFFU;
+ esmREG->ESTATUS4[2U] = 0xFFFFFFFFU;
+
+ /** - Setup LPC preload */
+ esmREG->LTCPRELOAD = 16384U - 1U;
+
+ /** - Reset error pin */
+ if (esmREG->EPSTATUS == 0U)
+ {
+ esmREG->KEY = 0x00000005U;
+ }
+ else
+ {
+ esmREG->KEY = 0x00000000U;
+ }
+
+ /** - Clear interrupt level */
+ esmREG->INTLVLCLR1 = 0xFFFFFFFFU;
+ esmREG->INTLVLCLR4 = 0xFFFFFFFFU;
+
+ /** - Set interrupt level */
+ esmREG->INTLVLSET1 = (0U << 31U)
+ | (0U << 30U)
+ | (0U << 29U)
+ | (0U << 28U)
+ | (0U << 27U)
+ | (0U << 26U)
+ | (0U << 25U)
+ | (0U << 24U)
+ | (0U << 23U)
+ | (0U << 22U)
+ | (0U << 21U)
+ | (0U << 20U)
+ | (0U << 19U)
+ | (0U << 18U)
+ | (0U << 17U)
+ | (0U << 16U)
+ | (0U << 15U)
+ | (0U << 14U)
+ | (0U << 13U)
+ | (0U << 12U)
+ | (0U << 11U)
+ | (0U << 10U)
+ | (0U << 9U)
+ | (0U << 8U)
+ | (0U << 7U)
+ | (0U << 6U)
+ | (0U << 5U)
+ | (0U << 4U)
+ | (0U << 3U)
+ | (0U << 2U)
+ | (0U << 1U)
+ | (0U);
+
+ esmREG->INTLVLSET4 = (0U << 31U)
+ | (0U << 30U)
+ | (0U << 29U)
+ | (0U << 28U)
+ | (0U << 27U)
+ | (0U << 26U)
+ | (0U << 25U)
+ | (0U << 24U)
+ | (0U << 23U)
+ | (0U << 22U)
+ | (0U << 21U)
+ | (0U << 20U)
+ | (0U << 19U)
+ | (0U << 18U)
+ | (0U << 17U)
+ | (0U << 16U)
+ | (0U << 15U)
+ | (0U << 14U)
+ | (0U << 13U)
+ | (0U << 12U)
+ | (0U << 11U)
+ | (0U << 10U)
+ | (0U << 9U)
+ | (0U << 8U)
+ | (0U << 7U)
+ | (0U << 6U)
+ | (0U << 5U)
+ | (0U << 4U)
+ | (0U << 3U)
+ | (0U << 2U)
+ | (0U << 1U)
+ | (0U);
+
+ /** - Enable error pin channels */
+ esmREG->EPENASET1 = (0U << 31U)
+ | (0U << 30U)
+ | (0U << 29U)
+ | (0U << 28U)
+ | (0U << 27U)
+ | (0U << 26U)
+ | (0U << 25U)
+ | (0U << 24U)
+ | (0U << 23U)
+ | (0U << 22U)
+ | (0U << 21U)
+ | (0U << 20U)
+ | (0U << 19U)
+ | (0U << 18U)
+ | (0U << 17U)
+ | (0U << 16U)
+ | (0U << 15U)
+ | (0U << 14U)
+ | (0U << 13U)
+ | (0U << 12U)
+ | (0U << 11U)
+ | (0U << 10U)
+ | (0U << 9U)
+ | (0U << 8U)
+ | (0U << 7U)
+ | (0U << 6U)
+ | (0U << 5U)
+ | (0U << 4U)
+ | (0U << 3U)
+ | (0U << 2U)
+ | (0U << 1U)
+ | (0U);
+
+ esmREG->EPENASET4 = (0U << 31U)
+ | (0U << 30U)
+ | (0U << 29U)
+ | (0U << 28U)
+ | (0U << 27U)
+ | (0U << 26U)
+ | (0U << 25U)
+ | (0U << 24U)
+ | (0U << 23U)
+ | (0U << 22U)
+ | (0U << 21U)
+ | (0U << 20U)
+ | (0U << 19U)
+ | (0U << 18U)
+ | (0U << 17U)
+ | (0U << 16U)
+ | (0U << 15U)
+ | (0U << 14U)
+ | (0U << 13U)
+ | (0U << 12U)
+ | (0U << 11U)
+ | (0U << 10U)
+ | (0U << 9U)
+ | (0U << 8U)
+ | (0U << 7U)
+ | (0U << 6U)
+ | (0U << 5U)
+ | (0U << 4U)
+ | (0U << 3U)
+ | (0U << 2U)
+ | (0U << 1U)
+ | (0U);
+
+ /** - Enable interrpts */
+ esmREG->INTENASET1 = (0U << 31U)
+ | (0U << 30U)
+ | (0U << 29U)
+ | (0U << 28U)
+ | (0U << 27U)
+ | (0U << 26U)
+ | (0U << 25U)
+ | (0U << 24U)
+ | (0U << 23U)
+ | (0U << 22U)
+ | (0U << 21U)
+ | (0U << 20U)
+ | (0U << 19U)
+ | (0U << 18U)
+ | (0U << 17U)
+ | (0U << 16U)
+ | (0U << 15U)
+ | (0U << 14U)
+ | (0U << 13U)
+ | (0U << 12U)
+ | (0U << 11U)
+ | (0U << 10U)
+ | (0U << 9U)
+ | (0U << 8U)
+ | (0U << 7U)
+ | (0U << 6U)
+ | (0U << 5U)
+ | (0U << 4U)
+ | (0U << 3U)
+ | (0U << 2U)
+ | (0U << 1U)
+ | (0U);
+
+ esmREG->INTENASET4 = (0U << 31U)
+ | (0U << 30U)
+ | (0U << 29U)
+ | (0U << 28U)
+ | (0U << 27U)
+ | (0U << 26U)
+ | (0U << 25U)
+ | (0U << 24U)
+ | (0U << 23U)
+ | (0U << 22U)
+ | (0U << 21U)
+ | (0U << 20U)
+ | (0U << 19U)
+ | (0U << 18U)
+ | (0U << 17U)
+ | (0U << 16U)
+ | (0U << 15U)
+ | (0U << 14U)
+ | (0U << 13U)
+ | (0U << 12U)
+ | (0U << 11U)
+ | (0U << 10U)
+ | (0U << 9U)
+ | (0U << 8U)
+ | (0U << 7U)
+ | (0U << 6U)
+ | (0U << 5U)
+ | (0U << 4U)
+ | (0U << 3U)
+ | (0U << 2U)
+ | (0U << 1U)
+ | (0U);
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+
+/** @fn uint32_t esmError(void)
+* @brief Return Error status
+*
+* @return The error status
+*
+* Returns the error status.
+*/
+uint32_t esmError(void)
+{
+ uint32_t status;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+ status = esmREG->EPSTATUS;
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+ return status;
+}
+
+
+/** @fn void esmEnableError(uint64_t channels)
+* @brief Enable Group 1 Channels Error Signals propagation
+*
+* @param[in] channels - Channel mask
+*
+* Enable Group 1 Channels Error Signals propagation to the error pin.
+*/
+void esmEnableError(uint64_t channels)
+{
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+ esmREG->EPENASET4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);
+ esmREG->EPENASET1 = (uint32_t)(channels & 0xFFFFFFFF);
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmDisableError(uint64_t channels)
+* @brief Disable Group 1 Channels Error Signals propagation
+*
+* @param[in] channels - Channel mask
+*
+* Disable Group 1 Channels Error Signals propagation to the error pin.
+*/
+void esmDisableError(uint64_t channels)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+ esmREG->EPENACLR4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);
+ esmREG->EPENACLR1 = (uint32_t)(channels & 0xFFFFFFFF);
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmTriggerErrorPinReset(void)
+* @brief Trigger error pin reset and switch back to normal operation
+*
+* Trigger error pin reset and switch back to normal operation.
+*/
+void esmTriggerErrorPinReset(void)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ esmREG->KEY = 5U;
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmActivateNormalOperation(void)
+* @brief Activate normal operation
+*
+* Activates normal operation mode.
+*/
+void esmActivateNormalOperation(void)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ esmREG->KEY = 0U;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmEnableInterrupt(uint64_t channels)
+* @brief Enable Group 1 Channels Interrupts
+*
+* @param[in] channels - Channel mask
+*
+* Enable Group 1 Channels Interrupts.
+*/
+void esmEnableInterrupt(uint64_t channels)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ esmREG->INTENASET4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);
+ esmREG->INTENASET1 = (uint32_t)(channels & 0xFFFFFFFF);
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmDisableInterrupt(uint64_t channels)
+* @brief Disable Group 1 Channels Interrupts
+*
+* @param[in] channels - Channel mask
+*
+* Disable Group 1 Channels Interrupts.
+*/
+void esmDisableInterrupt(uint64_t channels)
+{
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ esmREG->INTENACLR4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);
+ esmREG->INTENACLR1 = (uint32_t)(channels & 0xFFFFFFFF);
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmSetInterruptLevel(uint64_t channels, uint64_t flags)
+* @brief Set Group 1 Channels Interrupt Levels
+*
+* @param[in] channels - Channel mask
+* @param[in] flags - Level mask: - 0: Low priority interrupt
+* - 1: High priority interrupt
+*
+* Set Group 1 Channels Interrupts levels.
+*/
+void esmSetInterruptLevel(uint64_t channels, uint64_t flags)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ esmREG->INTLVLCLR4 = (uint32_t)(((channels & ~flags) >> 32) & 0xFFFFFFF);
+ esmREG->INTLVLSET4 = (uint32_t)(((channels & flags) >> 32) & 0xFFFFFFFF);
+ esmREG->INTLVLCLR1 = (uint32_t)(channels & ~flags & 0xFFFFFFF);
+ esmREG->INTLVLSET1 = (uint32_t)(channels & flags & 0xFFFFFFFF);
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmClearStatus(uint32_t group, uint64_t channels)
+* @brief Clear Group error status
+*
+* @param[in] group - Error group
+* @param[in] channels - Channel mask
+*
+* Clear Group error status.
+*/
+void esmClearStatus(uint32_t group, uint64_t channels)
+{
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+ esmREG->ESTATUS4[group] = (uint32_t)((channels >> 32) & 0xFFFFFFFF);
+ esmREG->ESTATUS1[group] = (uint32_t)(channels & 0xFFFFFFFF);
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmClearStatusBuffer(uint64_t channels)
+* @brief Clear Group 2 error status buffer
+*
+* @param[in] channels - Channel mask
+*
+* Clear Group 2 error status buffer.
+*/
+void esmClearStatusBuffer(uint64_t channels)
+{
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+ esmREG->ESTATUS5EMU = (uint32_t)((channels >> 32) & 0xFFFFFFFF);
+ esmREG->ESTATUS2EMU = (uint32_t)(channels & 0xFFFFFFFF);
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmSetCounterPreloadValue(uint32_t value)
+* @brief Set couter preload value
+*
+* @param[in] value - Counter preload value
+*
+* Set counter preload value.
+*/
+void esmSetCounterPreloadValue(uint32_t value)
+{
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+ esmREG->LTCPRELOAD = value & 0xC000U;
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+}
+
+
+/** @fn uint64_t esmGetStatus(uint32_t group, uint64_t channels)
+* @brief Return Error status
+*
+* @param[in] group - Error group
+* @param[in] channels - Error Channels
+*
+* @return The channels status of selected group
+*
+* Returns the channels status of selected group.
+*/
+uint64_t esmGetStatus(uint32_t group, uint64_t channels)
+{
+ uint64_t status;
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+ status = (((uint64_t)esmREG->ESTATUS4[group] << 32) | (uint64_t)esmREG->ESTATUS1[group]) & channels;
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ return status;
+}
+
+
+/** @fn uint64_t esmGetStatusBuffer(uint64_t channels)
+* @brief Return Group 2 channel x Error status buffer
+*
+* @param[in] channels - Error Channels
+*
+* @return The channels status
+*
+* Returns the group 2 bufferd status of selected channels.
+*/
+uint64_t esmGetStatusBuffer(uint64_t channels)
+{
+ uint64_t status;
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+ status = (((uint64_t)esmREG->ESTATUS5EMU << 32) | (uint64_t)esmREG->ESTATUS2EMU) & channels;
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+ return status;
+}
+
+/** @fn void esmHighInterrupt(void)
+* @brief High Level Interrupt for ESM
+*/
+#pragma INTERRUPT(esmHighInterrupt, FIQ)
+
+
+void esmHighInterrupt(void)
+{
+ int vec = esmREG->INTOFFH - 1;
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+ if (vec >= 96)
+ {
+ esmREG->ESTATUS4[1U] = 1U << (vec-96);
+ esmGroup2Notification(vec-64);
+ }
+ else if (vec >= 64)
+ {
+ esmREG->ESTATUS4[0U] = 1U << (vec-64);
+ esmGroup1Notification(vec-32);
+ }
+ else if (vec >= 32)
+ {
+ esmREG->ESTATUS1[1U] = 1U << (vec-32);
+ esmGroup2Notification(vec-32);
+ }
+ else if (vec >= 0)
+ {
+ esmREG->ESTATUS1[0U] = 1 << vec;
+ esmGroup1Notification(vec);
+ }
+ else
+ {
+ esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;
+ esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;
+ esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;
+ esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;
+ }
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmLowInterrupt(void)
+* @brief Low Level Interrupt for ESM
+*/
+#pragma INTERRUPT(esmLowInterrupt, IRQ)
+
+void esmLowInterrupt(void)
+{
+
+ /* Note : Group 1 Error */
+ /* 1 to 32 -> channel 0 to 31 */
+ /* 65 to 96 -> channel 32 to 63 */
+
+ int vec = esmREG->INTOFFL - 1;
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+
+ if (vec >= 64) /* channel 32 to 63 */
+ {
+ esmREG->ESTATUS4[0U] = 1U << (vec-64);
+ esmGroup1Notification(vec-32);
+ }
+ else if (vec >= 0) /* channel 0 to 31 */
+ {
+ esmREG->ESTATUS1[0U] = 1U << vec;
+ esmGroup1Notification(vec);
+ }
+ else
+ {
+ esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;
+ esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;
+ }
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
-/** @file gio.c \r
-* @brief GIO Driver Implementation File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-#include "ti_drv_gio.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-/** @fn void gioInit(void)\r
-* @brief Initializes the GIO Driver\r
-*\r
-* This function initializes the GIO module and set the GIO ports \r
-* to the inital values.\r
-*/\r
-void gioInit(void)\r
-{\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
- /** bring GIO module out of reset */\r
- gioREG->GCR0 = 1;\r
- gioREG->INTENACLR = 0xFF;\r
- gioREG->LVLCLR = 0xFF; \r
-\r
- /** @b initalise @b Port @b A */\r
-\r
- /** - Port A output values */\r
- gioPORTA->DOUT = 0 /* Bit 0 */\r
- | (0 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (0 << 4) /* Bit 4 */\r
- | (0 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7); /* Bit 7 */\r
-\r
- /** - Port A direction */\r
- gioPORTA->DIR = 0 /* Bit 0 */\r
- | (0 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (0 << 4) /* Bit 4 */\r
- | (0 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7); /* Bit 7 */\r
-\r
- /** - Port A open drain enable */\r
- gioPORTA->PDR = 0 /* Bit 0 */\r
- | (0 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (0 << 4) /* Bit 4 */\r
- | (0 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7); /* Bit 7 */\r
-\r
- /** - Port A pullup / pulldown selection */\r
- gioPORTA->PSL = 0 /* Bit 0 */\r
- | (0 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (0 << 4) /* Bit 4 */\r
- | (0 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7); /* Bit 7 */\r
-\r
- /** - Port A pullup / pulldown enable*/\r
- gioPORTA->PULDIS = 0 /* Bit 0 */\r
- | (0 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (0 << 4) /* Bit 4 */\r
- | (0 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7); /* Bit 7 */\r
-\r
- /** @b initalise @b Port @b B */\r
-\r
- /** - Port B output values */\r
- gioPORTB->DOUT = 0 /* Bit 0 */\r
- | (0 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (0 << 4) /* Bit 4 */\r
- | (0 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7); /* Bit 7 */\r
-\r
- /** - Port B direction */\r
- gioPORTB->DIR = 1 /* Bit 0 */\r
- | (1 << 1) /* Bit 1 */\r
- | (1 << 2) /* Bit 2 */\r
- | (1 << 3) /* Bit 3 */\r
- | (1 << 4) /* Bit 4 */\r
- | (1 << 5) /* Bit 5 */\r
- | (1 << 6) /* Bit 6 */\r
- | (1 << 7); /* Bit 7 */\r
-\r
- /** - Port B open drain enable */\r
- gioPORTB->PDR = 1 /* Bit 0 */\r
- | (1 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (1 << 4) /* Bit 4 */\r
- | (1 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7); /* Bit 7 */\r
-\r
- /** - Port B pullup / pulldown selection */\r
- gioPORTB->PSL = 0 /* Bit 0 */\r
- | (0 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (0 << 4) /* Bit 4 */\r
- | (0 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7); /* Bit 7 */\r
-\r
- /** - Port B pullup / pulldown enable*/\r
- gioPORTB->PULDIS = 1 /* Bit 0 */\r
- | (1 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (1 << 4) /* Bit 4 */\r
- | (1 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7); /* Bit 7 */\r
-\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-\r
- /** @b initalise @b interrupts */\r
-\r
- /** - interrupt polarity */\r
- gioREG->POL = 0 /* Bit 0 */\r
- | (0 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (0 << 4) /* Bit 4 */\r
- | (0 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7) /* Bit 7 */\r
-\r
- | (0 << 8) /* Bit 8 */\r
- | (0 << 9) /* Bit 9 */\r
- | (0 << 10) /* Bit 10 */\r
- | (0 << 11) /* Bit 11 */\r
- | (0 << 12) /* Bit 12 */\r
- | (0 << 13) /* Bit 13 */\r
- | (0 << 14) /* Bit 14 */\r
- | (0 << 15);/* Bit 15 */\r
-\r
-\r
- /** - interrupt level */\r
- gioREG->LVLSET = 0 /* Bit 0 */\r
- | (0 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (0 << 4) /* Bit 4 */\r
- | (0 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7) /* Bit 7 */\r
-\r
- | (0 << 8) /* Bit 8 */\r
- | (0 << 9) /* Bit 9 */\r
- | (0 << 10) /* Bit 10 */\r
- | (0 << 11) /* Bit 11 */\r
- | (0 << 12) /* Bit 12 */\r
- | (0 << 13) /* Bit 13 */\r
- | (0 << 14) /* Bit 14 */\r
- | (0 << 15);/* Bit 15 */\r
-\r
- \r
-\r
-\r
- /** - clear all pending interrupts */\r
- gioREG->FLG = 0xFF;\r
-\r
- /** - enable interrupts */\r
- gioREG->INTENASET = 0 /* Bit 0 */\r
- | (0 << 1) /* Bit 1 */\r
- | (0 << 2) /* Bit 2 */\r
- | (0 << 3) /* Bit 3 */\r
- | (0 << 4) /* Bit 4 */\r
- | (0 << 5) /* Bit 5 */\r
- | (0 << 6) /* Bit 6 */\r
- | (0 << 7) /* Bit 7 */\r
-\r
- | (0 << 8) /* Bit 8 */\r
- | (0 << 9) /* Bit 9 */\r
- | (0 << 10) /* Bit 10 */\r
- | (0 << 11) /* Bit 11 */\r
- | (0 << 12) /* Bit 12 */\r
- | (0 << 13) /* Bit 13 */\r
- | (0 << 14) /* Bit 14 */\r
- | (0 << 15);/* Bit 15 */\r
-\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void gioSetDirection(gioPORT_t *port, uint32_t dir)\r
-* @brief Set Port Direction\r
-* @param[in] port pointer to GIO port:\r
-* - gioPORTA: PortA pointer\r
-* - gioPORTB: PortB pointer\r
-* @param[in] dir value to write to DIR register\r
-*\r
-* Set the direction of GIO pins at runtime.\r
-*/\r
-void gioSetDirection(gioPORT_t *port, uint32_t dir)\r
-{\r
- port->DIR = dir;\r
-}\r
-\r
-\r
-/** @fn void gioSetBit(gioPORT_t *port, uint32_t bit, uint32_t value)\r
-* @brief Write Bit\r
-* @param[in] port pointer to GIO port:\r
-* - gioPORTA: PortA pointer\r
-* - gioPORTB: PortB pointer\r
-* @param[in] bit number 0-7 that specifies the bit to be written to.\r
-* - 0: LSB\r
-* - 7: MSB\r
-* @param[in] value binrary value to write to bit\r
-*\r
-* Writes a value to the specified pin of the given GIO port\r
-*/\r
-void gioSetBit(gioPORT_t *port, uint32_t bit, uint32_t value)\r
-{\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
-\r
- if (value != 0)\r
- {\r
- port->DSET = 1 << bit;\r
- }\r
- else\r
- {\r
- port->DCLR = 1 << bit;\r
- }\r
-}\r
-\r
-\r
-/** @fn void gioSetPort(gioPORT_t *port, uint32_t value)\r
-* @brief Write Port Value\r
-* @param[in] port pointer to GIO port:\r
-* - gioPORTA: PortA pointer\r
-* - gioPORTB: PortB pointer\r
-* @param[in] value value to write to port\r
-*\r
-* Writes a value to all pin of a given GIO port\r
-*/\r
-void gioSetPort(gioPORT_t *port, uint32_t value)\r
-{\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
-\r
- port->DOUT = value;\r
-\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-\r
-/** @fn uint32_t gioGetBit(gioPORT_t *port, uint32_t bit)\r
-* @brief Read Bit\r
-* @param[in] port pointer to GIO port:\r
-* - gioPORTA: PortA pointer\r
-* - gioPORTB: PortB pointer\r
-* @param[in] bit number 0-7 that specifies the bit to be written to.\r
-* - 0: LSB\r
-* - 7: MSB\r
-*\r
-* Reads a the current value from the specified pin of the given GIO port\r
-*/\r
-uint32_t gioGetBit(gioPORT_t *port, uint32_t bit)\r
-{\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
-\r
- return (port->DIN >> bit) & 1U;\r
-}\r
-\r
-\r
-/** @fn uint32_t gioGetPort(gioPORT_t *port)\r
-* @brief Read Port Value\r
-* @param[in] port pointer to GIO port:\r
-* - gioPORTA: PortA pointer\r
-* - gioPORTB: PortB pointer\r
-*\r
-* Reads a the current value of a given GIO port\r
-*/\r
-uint32_t gioGetPort(gioPORT_t *port)\r
-{\r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
-\r
- return port->DIN;\r
-}\r
-\r
-/** @fn void gioToggleBit(gioPORT_t *port, uint32_t bit)\r
-* @brief Write Bit\r
-* @param[in] port pointer to GIO port:\r
-* - gioPORTA: PortA pointer\r
-* - gioPORTB: PortB pointer\r
-* @param[in] bit number 0-7 that specifies the bit to be written to.\r
-* - 0: LSB\r
-* - 7: MSB\r
-*\r
-* Toggle a value to the specified pin of the given GIO port\r
-*/\r
-void gioToggleBit(gioPORT_t *port, uint32_t bit)\r
-{\r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
-\r
- if ((port->DIN & (1 << bit)) != 0)\r
- {\r
- port->DCLR = 1 << bit;\r
- }\r
- else\r
- {\r
- port->DSET = 1 << bit;\r
- }\r
-}\r
-\r
-/** @fn void gioEnableNotification(uint32_t bit)\r
-* @brief Enable Interrupt\r
-* @param[in] bit interrupt pin to enable\r
-* - 0: LSB\r
-* - 7: MSB\r
-*\r
-* Enables an innterrupt pin of PortA\r
-*/\r
-void gioEnableNotification(uint32_t bit)\r
-{\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
-\r
- gioREG->INTENASET = 1 << bit;\r
-}\r
-\r
-\r
-/** @fn void gioDisableNotification(uint32_t bit)\r
-* @brief Disable Interrupt\r
-* @param[in] bit interrupt pin to enable\r
-* - 0: LSB\r
-* - 7: MSB\r
-*\r
-* Disables an innterrupt pin of PortA\r
-*/\r
-void gioDisableNotification(uint32_t bit)\r
-{\r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
-\r
- gioREG->INTENACLR = 1 << bit;\r
-}\r
-\r
-\r
-/** @fn void gioHighLevelInterrupt(void)\r
-* @brief GIO Interrupt Handler\r
-*\r
-* High Level Interrupt handler for GIO pin interrupt \r
-*\r
-*/\r
-#pragma INTERRUPT(gioHighLevelInterrupt, IRQ)\r
-\r
-void gioHighLevelInterrupt(void)\r
-{\r
- int offset = gioREG->OFFSET0 - 1U;\r
-\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
-\r
- if (offset >= 0)\r
- {\r
- gioNotification(offset);\r
- }\r
-\r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-\r
-/** @fn void gioLowLevelInterrupt(void)\r
-* @brief GIO Interrupt Handler\r
-*\r
-* Low Level Interrupt handler for GIO pin interrupt \r
-*\r
-*/\r
-#pragma INTERRUPT(gioLowLevelInterrupt, IRQ)\r
-\r
-void gioLowLevelInterrupt(void)\r
-{\r
- int offset = gioREG->OFFSET1 - 1U;\r
-\r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
-\r
- if (offset >= 0)\r
- {\r
- gioNotification(offset);\r
- }\r
-\r
-/* USER CODE BEGIN (16) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-\r
-\r
+/** @file gio.c
+* @brief GIO Driver Implementation File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "ti_drv_gio.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void gioInit(void)
+* @brief Initializes the GIO Driver
+*
+* This function initializes the GIO module and set the GIO ports
+* to the inital values.
+*/
+void gioInit(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+ /** bring GIO module out of reset */
+ gioREG->GCR0 = 1;
+ gioREG->INTENACLR = 0xFF;
+ gioREG->LVLCLR = 0xFF;
+
+ /** @b initalise @b Port @b A */
+
+ /** - Port A output values */
+ gioPORTA->DOUT = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port A direction */
+ gioPORTA->DIR = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port A open drain enable */
+ gioPORTA->PDR = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port A pullup / pulldown selection */
+ gioPORTA->PSL = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port A pullup / pulldown enable*/
+ gioPORTA->PULDIS = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** @b initalise @b Port @b B */
+
+ /** - Port B output values */
+ gioPORTB->DOUT = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port B direction */
+ gioPORTB->DIR = 1 /* Bit 0 */
+ | (1 << 1) /* Bit 1 */
+ | (1 << 2) /* Bit 2 */
+ | (1 << 3) /* Bit 3 */
+ | (1 << 4) /* Bit 4 */
+ | (1 << 5) /* Bit 5 */
+ | (1 << 6) /* Bit 6 */
+ | (1 << 7); /* Bit 7 */
+
+ /** - Port B open drain enable */
+ gioPORTB->PDR = 1 /* Bit 0 */
+ | (1 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (1 << 4) /* Bit 4 */
+ | (1 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port B pullup / pulldown selection */
+ gioPORTB->PSL = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port B pullup / pulldown enable*/
+ gioPORTB->PULDIS = 1 /* Bit 0 */
+ | (1 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (1 << 4) /* Bit 4 */
+ | (1 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+ /** @b initalise @b interrupts */
+
+ /** - interrupt polarity */
+ gioREG->POL = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7) /* Bit 7 */
+
+ | (0 << 8) /* Bit 8 */
+ | (0 << 9) /* Bit 9 */
+ | (0 << 10) /* Bit 10 */
+ | (0 << 11) /* Bit 11 */
+ | (0 << 12) /* Bit 12 */
+ | (0 << 13) /* Bit 13 */
+ | (0 << 14) /* Bit 14 */
+ | (0 << 15);/* Bit 15 */
+
+
+ /** - interrupt level */
+ gioREG->LVLSET = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7) /* Bit 7 */
+
+ | (0 << 8) /* Bit 8 */
+ | (0 << 9) /* Bit 9 */
+ | (0 << 10) /* Bit 10 */
+ | (0 << 11) /* Bit 11 */
+ | (0 << 12) /* Bit 12 */
+ | (0 << 13) /* Bit 13 */
+ | (0 << 14) /* Bit 14 */
+ | (0 << 15);/* Bit 15 */
+
+
+
+
+ /** - clear all pending interrupts */
+ gioREG->FLG = 0xFF;
+
+ /** - enable interrupts */
+ gioREG->INTENASET = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7) /* Bit 7 */
+
+ | (0 << 8) /* Bit 8 */
+ | (0 << 9) /* Bit 9 */
+ | (0 << 10) /* Bit 10 */
+ | (0 << 11) /* Bit 11 */
+ | (0 << 12) /* Bit 12 */
+ | (0 << 13) /* Bit 13 */
+ | (0 << 14) /* Bit 14 */
+ | (0 << 15);/* Bit 15 */
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+
+/** @fn void gioSetDirection(gioPORT_t *port, uint32_t dir)
+* @brief Set Port Direction
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] dir value to write to DIR register
+*
+* Set the direction of GIO pins at runtime.
+*/
+void gioSetDirection(gioPORT_t *port, uint32_t dir)
+{
+ port->DIR = dir;
+}
+
+
+/** @fn void gioSetBit(gioPORT_t *port, uint32_t bit, uint32_t value)
+* @brief Write Bit
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] bit number 0-7 that specifies the bit to be written to.
+* - 0: LSB
+* - 7: MSB
+* @param[in] value binrary value to write to bit
+*
+* Writes a value to the specified pin of the given GIO port
+*/
+void gioSetBit(gioPORT_t *port, uint32_t bit, uint32_t value)
+{
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+ if (value != 0)
+ {
+ port->DSET = 1 << bit;
+ }
+ else
+ {
+ port->DCLR = 1 << bit;
+ }
+}
+
+
+/** @fn void gioSetPort(gioPORT_t *port, uint32_t value)
+* @brief Write Port Value
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] value value to write to port
+*
+* Writes a value to all pin of a given GIO port
+*/
+void gioSetPort(gioPORT_t *port, uint32_t value)
+{
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+ port->DOUT = value;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+}
+
+
+/** @fn uint32_t gioGetBit(gioPORT_t *port, uint32_t bit)
+* @brief Read Bit
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] bit number 0-7 that specifies the bit to be written to.
+* - 0: LSB
+* - 7: MSB
+*
+* Reads a the current value from the specified pin of the given GIO port
+*/
+uint32_t gioGetBit(gioPORT_t *port, uint32_t bit)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ return (port->DIN >> bit) & 1U;
+}
+
+
+/** @fn uint32_t gioGetPort(gioPORT_t *port)
+* @brief Read Port Value
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+*
+* Reads a the current value of a given GIO port
+*/
+uint32_t gioGetPort(gioPORT_t *port)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+ return port->DIN;
+}
+
+/** @fn void gioToggleBit(gioPORT_t *port, uint32_t bit)
+* @brief Write Bit
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] bit number 0-7 that specifies the bit to be written to.
+* - 0: LSB
+* - 7: MSB
+*
+* Toggle a value to the specified pin of the given GIO port
+*/
+void gioToggleBit(gioPORT_t *port, uint32_t bit)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+ if ((port->DIN & (1 << bit)) != 0)
+ {
+ port->DCLR = 1 << bit;
+ }
+ else
+ {
+ port->DSET = 1 << bit;
+ }
+}
+
+/** @fn void gioEnableNotification(uint32_t bit)
+* @brief Enable Interrupt
+* @param[in] bit interrupt pin to enable
+* - 0: LSB
+* - 7: MSB
+*
+* Enables an innterrupt pin of PortA
+*/
+void gioEnableNotification(uint32_t bit)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ gioREG->INTENASET = 1 << bit;
+}
+
+
+/** @fn void gioDisableNotification(uint32_t bit)
+* @brief Disable Interrupt
+* @param[in] bit interrupt pin to enable
+* - 0: LSB
+* - 7: MSB
+*
+* Disables an innterrupt pin of PortA
+*/
+void gioDisableNotification(uint32_t bit)
+{
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+ gioREG->INTENACLR = 1 << bit;
+}
+
+
+/** @fn void gioHighLevelInterrupt(void)
+* @brief GIO Interrupt Handler
+*
+* High Level Interrupt handler for GIO pin interrupt
+*
+*/
+#pragma INTERRUPT(gioHighLevelInterrupt, IRQ)
+
+void gioHighLevelInterrupt(void)
+{
+ int offset = gioREG->OFFSET0 - 1U;
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ if (offset >= 0)
+ {
+ gioNotification(offset);
+ }
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+}
+
+
+/** @fn void gioLowLevelInterrupt(void)
+* @brief GIO Interrupt Handler
+*
+* Low Level Interrupt handler for GIO pin interrupt
+*
+*/
+#pragma INTERRUPT(gioLowLevelInterrupt, IRQ)
+
+void gioLowLevelInterrupt(void)
+{
+ int offset = gioREG->OFFSET1 - 1U;
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ if (offset >= 0)
+ {
+ gioNotification(offset);
+ }
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+}
+
+
+
-/** @file het.c \r
-* @brief HET Driver Implementation File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-#include "ti_drv_het.h"\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Global variables */\r
-\r
-static const uint32_t s_het1pwmPolarity[] =\r
-{\r
- 3U,\r
- 3U,\r
- 3U,\r
- 3U,\r
- 3U,\r
- 3U,\r
- 3U,\r
- 3U,\r
-};\r
-\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Default Program */\r
-\r
-/** @var const hetINSTRUCTION_t het1PROGRAM[]\r
-* @brief Default Program\r
-*\r
-* Het program running after initialization.\r
-*/\r
-\r
-static const hetINSTRUCTION_t het1PROGRAM[58] =\r
-{\r
- /* CNT: Timebase\r
- * - Instruction = 0\r
- * - Next instruction = 1\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = na\r
- * - Reg = T\r
- */\r
- {\r
- /* Program */\r
- 0x00002C80U,\r
- /* Control */\r
- 0x01FFFFFFU,\r
- /* Data */\r
- 0xFFFFFF80U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PWCNT: PWM 0 -> Duty Cycle\r
- * - Instruction = 1\r
- * - Next instruction = 2\r
- * - Conditional next instruction = 2\r
- * - Interrupt = 1\r
- * - Pin = 7\r
- */\r
- {\r
- /* Program */\r
- 0x000055C0U,\r
- /* Control */\r
- (0x00004006U | (7U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* DJZ: PWM 0 -> Period\r
- * - Instruction = 2\r
- * - Next instruction = 3\r
- * - Conditional next instruction = 41\r
- * - Interrupt = 2\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x00007480U,\r
- /* Control */\r
- 0x00052006U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PWCNT: PWM 1 -> Duty Cycle\r
- * - Instruction = 3\r
- * - Next instruction = 4\r
- * - Conditional next instruction = 4\r
- * - Interrupt = 3\r
- * - Pin = 16\r
- */\r
- {\r
- /* Program */\r
- 0x000095C0U,\r
- /* Control */\r
- (0x00008006U | (16U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* DJZ: PWM 1 -> Period\r
- * - Instruction = 4\r
- * - Next instruction = 5\r
- * - Conditional next instruction = 43\r
- * - Interrupt = 4\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x0000B480U,\r
- /* Control */\r
- 0x00056006U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PWCNT: PWM 2 -> Duty Cycle\r
- * - Instruction = 5\r
- * - Next instruction = 6\r
- * - Conditional next instruction = 6\r
- * - Interrupt = 5\r
- * - Pin = 18\r
- */\r
- {\r
- /* Program */\r
- 0x0000D5C0U,\r
- /* Control */\r
- (0x0000C006U | (18U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* DJZ: PWM 2 -> Period\r
- * - Instruction = 6\r
- * - Next instruction = 7\r
- * - Conditional next instruction = 45\r
- * - Interrupt = 6\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x0000F480U,\r
- /* Control */\r
- 0x0005A006U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PWCNT: PWM 3 -> Duty Cycle\r
- * - Instruction = 7\r
- * - Next instruction = 8\r
- * - Conditional next instruction = 8\r
- * - Interrupt = 7\r
- * - Pin = 20\r
- */\r
- {\r
- /* Program */\r
- 0x000115C0U,\r
- /* Control */\r
- (0x00010006U | (20U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* DJZ: PWM 3 -> Period\r
- * - Instruction = 8\r
- * - Next instruction = 9\r
- * - Conditional next instruction = 47\r
- * - Interrupt = 8\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x00013480U,\r
- /* Control */\r
- 0x0005E006U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PWCNT: PWM 4 -> Duty Cycle\r
- * - Instruction = 9\r
- * - Next instruction = 10\r
- * - Conditional next instruction = 10\r
- * - Interrupt = 9\r
- * - Pin = 22\r
- */\r
- {\r
- /* Program */\r
- 0x000155C0U,\r
- /* Control */\r
- (0x00014006U | (22U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* DJZ: PWM 4 -> Period\r
- * - Instruction = 10\r
- * - Next instruction = 11\r
- * - Conditional next instruction = 49\r
- * - Interrupt = 10\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x00017480U,\r
- /* Control */\r
- 0x00062006U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PWCNT: PWM 5 -> Duty Cycle\r
- * - Instruction = 11\r
- * - Next instruction = 12\r
- * - Conditional next instruction = 12\r
- * - Interrupt = 11\r
- * - Pin = 25\r
- */\r
- {\r
- /* Program */\r
- 0x000195C0U,\r
- /* Control */\r
- (0x00018006U | (25U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* DJZ: PWM 5 -> Period\r
- * - Instruction = 12\r
- * - Next instruction = 13\r
- * - Conditional next instruction = 51\r
- * - Interrupt = 12\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x0001B480U,\r
- /* Control */\r
- 0x00066006U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PWCNT: PWM 6 -> Duty Cycle\r
- * - Instruction = 13\r
- * - Next instruction = 14\r
- * - Conditional next instruction = 14\r
- * - Interrupt = 13\r
- * - Pin = 29\r
- */\r
- {\r
- /* Program */\r
- 0x0001D5C0U,\r
- /* Control */\r
- (0x0001C006U | (29U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* DJZ: PWM 6 -> Period\r
- * - Instruction = 14\r
- * - Next instruction = 15\r
- * - Conditional next instruction = 53\r
- * - Interrupt = 14\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x0001F480U,\r
- /* Control */\r
- 0x0006A006U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PWCNT: PWM 7 -> Duty Cycle\r
- * - Instruction = 15\r
- * - Next instruction = 16\r
- * - Conditional next instruction = 16\r
- * - Interrupt = 15\r
- * - Pin = 19\r
- */\r
- {\r
- /* Program */\r
- 0x000215C0U,\r
- /* Control */\r
- (0x00020006U | (19U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* DJZ: PWM 7 -> Period\r
- * - Instruction = 16\r
- * - Next instruction = 17\r
- * - Conditional next instruction = 55\r
- * - Interrupt = 16\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x00023480U,\r
- /* Control */\r
- 0x0006E006U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* ECNT: CCU Edge 0\r
- * - Instruction = 17\r
- * - Next instruction = 18\r
- * - Conditional next instruction = 18\r
- * - Interrupt = 17\r
- * - Pin = 9\r
- */\r
- {\r
- /* Program */\r
- 0x00025440U,\r
- /* Control */\r
- (0x00024007U | (9U << 8U) | (1U << 4U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* ECNT: CCU Edge 1\r
- * - Instruction = 18\r
- * - Next instruction = 19\r
- * - Conditional next instruction = 19\r
- * - Interrupt = 18\r
- * - Pin = 11\r
- */\r
- {\r
- /* Program */\r
- 0x00027440U,\r
- /* Control */\r
- (0x00026007U | (11U << 8U) | (1U << 4U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* ECNT: CCU Edge 2\r
- * - Instruction = 19\r
- * - Next instruction = 20\r
- * - Conditional next instruction = 20\r
- * - Interrupt = 19\r
- * - Pin = 13\r
- */\r
- {\r
- /* Program */\r
- 0x00029440U,\r
- /* Control */\r
- (0x00028007U | (13U << 8U) | (1U << 4U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* ECNT: CCU Edge 3\r
- * - Instruction = 20\r
- * - Next instruction = 21\r
- * - Conditional next instruction = 21\r
- * - Interrupt = 20\r
- * - Pin = 15\r
- */\r
- {\r
- /* Program */\r
- 0x0002B440U,\r
- /* Control */\r
- (0x0002A007U | (15U << 8U) | (1U << 4U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* ECNT: CCU Edge 4\r
- * - Instruction = 21\r
- * - Next instruction = 22\r
- * - Conditional next instruction = 22\r
- * - Interrupt = 21\r
- * - Pin = 20\r
- */\r
- {\r
- /* Program */\r
- 0x0002D440U,\r
- /* Control */\r
- (0x0002C007U | (20U << 8U) | (1U << 4U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* ECNT: CCU Edge 5\r
- * - Instruction = 22\r
- * - Next instruction = 23\r
- * - Conditional next instruction = 23\r
- * - Interrupt = 22\r
- * - Pin = 21\r
- */\r
- {\r
- /* Program */\r
- 0x0002F440U,\r
- /* Control */\r
- (0x0002E007U | (21U << 8U) | (1U << 4U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* ECNT: CCU Edge 6\r
- * - Instruction = 23\r
- * - Next instruction = 24\r
- * - Conditional next instruction = 24\r
- * - Interrupt = 23\r
- * - Pin = 22\r
- */\r
- {\r
- /* Program */\r
- 0x00031440U,\r
- /* Control */\r
- (0x00030007U | (22U << 8U) | (1U << 4U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* ECNT: CCU Edge 7\r
- * - Instruction = 24\r
- * - Next instruction = 25\r
- * - Conditional next instruction = 25\r
- * - Interrupt = 24\r
- * - Pin = 23\r
- */\r
- {\r
- /* Program */\r
- 0x00033440U,\r
- /* Control */\r
- (0x00032007U | (23U << 8U) | (1U << 4U)),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Duty 0\r
- * - Instruction = 25\r
- * - Next instruction = 26\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 0\r
- */\r
- {\r
- /* Program */\r
- 0x00034E00U | (0U << 6U) | (0U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Period 0\r
- * - Instruction = 26\r
- * - Next instruction = 27\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 0 + 1\r
- */\r
- {\r
- /* Program */\r
- 0x00036E80U | (0U << 6U) | ((0U) + 1U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Duty 1\r
- * - Instruction = 27\r
- * - Next instruction = 28\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 2\r
- */\r
- {\r
- /* Program */\r
- 0x00038E00U | (0U << 6U) | (2U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Period 1\r
- * - Instruction = 28\r
- * - Next instruction = 29\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 2 + 1\r
- */\r
- {\r
- /* Program */\r
- 0x0003AE80U | (0U << 6U) | ((2U) + 1U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Duty 2\r
- * - Instruction = 29\r
- * - Next instruction = 30\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 4\r
- */\r
- {\r
- /* Program */\r
- 0x0003CE00U | (0U << 6U) | (4U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Period 2\r
- * - Instruction = 30\r
- * - Next instruction = 31\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 4 + 1\r
- */\r
- {\r
- /* Program */\r
- 0x0003EE80U | (0U << 6U) | ((4U) + 1U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Duty 3\r
- * - Instruction = 31\r
- * - Next instruction = 32\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 6\r
- */\r
- {\r
- /* Program */\r
- 0x00040E00U | (0U << 6U) | (6U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Period 3\r
- * - Instruction = 32\r
- * - Next instruction = 33\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 6 + 1\r
- */\r
- {\r
- /* Program */\r
- 0x00042E80U | (0U << 6U) | ((6U) + 1U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Duty 4\r
- * - Instruction = 33\r
- * - Next instruction = 34\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 24\r
- */\r
- {\r
- /* Program */\r
- 0x00044E00U | (0U << 6U) | (24U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Period 4\r
- * - Instruction = 34\r
- * - Next instruction = 35\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 24 + 1\r
- */\r
- {\r
- /* Program */\r
- 0x00046E80U | (0U << 6U) | ((24U) + 1U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Duty 5\r
- * - Instruction = 35\r
- * - Next instruction = 36\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 26\r
- */\r
- {\r
- /* Program */\r
- 0x00048E00U | (0U << 6U) | (26U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Period 5\r
- * - Instruction = 36\r
- * - Next instruction = 37\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 26 + 1\r
- */\r
- {\r
- /* Program */\r
- 0x0004AE80U | (0U << 6U) | ((26U) + 1U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Duty 6\r
- * - Instruction = 37\r
- * - Next instruction = 38\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 28\r
- */\r
- {\r
- /* Program */\r
- 0x0004CE00U | (0U << 6U) | (28U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Period 6\r
- * - Instruction = 38\r
- * - Next instruction = 39\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 28 + 1\r
- */\r
- {\r
- /* Program */\r
- 0x0004EE80U | (0U << 6U) | ((28U) + 1U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Duty 7\r
- * - Instruction = 39\r
- * - Next instruction = 40\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 30\r
- */\r
- {\r
- /* Program */\r
- 0x00050E00U | (0U << 6U) | (30U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* PCNT: Capture Period 7\r
- * - Instruction = 40\r
- * - Next instruction = 57\r
- * - Conditional next instruction = na\r
- * - Interrupt = na\r
- * - Pin = 30 + 1\r
- */\r
- {\r
- /* Program */\r
- 0x00072E80U | (0U << 6U) | ((30U) + 1U),\r
- /* Control */\r
- 0x00000000U,\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 0 -> Duty Cycle Update\r
- * - Instruction = 41\r
- * - Next instruction = 42\r
- * - Conditional next instruction = 2\r
- * - Interrupt = 1\r
- * - Pin = 7\r
- */\r
- {\r
- /* Program */\r
- 0x00054201U,\r
- /* Control */\r
- (0x00004007U | (0U << 22U) | (7U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 48128U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 0 -> Period Update\r
- * - Instruction = 42\r
- * - Next instruction = 3\r
- * - Conditional next instruction = 41\r
- * - Interrupt = 2\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x00006202U,\r
- /* Control */\r
- (0x00052007U),\r
- /* Data */\r
- 159872U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 1 -> Duty Cycle Update\r
- * - Instruction = 43\r
- * - Next instruction = 44\r
- * - Conditional next instruction = 4\r
- * - Interrupt = 3\r
- * - Pin = 16\r
- */\r
- {\r
- /* Program */\r
- 0x00058203U,\r
- /* Control */\r
- (0x00008007U | (0U << 22U) | (16U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 80128U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 1 -> Period Update\r
- * - Instruction = 44\r
- * - Next instruction = 5\r
- * - Conditional next instruction = 43\r
- * - Interrupt = 4\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x0000A204U,\r
- /* Control */\r
- (0x00056007U),\r
- /* Data */\r
- 159872U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 2 -> Duty Cycle Update\r
- * - Instruction = 45\r
- * - Next instruction = 46\r
- * - Conditional next instruction = 6\r
- * - Interrupt = 5\r
- * - Pin = 18\r
- */\r
- {\r
- /* Program */\r
- 0x0005C205U,\r
- /* Control */\r
- (0x0000C007U | (0U << 22U) | (18U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 80128U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 2 -> Period Update\r
- * - Instruction = 46\r
- * - Next instruction = 7\r
- * - Conditional next instruction = 45\r
- * - Interrupt = 6\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x0000E206U,\r
- /* Control */\r
- (0x0005A007U),\r
- /* Data */\r
- 159872U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 3 -> Duty Cycle Update\r
- * - Instruction = 47\r
- * - Next instruction = 48\r
- * - Conditional next instruction = 8\r
- * - Interrupt = 7\r
- * - Pin = 20\r
- */\r
- {\r
- /* Program */\r
- 0x00060207U,\r
- /* Control */\r
- (0x00010007U | (0U << 22U) | (20U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 80128U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 3 -> Period Update\r
- * - Instruction = 48\r
- * - Next instruction = 9\r
- * - Conditional next instruction = 47\r
- * - Interrupt = 8\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x00012208U,\r
- /* Control */\r
- (0x0005E007U),\r
- /* Data */\r
- 159872U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 4 -> Duty Cycle Update\r
- * - Instruction = 49\r
- * - Next instruction = 50\r
- * - Conditional next instruction = 10\r
- * - Interrupt = 9\r
- * - Pin = 22\r
- */\r
- {\r
- /* Program */\r
- 0x00064209U,\r
- /* Control */\r
- (0x00014007U | (0U << 22U) | (22U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 80128U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 4 -> Period Update\r
- * - Instruction = 50\r
- * - Next instruction = 11\r
- * - Conditional next instruction = 49\r
- * - Interrupt = 10\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x0001620AU,\r
- /* Control */\r
- (0x00062007U),\r
- /* Data */\r
- 159872U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 5 -> Duty Cycle Update\r
- * - Instruction = 51\r
- * - Next instruction = 52\r
- * - Conditional next instruction = 12\r
- * - Interrupt = 11\r
- * - Pin = 25\r
- */\r
- {\r
- /* Program */\r
- 0x0006820BU,\r
- /* Control */\r
- (0x00018007U | (0U << 22U) | (25U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 80128U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 5 -> Period Update\r
- * - Instruction = 52\r
- * - Next instruction = 13\r
- * - Conditional next instruction = 51\r
- * - Interrupt = 12\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x0001A20CU,\r
- /* Control */\r
- (0x00066007U),\r
- /* Data */\r
- 159872U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 6 -> Duty Cycle Update\r
- * - Instruction = 53\r
- * - Next instruction = 54\r
- * - Conditional next instruction = 14\r
- * - Interrupt = 13\r
- * - Pin = 29\r
- */\r
- {\r
- /* Program */\r
- 0x0006C20DU,\r
- /* Control */\r
- (0x0001C007U | (0U << 22U) | (29U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 80128U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 6 -> Period Update\r
- * - Instruction = 54\r
- * - Next instruction = 15\r
- * - Conditional next instruction = 53\r
- * - Interrupt = 14\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x0001E20EU,\r
- /* Control */\r
- (0x0006A007U),\r
- /* Data */\r
- 159872U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 7 -> Duty Cycle Update\r
- * - Instruction = 55\r
- * - Next instruction = 56\r
- * - Conditional next instruction = 16\r
- * - Interrupt = 15\r
- * - Pin = 19\r
- */\r
- {\r
- /* Program */\r
- 0x0007020FU,\r
- /* Control */\r
- (0x00020007U | (0U << 22U) | (19U << 8U) | (3U << 3U)),\r
- /* Data */\r
- 80128U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* MOV64: PWM 7 -> Period Update\r
- * - Instruction = 56\r
- * - Next instruction = 17\r
- * - Conditional next instruction = 55\r
- * - Interrupt = 16\r
- * - Pin = na\r
- */\r
- {\r
- /* Program */\r
- 0x00022210U,\r
- /* Control */\r
- (0x0006E007U),\r
- /* Data */\r
- 159872U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
- /* WCAP: Capture timestamp\r
- * - Instruction = 57\r
- * - Next instruction = 0\r
- * - Conditional next instruction = 0\r
- * - Interrupt = na\r
- * - Pin = na\r
- * - Reg = T\r
- */\r
- {\r
- /* Program */\r
- 0x00001600U,\r
- /* Control */\r
- (0x00000004U),\r
- /* Data */\r
- 0x00000000U,\r
- /* Reserved */\r
- 0x00000000U\r
- },\r
-};\r
-\r
-\r
-\r
-/** @fn void hetInit(void)\r
-* @brief Initializes the het Driver\r
-*\r
-* This function initializes the het 1 module.\r
-*/\r
-void hetInit(void)\r
-{\r
- /** @b intalise @b HET */\r
-\r
- /** - Set HET pins default output value */\r
- hetREG1->DOUT = (0U << 31U)\r
- | (0U << 30U)\r
- | (0U << 29U)\r
- | (0U << 28U) \r
- | (0U << 27U) \r
- | (0U << 26U) \r
- | (0U << 25U) \r
- | (0U << 24U) \r
- | (0U << 23U) \r
- | (0U << 22U) \r
- | (0U << 21U) \r
- | (0U << 20U) \r
- | (0U << 19U) \r
- | (0U << 18U) \r
- | (0U << 17U) \r
- | (0U << 16U) \r
- | (0U << 15U) \r
- | (0U << 14U) \r
- | (0U << 13U) \r
- | (0U << 12U) \r
- | (0U << 11U) \r
- | (0U << 10U) \r
- | (0U << 9U)\r
- | (0U << 8U)\r
- | (0U << 7U)\r
- | (0U << 6U)\r
- | (0U << 5U)\r
- | (0U << 4U)\r
- | (0U << 3U)\r
- | (0U << 2U)\r
- | (0U << 1U)\r
- | (0U);\r
-\r
- /** - Set HET pins direction */\r
- hetREG1->DIR = 0x00000000U \r
- | 0x00000000U \r
- | 0x20000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x02000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00400000U \r
- | 0x00000000U \r
- | 0x00100000U \r
- | 0x00000000U \r
- | 0x00040000U \r
- | 0x00000000U \r
- | 0x00010000U \r
- | 0x00000000U \r
- | 0x00004000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000200U\r
- | 0x00000000U\r
- | 0x00000080U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000010U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000002U\r
- | 0x00000000U;\r
-\r
- /** - Set HET pins open drain enable */\r
- hetREG1->PDR = 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Set HET pins pullup/down enable */\r
- hetREG1->PULDIS = 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000080U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000010U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Set HET pins pullup/down select */\r
- hetREG1->PSL = 0x80000000U \r
- | 0x40000000U \r
- | 0x20000000U \r
- | 0x10000000U \r
- | 0x08000000U \r
- | 0x04000000U \r
- | 0x02000000U \r
- | 0x01000000U \r
- | 0x00800000U \r
- | 0x00400000U \r
- | 0x00200000U \r
- | 0x00100000U \r
- | 0x00080000U \r
- | 0x00040000U \r
- | 0x00020000U \r
- | 0x00010000U \r
- | 0x00008000U \r
- | 0x00004000U \r
- | 0x00002000U \r
- | 0x00001000U \r
- | 0x00000800U \r
- | 0x00000400U \r
- | 0x00000200U\r
- | 0x00000100U\r
- | 0x00000000U\r
- | 0x00000040U\r
- | 0x00000020U\r
- | 0x00000000U\r
- | 0x00000008U\r
- | 0x00000004U\r
- | 0x00000002U\r
- | 0x00000001U;\r
-\r
- /** - Set HET pins high resolution share */\r
- hetREG1->HRSH = 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Set HET pins AND share */\r
- hetREG1->AND = 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U; \r
-\r
- /** - Set HET pins XOR share */\r
- hetREG1->XOR = 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U \r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
- \r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
- /** - Setup prescaler values\r
- * - Loop resolution prescaler\r
- * - High resolution prescaler\r
- */\r
- hetREG1->PFR = (6U << 8U)\r
- | (0U);\r
- \r
- /** - Fill HET RAM with opcodes and Data */\r
- memcpy((void *)hetRAM1, (const void *)het1PROGRAM, sizeof(het1PROGRAM));\r
-\r
- /** - Setup interrupt priority level \r
- * - PWM 0 end of duty level\r
- * - PWM 0 end of period level\r
- * - PWM 1 end of duty level\r
- * - PWM 1 end of period level\r
- * - PWM 2 end of duty level\r
- * - PWM 2 end of period level\r
- * - PWM 3 end of duty level\r
- * - PWM 3 end of period level\r
- * - PWM 4 end of duty level\r
- * - PWM 4 end of period level\r
- * - PWM 5 end of duty level\r
- * - PWM 5 end of period level\r
- * - PWM 6 end of duty level\r
- * - PWM 6 end of period level\r
- * - PWM 7 end of duty level\r
- * - PWM 7 end of period level\r
-\r
- * - CCU Edge Detection 0 level\r
- * - CCU Edge Detection 1 level\r
- * - CCU Edge Detection 2 level\r
- * - CCU Edge Detection 3 level\r
- * - CCU Edge Detection 4 level\r
- * - CCU Edge Detection 5 level\r
- * - CCU Edge Detection 6 level\r
- * - CCU Edge Detection 7 level\r
- */\r
- hetREG1->PRY = 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
- \r
- /** - Enable interrupts \r
- * - PWM 0 end of duty\r
- * - PWM 0 end of period\r
- * - PWM 1 end of duty\r
- * - PWM 1 end of period\r
- * - PWM 2 end of duty\r
- * - PWM 2 end of period\r
- * - PWM 3 end of duty\r
- * - PWM 3 end of period\r
- * - PWM 4 end of duty\r
- * - PWM 4 end of period\r
- * - PWM 5 end of duty\r
- * - PWM 5 end of period\r
- * - PWM 6 end of duty\r
- * - PWM 6 end of period\r
- * - PWM 7 end of duty\r
- * - PWM 7 end of period\r
- * - CCU Edge Detection 0\r
- * - CCU Edge Detection 1\r
- * - CCU Edge Detection 2\r
- * - CCU Edge Detection 3\r
- * - CCU Edge Detection 4\r
- * - CCU Edge Detection 5\r
- * - CCU Edge Detection 6\r
- * - CCU Edge Detection 7\r
- */\r
- hetREG1->INTENAC = 0xFFFFFFFFU;\r
- hetREG1->INTENAS = 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- \r
- /** - Parity control register \r
- * - Enable/Disable Parity check\r
- */\r
- hetREG1->PCREG = 0x00000005U;\r
- \r
- /** - Setup control register \r
- * - Enable output buffers\r
- * - Ignore software breakpoints\r
- * - Master mode\r
- * - Enable HET\r
- */\r
- hetREG1->GCR = 0x01030001U;\r
- /** @note This function has to be called before the driver can be used.\n\r
- * This function has to be executed in priviledged mode.\n\r
- */\r
-\r
-\r
-\r
-}\r
-\r
-/** @fn void pwmStart( hetRAMBASE_t * hetRAM, uint32_t pwm)\r
-* @brief Start pwm signal\r
-* @param[in] hetRAM Pointer to HET RAM:\r
-* - hetRAM1: HET1 RAM pointer\r
-* - hetRAM2: HET2 RAM pointer\r
-* @param[in] pwm Pwm signal:\r
-* - pwm0: Pwm 0\r
-* - pwm1: Pwm 1\r
-* - pwm2: Pwm 2\r
-* - pwm3: Pwm 3\r
-* - pwm4: Pwm 4\r
-* - pwm5: Pwm 5\r
-* - pwm6: Pwm 6\r
-* - pwm7: Pwm 7\r
-*\r
-* Start the given pwm signal\r
-*/\r
-\r
-void pwmStart( hetRAMBASE_t * hetRAM, uint32_t pwm)\r
-{\r
- \r
- hetRAM->Instruction[(pwm << 1U) + 41U].Control |= 0x00400000U;\r
-}\r
-\r
-\r
-/** @fn void pwmStop( hetRAMBASE_t * hetRAM, uint32_t pwm)\r
-* @brief Stop pwm signal\r
-* @param[in] hetRAM Pointer to HET RAM:\r
-* - hetRAM1: HET1 RAM pointer\r
-* - hetRAM2: HET2 RAM pointer\r
-* @param[in] pwm Pwm signal:\r
-* - pwm0: Pwm 0\r
-* - pwm1: Pwm 1\r
-* - pwm2: Pwm 2\r
-* - pwm3: Pwm 3\r
-* - pwm4: Pwm 4\r
-* - pwm5: Pwm 5\r
-* - pwm6: Pwm 6\r
-* - pwm7: Pwm 7\r
-*\r
-* Stop the given pwm signal\r
-*/\r
-\r
-void pwmStop( hetRAMBASE_t * hetRAM, uint32_t pwm)\r
-{\r
- hetRAM->Instruction[(pwm << 1U) + 41U].Control &= ~0x00400000U;\r
-}\r
-\r
-\r
-/** @fn void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32_t pwm, uint32_t duty)\r
-* @brief Set duty cycle\r
-* @param[in] hetRAM Pointer to HET RAM:\r
-* - hetRAM1: HET1 RAM pointer\r
-* - hetRAM2: HET2 RAM pointer\r
-* @param[in] pwm Pwm signal:\r
-* - pwm0: Pwm 0\r
-* - pwm1: Pwm 1\r
-* - pwm2: Pwm 2\r
-* - pwm3: Pwm 3\r
-* - pwm4: Pwm 4\r
-* - pwm5: Pwm 5\r
-* - pwm6: Pwm 6\r
-* - pwm7: Pwm 7\r
-* @param[in] duty duty cycle in %.\r
-*\r
-* Sets a new duty cycle on the given pwm signal\r
-*/\r
-\r
-void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32_t pwm, uint32_t duty)\r
-{\r
- uint32_t action;\r
- uint32_t pwmPolarity;\r
- double period = hetRAM->Instruction[(pwm << 1U) + 42U].Data + 128U;\r
- if(hetRAM == hetRAM1)\r
- {\r
- pwmPolarity = s_het1pwmPolarity[pwm];\r
- }\r
- else\r
- {\r
- }\r
- if (duty == 0U)\r
- {\r
- action = (pwmPolarity == 3U) ? 0U : 2U;\r
- }\r
- else if (duty >= 100U)\r
- {\r
- action = (pwmPolarity == 3U) ? 2U : 0U;\r
- }\r
- else\r
- {\r
- action = pwmPolarity;\r
- }\r
- \r
- hetRAM->Instruction[(pwm << 1U) + 41U].Control = (hetRAM->Instruction[(pwm << 1U) + 41U].Control & ~0x18U) | (action << 3U);\r
- hetRAM->Instruction[(pwm << 1U) + 41U].Data = (uint32_t)(period * duty / 100.0) + 128U;\r
-}\r
-\r
-\r
-/** @fn void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32_t pwm, hetSIGNAL_t signal)\r
-* @brief Set period\r
-* @param[in] hetRAM Pointer to HET RAM:\r
-* - hetRAM1: HET1 RAM pointer\r
-* - hetRAM2: HET2 RAM pointer\r
-* @param[in] pwm Pwm signal:\r
-* - pwm0: Pwm 0\r
-* - pwm1: Pwm 1\r
-* - pwm2: Pwm 2\r
-* - pwm3: Pwm 3\r
-* - pwm4: Pwm 4\r
-* - pwm5: Pwm 5\r
-* - pwm6: Pwm 6\r
-* - pwm7: Pwm 7\r
-* @param[in] signal signal \r
- - duty cycle in %.\r
-* - period period in us.\r
-*\r
-* Sets a new pwm signal\r
-*/\r
-\r
-void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32_t pwm, hetSIGNAL_t signal)\r
-{\r
- uint32_t action;\r
- uint32_t period;\r
- uint32_t pwmPolarity;\r
- \r
- if(hetRAM == hetRAM1)\r
- {\r
- period = (uint32_t)(signal.period * 1000.0 / 800.000) << 7U;\r
- pwmPolarity = s_het1pwmPolarity[pwm];\r
- }\r
- else\r
- {\r
- }\r
- if (signal.duty == 0U)\r
- {\r
- action = (pwmPolarity == 3U) ? 0U : 2U;\r
- }\r
- else if (signal.duty >= 100U)\r
- {\r
- action = (pwmPolarity == 3U) ? 2U : 0U;\r
- }\r
- else\r
- {\r
- action = pwmPolarity;\r
- }\r
- \r
- hetRAM->Instruction[(pwm << 1U) + 41U].Control = (hetRAM->Instruction[(pwm << 1U) + 41U].Control & ~0x18U) | (action << 3U);\r
- hetRAM->Instruction[(pwm << 1U) + 41U].Data = (uint32_t)(period * signal.duty / 100.0) + 128U;\r
- hetRAM->Instruction[(pwm << 1U) + 42U].Data = period - 128U;\r
-}\r
-\r
-\r
-/** @fn hetSIGNAL_t pwmGetSignal(hetRAMBASE_t * hetRAM, uint32_t pwm)\r
-* @brief Get duty cycle\r
-* @param[in] hetRAM Pointer to HET RAM:\r
-* - hetRAM1: HET1 RAM pointer\r
-* - hetRAM2: HET2 RAM pointer\r
-* @param[in] pwm Pwm signal:\r
-* - pwm0: Pwm 0\r
-* - pwm1: Pwm 1\r
-* - pwm2: Pwm 2\r
-* - pwm3: Pwm 3\r
-* - pwm4: Pwm 4\r
-* - pwm5: Pwm 5\r
-* - pwm6: Pwm 6\r
-* - pwm7: Pwm 7\r
-*\r
-* Gets current signal of the given pwm signal.\r
-*/\r
-\r
-hetSIGNAL_t pwmGetSignal(hetRAMBASE_t * hetRAM, uint32_t pwm)\r
-{\r
- hetSIGNAL_t signal; \r
- uint32_t duty = hetRAM->Instruction[(pwm << 1U) + 41U].Data - 128;\r
- uint32_t period = hetRAM->Instruction[(pwm << 1U) + 42U].Data + 128;\r
- \r
- signal.duty = (uint32_t)(100.0 * duty / period);\r
-\r
- if(hetRAM == hetRAM1)\r
- {\r
- signal.period = (period >> 7U) * 800.000 / 1000.0;\r
- }\r
- else\r
- {\r
- signal.period = (period >> 7U) * 800.000 / 1000.0;\r
- }\r
- return signal;\r
-}\r
-\r
-\r
-/** @fn void pwmEnableNotification(hetBASE_t * hetREG, uint32_t pwm, uint32_t notification)\r
-* @brief Enable pwm notification\r
-* @param[in] hetREG Pointer to HET Module:\r
-* - hetREG1: HET1 Module pointer\r
-* - hetREG2: HET2 Module pointer\r
-* @param[in] pwm Pwm signal:\r
-* - pwm0: Pwm 0\r
-* - pwm1: Pwm 1\r
-* - pwm2: Pwm 2\r
-* - pwm3: Pwm 3\r
-* - pwm4: Pwm 4\r
-* - pwm5: Pwm 5\r
-* - pwm6: Pwm 6\r
-* - pwm7: Pwm 7\r
-* @param[in] notification Pwm notification:\r
-* - pwmEND_OF_DUTY: Notification on end of duty\r
-* - pwmEND_OF_PERIOD: Notification on end of end period\r
-* - pwmEND_OF_BOTH: Notification on end of both duty and period\r
-*/\r
-\r
-void pwmEnableNotification(hetBASE_t * hetREG, uint32_t pwm, uint32_t notification)\r
-{\r
- hetREG->FLG = notification << (pwm << 1U);\r
- hetREG->INTENAS = notification << (pwm << 1U);\r
-}\r
-\r
-\r
-/** @fn void pwmDisableNotification(hetBASE_t * hetREG, uint32_t pwm, uint32_t notification)\r
-* @brief Enable pwm notification\r
-* @param[in] hetREG Pointer to HET Module:\r
-* - hetREG1: HET1 Module pointer\r
-* - hetREG2: HET2 Module pointer\r
-* @param[in] pwm Pwm signal:\r
-* - pwm0: Pwm 0\r
-* - pwm1: Pwm 1\r
-* - pwm2: Pwm 2\r
-* - pwm3: Pwm 3\r
-* - pwm4: Pwm 4\r
-* - pwm5: Pwm 5\r
-* - pwm6: Pwm 6\r
-* - pwm7: Pwm 7\r
-* @param[in] notification Pwm notification:\r
-* - pwmEND_OF_DUTY: Notification on end of duty\r
-* - pwmEND_OF_PERIOD: Notification on end of end period\r
-* - pwmEND_OF_BOTH: Notification on end of both duty and period\r
-*/\r
-\r
-void pwmDisableNotification(hetBASE_t * hetREG, uint32_t pwm, uint32_t notification)\r
-{\r
- hetREG->INTENAC = notification << (pwm << 1U);\r
-}\r
-\r
-\r
-/** @fn void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32_t edge)\r
-* @brief Resets edge counter to 0\r
-* @param[in] hetRAM Pointer to HET RAM:\r
-* - hetRAM1: HET1 RAM pointer\r
-* - hetRAM2: HET2 RAM pointer\r
-* @param[in] edge Edge signal:\r
-* - edge0: Edge 0\r
-* - edge1: Edge 1\r
-* - edge2: Edge 2\r
-* - edge3: Edge 3\r
-* - edge4: Edge 4\r
-* - edge5: Edge 5\r
-* - edge6: Edge 6\r
-* - edge7: Edge 7\r
-*\r
-* Reset edge counter to 0.\r
-*/\r
-\r
-void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32_t edge)\r
-{\r
- hetRAM->Instruction[edge + 17U].Data = 0U;\r
-}\r
-\r
-\r
-/** @fn uint32_t edgeGetCounter(hetRAMBASE_t * hetRAM, uint32_t edge)\r
-* @brief Get current edge counter value\r
-* @param[in] hetRAM Pointer to HET RAM:\r
-* - hetRAM1: HET1 RAM pointer\r
-* - hetRAM2: HET2 RAM pointer\r
-* @param[in] edge Edge signal:\r
-* - edge0: Edge 0\r
-* - edge1: Edge 1\r
-* - edge2: Edge 2\r
-* - edge3: Edge 3\r
-* - edge4: Edge 4\r
-* - edge5: Edge 5\r
-* - edge6: Edge 6\r
-* - edge7: Edge 7\r
-*\r
-* Gets current edge counter value.\r
-*/\r
-\r
-uint32_t edgeGetCounter(hetRAMBASE_t * hetRAM, uint32_t edge)\r
-{\r
- return hetRAM->Instruction[edge + 17U].Data >> 7U;\r
-}\r
-\r
-\r
-/** @fn void edgeEnableNotification(hetBASE_t * hetREG, uint32_t edge)\r
-* @brief Enable edge notification\r
-* @param[in] hetREG Pointer to HET Module:\r
-* - hetREG1: HET1 Module pointer\r
-* - hetREG2: HET2 Module pointer\r
-* @param[in] edge Edge signal:\r
-* - edge0: Edge 0\r
-* - edge1: Edge 1\r
-* - edge2: Edge 2\r
-* - edge3: Edge 3\r
-* - edge4: Edge 4\r
-* - edge5: Edge 5\r
-* - edge6: Edge 6\r
-* - edge7: Edge 7\r
-*/\r
-\r
-void edgeEnableNotification(hetBASE_t * hetREG, uint32_t edge)\r
-{\r
- hetREG->FLG = 0x20000U << edge;\r
- hetREG->INTENAS = 0x20000U << edge;\r
-}\r
-\r
-\r
-/** @fn void edgeDisableNotification(hetBASE_t * hetREG, uint32_t edge)\r
-* @brief Enable edge notification\r
-* @param[in] hetREG Pointer to HET Module:\r
-* - hetREG1: HET1 Module pointer\r
-* - hetREG2: HET2 Module pointer\r
-* @param[in] edge Edge signal:\r
-* - edge0: Edge 0\r
-* - edge1: Edge 1\r
-* - edge2: Edge 2\r
-* - edge3: Edge 3\r
-* - edge4: Edge 4\r
-* - edge5: Edge 5\r
-* - edge6: Edge 6\r
-* - edge7: Edge 7\r
-*/\r
-\r
-void edgeDisableNotification(hetBASE_t * hetREG, uint32_t edge)\r
-{\r
- hetREG->INTENAC = 0x20000U << edge;\r
-}\r
-\r
-\r
-/** @fn hetSIGNAL_t capGetSignal(hetRAMBASE_t * hetRAM, uint32_t cap)\r
-* @brief Get capture signal\r
-* @param[in] hetRAM Pointer to HET RAM:\r
-* - hetRAM1: HET1 RAM pointer\r
-* - hetRAM2: HET2 RAM pointer\r
-* @param[in] cap captured signal:\r
-* - cap0: Captured signal 0\r
-* - cap1: Captured signal 1\r
-* - cap2: Captured signal 2\r
-* - cap3: Captured signal 3\r
-* - cap4: Captured signal 4\r
-* - cap5: Captured signal 5\r
-* - cap6: Captured signal 6\r
-* - cap7: Captured signal 7\r
-*\r
-* Gets current signal of the given capture signal.\r
-*/\r
-\r
-hetSIGNAL_t capGetSignal(hetRAMBASE_t * hetRAM, uint32_t cap)\r
-{\r
- uint32_t duty = hetRAM->Instruction[(cap << 1U) + 25U].Data;\r
- uint32_t period = hetRAM->Instruction[(cap << 1U) + 26U].Data;\r
- hetSIGNAL_t signal; \r
- \r
- signal.duty = (uint32_t)(100.0 * duty / period);\r
- \r
- if( hetRAM == hetRAM1)\r
- {\r
- signal.period = (period >> 7U) * 800.000 / 1000.0;\r
- }\r
- else\r
- {\r
- signal.period = (period >> 7U) * 800.000 / 1000.0;\r
- }\r
- return signal;\r
-}\r
-\r
-\r
-/** @fn void hetResetTimestamp(hetRAMBASE_t *hetRAM)\r
-* @brief Resets timestamp\r
-* @param[in] hetRAM Pointer to HET RAM:\r
-* - hetRAM1: HET1 RAM pointer\r
-* - hetRAM2: HET2 RAM pointer\r
-*\r
-* Resets loop count based timstamp.\r
-*/\r
-\r
-void hetResetTimestamp(hetRAMBASE_t * hetRAM)\r
-{\r
- hetRAM->Instruction[0U].Data = 0;\r
-}\r
-\r
-\r
-/** @fn uint32_t hetGetTimestamp(hetRAMBASE_t *hetRAM)\r
-* @brief Returns timestamp\r
-*\r
-* Returns loop count based timstamp.\r
-*/\r
-\r
-uint32_t hetGetTimestamp(hetRAMBASE_t * hetRAM)\r
-{\r
- return hetRAM->Instruction[57U].Data;\r
-}\r
-\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-\r
-/** @fn void het1HighLevelInterrupt(void)\r
-* @brief Level 0 Interrupt for HET1\r
-*/\r
-#pragma INTERRUPT(het1HighLevelInterrupt, IRQ)\r
-\r
-void het1HighLevelInterrupt(void)\r
-{\r
- uint32_t vec = hetREG1->OFF1;\r
- \r
- if (vec < 18U)\r
- {\r
- if ((vec & 1U) != 0)\r
- {\r
- pwmNotification(hetREG1,(vec >> 1U) - 1U, pwmEND_OF_PERIOD);\r
- }\r
- else\r
- {\r
- pwmNotification(hetREG1,(vec >> 1U) - 1U, pwmEND_OF_DUTY);\r
- }\r
- }\r
- else\r
- {\r
- edgeNotification(hetREG1,vec - 18U);\r
- }\r
-}\r
-\r
-\r
-/** @fn void het1LowLevelInterrupt(void)\r
-* @brief Level 1 Interrupt for HET1\r
-*/\r
-#pragma INTERRUPT(het1LowLevelInterrupt, IRQ)\r
-\r
-void het1LowLevelInterrupt(void)\r
-{\r
- uint32_t vec = hetREG1->OFF2;\r
- \r
- if (vec < 18U)\r
- {\r
- if ((vec & 1U) != 0)\r
- {\r
- pwmNotification(hetREG1,(vec >> 1U) - 1U, pwmEND_OF_PERIOD);\r
- }\r
- else\r
- {\r
- pwmNotification(hetREG1,(vec >> 1U) - 1U, pwmEND_OF_DUTY);\r
- }\r
- }\r
- else\r
- {\r
- edgeNotification(hetREG1,vec - 18U);\r
- }\r
-}\r
-\r
+/** @file het.c
+* @brief HET Driver Implementation File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+#include "ti_drv_het.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/*----------------------------------------------------------------------------*/
+/* Global variables */
+
+static const uint32_t s_het1pwmPolarity[] =
+{
+ 3U,
+ 3U,
+ 3U,
+ 3U,
+ 3U,
+ 3U,
+ 3U,
+ 3U,
+};
+
+
+/*----------------------------------------------------------------------------*/
+/* Default Program */
+
+/** @var const hetINSTRUCTION_t het1PROGRAM[]
+* @brief Default Program
+*
+* Het program running after initialization.
+*/
+
+static const hetINSTRUCTION_t het1PROGRAM[58] =
+{
+ /* CNT: Timebase
+ * - Instruction = 0
+ * - Next instruction = 1
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = na
+ * - Reg = T
+ */
+ {
+ /* Program */
+ 0x00002C80U,
+ /* Control */
+ 0x01FFFFFFU,
+ /* Data */
+ 0xFFFFFF80U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 0 -> Duty Cycle
+ * - Instruction = 1
+ * - Next instruction = 2
+ * - Conditional next instruction = 2
+ * - Interrupt = 1
+ * - Pin = 7
+ */
+ {
+ /* Program */
+ 0x000055C0U,
+ /* Control */
+ (0x00004006U | (7U << 8U) | (3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 0 -> Period
+ * - Instruction = 2
+ * - Next instruction = 3
+ * - Conditional next instruction = 41
+ * - Interrupt = 2
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00007480U,
+ /* Control */
+ 0x00052006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 1 -> Duty Cycle
+ * - Instruction = 3
+ * - Next instruction = 4
+ * - Conditional next instruction = 4
+ * - Interrupt = 3
+ * - Pin = 16
+ */
+ {
+ /* Program */
+ 0x000095C0U,
+ /* Control */
+ (0x00008006U | (16U << 8U) | (3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 1 -> Period
+ * - Instruction = 4
+ * - Next instruction = 5
+ * - Conditional next instruction = 43
+ * - Interrupt = 4
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0000B480U,
+ /* Control */
+ 0x00056006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 2 -> Duty Cycle
+ * - Instruction = 5
+ * - Next instruction = 6
+ * - Conditional next instruction = 6
+ * - Interrupt = 5
+ * - Pin = 18
+ */
+ {
+ /* Program */
+ 0x0000D5C0U,
+ /* Control */
+ (0x0000C006U | (18U << 8U) | (3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 2 -> Period
+ * - Instruction = 6
+ * - Next instruction = 7
+ * - Conditional next instruction = 45
+ * - Interrupt = 6
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0000F480U,
+ /* Control */
+ 0x0005A006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 3 -> Duty Cycle
+ * - Instruction = 7
+ * - Next instruction = 8
+ * - Conditional next instruction = 8
+ * - Interrupt = 7
+ * - Pin = 20
+ */
+ {
+ /* Program */
+ 0x000115C0U,
+ /* Control */
+ (0x00010006U | (20U << 8U) | (3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 3 -> Period
+ * - Instruction = 8
+ * - Next instruction = 9
+ * - Conditional next instruction = 47
+ * - Interrupt = 8
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00013480U,
+ /* Control */
+ 0x0005E006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 4 -> Duty Cycle
+ * - Instruction = 9
+ * - Next instruction = 10
+ * - Conditional next instruction = 10
+ * - Interrupt = 9
+ * - Pin = 22
+ */
+ {
+ /* Program */
+ 0x000155C0U,
+ /* Control */
+ (0x00014006U | (22U << 8U) | (3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 4 -> Period
+ * - Instruction = 10
+ * - Next instruction = 11
+ * - Conditional next instruction = 49
+ * - Interrupt = 10
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00017480U,
+ /* Control */
+ 0x00062006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 5 -> Duty Cycle
+ * - Instruction = 11
+ * - Next instruction = 12
+ * - Conditional next instruction = 12
+ * - Interrupt = 11
+ * - Pin = 25
+ */
+ {
+ /* Program */
+ 0x000195C0U,
+ /* Control */
+ (0x00018006U | (25U << 8U) | (3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 5 -> Period
+ * - Instruction = 12
+ * - Next instruction = 13
+ * - Conditional next instruction = 51
+ * - Interrupt = 12
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0001B480U,
+ /* Control */
+ 0x00066006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 6 -> Duty Cycle
+ * - Instruction = 13
+ * - Next instruction = 14
+ * - Conditional next instruction = 14
+ * - Interrupt = 13
+ * - Pin = 29
+ */
+ {
+ /* Program */
+ 0x0001D5C0U,
+ /* Control */
+ (0x0001C006U | (29U << 8U) | (3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 6 -> Period
+ * - Instruction = 14
+ * - Next instruction = 15
+ * - Conditional next instruction = 53
+ * - Interrupt = 14
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0001F480U,
+ /* Control */
+ 0x0006A006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 7 -> Duty Cycle
+ * - Instruction = 15
+ * - Next instruction = 16
+ * - Conditional next instruction = 16
+ * - Interrupt = 15
+ * - Pin = 19
+ */
+ {
+ /* Program */
+ 0x000215C0U,
+ /* Control */
+ (0x00020006U | (19U << 8U) | (3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 7 -> Period
+ * - Instruction = 16
+ * - Next instruction = 17
+ * - Conditional next instruction = 55
+ * - Interrupt = 16
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00023480U,
+ /* Control */
+ 0x0006E006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 0
+ * - Instruction = 17
+ * - Next instruction = 18
+ * - Conditional next instruction = 18
+ * - Interrupt = 17
+ * - Pin = 9
+ */
+ {
+ /* Program */
+ 0x00025440U,
+ /* Control */
+ (0x00024007U | (9U << 8U) | (1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 1
+ * - Instruction = 18
+ * - Next instruction = 19
+ * - Conditional next instruction = 19
+ * - Interrupt = 18
+ * - Pin = 11
+ */
+ {
+ /* Program */
+ 0x00027440U,
+ /* Control */
+ (0x00026007U | (11U << 8U) | (1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 2
+ * - Instruction = 19
+ * - Next instruction = 20
+ * - Conditional next instruction = 20
+ * - Interrupt = 19
+ * - Pin = 13
+ */
+ {
+ /* Program */
+ 0x00029440U,
+ /* Control */
+ (0x00028007U | (13U << 8U) | (1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 3
+ * - Instruction = 20
+ * - Next instruction = 21
+ * - Conditional next instruction = 21
+ * - Interrupt = 20
+ * - Pin = 15
+ */
+ {
+ /* Program */
+ 0x0002B440U,
+ /* Control */
+ (0x0002A007U | (15U << 8U) | (1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 4
+ * - Instruction = 21
+ * - Next instruction = 22
+ * - Conditional next instruction = 22
+ * - Interrupt = 21
+ * - Pin = 20
+ */
+ {
+ /* Program */
+ 0x0002D440U,
+ /* Control */
+ (0x0002C007U | (20U << 8U) | (1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 5
+ * - Instruction = 22
+ * - Next instruction = 23
+ * - Conditional next instruction = 23
+ * - Interrupt = 22
+ * - Pin = 21
+ */
+ {
+ /* Program */
+ 0x0002F440U,
+ /* Control */
+ (0x0002E007U | (21U << 8U) | (1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 6
+ * - Instruction = 23
+ * - Next instruction = 24
+ * - Conditional next instruction = 24
+ * - Interrupt = 23
+ * - Pin = 22
+ */
+ {
+ /* Program */
+ 0x00031440U,
+ /* Control */
+ (0x00030007U | (22U << 8U) | (1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 7
+ * - Instruction = 24
+ * - Next instruction = 25
+ * - Conditional next instruction = 25
+ * - Interrupt = 24
+ * - Pin = 23
+ */
+ {
+ /* Program */
+ 0x00033440U,
+ /* Control */
+ (0x00032007U | (23U << 8U) | (1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 0
+ * - Instruction = 25
+ * - Next instruction = 26
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 0
+ */
+ {
+ /* Program */
+ 0x00034E00U | (0U << 6U) | (0U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 0
+ * - Instruction = 26
+ * - Next instruction = 27
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 0 + 1
+ */
+ {
+ /* Program */
+ 0x00036E80U | (0U << 6U) | ((0U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 1
+ * - Instruction = 27
+ * - Next instruction = 28
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 2
+ */
+ {
+ /* Program */
+ 0x00038E00U | (0U << 6U) | (2U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 1
+ * - Instruction = 28
+ * - Next instruction = 29
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 2 + 1
+ */
+ {
+ /* Program */
+ 0x0003AE80U | (0U << 6U) | ((2U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 2
+ * - Instruction = 29
+ * - Next instruction = 30
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 4
+ */
+ {
+ /* Program */
+ 0x0003CE00U | (0U << 6U) | (4U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 2
+ * - Instruction = 30
+ * - Next instruction = 31
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 4 + 1
+ */
+ {
+ /* Program */
+ 0x0003EE80U | (0U << 6U) | ((4U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 3
+ * - Instruction = 31
+ * - Next instruction = 32
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 6
+ */
+ {
+ /* Program */
+ 0x00040E00U | (0U << 6U) | (6U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 3
+ * - Instruction = 32
+ * - Next instruction = 33
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 6 + 1
+ */
+ {
+ /* Program */
+ 0x00042E80U | (0U << 6U) | ((6U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 4
+ * - Instruction = 33
+ * - Next instruction = 34
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 24
+ */
+ {
+ /* Program */
+ 0x00044E00U | (0U << 6U) | (24U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 4
+ * - Instruction = 34
+ * - Next instruction = 35
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 24 + 1
+ */
+ {
+ /* Program */
+ 0x00046E80U | (0U << 6U) | ((24U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 5
+ * - Instruction = 35
+ * - Next instruction = 36
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 26
+ */
+ {
+ /* Program */
+ 0x00048E00U | (0U << 6U) | (26U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 5
+ * - Instruction = 36
+ * - Next instruction = 37
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 26 + 1
+ */
+ {
+ /* Program */
+ 0x0004AE80U | (0U << 6U) | ((26U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 6
+ * - Instruction = 37
+ * - Next instruction = 38
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 28
+ */
+ {
+ /* Program */
+ 0x0004CE00U | (0U << 6U) | (28U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 6
+ * - Instruction = 38
+ * - Next instruction = 39
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 28 + 1
+ */
+ {
+ /* Program */
+ 0x0004EE80U | (0U << 6U) | ((28U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 7
+ * - Instruction = 39
+ * - Next instruction = 40
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 30
+ */
+ {
+ /* Program */
+ 0x00050E00U | (0U << 6U) | (30U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 7
+ * - Instruction = 40
+ * - Next instruction = 57
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 30 + 1
+ */
+ {
+ /* Program */
+ 0x00072E80U | (0U << 6U) | ((30U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 0 -> Duty Cycle Update
+ * - Instruction = 41
+ * - Next instruction = 42
+ * - Conditional next instruction = 2
+ * - Interrupt = 1
+ * - Pin = 7
+ */
+ {
+ /* Program */
+ 0x00054201U,
+ /* Control */
+ (0x00004007U | (0U << 22U) | (7U << 8U) | (3U << 3U)),
+ /* Data */
+ 48128U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 0 -> Period Update
+ * - Instruction = 42
+ * - Next instruction = 3
+ * - Conditional next instruction = 41
+ * - Interrupt = 2
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00006202U,
+ /* Control */
+ (0x00052007U),
+ /* Data */
+ 159872U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 1 -> Duty Cycle Update
+ * - Instruction = 43
+ * - Next instruction = 44
+ * - Conditional next instruction = 4
+ * - Interrupt = 3
+ * - Pin = 16
+ */
+ {
+ /* Program */
+ 0x00058203U,
+ /* Control */
+ (0x00008007U | (0U << 22U) | (16U << 8U) | (3U << 3U)),
+ /* Data */
+ 80128U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 1 -> Period Update
+ * - Instruction = 44
+ * - Next instruction = 5
+ * - Conditional next instruction = 43
+ * - Interrupt = 4
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0000A204U,
+ /* Control */
+ (0x00056007U),
+ /* Data */
+ 159872U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 2 -> Duty Cycle Update
+ * - Instruction = 45
+ * - Next instruction = 46
+ * - Conditional next instruction = 6
+ * - Interrupt = 5
+ * - Pin = 18
+ */
+ {
+ /* Program */
+ 0x0005C205U,
+ /* Control */
+ (0x0000C007U | (0U << 22U) | (18U << 8U) | (3U << 3U)),
+ /* Data */
+ 80128U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 2 -> Period Update
+ * - Instruction = 46
+ * - Next instruction = 7
+ * - Conditional next instruction = 45
+ * - Interrupt = 6
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0000E206U,
+ /* Control */
+ (0x0005A007U),
+ /* Data */
+ 159872U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 3 -> Duty Cycle Update
+ * - Instruction = 47
+ * - Next instruction = 48
+ * - Conditional next instruction = 8
+ * - Interrupt = 7
+ * - Pin = 20
+ */
+ {
+ /* Program */
+ 0x00060207U,
+ /* Control */
+ (0x00010007U | (0U << 22U) | (20U << 8U) | (3U << 3U)),
+ /* Data */
+ 80128U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 3 -> Period Update
+ * - Instruction = 48
+ * - Next instruction = 9
+ * - Conditional next instruction = 47
+ * - Interrupt = 8
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00012208U,
+ /* Control */
+ (0x0005E007U),
+ /* Data */
+ 159872U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 4 -> Duty Cycle Update
+ * - Instruction = 49
+ * - Next instruction = 50
+ * - Conditional next instruction = 10
+ * - Interrupt = 9
+ * - Pin = 22
+ */
+ {
+ /* Program */
+ 0x00064209U,
+ /* Control */
+ (0x00014007U | (0U << 22U) | (22U << 8U) | (3U << 3U)),
+ /* Data */
+ 80128U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 4 -> Period Update
+ * - Instruction = 50
+ * - Next instruction = 11
+ * - Conditional next instruction = 49
+ * - Interrupt = 10
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0001620AU,
+ /* Control */
+ (0x00062007U),
+ /* Data */
+ 159872U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 5 -> Duty Cycle Update
+ * - Instruction = 51
+ * - Next instruction = 52
+ * - Conditional next instruction = 12
+ * - Interrupt = 11
+ * - Pin = 25
+ */
+ {
+ /* Program */
+ 0x0006820BU,
+ /* Control */
+ (0x00018007U | (0U << 22U) | (25U << 8U) | (3U << 3U)),
+ /* Data */
+ 80128U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 5 -> Period Update
+ * - Instruction = 52
+ * - Next instruction = 13
+ * - Conditional next instruction = 51
+ * - Interrupt = 12
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0001A20CU,
+ /* Control */
+ (0x00066007U),
+ /* Data */
+ 159872U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 6 -> Duty Cycle Update
+ * - Instruction = 53
+ * - Next instruction = 54
+ * - Conditional next instruction = 14
+ * - Interrupt = 13
+ * - Pin = 29
+ */
+ {
+ /* Program */
+ 0x0006C20DU,
+ /* Control */
+ (0x0001C007U | (0U << 22U) | (29U << 8U) | (3U << 3U)),
+ /* Data */
+ 80128U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 6 -> Period Update
+ * - Instruction = 54
+ * - Next instruction = 15
+ * - Conditional next instruction = 53
+ * - Interrupt = 14
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0001E20EU,
+ /* Control */
+ (0x0006A007U),
+ /* Data */
+ 159872U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 7 -> Duty Cycle Update
+ * - Instruction = 55
+ * - Next instruction = 56
+ * - Conditional next instruction = 16
+ * - Interrupt = 15
+ * - Pin = 19
+ */
+ {
+ /* Program */
+ 0x0007020FU,
+ /* Control */
+ (0x00020007U | (0U << 22U) | (19U << 8U) | (3U << 3U)),
+ /* Data */
+ 80128U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 7 -> Period Update
+ * - Instruction = 56
+ * - Next instruction = 17
+ * - Conditional next instruction = 55
+ * - Interrupt = 16
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00022210U,
+ /* Control */
+ (0x0006E007U),
+ /* Data */
+ 159872U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* WCAP: Capture timestamp
+ * - Instruction = 57
+ * - Next instruction = 0
+ * - Conditional next instruction = 0
+ * - Interrupt = na
+ * - Pin = na
+ * - Reg = T
+ */
+ {
+ /* Program */
+ 0x00001600U,
+ /* Control */
+ (0x00000004U),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+};
+
+
+
+/** @fn void hetInit(void)
+* @brief Initializes the het Driver
+*
+* This function initializes the het 1 module.
+*/
+void hetInit(void)
+{
+ /** @b intalise @b HET */
+
+ /** - Set HET pins default output value */
+ hetREG1->DOUT = (0U << 31U)
+ | (0U << 30U)
+ | (0U << 29U)
+ | (0U << 28U)
+ | (0U << 27U)
+ | (0U << 26U)
+ | (0U << 25U)
+ | (0U << 24U)
+ | (0U << 23U)
+ | (0U << 22U)
+ | (0U << 21U)
+ | (0U << 20U)
+ | (0U << 19U)
+ | (0U << 18U)
+ | (0U << 17U)
+ | (0U << 16U)
+ | (0U << 15U)
+ | (0U << 14U)
+ | (0U << 13U)
+ | (0U << 12U)
+ | (0U << 11U)
+ | (0U << 10U)
+ | (0U << 9U)
+ | (0U << 8U)
+ | (0U << 7U)
+ | (0U << 6U)
+ | (0U << 5U)
+ | (0U << 4U)
+ | (0U << 3U)
+ | (0U << 2U)
+ | (0U << 1U)
+ | (0U);
+
+ /** - Set HET pins direction */
+ hetREG1->DIR = 0x00000000U
+ | 0x00000000U
+ | 0x20000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x02000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00400000U
+ | 0x00000000U
+ | 0x00100000U
+ | 0x00000000U
+ | 0x00040000U
+ | 0x00000000U
+ | 0x00010000U
+ | 0x00000000U
+ | 0x00004000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000200U
+ | 0x00000000U
+ | 0x00000080U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000010U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000002U
+ | 0x00000000U;
+
+ /** - Set HET pins open drain enable */
+ hetREG1->PDR = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Set HET pins pullup/down enable */
+ hetREG1->PULDIS = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000080U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000010U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Set HET pins pullup/down select */
+ hetREG1->PSL = 0x80000000U
+ | 0x40000000U
+ | 0x20000000U
+ | 0x10000000U
+ | 0x08000000U
+ | 0x04000000U
+ | 0x02000000U
+ | 0x01000000U
+ | 0x00800000U
+ | 0x00400000U
+ | 0x00200000U
+ | 0x00100000U
+ | 0x00080000U
+ | 0x00040000U
+ | 0x00020000U
+ | 0x00010000U
+ | 0x00008000U
+ | 0x00004000U
+ | 0x00002000U
+ | 0x00001000U
+ | 0x00000800U
+ | 0x00000400U
+ | 0x00000200U
+ | 0x00000100U
+ | 0x00000000U
+ | 0x00000040U
+ | 0x00000020U
+ | 0x00000000U
+ | 0x00000008U
+ | 0x00000004U
+ | 0x00000002U
+ | 0x00000001U;
+
+ /** - Set HET pins high resolution share */
+ hetREG1->HRSH = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Set HET pins AND share */
+ hetREG1->AND = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Set HET pins XOR share */
+ hetREG1->XOR = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+ /** - Setup prescaler values
+ * - Loop resolution prescaler
+ * - High resolution prescaler
+ */
+ hetREG1->PFR = (6U << 8U)
+ | (0U);
+
+ /** - Fill HET RAM with opcodes and Data */
+ memcpy((void *)hetRAM1, (const void *)het1PROGRAM, sizeof(het1PROGRAM));
+
+ /** - Setup interrupt priority level
+ * - PWM 0 end of duty level
+ * - PWM 0 end of period level
+ * - PWM 1 end of duty level
+ * - PWM 1 end of period level
+ * - PWM 2 end of duty level
+ * - PWM 2 end of period level
+ * - PWM 3 end of duty level
+ * - PWM 3 end of period level
+ * - PWM 4 end of duty level
+ * - PWM 4 end of period level
+ * - PWM 5 end of duty level
+ * - PWM 5 end of period level
+ * - PWM 6 end of duty level
+ * - PWM 6 end of period level
+ * - PWM 7 end of duty level
+ * - PWM 7 end of period level
+
+ * - CCU Edge Detection 0 level
+ * - CCU Edge Detection 1 level
+ * - CCU Edge Detection 2 level
+ * - CCU Edge Detection 3 level
+ * - CCU Edge Detection 4 level
+ * - CCU Edge Detection 5 level
+ * - CCU Edge Detection 6 level
+ * - CCU Edge Detection 7 level
+ */
+ hetREG1->PRY = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Enable interrupts
+ * - PWM 0 end of duty
+ * - PWM 0 end of period
+ * - PWM 1 end of duty
+ * - PWM 1 end of period
+ * - PWM 2 end of duty
+ * - PWM 2 end of period
+ * - PWM 3 end of duty
+ * - PWM 3 end of period
+ * - PWM 4 end of duty
+ * - PWM 4 end of period
+ * - PWM 5 end of duty
+ * - PWM 5 end of period
+ * - PWM 6 end of duty
+ * - PWM 6 end of period
+ * - PWM 7 end of duty
+ * - PWM 7 end of period
+ * - CCU Edge Detection 0
+ * - CCU Edge Detection 1
+ * - CCU Edge Detection 2
+ * - CCU Edge Detection 3
+ * - CCU Edge Detection 4
+ * - CCU Edge Detection 5
+ * - CCU Edge Detection 6
+ * - CCU Edge Detection 7
+ */
+ hetREG1->INTENAC = 0xFFFFFFFFU;
+ hetREG1->INTENAS = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+
+ /** - Parity control register
+ * - Enable/Disable Parity check
+ */
+ hetREG1->PCREG = 0x00000005U;
+
+ /** - Setup control register
+ * - Enable output buffers
+ * - Ignore software breakpoints
+ * - Master mode
+ * - Enable HET
+ */
+ hetREG1->GCR = 0x01030001U;
+ /** @note This function has to be called before the driver can be used.\n
+ * This function has to be executed in priviledged mode.\n
+ */
+
+
+
+}
+
+/** @fn void pwmStart( hetRAMBASE_t * hetRAM, uint32_t pwm)
+* @brief Start pwm signal
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+*
+* Start the given pwm signal
+*/
+
+void pwmStart( hetRAMBASE_t * hetRAM, uint32_t pwm)
+{
+
+ hetRAM->Instruction[(pwm << 1U) + 41U].Control |= 0x00400000U;
+}
+
+
+/** @fn void pwmStop( hetRAMBASE_t * hetRAM, uint32_t pwm)
+* @brief Stop pwm signal
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+*
+* Stop the given pwm signal
+*/
+
+void pwmStop( hetRAMBASE_t * hetRAM, uint32_t pwm)
+{
+ hetRAM->Instruction[(pwm << 1U) + 41U].Control &= ~0x00400000U;
+}
+
+
+/** @fn void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32_t pwm, uint32_t duty)
+* @brief Set duty cycle
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+* @param[in] duty duty cycle in %.
+*
+* Sets a new duty cycle on the given pwm signal
+*/
+
+void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32_t pwm, uint32_t duty)
+{
+ uint32_t action;
+ uint32_t pwmPolarity;
+ double period = hetRAM->Instruction[(pwm << 1U) + 42U].Data + 128U;
+ if(hetRAM == hetRAM1)
+ {
+ pwmPolarity = s_het1pwmPolarity[pwm];
+ }
+ else
+ {
+ }
+ if (duty == 0U)
+ {
+ action = (pwmPolarity == 3U) ? 0U : 2U;
+ }
+ else if (duty >= 100U)
+ {
+ action = (pwmPolarity == 3U) ? 2U : 0U;
+ }
+ else
+ {
+ action = pwmPolarity;
+ }
+
+ hetRAM->Instruction[(pwm << 1U) + 41U].Control = (hetRAM->Instruction[(pwm << 1U) + 41U].Control & ~0x18U) | (action << 3U);
+ hetRAM->Instruction[(pwm << 1U) + 41U].Data = (uint32_t)(period * duty / 100.0) + 128U;
+}
+
+
+/** @fn void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32_t pwm, hetSIGNAL_t signal)
+* @brief Set period
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+* @param[in] signal signal
+ - duty cycle in %.
+* - period period in us.
+*
+* Sets a new pwm signal
+*/
+
+void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32_t pwm, hetSIGNAL_t signal)
+{
+ uint32_t action;
+ uint32_t period;
+ uint32_t pwmPolarity;
+
+ if(hetRAM == hetRAM1)
+ {
+ period = (uint32_t)(signal.period * 1000.0 / 800.000) << 7U;
+ pwmPolarity = s_het1pwmPolarity[pwm];
+ }
+ else
+ {
+ }
+ if (signal.duty == 0U)
+ {
+ action = (pwmPolarity == 3U) ? 0U : 2U;
+ }
+ else if (signal.duty >= 100U)
+ {
+ action = (pwmPolarity == 3U) ? 2U : 0U;
+ }
+ else
+ {
+ action = pwmPolarity;
+ }
+
+ hetRAM->Instruction[(pwm << 1U) + 41U].Control = (hetRAM->Instruction[(pwm << 1U) + 41U].Control & ~0x18U) | (action << 3U);
+ hetRAM->Instruction[(pwm << 1U) + 41U].Data = (uint32_t)(period * signal.duty / 100.0) + 128U;
+ hetRAM->Instruction[(pwm << 1U) + 42U].Data = period - 128U;
+}
+
+
+/** @fn hetSIGNAL_t pwmGetSignal(hetRAMBASE_t * hetRAM, uint32_t pwm)
+* @brief Get duty cycle
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+*
+* Gets current signal of the given pwm signal.
+*/
+
+hetSIGNAL_t pwmGetSignal(hetRAMBASE_t * hetRAM, uint32_t pwm)
+{
+ hetSIGNAL_t signal;
+ uint32_t duty = hetRAM->Instruction[(pwm << 1U) + 41U].Data - 128;
+ uint32_t period = hetRAM->Instruction[(pwm << 1U) + 42U].Data + 128;
+
+ signal.duty = (uint32_t)(100.0 * duty / period);
+
+ if(hetRAM == hetRAM1)
+ {
+ signal.period = (period >> 7U) * 800.000 / 1000.0;
+ }
+ else
+ {
+ signal.period = (period >> 7U) * 800.000 / 1000.0;
+ }
+ return signal;
+}
+
+
+/** @fn void pwmEnableNotification(hetBASE_t * hetREG, uint32_t pwm, uint32_t notification)
+* @brief Enable pwm notification
+* @param[in] hetREG Pointer to HET Module:
+* - hetREG1: HET1 Module pointer
+* - hetREG2: HET2 Module pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+* @param[in] notification Pwm notification:
+* - pwmEND_OF_DUTY: Notification on end of duty
+* - pwmEND_OF_PERIOD: Notification on end of end period
+* - pwmEND_OF_BOTH: Notification on end of both duty and period
+*/
+
+void pwmEnableNotification(hetBASE_t * hetREG, uint32_t pwm, uint32_t notification)
+{
+ hetREG->FLG = notification << (pwm << 1U);
+ hetREG->INTENAS = notification << (pwm << 1U);
+}
+
+
+/** @fn void pwmDisableNotification(hetBASE_t * hetREG, uint32_t pwm, uint32_t notification)
+* @brief Enable pwm notification
+* @param[in] hetREG Pointer to HET Module:
+* - hetREG1: HET1 Module pointer
+* - hetREG2: HET2 Module pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+* @param[in] notification Pwm notification:
+* - pwmEND_OF_DUTY: Notification on end of duty
+* - pwmEND_OF_PERIOD: Notification on end of end period
+* - pwmEND_OF_BOTH: Notification on end of both duty and period
+*/
+
+void pwmDisableNotification(hetBASE_t * hetREG, uint32_t pwm, uint32_t notification)
+{
+ hetREG->INTENAC = notification << (pwm << 1U);
+}
+
+
+/** @fn void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32_t edge)
+* @brief Resets edge counter to 0
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] edge Edge signal:
+* - edge0: Edge 0
+* - edge1: Edge 1
+* - edge2: Edge 2
+* - edge3: Edge 3
+* - edge4: Edge 4
+* - edge5: Edge 5
+* - edge6: Edge 6
+* - edge7: Edge 7
+*
+* Reset edge counter to 0.
+*/
+
+void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32_t edge)
+{
+ hetRAM->Instruction[edge + 17U].Data = 0U;
+}
+
+
+/** @fn uint32_t edgeGetCounter(hetRAMBASE_t * hetRAM, uint32_t edge)
+* @brief Get current edge counter value
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] edge Edge signal:
+* - edge0: Edge 0
+* - edge1: Edge 1
+* - edge2: Edge 2
+* - edge3: Edge 3
+* - edge4: Edge 4
+* - edge5: Edge 5
+* - edge6: Edge 6
+* - edge7: Edge 7
+*
+* Gets current edge counter value.
+*/
+
+uint32_t edgeGetCounter(hetRAMBASE_t * hetRAM, uint32_t edge)
+{
+ return hetRAM->Instruction[edge + 17U].Data >> 7U;
+}
+
+
+/** @fn void edgeEnableNotification(hetBASE_t * hetREG, uint32_t edge)
+* @brief Enable edge notification
+* @param[in] hetREG Pointer to HET Module:
+* - hetREG1: HET1 Module pointer
+* - hetREG2: HET2 Module pointer
+* @param[in] edge Edge signal:
+* - edge0: Edge 0
+* - edge1: Edge 1
+* - edge2: Edge 2
+* - edge3: Edge 3
+* - edge4: Edge 4
+* - edge5: Edge 5
+* - edge6: Edge 6
+* - edge7: Edge 7
+*/
+
+void edgeEnableNotification(hetBASE_t * hetREG, uint32_t edge)
+{
+ hetREG->FLG = 0x20000U << edge;
+ hetREG->INTENAS = 0x20000U << edge;
+}
+
+
+/** @fn void edgeDisableNotification(hetBASE_t * hetREG, uint32_t edge)
+* @brief Enable edge notification
+* @param[in] hetREG Pointer to HET Module:
+* - hetREG1: HET1 Module pointer
+* - hetREG2: HET2 Module pointer
+* @param[in] edge Edge signal:
+* - edge0: Edge 0
+* - edge1: Edge 1
+* - edge2: Edge 2
+* - edge3: Edge 3
+* - edge4: Edge 4
+* - edge5: Edge 5
+* - edge6: Edge 6
+* - edge7: Edge 7
+*/
+
+void edgeDisableNotification(hetBASE_t * hetREG, uint32_t edge)
+{
+ hetREG->INTENAC = 0x20000U << edge;
+}
+
+
+/** @fn hetSIGNAL_t capGetSignal(hetRAMBASE_t * hetRAM, uint32_t cap)
+* @brief Get capture signal
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] cap captured signal:
+* - cap0: Captured signal 0
+* - cap1: Captured signal 1
+* - cap2: Captured signal 2
+* - cap3: Captured signal 3
+* - cap4: Captured signal 4
+* - cap5: Captured signal 5
+* - cap6: Captured signal 6
+* - cap7: Captured signal 7
+*
+* Gets current signal of the given capture signal.
+*/
+
+hetSIGNAL_t capGetSignal(hetRAMBASE_t * hetRAM, uint32_t cap)
+{
+ uint32_t duty = hetRAM->Instruction[(cap << 1U) + 25U].Data;
+ uint32_t period = hetRAM->Instruction[(cap << 1U) + 26U].Data;
+ hetSIGNAL_t signal;
+
+ signal.duty = (uint32_t)(100.0 * duty / period);
+
+ if( hetRAM == hetRAM1)
+ {
+ signal.period = (period >> 7U) * 800.000 / 1000.0;
+ }
+ else
+ {
+ signal.period = (period >> 7U) * 800.000 / 1000.0;
+ }
+ return signal;
+}
+
+
+/** @fn void hetResetTimestamp(hetRAMBASE_t *hetRAM)
+* @brief Resets timestamp
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+*
+* Resets loop count based timstamp.
+*/
+
+void hetResetTimestamp(hetRAMBASE_t * hetRAM)
+{
+ hetRAM->Instruction[0U].Data = 0;
+}
+
+
+/** @fn uint32_t hetGetTimestamp(hetRAMBASE_t *hetRAM)
+* @brief Returns timestamp
+*
+* Returns loop count based timstamp.
+*/
+
+uint32_t hetGetTimestamp(hetRAMBASE_t * hetRAM)
+{
+ return hetRAM->Instruction[57U].Data;
+}
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+/** @fn void het1HighLevelInterrupt(void)
+* @brief Level 0 Interrupt for HET1
+*/
+#pragma INTERRUPT(het1HighLevelInterrupt, IRQ)
+
+void het1HighLevelInterrupt(void)
+{
+ uint32_t vec = hetREG1->OFF1;
+
+ if (vec < 18U)
+ {
+ if ((vec & 1U) != 0)
+ {
+ pwmNotification(hetREG1,(vec >> 1U) - 1U, pwmEND_OF_PERIOD);
+ }
+ else
+ {
+ pwmNotification(hetREG1,(vec >> 1U) - 1U, pwmEND_OF_DUTY);
+ }
+ }
+ else
+ {
+ edgeNotification(hetREG1,vec - 18U);
+ }
+}
+
+
+/** @fn void het1LowLevelInterrupt(void)
+* @brief Level 1 Interrupt for HET1
+*/
+#pragma INTERRUPT(het1LowLevelInterrupt, IRQ)
+
+void het1LowLevelInterrupt(void)
+{
+ uint32_t vec = hetREG1->OFF2;
+
+ if (vec < 18U)
+ {
+ if ((vec & 1U) != 0)
+ {
+ pwmNotification(hetREG1,(vec >> 1U) - 1U, pwmEND_OF_PERIOD);
+ }
+ else
+ {
+ pwmNotification(hetREG1,(vec >> 1U) - 1U, pwmEND_OF_DUTY);
+ }
+ }
+ else
+ {
+ edgeNotification(hetREG1,vec - 18U);
+ }
+}
+
-/** @file i2c.c \r
-* @brief I2C Driver Implementation File\r
-* @date 10.March.2012\r
-* @version 03.01.00\r
-*\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-#include "ti_drv_i2c.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-/** @struct g_I2CTransfer\r
-* @brief Interrupt mode globals\r
-*\r
-*/\r
-struct g_i2cTransfer\r
-{\r
- uint32_t mode;\r
- uint32_t length;\r
- uint8_t *data;\r
-} g_i2cTransfer[2];\r
-\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
-/** @fn void i2cInit(void)\r
-* @brief Initializes the i2c Driver\r
-*\r
-* This function initializes the i2c module.\r
-*/\r
-void i2cInit(void)\r
-{\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-\r
- /** @b intialize @b I2C */\r
-\r
- /** - i2c out of reset */\r
- i2cREG1->MDR = (1 << 5);\r
-\r
- /** - set i2c mode */\r
- i2cREG1->MDR = (0 << 15) /* nack mode */ \r
- | (0 << 14) /* free running */ \r
- | 0 /* start condtion - master mode only */ \r
- | (1 <<11) /* stop condtion */ \r
- | (1 <<10) /* Master/Slave mode */ \r
- | (I2C_TRANSMITTER) /* Transmitter/receiver */ \r
- | (I2C_7BIT_AMODE) /* xpanded address */ \r
- | (0 << 7) /* repeat mode */ \r
- | (0 << 6) /* digital loopback */ \r
- | (0 << 4) /* start byte - master only */ \r
- | (0) /* free data format */ \r
- | I2C_8_BIT; /* bit count */ \r
-\r
-\r
- /** - set i2c extended mode */\r
- i2cREG1->EMDR = (0 << 25);\r
-\r
- /** - set i2c data count */\r
- i2cREG1->CNT = 3;\r
-\r
- /** - disable all interrupts */\r
- i2cREG1->IMR = 0x00U; \r
-\r
- /** - set prescale */\r
- i2cREG1->PSC = 9;\r
-\r
- /** - set clock rate */\r
- i2cREG1->CLKH = 35;\r
- i2cREG1->CLKL = 35;\r
-\r
- /** - set i2c pins functional mode */\r
- i2cREG1->FUN = (0 );\r
-\r
- /** - set i2c pins default output value */\r
- i2cREG1->DOUT = (0 << 1) /* sda pin */\r
- | (0); /* scl pin */\r
-\r
- /** - set i2c pins output direction */\r
- i2cREG1->DIR = (1 << 1) /* sda pin */\r
- | (1); /* scl pin */\r
-\r
- /** - set i2c pins open drain enable */\r
- i2cREG1->ODR = (0 << 1) /* sda pin */\r
- | (0); /* scl pin */\r
-\r
- /** - set i2c pins pullup/pulldown enable */\r
- i2cREG1->PD = (0 << 1) /* sda pin */\r
- | (0); /* scl pin */\r
-\r
- /** - set i2c pins pullup/pulldown select */\r
- i2cREG1->PSL = (1 << 1) /* sda pin */\r
- | (1); /* scl pin */\r
-\r
- /** - set interrupt enable */\r
- i2cREG1->IMR = (0 << 6) /* Address as slave interrupt */\r
- | (0 << 5) /* Stop Condition detect interrupt */\r
- | (1 << 4) /* Transmit data ready interrupt */\r
- | (1 << 3) /* Receive data ready interrupt */\r
- | (0 << 2) /* Register Access ready interrupt */\r
- | (0 << 1) /* No Acknowledgement interrupt */\r
- | (1); /* Arbitration Lost interrupt */\r
- \r
- i2cREG1->MDR |= I2C_RESET_OUT; /* i2c out of reset */ \r
- \r
- /** - inialise global transfer variables */\r
- g_i2cTransfer[0].mode = 1 << 8;\r
- g_i2cTransfer[0].length = 0;\r
-\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-/** @fn void i2cSetOwnAdd(i2cBASE_t *i2c, uint32_t oadd)\r
-* @brief Set I2C Own Address\r
-* @param[in] oadd - I2C Own address (7-bit or 10 -bit address)\r
-* @param[in] i2c - i2c module base address\r
-* Set the Own address of the I2C module.\r
-*/\r
-void i2cSetOwnAdd(i2cBASE_t *i2c, uint32_t oadd)\r
-{\r
- i2cREG1->OAR = oadd; /* set own address */\r
-}\r
-\r
-/** @fn void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32_t sadd)\r
-* @brief Set Port Direction\r
-* @param[in] sadd - I2C Slave address\r
-* @param[in] i2c - i2c module base address\r
-* Set the Slave address to communicate which is must in Master mode.\r
-*/\r
-void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32_t sadd)\r
-{\r
- i2cREG1->SAR = sadd; /* set slave address */\r
-}\r
-\r
-/** @fn void i2cSetBaudrate(i2cBASE_t *i2c, uint32_t baud)\r
-* @brief Change baudrate at runtime.\r
-* @param[in] i2c - i2c module base address\r
-* @param[in] baud - baudrate in KHz\r
-*\r
-* Change the i2c baudrate at runtime.\r
-*/\r
-void i2cSetBaudrate(i2cBASE_t *i2c, uint32_t baud)\r
-{\r
- uint32_t prescale;\r
- uint32_t d; \r
- uint32_t ck; \r
- double vclk = 80.000 * 1000000.0;\r
-\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
- prescale = (uint32_t) ((vclk /8000000) - 1);\r
-\r
- if(prescale>=2)\r
- {\r
- d = 5;\r
- }\r
- else\r
- {\r
- d = prescale ? 6 : 7;\r
- }\r
-\r
- ck = ((vclk)/(2*baud*1000*(prescale+1)))-d;\r
-\r
- i2cREG1->PSC = prescale;\r
- i2cREG1->CLKH = ck;\r
- i2cREG1->CLKL = ck; \r
-\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-/** @fn void i2cSetStart(i2cBASE_t *i2c)\r
-* @brief Set i2c start condition\r
-* @param[in] i2c - i2c module base address\r
-* Set i2c to generate a start bit (Only in Master mode)\r
-*/\r
-void i2cSetStart(i2cBASE_t *i2c)\r
-{\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
-\r
- i2cREG1->MDR |= I2C_START_COND; /* set start condition */\r
-\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void i2cSetStop(i2cBASE_t *i2c)\r
-* @brief Set i2c stop condition\r
-* @param[in] i2c - i2c module base address\r
-* Set i2c to generate a stop bit (Only in Master mode)\r
-*/\r
-void i2cSetStop(i2cBASE_t *i2c)\r
-{\r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
-\r
- i2cREG1->MDR |= I2C_STOP_COND; /* generate stop condition */\r
-\r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void i2cSetCount(i2cBASE_t *i2c,uint32_t cnt)\r
-* @brief Set i2c data count\r
-* @param[in] i2c - i2c module base address\r
-* @param[in] cnt - data count\r
-* Set i2c count to a transfer value after which the stop condition needs to be generated.\r
-* (Only in Master Mode)\r
-*/\r
-void i2cSetCount(i2cBASE_t *i2c ,uint32_t cnt)\r
-{\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
-\r
- i2cREG1->CNT = cnt; /* set i2c count */\r
-\r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn uint32_t i2cIsTxReady(i2cBASE_t *i2c)\r
-* @brief Check if Tx buffer empty\r
-* @param[in] i2c - i2c module base address\r
-*\r
-* @return The TX ready flag\r
-*\r
-* Checks to see if the Tx buffer ready flag is set, returns\r
-* 0 is flags not set otherwise will return the Tx flag itself.\r
-*/\r
-uint32_t i2cIsTxReady(i2cBASE_t *i2c)\r
-{\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
-\r
- return i2cREG1->STR & I2C_TX_INT;\r
-\r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void i2cSendByte(i2cBASE_t *i2c, uint8_t byte)\r
-* @brief Send Byte\r
-* @param[in] i2c - i2c module base address\r
-* @param[in] byte - byte to transfer\r
-*\r
-* Sends a single byte in polling mode, will wait in the\r
-* routine until the transmit buffer is empty before sending\r
-* the byte. Use i2cIsTxReady to check for Tx buffer empty\r
-* before calling i2cSendByte to avoid waiting.\r
-*/\r
-void i2cSendByte(i2cBASE_t *i2c, uint8_t byte)\r
-{\r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
-\r
- while ((i2cREG1->STR & I2C_TX_INT) == 0) { /* wait */ };\r
- i2cREG1->DXR = byte;\r
-\r
-/* USER CODE BEGIN (16) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void i2cSend(i2cBASE_t *i2c, uint32_t length, uint8_t *data)\r
-* @brief Send Data\r
-* @param[in] i2c - i2c module base address\r
-* @param[in] length - number of data words to transfer\r
-* @param[in] data - pointer to data to send\r
-*\r
-* Send a block of data pointed to by 'data' and 'length' bytes\r
-* long. If interrupts have been enabled the data is sent using\r
-* interrupt mode, otherwise polling mode is used. In interrupt\r
-* mode transmition of the first byte is started and the routine\r
-* returns imediatly, i2cSend must not be called again until the\r
-* transfer is complete, when the i2cNotification callback will\r
-* be called. In polling mode, i2cSend will not return until \r
-* the transfer is complete.\r
-*\r
-* @note if data word is less than 8 bits, then the data must be left\r
-* aligned in the data byte.\r
-*/\r
-void i2cSend(i2cBASE_t *i2c, uint32_t length, uint8_t *data)\r
-{\r
- uint32_t index = i2c == i2cREG1 ? 0 : 1;\r
-\r
-/* USER CODE BEGIN (17) */\r
-/* USER CODE END */\r
-\r
- if ((g_i2cTransfer[index].mode & I2C_TX_INT) != 0)\r
- {\r
- /* we are in interrupt mode */\r
- \r
- g_i2cTransfer[index].length = length;\r
- g_i2cTransfer[index].data = data;\r
-\r
- /* start transmit by sending first byte */ \r
- i2cREG1->DXR = *g_i2cTransfer[index].data++;\r
- i2cREG1->IMR = I2C_TX_INT;\r
- }\r
- else\r
- {\r
- /* send the data */\r
- while (length-- > 0)\r
- {\r
- while ((i2cREG1->STR & I2C_TX_INT) == 0) { /* wait */ };\r
- i2cREG1->DXR = *data++;\r
- }\r
- }\r
-/* USER CODE BEGIN (18) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn uint32_t i2cIsRxReady(i2cBASE_t *i2c)\r
-* @brief Check if Rx buffer full\r
-* @param[in] i2c - i2c module base address\r
-*\r
-* @return The Rx ready flag\r
-*\r
-* Checks to see if the Rx buffer full flag is set, returns\r
-* 0 is flags not set otherwise will return the Rx flag itself.\r
-*/\r
-uint32_t i2cIsRxReady(i2cBASE_t *i2c)\r
-{\r
-/* USER CODE BEGIN (19) */\r
-/* USER CODE END */\r
-\r
- return i2cREG1->STR & I2C_RX_INT;\r
-\r
-/* USER CODE BEGIN (20) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn uint32_t i2cRxError(i2cBASE_t *i2c)\r
-* @brief Return Rx Error flags\r
-* @param[in] i2c - i2c module base address\r
-*\r
-* @return The Rx error flags\r
-*\r
-* Returns the Rx framing, overun and parity errors flags,\r
-* also clears the error flags before returning.\r
-*/\r
-uint32_t i2cRxError(i2cBASE_t *i2c)\r
-{\r
- uint32_t status = i2cREG1->STR & (I2C_AL_INT | I2C_NACK_INT);\r
-\r
-/* USER CODE BEGIN (21) */\r
-/* USER CODE END */\r
-\r
- i2cREG1->STR = I2C_AL_INT | I2C_NACK_INT;\r
- \r
-/* USER CODE BEGIN (22) */\r
-/* USER CODE END */\r
- \r
- return status;\r
-\r
-}\r
-\r
-/** @fn void i2cClearSCD(i2cBASE_t *i2c)\r
-* @brief Clears the Stop condition detect flags.\r
-* @param[in] i2c - i2c module base address\r
-*\r
-* This sunction is called to clear the Stop condition detect(SCD) flag\r
-*/\r
-void i2cClearSCD(i2cBASE_t *i2c)\r
-{\r
-/* USER CODE BEGIN (23) */\r
-/* USER CODE END */\r
-\r
- i2cREG1->STR = I2C_SCD_INT;\r
- \r
-/* USER CODE BEGIN (24) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn uint32_t i2cReceiveByte(i2cBASE_t *i2c)\r
-* @brief Receive Byte\r
-* @param[in] i2c - i2c module base address\r
-*\r
-* @return Received byte\r
-*\r
-* Recieves a single byte in polling mode. If there is\r
-* not a byte in the receive buffer the routine will wait\r
-* until one is received. Use i2cIsRxReady to check to\r
-* see if the buffer is full to avoid waiting.\r
-*/\r
-uint32_t i2cReceiveByte(i2cBASE_t *i2c)\r
-{\r
- while ((i2cREG1->STR & I2C_RX_INT) == 0) { /* wait */ };\r
-\r
-/* USER CODE BEGIN (25) */\r
-/* USER CODE END */\r
-\r
- return i2cREG1->DRR;\r
-}\r
-\r
-/** @fn void i2cReceive(i2cBASE_t *i2c, uint32_t length, uint8_t *data)\r
-* @brief Receive Data\r
-* @param[in] i2c - i2c module base address\r
-* @param[in] length - number of data words to transfer\r
-* @param[in] data - pointer to data buffer\r
-*\r
-* Receive a block of 'length' bytes long and place it into the \r
-* data buffer pointed to by 'data'. If interrupts have been \r
-* enabled the data is received using interrupt mode, otherwise\r
-* polling mode is used. In interrupt mode receive is setup and\r
-* the routine returns imediatly, i2cReceive must not be called \r
-* again until the transfer is complete, when the i2cNotification \r
-* callback will be called. In polling mode, i2cReceive will not\r
-* return until the transfer is complete.\r
-*/\r
-void i2cReceive(i2cBASE_t *i2c, uint32_t length, uint8_t *data)\r
-{\r
-\r
-/* USER CODE BEGIN (26) */\r
-/* USER CODE END */\r
- if ((i2cREG1->IMR & I2C_RX_INT) != 0)\r
- {\r
- /* we are in interrupt mode */\r
- uint32_t index = i2c == i2cREG1 ? 0 : 1;\r
- \r
- /* clear error flags */\r
- i2cREG1->STR = I2C_AL_INT | I2C_NACK_INT;\r
-\r
- g_i2cTransfer[index].length = length;\r
- g_i2cTransfer[index].data = data;\r
- }\r
- else\r
- { \r
- while (length-- > 0)\r
- {\r
- while ((i2cREG1->STR & I2C_RX_INT) == 0) { /* wait */ };\r
- *data++ = i2cREG1->DRR;\r
- }\r
- }\r
-\r
-/* USER CODE BEGIN (27) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void i2cEnableLoopback(i2cBASE_t *i2c)\r
-* @brief Enable Loopback mode for self test\r
-* @param[in] i2c - i2c module base address\r
-*\r
-* This function enables the Loopback mode for self test.\r
-*/\r
-void i2cEnableLoopback(i2cBASE_t *i2c)\r
-{\r
-/* USER CODE BEGIN (28) */\r
-/* USER CODE END */\r
-\r
- /* enable digital loopback */\r
- i2cREG1->MDR |= (1 << 6); \r
-\r
-/* USER CODE BEGIN (29) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void i2cDisableLoopback(i2cBASE_t *i2c)\r
-* @brief Enable Loopback mode for self test\r
-* @param[in] i2c - i2c module base address\r
-*\r
-* This function disable the Loopback mode.\r
-*/\r
-void i2cDisableLoopback(i2cBASE_t *i2c)\r
-{\r
-/* USER CODE BEGIN (30) */\r
-/* USER CODE END */\r
- \r
- /* Disable Loopback Mode */\r
- i2cREG1->MDR &= 0xFFFFFFBF; \r
-\r
-/* USER CODE BEGIN (31) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn i2cEnableNotification(i2cBASE_t *i2c, uint32_t flags)\r
-* @brief Enable interrupts\r
-* @param[in] i2c - i2c module base address\r
-* @param[in] flags - Interrupts to be enabled, can be ored value of:\r
-* i2c_FE_INT - framming error,\r
-* i2c_OE_INT - overrun error,\r
-* i2c_PE_INT - parity error,\r
-* i2c_RX_INT - receive buffer ready,\r
-* i2c_TX_INT - transmit buffer ready,\r
-* i2c_WAKE_INT - wakeup,\r
-* i2c_BREAK_INT - break detect\r
-*/\r
-void i2cEnableNotification(i2cBASE_t *i2c, uint32_t flags)\r
-{\r
- uint32_t index = i2c == i2cREG1 ? 0 : 1;\r
-\r
-/* USER CODE BEGIN (32) */\r
-/* USER CODE END */\r
-\r
- g_i2cTransfer[index].mode |= (flags & I2C_TX_INT);\r
- i2cREG1->IMR = (flags & ~I2C_TX_INT);\r
-}\r
-\r
-/** @fn i2cDisableNotification(i2cBASE_t *i2c, uint32_t flags)\r
-* @brief Disable interrupts\r
-* @param[in] i2c - i2c module base address\r
-* @param[in] flags - Interrupts to be disabled, can be ored value of:\r
-* i2c_FE_INT - framming error,\r
-* i2c_OE_INT - overrun error,\r
-* i2c_PE_INT - parity error,\r
-* i2c_RX_INT - receive buffer ready,\r
-* i2c_TX_INT - transmit buffer ready,\r
-* i2c_WAKE_INT - wakeup,\r
-* i2c_BREAK_INT - break detect\r
-*/\r
-void i2cDisableNotification(i2cBASE_t *i2c, uint32_t flags)\r
-{\r
- uint32_t index = i2c == i2cREG1 ? 0 : 1;\r
-\r
-/* USER CODE BEGIN (33) */\r
-/* USER CODE END */\r
-\r
- g_i2cTransfer[index].mode &= ~(flags & I2C_TX_INT);\r
- i2cREG1->IMR = (flags & ~I2C_TX_INT);\r
-}\r
-\r
-/** @fn void i2cInterrupt(void)\r
-* @brief Interrupt for I2C\r
-*/\r
-#pragma INTERRUPT(i2cInterrupt, IRQ)\r
-\r
-void i2cInterrupt(void)\r
-{\r
- uint32_t vec = (i2cREG1->IVR & 0x00000007);\r
-\r
-/* USER CODE BEGIN (34) */\r
-/* USER CODE END */\r
-\r
- switch (vec)\r
- {\r
- case 1:\r
-/* USER CODE BEGIN (35) */\r
-/* USER CODE END */\r
- i2cNotification(i2cREG1, I2C_AL_INT);\r
- break;\r
- case 2:\r
-/* USER CODE BEGIN (36) */\r
-/* USER CODE END */\r
- i2cNotification(i2cREG1, I2C_NACK_INT);\r
- break;\r
- case 3:\r
-/* USER CODE BEGIN (37) */\r
-/* USER CODE END */\r
- i2cNotification(i2cREG1, I2C_ARDY_INT);\r
- break;\r
- case 4:\r
-/* USER CODE BEGIN (38) */\r
-/* USER CODE END */\r
- /* receive */\r
- { uint32_t byte = i2cREG1->DRR;\r
-\r
- if (g_i2cTransfer[0].length > 0)\r
- {\r
- *g_i2cTransfer[0].data++ = byte;\r
- g_i2cTransfer[0].length--;\r
- if (g_i2cTransfer[0].length == 0)\r
- {\r
- i2cNotification(i2cREG1, I2C_RX_INT);\r
- }\r
- }\r
- }\r
- break;\r
- case 5:\r
-/* USER CODE BEGIN (39) */\r
-/* USER CODE END */\r
- /* transmit */\r
- if (--g_i2cTransfer[0].length > 0)\r
- {\r
- i2cREG1->DXR = *g_i2cTransfer[0].data++;\r
- }\r
- else\r
- {\r
- i2cREG1->STR = I2C_TX_INT;\r
- i2cNotification(i2cREG1, I2C_TX_INT);\r
- }\r
- break;\r
-\r
-\r
- case 6:\r
-/* USER CODE BEGIN (40) */\r
-/* USER CODE END */\r
- /* transmit */ \r
- i2cNotification(i2cREG1, I2C_SCD_INT);\r
- break;\r
-\r
- case 7:\r
-/* USER CODE BEGIN (41) */\r
-/* USER CODE END */\r
- i2cNotification(i2cREG1, I2C_AAS_INT);\r
- break;\r
-\r
- default:\r
-/* USER CODE BEGIN (42) */\r
-/* USER CODE END */\r
- /* phantom interrupt, clear flags and return */\r
- i2cREG1->STR = 0x000007FF;\r
- break;\r
- }\r
-/* USER CODE BEGIN (43) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
+/** @file i2c.c
+* @brief I2C Driver Implementation File
+* @date 10.March.2012
+* @version 03.01.00
+*
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "ti_drv_i2c.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @struct g_I2CTransfer
+* @brief Interrupt mode globals
+*
+*/
+struct g_i2cTransfer
+{
+ uint32_t mode;
+ uint32_t length;
+ uint8_t *data;
+} g_i2cTransfer[2];
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/** @fn void i2cInit(void)
+* @brief Initializes the i2c Driver
+*
+* This function initializes the i2c module.
+*/
+void i2cInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+ /** @b intialize @b I2C */
+
+ /** - i2c out of reset */
+ i2cREG1->MDR = (1 << 5);
+
+ /** - set i2c mode */
+ i2cREG1->MDR = (0 << 15) /* nack mode */
+ | (0 << 14) /* free running */
+ | 0 /* start condtion - master mode only */
+ | (1 <<11) /* stop condtion */
+ | (1 <<10) /* Master/Slave mode */
+ | (I2C_TRANSMITTER) /* Transmitter/receiver */
+ | (I2C_7BIT_AMODE) /* xpanded address */
+ | (0 << 7) /* repeat mode */
+ | (0 << 6) /* digital loopback */
+ | (0 << 4) /* start byte - master only */
+ | (0) /* free data format */
+ | I2C_8_BIT; /* bit count */
+
+
+ /** - set i2c extended mode */
+ i2cREG1->EMDR = (0 << 25);
+
+ /** - set i2c data count */
+ i2cREG1->CNT = 3;
+
+ /** - disable all interrupts */
+ i2cREG1->IMR = 0x00U;
+
+ /** - set prescale */
+ i2cREG1->PSC = 9;
+
+ /** - set clock rate */
+ i2cREG1->CLKH = 35;
+ i2cREG1->CLKL = 35;
+
+ /** - set i2c pins functional mode */
+ i2cREG1->FUN = (0 );
+
+ /** - set i2c pins default output value */
+ i2cREG1->DOUT = (0 << 1) /* sda pin */
+ | (0); /* scl pin */
+
+ /** - set i2c pins output direction */
+ i2cREG1->DIR = (1 << 1) /* sda pin */
+ | (1); /* scl pin */
+
+ /** - set i2c pins open drain enable */
+ i2cREG1->ODR = (0 << 1) /* sda pin */
+ | (0); /* scl pin */
+
+ /** - set i2c pins pullup/pulldown enable */
+ i2cREG1->PD = (0 << 1) /* sda pin */
+ | (0); /* scl pin */
+
+ /** - set i2c pins pullup/pulldown select */
+ i2cREG1->PSL = (1 << 1) /* sda pin */
+ | (1); /* scl pin */
+
+ /** - set interrupt enable */
+ i2cREG1->IMR = (0 << 6) /* Address as slave interrupt */
+ | (0 << 5) /* Stop Condition detect interrupt */
+ | (1 << 4) /* Transmit data ready interrupt */
+ | (1 << 3) /* Receive data ready interrupt */
+ | (0 << 2) /* Register Access ready interrupt */
+ | (0 << 1) /* No Acknowledgement interrupt */
+ | (1); /* Arbitration Lost interrupt */
+
+ i2cREG1->MDR |= I2C_RESET_OUT; /* i2c out of reset */
+
+ /** - inialise global transfer variables */
+ g_i2cTransfer[0].mode = 1 << 8;
+ g_i2cTransfer[0].length = 0;
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+}
+
+/** @fn void i2cSetOwnAdd(i2cBASE_t *i2c, uint32_t oadd)
+* @brief Set I2C Own Address
+* @param[in] oadd - I2C Own address (7-bit or 10 -bit address)
+* @param[in] i2c - i2c module base address
+* Set the Own address of the I2C module.
+*/
+void i2cSetOwnAdd(i2cBASE_t *i2c, uint32_t oadd)
+{
+ i2cREG1->OAR = oadd; /* set own address */
+}
+
+/** @fn void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32_t sadd)
+* @brief Set Port Direction
+* @param[in] sadd - I2C Slave address
+* @param[in] i2c - i2c module base address
+* Set the Slave address to communicate which is must in Master mode.
+*/
+void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32_t sadd)
+{
+ i2cREG1->SAR = sadd; /* set slave address */
+}
+
+/** @fn void i2cSetBaudrate(i2cBASE_t *i2c, uint32_t baud)
+* @brief Change baudrate at runtime.
+* @param[in] i2c - i2c module base address
+* @param[in] baud - baudrate in KHz
+*
+* Change the i2c baudrate at runtime.
+*/
+void i2cSetBaudrate(i2cBASE_t *i2c, uint32_t baud)
+{
+ uint32_t prescale;
+ uint32_t d;
+ uint32_t ck;
+ double vclk = 80.000 * 1000000.0;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+ prescale = (uint32_t) ((vclk /8000000) - 1);
+
+ if(prescale>=2)
+ {
+ d = 5;
+ }
+ else
+ {
+ d = prescale ? 6 : 7;
+ }
+
+ ck = ((vclk)/(2*baud*1000*(prescale+1)))-d;
+
+ i2cREG1->PSC = prescale;
+ i2cREG1->CLKH = ck;
+ i2cREG1->CLKL = ck;
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+}
+
+/** @fn void i2cSetStart(i2cBASE_t *i2c)
+* @brief Set i2c start condition
+* @param[in] i2c - i2c module base address
+* Set i2c to generate a start bit (Only in Master mode)
+*/
+void i2cSetStart(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+ i2cREG1->MDR |= I2C_START_COND; /* set start condition */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+/** @fn void i2cSetStop(i2cBASE_t *i2c)
+* @brief Set i2c stop condition
+* @param[in] i2c - i2c module base address
+* Set i2c to generate a stop bit (Only in Master mode)
+*/
+void i2cSetStop(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+ i2cREG1->MDR |= I2C_STOP_COND; /* generate stop condition */
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+}
+
+/** @fn void i2cSetCount(i2cBASE_t *i2c,uint32_t cnt)
+* @brief Set i2c data count
+* @param[in] i2c - i2c module base address
+* @param[in] cnt - data count
+* Set i2c count to a transfer value after which the stop condition needs to be generated.
+* (Only in Master Mode)
+*/
+void i2cSetCount(i2cBASE_t *i2c ,uint32_t cnt)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ i2cREG1->CNT = cnt; /* set i2c count */
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+/** @fn uint32_t i2cIsTxReady(i2cBASE_t *i2c)
+* @brief Check if Tx buffer empty
+* @param[in] i2c - i2c module base address
+*
+* @return The TX ready flag
+*
+* Checks to see if the Tx buffer ready flag is set, returns
+* 0 is flags not set otherwise will return the Tx flag itself.
+*/
+uint32_t i2cIsTxReady(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ return i2cREG1->STR & I2C_TX_INT;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+}
+
+/** @fn void i2cSendByte(i2cBASE_t *i2c, uint8_t byte)
+* @brief Send Byte
+* @param[in] i2c - i2c module base address
+* @param[in] byte - byte to transfer
+*
+* Sends a single byte in polling mode, will wait in the
+* routine until the transmit buffer is empty before sending
+* the byte. Use i2cIsTxReady to check for Tx buffer empty
+* before calling i2cSendByte to avoid waiting.
+*/
+void i2cSendByte(i2cBASE_t *i2c, uint8_t byte)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ while ((i2cREG1->STR & I2C_TX_INT) == 0) { /* wait */ };
+ i2cREG1->DXR = byte;
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+}
+
+/** @fn void i2cSend(i2cBASE_t *i2c, uint32_t length, uint8_t *data)
+* @brief Send Data
+* @param[in] i2c - i2c module base address
+* @param[in] length - number of data words to transfer
+* @param[in] data - pointer to data to send
+*
+* Send a block of data pointed to by 'data' and 'length' bytes
+* long. If interrupts have been enabled the data is sent using
+* interrupt mode, otherwise polling mode is used. In interrupt
+* mode transmition of the first byte is started and the routine
+* returns imediatly, i2cSend must not be called again until the
+* transfer is complete, when the i2cNotification callback will
+* be called. In polling mode, i2cSend will not return until
+* the transfer is complete.
+*
+* @note if data word is less than 8 bits, then the data must be left
+* aligned in the data byte.
+*/
+void i2cSend(i2cBASE_t *i2c, uint32_t length, uint8_t *data)
+{
+ uint32_t index = i2c == i2cREG1 ? 0 : 1;
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ if ((g_i2cTransfer[index].mode & I2C_TX_INT) != 0)
+ {
+ /* we are in interrupt mode */
+
+ g_i2cTransfer[index].length = length;
+ g_i2cTransfer[index].data = data;
+
+ /* start transmit by sending first byte */
+ i2cREG1->DXR = *g_i2cTransfer[index].data++;
+ i2cREG1->IMR = I2C_TX_INT;
+ }
+ else
+ {
+ /* send the data */
+ while (length-- > 0)
+ {
+ while ((i2cREG1->STR & I2C_TX_INT) == 0) { /* wait */ };
+ i2cREG1->DXR = *data++;
+ }
+ }
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+/** @fn uint32_t i2cIsRxReady(i2cBASE_t *i2c)
+* @brief Check if Rx buffer full
+* @param[in] i2c - i2c module base address
+*
+* @return The Rx ready flag
+*
+* Checks to see if the Rx buffer full flag is set, returns
+* 0 is flags not set otherwise will return the Rx flag itself.
+*/
+uint32_t i2cIsRxReady(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ return i2cREG1->STR & I2C_RX_INT;
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+
+/** @fn uint32_t i2cRxError(i2cBASE_t *i2c)
+* @brief Return Rx Error flags
+* @param[in] i2c - i2c module base address
+*
+* @return The Rx error flags
+*
+* Returns the Rx framing, overun and parity errors flags,
+* also clears the error flags before returning.
+*/
+uint32_t i2cRxError(i2cBASE_t *i2c)
+{
+ uint32_t status = i2cREG1->STR & (I2C_AL_INT | I2C_NACK_INT);
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+ i2cREG1->STR = I2C_AL_INT | I2C_NACK_INT;
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+ return status;
+
+}
+
+/** @fn void i2cClearSCD(i2cBASE_t *i2c)
+* @brief Clears the Stop condition detect flags.
+* @param[in] i2c - i2c module base address
+*
+* This sunction is called to clear the Stop condition detect(SCD) flag
+*/
+void i2cClearSCD(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+ i2cREG1->STR = I2C_SCD_INT;
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+/** @fn uint32_t i2cReceiveByte(i2cBASE_t *i2c)
+* @brief Receive Byte
+* @param[in] i2c - i2c module base address
+*
+* @return Received byte
+*
+* Recieves a single byte in polling mode. If there is
+* not a byte in the receive buffer the routine will wait
+* until one is received. Use i2cIsRxReady to check to
+* see if the buffer is full to avoid waiting.
+*/
+uint32_t i2cReceiveByte(i2cBASE_t *i2c)
+{
+ while ((i2cREG1->STR & I2C_RX_INT) == 0) { /* wait */ };
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+ return i2cREG1->DRR;
+}
+
+/** @fn void i2cReceive(i2cBASE_t *i2c, uint32_t length, uint8_t *data)
+* @brief Receive Data
+* @param[in] i2c - i2c module base address
+* @param[in] length - number of data words to transfer
+* @param[in] data - pointer to data buffer
+*
+* Receive a block of 'length' bytes long and place it into the
+* data buffer pointed to by 'data'. If interrupts have been
+* enabled the data is received using interrupt mode, otherwise
+* polling mode is used. In interrupt mode receive is setup and
+* the routine returns imediatly, i2cReceive must not be called
+* again until the transfer is complete, when the i2cNotification
+* callback will be called. In polling mode, i2cReceive will not
+* return until the transfer is complete.
+*/
+void i2cReceive(i2cBASE_t *i2c, uint32_t length, uint8_t *data)
+{
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+ if ((i2cREG1->IMR & I2C_RX_INT) != 0)
+ {
+ /* we are in interrupt mode */
+ uint32_t index = i2c == i2cREG1 ? 0 : 1;
+
+ /* clear error flags */
+ i2cREG1->STR = I2C_AL_INT | I2C_NACK_INT;
+
+ g_i2cTransfer[index].length = length;
+ g_i2cTransfer[index].data = data;
+ }
+ else
+ {
+ while (length-- > 0)
+ {
+ while ((i2cREG1->STR & I2C_RX_INT) == 0) { /* wait */ };
+ *data++ = i2cREG1->DRR;
+ }
+ }
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+}
+
+/** @fn void i2cEnableLoopback(i2cBASE_t *i2c)
+* @brief Enable Loopback mode for self test
+* @param[in] i2c - i2c module base address
+*
+* This function enables the Loopback mode for self test.
+*/
+void i2cEnableLoopback(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ /* enable digital loopback */
+ i2cREG1->MDR |= (1 << 6);
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+}
+
+/** @fn void i2cDisableLoopback(i2cBASE_t *i2c)
+* @brief Enable Loopback mode for self test
+* @param[in] i2c - i2c module base address
+*
+* This function disable the Loopback mode.
+*/
+void i2cDisableLoopback(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+ /* Disable Loopback Mode */
+ i2cREG1->MDR &= 0xFFFFFFBF;
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+/** @fn i2cEnableNotification(i2cBASE_t *i2c, uint32_t flags)
+* @brief Enable interrupts
+* @param[in] i2c - i2c module base address
+* @param[in] flags - Interrupts to be enabled, can be ored value of:
+* i2c_FE_INT - framming error,
+* i2c_OE_INT - overrun error,
+* i2c_PE_INT - parity error,
+* i2c_RX_INT - receive buffer ready,
+* i2c_TX_INT - transmit buffer ready,
+* i2c_WAKE_INT - wakeup,
+* i2c_BREAK_INT - break detect
+*/
+void i2cEnableNotification(i2cBASE_t *i2c, uint32_t flags)
+{
+ uint32_t index = i2c == i2cREG1 ? 0 : 1;
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+ g_i2cTransfer[index].mode |= (flags & I2C_TX_INT);
+ i2cREG1->IMR = (flags & ~I2C_TX_INT);
+}
+
+/** @fn i2cDisableNotification(i2cBASE_t *i2c, uint32_t flags)
+* @brief Disable interrupts
+* @param[in] i2c - i2c module base address
+* @param[in] flags - Interrupts to be disabled, can be ored value of:
+* i2c_FE_INT - framming error,
+* i2c_OE_INT - overrun error,
+* i2c_PE_INT - parity error,
+* i2c_RX_INT - receive buffer ready,
+* i2c_TX_INT - transmit buffer ready,
+* i2c_WAKE_INT - wakeup,
+* i2c_BREAK_INT - break detect
+*/
+void i2cDisableNotification(i2cBASE_t *i2c, uint32_t flags)
+{
+ uint32_t index = i2c == i2cREG1 ? 0 : 1;
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+ g_i2cTransfer[index].mode &= ~(flags & I2C_TX_INT);
+ i2cREG1->IMR = (flags & ~I2C_TX_INT);
+}
+
+/** @fn void i2cInterrupt(void)
+* @brief Interrupt for I2C
+*/
+#pragma INTERRUPT(i2cInterrupt, IRQ)
+
+void i2cInterrupt(void)
+{
+ uint32_t vec = (i2cREG1->IVR & 0x00000007);
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+ switch (vec)
+ {
+ case 1:
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+ i2cNotification(i2cREG1, I2C_AL_INT);
+ break;
+ case 2:
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+ i2cNotification(i2cREG1, I2C_NACK_INT);
+ break;
+ case 3:
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+ i2cNotification(i2cREG1, I2C_ARDY_INT);
+ break;
+ case 4:
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+ /* receive */
+ { uint32_t byte = i2cREG1->DRR;
+
+ if (g_i2cTransfer[0].length > 0)
+ {
+ *g_i2cTransfer[0].data++ = byte;
+ g_i2cTransfer[0].length--;
+ if (g_i2cTransfer[0].length == 0)
+ {
+ i2cNotification(i2cREG1, I2C_RX_INT);
+ }
+ }
+ }
+ break;
+ case 5:
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+ /* transmit */
+ if (--g_i2cTransfer[0].length > 0)
+ {
+ i2cREG1->DXR = *g_i2cTransfer[0].data++;
+ }
+ else
+ {
+ i2cREG1->STR = I2C_TX_INT;
+ i2cNotification(i2cREG1, I2C_TX_INT);
+ }
+ break;
+
+
+ case 6:
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+ /* transmit */
+ i2cNotification(i2cREG1, I2C_SCD_INT);
+ break;
+
+ case 7:
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+ i2cNotification(i2cREG1, I2C_AAS_INT);
+ break;
+
+ default:
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+ /* phantom interrupt, clear flags and return */
+ i2cREG1->STR = 0x000007FF;
+ break;
+ }
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+}
+
+
-/** @file lin.c \r
-* @brief LIN Driver Implementation File\r
-* @date 20.Mar.2012\r
-* @version 03.01.00\r
-*\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-#include "ti_drv_lin.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-/** @fn void linInit(void)\r
-* @brief Initializes the lin Driver\r
-*\r
-* This function initializes the lin module.\r
-*/\r
-void linInit(void)\r
-{\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
- /** @b intalise @b LIN */\r
-\r
- /** - Release from reset */\r
- linREG->GCR0 = 1U;\r
-\r
- /** - Start LIN configuration \r
- * - Keep state machine in software reset\r
- */\r
- linREG->GCR1 = 00U;\r
-\r
- /** - Enable LIN Mode */\r
- linREG->GCR1 = 0x40U;\r
- \r
- /** - Setup control register 1\r
- * - Enable transmitter\r
- * - Enable receiver\r
- * - Stop when debug mode is entered\r
- * - Disable Loopback mode\r
- * - Disable / Enable HGENCTRL (Mask filtering with ID-Byte)\r
- * - Use enhance checksum\r
- * - Enable multi buffer mode\r
- * - Disable automatic baudrate adjustment\r
- * - Disable sleep mode\r
- * - Set LIN module as master\r
- * - Enable/Disable parity\r
- * - Disable data length control in ID4 and ID5\r
- */\r
- linREG->GCR1 |= 0x03000C60U \r
- | (1U << 12U)\r
- | (0U << 2U);\r
- \r
- /** - Setup maximum baud rate prescaler */\r
- linREG->MBRSR = 3600U;\r
-\r
- /** - Setup baud rate prescaler */\r
- linREG->BRSR = 249U;\r
-\r
- /** - Setup RX and TX reception masks */\r
- linREG->MASK = (0xFFU << 16U) | 0xFFU;\r
-\r
- /** - Setup compare\r
- * - Sync delimiter\r
- * - Sync break extension\r
- */\r
- linREG->COMP = ((1U - 1U) << 8U) | (13U - 13U);\r
-\r
- /** - Setup response length */\r
- linREG->LENGTH = (8U - 1U);\r
-\r
- /** - Set LIN pins functional mode \r
- * - TX\r
- * - RX\r
- * - CLK\r
- */\r
- linREG->FUN = 4U | 2U | 0U;\r
-\r
- /** - Set LIN pins default output value\r
- * - TX\r
- * - RX\r
- * - CLK\r
- */\r
- linREG->DOUT = 0U | 0U | 0U;\r
-\r
- /** - Set LIN pins output direction\r
- * - TX\r
- * - RX\r
- * - CLK\r
- */\r
- linREG->DIR = 0U | 0U | 0U;\r
-\r
- /** - Set LIN pins open drain enable\r
- * - TX\r
- * - RX\r
- * - CLK\r
- */\r
- linREG->ODR = 0U | 0U | 0U;\r
-\r
- /** - Set LIN pins pullup/pulldown enable\r
- * - TX\r
- * - RX\r
- * - CLK\r
- */\r
- linREG->PD = 0U | 0U | 0U;\r
-\r
- /** - Set LIN pins pullup/pulldown select\r
- * - TX\r
- * - RX\r
- * - CLK\r
- */\r
- linREG->PSL = 4U | 2U | 1U;\r
-\r
- /** - Set interrupt level \r
- * - Bit error level\r
- * - Physical bus error level\r
- * - Checksum error level\r
- * - Inconsistent sync field error level\r
- * - No response error level\r
- * - Framing error level\r
- * - Overrun error level\r
- * - Parity error level\r
- * - Identifier level\r
- * - RX level\r
- * - TX level\r
- * - Timeout after 3 wakeup signals level\r
- * - Timeout after wakeup signal level\r
- * - Timeout level\r
- * - Wakeup level\r
- * - Break detect level\r
- */\r
- linREG->SETINTLVL = 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Set interrupt enable \r
- * - Enable/Disable bit error\r
- * - Enable/Disable physical bus error level\r
- * - Enable/Disable checksum error level\r
- * - Enable/Disable inconsistent sync field error level\r
- * - Enable/Disable no response error level\r
- * - Enable/Disable framing error level\r
- * - Enable/Disable overrun error level\r
- * - Enable/Disable parity error level\r
- * - Enable/Disable identifier level\r
- * - Enable/Disable RX level\r
- * - Enable/Disable TX level\r
- * - Enable/Disable timeout after 3 wakeup signals level\r
- * - Enable/Disable timeout after wakeup signal level\r
- * - Enable/Disable timeout level\r
- * - Enable/Disable wakeup level\r
- * - Enable/Disable break detect level\r
- */\r
- linREG->SETINT = 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00002000U\r
- | 0x00000200U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U\r
- | 0x00000000U;\r
-\r
- /** - Finaly start LIN */\r
- linREG->GCR1 |= 0x00000080U;\r
-\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void linSetFunctional(linBASE_t *lin, uint32_t port)\r
-* @brief Change functional behavoiur of pins at runtime.\r
-* @param[in] lin - lin module base address\r
-* @param[in] port - Value to write to FUN register\r
-*\r
-* Change the value of the PCFUN register at runtime, this allows to\r
-* dynaimcaly change the functionality of the LIN pins between functional\r
-* and GIO mode.\r
-*/\r
-void linSetFunctional(linBASE_t *lin, uint32_t port)\r
-{\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-\r
- lin->FUN = port;\r
-\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void linSendHeader(linBASE_t *lin, uint8_t identifier)\r
-* @brief Send lin header.\r
-* @param[in] lin - lin module base address\r
-* @param[in] identifier - lin header id\r
-*\r
-* Send lin header including sync break field, sync field and identifier.\r
-*/\r
-void linSendHeader(linBASE_t *lin, uint8_t identifier)\r
-{\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
-\r
- lin->IDBYTE = identifier;\r
-\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void linSendWakupSignal(linBASE_t *lin)\r
-* @brief Send lin wakeup signal.\r
-* @param[in] lin - lin module base address\r
-*\r
-* Send lin wakeup signal to terminate the sleep mode of any lin node connected to the BUS.\r
-*/\r
-void linSendWakupSignal(linBASE_t *lin)\r
-{\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
-\r
- lin->TDx[0] = 0xF0;\r
- lin->GCR2 |= 0x00000100U;\r
-\r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void linEnterSleep(linBASE_t *lin)\r
-* @brief Take Module to Sleep.\r
-* @param[in] lin - lin module base address\r
-*\r
-* Application must call this function to take Module to Sleep when Sleep command is received.\r
-* This function can also be called to forcefully enter Sleep when no activity on BUS.\r
-*/\r
-void linEnterSleep(linBASE_t *lin)\r
-{\r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
- lin->GCR2 |= 0x00000001U;\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void linSoftwareReset(linBASE_t *lin)\r
-* @brief Perform sofware reset.\r
-* @param[in] lin - lin module base address\r
-*\r
-* Perform software reset of lin module.\r
-* This function will reset the lin state machine and clear all pending flags.\r
-* It is required to call this function after a wakeup signal has been sent.\r
-*/\r
-void linSoftwareReset(linBASE_t *lin)\r
-{\r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
-\r
- lin->GCR1 &= ~0x00000080U;\r
- lin->GCR1 |= 0x00000080U;\r
-\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn uint32_t linIsTxReady(linBASE_t *lin)\r
-* @brief Check if Tx buffer empty\r
-* @param[in] lin - lin module base address\r
-*\r
-* @return The TX ready flag\r
-*\r
-* Checks to see if the Tx buffer ready flag is set, returns\r
-* 0 is flags not set otherwise will return the Tx flag itself.\r
-*/\r
-uint32_t linIsTxReady(linBASE_t *lin)\r
-{\r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
-\r
- return lin->FLR & LIN_TX_READY;\r
-}\r
-\r
-/** @fn void linSetLength(linBASE_t *lin, uint32_t length)\r
-* @brief Send Data\r
-* @param[in] lin - lin module base address\r
-* @param[in] length - number of data words in bytes. Range: 1-8.\r
-*\r
-* Send data response length in bytes. \r
-*/\r
-void linSetLength(linBASE_t *lin, uint32_t length)\r
-{\r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
-\r
- lin->LENGTH = length - 1U;\r
-\r
-/* USER CODE BEGIN (16) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void linSend(linBASE_t *lin, const uint8_t *data)\r
-* @brief Send Data\r
-* @param[in] lin - lin module base address\r
-* @param[in] data - pointer to data to send\r
-*\r
-* Send a block of data pointed to by 'data'.\r
-* The number of data to transmit must be set with 'linSetLength' before. \r
-*/\r
-void linSend(linBASE_t *lin, const uint8_t *data)\r
-{\r
- int i;\r
- int length = lin->LENGTH;\r
- uint8_t *pData = (uint8_t *)data + length;\r
-\r
-/* USER CODE BEGIN (17) */\r
-/* USER CODE END */\r
-\r
- for (i = length; i >= 0; i--)\r
- {\r
- lin->TDx[i] = *pData--;\r
- }\r
-\r
-/* USER CODE BEGIN (18) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn uint32_t linIsRxReady(linBASE_t *lin)\r
-* @brief Check if Rx buffer full\r
-* @param[in] lin - lin module base address\r
-*\r
-* @return The Rx ready flag\r
-*\r
-* Checks to see if the Rx buffer full flag is set, returns\r
-* 0 is flags not set otherwise will return the Rx flag itself.\r
-*/\r
-uint32_t linIsRxReady(linBASE_t *lin)\r
-{\r
-/* USER CODE BEGIN (19) */\r
-/* USER CODE END */\r
-\r
- return lin->FLR & LIN_RX_INT;\r
-}\r
-\r
-\r
-/** @fn uint32_t linTxRxError(linBASE_t *lin)\r
-* @brief Return Tx and Rx Error flags\r
-* @param[in] lin - lin module base address\r
-*\r
-* @return The Tx and Rx error flags\r
-*\r
-* Returns the bit, physical bus, checksum, inconsisten sync field,\r
-* no response, framing, overun, parity and timeout error flags.\r
-* It also clears the error flags before returning.\r
-*/\r
-uint32_t linTxRxError(linBASE_t *lin)\r
-{\r
- uint32_t status = lin->FLR & (LIN_BE_INT \r
- | LIN_PBE_INT \r
- | LIN_CE_INT \r
- | LIN_ISFE_INT \r
- | LIN_NRE_INT \r
- | LIN_FE_INT \r
- | LIN_OE_INT \r
- | LIN_PE_INT \r
- | LIN_TOA3WUS_INT \r
- | LIN_TOAWUS_INT \r
- | LIN_TO_INT);\r
-\r
- lin->FLR = LIN_BE_INT \r
- | LIN_PBE_INT \r
- | LIN_CE_INT \r
- | LIN_ISFE_INT \r
- | LIN_NRE_INT \r
- | LIN_FE_INT \r
- | LIN_OE_INT \r
- | LIN_PE_INT \r
- | LIN_TOA3WUS_INT \r
- | LIN_TOAWUS_INT \r
- | LIN_TO_INT;\r
-\r
-/* USER CODE BEGIN (20) */\r
-/* USER CODE END */\r
-\r
- return status;\r
-}\r
-\r
-\r
-/** @fn uint32_t linGetIdentifier(linBASE_t *lin)\r
-* @brief Get last received identifier\r
-* @param[in] lin - lin module base address\r
-*\r
-* @return Identifier\r
-*\r
-* Read last received identifier.\r
-*/\r
-uint32_t linGetIdentifier(linBASE_t *lin)\r
-{\r
-/* USER CODE BEGIN (21) */\r
-/* USER CODE END */\r
- return lin->RXID;\r
-}\r
-\r
-\r
-/** @fn void linGetData(linBASE_t *lin, uint8_t * const data)\r
-* @brief Read received data\r
-* @param[in] lin - lin module base address\r
-* @param[in] data - pointer to data buffer\r
-*\r
-* Read a block of bytes and place it into the data buffer pointed to by 'data'.\r
-*/\r
-void linGetData(linBASE_t *lin, uint8_t * const data)\r
-{\r
- uint32_t i;\r
- uint32_t length = lin->LENGTH;\r
- uint8_t *pData = (uint8_t *)data;\r
-\r
-/* USER CODE BEGIN (22) */\r
-/* USER CODE END */\r
-\r
- for (i = 0U; i <= length; i++)\r
- {\r
- *pData++ = lin->RDx[i];\r
- }\r
-\r
-/* USER CODE BEGIN (23) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void linEnableLoopback(linBASE_t *lin, Loopbacktype_t Loopbacktype)\r
-* @brief Enable Loopback mode for self test\r
-* @param[in] lin - lin module base address\r
-* @param[in] Loopbacktype - Digital or Analog\r
-*\r
-* This function enables the Loopback mode for self test.\r
-*/\r
-void linEnableLoopback(linBASE_t *lin, Loopbacktype_t Loopbacktype)\r
-{\r
-/* USER CODE BEGIN (24) */\r
-/* USER CODE END */\r
- \r
- /* Clear Loopback incase enbaled already */\r
- lin->IODFTCTRL = 0;\r
- \r
- /* Enable Loopback either in Analog or Digital Mode */\r
- lin->IODFTCTRL = 0x00000A00\r
- | Loopbacktype << 1;\r
- \r
-/* USER CODE BEGIN (25) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void linDisableLoopback(linBASE_t *lin)\r
-* @brief Enable Loopback mode for self test\r
-* @param[in] lin - lin module base address\r
-*\r
-* This function disable the Loopback mode.\r
-*/\r
-void linDisableLoopback(linBASE_t *lin)\r
-{\r
-/* USER CODE BEGIN (26) */\r
-/* USER CODE END */\r
- \r
- /* Disable Loopback Mode */\r
- lin->IODFTCTRL = 0x000005000;\r
- \r
-/* USER CODE BEGIN (27) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn linEnableNotification(linBASE_t *lin, uint32_t flags)\r
-* @brief Enable interrupts\r
-* @param[in] lin - lin module base address\r
-* @param[in] flags - Interrupts to be enabled, can be ored value of:\r
-* LIN_BE_INT - bit error,\r
-* LIN_PBE_INT - physical bus error,\r
-* LIN_CE_INT - checksum error,\r
-* LIN_ISFE_INT - inconsistent sync field error,\r
-* LIN_NRE_INT - no response error,\r
-* LIN_FE_INT - framming error,\r
-* LIN_OE_INT - overrun error,\r
-* LIN_PE_INT - parity error,\r
-* LIN_ID_INT - received matching identifier,\r
-* LIN_RX_INT - receive buffer ready,\r
-* LIN_TOA3WUS_INT - time out after 3 wakeup signals,\r
-* LIN_TOAWUS_INT - time out after wakeup signal,\r
-* LIN_TO_INT - time out signal,\r
-* LIN_WAKEUP_INT - wakeup,\r
-* LIN_BREAK_INT - break detect\r
-*/\r
-void linEnableNotification(linBASE_t *lin, uint32_t flags)\r
-{\r
-/* USER CODE BEGIN (28) */\r
-/* USER CODE END */\r
-\r
- lin->SETINT = flags;\r
-\r
-/* USER CODE BEGIN (29) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn linDisableNotification(linBASE_t *lin, uint32_t flags)\r
-* @brief Disable interrupts\r
-* @param[in] lin - lin module base address\r
-* @param[in] flags - Interrupts to be disabled, can be ored value of:\r
-* LIN_BE_INT - bit error,\r
-* LIN_PBE_INT - physical bus error,\r
-* LIN_CE_INT - checksum error,\r
-* LIN_ISFE_INT - inconsistent sync field error,\r
-* LIN_NRE_INT - no response error,\r
-* LIN_FE_INT - framming error,\r
-* LIN_OE_INT - overrun error,\r
-* LIN_PE_INT - parity error,\r
-* LIN_ID_INT - received matching identifier,\r
-* LIN_RX_INT - receive buffer ready,\r
-* LIN_TOA3WUS_INT - time out after 3 wakeup signals,\r
-* LIN_TOAWUS_INT - time out after wakeup signal,\r
-* LIN_TO_INT - time out signal,\r
-* LIN_WAKEUP_INT - wakeup,\r
-* LIN_BREAK_INT - break detect\r
-*/\r
-void linDisableNotification(linBASE_t *lin, uint32_t flags)\r
-{\r
-/* USER CODE BEGIN (30) */\r
-/* USER CODE END */\r
-\r
- lin->CLRINT = flags;\r
-\r
-/* USER CODE BEGIN (31) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void linHighLevelInterrupt(void)\r
-* @brief Level 0 Interrupt for LIN\r
-*/\r
-#pragma INTERRUPT(linHighLevelInterrupt, IRQ)\r
-\r
-void linHighLevelInterrupt(void)\r
-{\r
- uint32_t vec = linREG->INTVECT0;\r
-\r
-/* USER CODE BEGIN (32) */\r
-/* USER CODE END */\r
-\r
- switch (vec)\r
- {\r
- case 1: linNotification(linREG, LIN_WAKEUP_INT); break;\r
- case 2: linNotification(linREG, LIN_ISFE_INT); break;\r
- case 3: linNotification(linREG, LIN_PE_INT); break;\r
- case 4: linNotification(linREG, LIN_ID_INT); break;\r
- case 5: linNotification(linREG, LIN_PBE_INT); break;\r
- case 6: linNotification(linREG, LIN_FE_INT); break;\r
- case 7: linNotification(linREG, LIN_BREAK_INT); break;\r
- case 8: linNotification(linREG, LIN_CE_INT); break;\r
- case 9: linNotification(linREG, LIN_OE_INT); break;\r
- case 10: linNotification(linREG, LIN_BE_INT); break;\r
- case 11: linNotification(linREG, LIN_RX_INT); break;\r
- case 13: linNotification(linREG, LIN_NRE_INT); break;\r
- case 14: linNotification(linREG, LIN_TOAWUS_INT); break;\r
- case 15: linNotification(linREG, LIN_TOA3WUS_INT); break;\r
- case 16: linNotification(linREG, LIN_TO_INT); break;\r
- default:\r
- /* phantom interrupt, perform software reset */\r
- linREG->GCR1 &= ~0x00000080U;\r
- linREG->GCR1 |= 0x00000080U;\r
- break;\r
- }\r
-/* USER CODE BEGIN (33) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void linLowLevelInterrupt(void)\r
-* @brief Level 1 Interrupt for LIN\r
-*/\r
-#pragma INTERRUPT(linLowLevelInterrupt, IRQ)\r
-\r
-void linLowLevelInterrupt(void)\r
-{\r
- uint32_t vec = linREG->INTVECT1;\r
-\r
-/* USER CODE BEGIN (34) */\r
-/* USER CODE END */\r
-\r
- switch (vec)\r
- {\r
- case 1: linNotification(linREG, LIN_WAKEUP_INT); break;\r
- case 2: linNotification(linREG, LIN_ISFE_INT); break;\r
- case 3: linNotification(linREG, LIN_PE_INT); break;\r
- case 4: linNotification(linREG, LIN_ID_INT); break;\r
- case 5: linNotification(linREG, LIN_PBE_INT); break;\r
- case 6: linNotification(linREG, LIN_FE_INT); break;\r
- case 7: linNotification(linREG, LIN_BREAK_INT); break;\r
- case 8: linNotification(linREG, LIN_CE_INT); break;\r
- case 9: linNotification(linREG, LIN_OE_INT); break;\r
- case 10: linNotification(linREG, LIN_BE_INT); break;\r
- case 11: linNotification(linREG, LIN_RX_INT); break;\r
- case 13: linNotification(linREG, LIN_NRE_INT); break;\r
- case 14: linNotification(linREG, LIN_TOAWUS_INT); break;\r
- case 15: linNotification(linREG, LIN_TOA3WUS_INT); break;\r
- case 16: linNotification(linREG, LIN_TO_INT); break;\r
- default:\r
- /* phantom interrupt, perform software reset */\r
- linREG->GCR1 &= ~0x00000080U;\r
- linREG->GCR1 |= 0x00000080U;\r
- break;\r
- }\r
-/* USER CODE BEGIN (35) */\r
-/* USER CODE END */\r
-}\r
-\r
+/** @file lin.c
+* @brief LIN Driver Implementation File
+* @date 20.Mar.2012
+* @version 03.01.00
+*
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "ti_drv_lin.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void linInit(void)
+* @brief Initializes the lin Driver
+*
+* This function initializes the lin module.
+*/
+void linInit(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+ /** @b intalise @b LIN */
+
+ /** - Release from reset */
+ linREG->GCR0 = 1U;
+
+ /** - Start LIN configuration
+ * - Keep state machine in software reset
+ */
+ linREG->GCR1 = 00U;
+
+ /** - Enable LIN Mode */
+ linREG->GCR1 = 0x40U;
+
+ /** - Setup control register 1
+ * - Enable transmitter
+ * - Enable receiver
+ * - Stop when debug mode is entered
+ * - Disable Loopback mode
+ * - Disable / Enable HGENCTRL (Mask filtering with ID-Byte)
+ * - Use enhance checksum
+ * - Enable multi buffer mode
+ * - Disable automatic baudrate adjustment
+ * - Disable sleep mode
+ * - Set LIN module as master
+ * - Enable/Disable parity
+ * - Disable data length control in ID4 and ID5
+ */
+ linREG->GCR1 |= 0x03000C60U
+ | (1U << 12U)
+ | (0U << 2U);
+
+ /** - Setup maximum baud rate prescaler */
+ linREG->MBRSR = 3600U;
+
+ /** - Setup baud rate prescaler */
+ linREG->BRSR = 249U;
+
+ /** - Setup RX and TX reception masks */
+ linREG->MASK = (0xFFU << 16U) | 0xFFU;
+
+ /** - Setup compare
+ * - Sync delimiter
+ * - Sync break extension
+ */
+ linREG->COMP = ((1U - 1U) << 8U) | (13U - 13U);
+
+ /** - Setup response length */
+ linREG->LENGTH = (8U - 1U);
+
+ /** - Set LIN pins functional mode
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->FUN = 4U | 2U | 0U;
+
+ /** - Set LIN pins default output value
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->DOUT = 0U | 0U | 0U;
+
+ /** - Set LIN pins output direction
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->DIR = 0U | 0U | 0U;
+
+ /** - Set LIN pins open drain enable
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->ODR = 0U | 0U | 0U;
+
+ /** - Set LIN pins pullup/pulldown enable
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->PD = 0U | 0U | 0U;
+
+ /** - Set LIN pins pullup/pulldown select
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->PSL = 4U | 2U | 1U;
+
+ /** - Set interrupt level
+ * - Bit error level
+ * - Physical bus error level
+ * - Checksum error level
+ * - Inconsistent sync field error level
+ * - No response error level
+ * - Framing error level
+ * - Overrun error level
+ * - Parity error level
+ * - Identifier level
+ * - RX level
+ * - TX level
+ * - Timeout after 3 wakeup signals level
+ * - Timeout after wakeup signal level
+ * - Timeout level
+ * - Wakeup level
+ * - Break detect level
+ */
+ linREG->SETINTLVL = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Set interrupt enable
+ * - Enable/Disable bit error
+ * - Enable/Disable physical bus error level
+ * - Enable/Disable checksum error level
+ * - Enable/Disable inconsistent sync field error level
+ * - Enable/Disable no response error level
+ * - Enable/Disable framing error level
+ * - Enable/Disable overrun error level
+ * - Enable/Disable parity error level
+ * - Enable/Disable identifier level
+ * - Enable/Disable RX level
+ * - Enable/Disable TX level
+ * - Enable/Disable timeout after 3 wakeup signals level
+ * - Enable/Disable timeout after wakeup signal level
+ * - Enable/Disable timeout level
+ * - Enable/Disable wakeup level
+ * - Enable/Disable break detect level
+ */
+ linREG->SETINT = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00002000U
+ | 0x00000200U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U;
+
+ /** - Finaly start LIN */
+ linREG->GCR1 |= 0x00000080U;
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+}
+
+
+/** @fn void linSetFunctional(linBASE_t *lin, uint32_t port)
+* @brief Change functional behavoiur of pins at runtime.
+* @param[in] lin - lin module base address
+* @param[in] port - Value to write to FUN register
+*
+* Change the value of the PCFUN register at runtime, this allows to
+* dynaimcaly change the functionality of the LIN pins between functional
+* and GIO mode.
+*/
+void linSetFunctional(linBASE_t *lin, uint32_t port)
+{
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+ lin->FUN = port;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+}
+
+
+/** @fn void linSendHeader(linBASE_t *lin, uint8_t identifier)
+* @brief Send lin header.
+* @param[in] lin - lin module base address
+* @param[in] identifier - lin header id
+*
+* Send lin header including sync break field, sync field and identifier.
+*/
+void linSendHeader(linBASE_t *lin, uint8_t identifier)
+{
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+ lin->IDBYTE = identifier;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+
+/** @fn void linSendWakupSignal(linBASE_t *lin)
+* @brief Send lin wakeup signal.
+* @param[in] lin - lin module base address
+*
+* Send lin wakeup signal to terminate the sleep mode of any lin node connected to the BUS.
+*/
+void linSendWakupSignal(linBASE_t *lin)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ lin->TDx[0] = 0xF0;
+ lin->GCR2 |= 0x00000100U;
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+}
+
+/** @fn void linEnterSleep(linBASE_t *lin)
+* @brief Take Module to Sleep.
+* @param[in] lin - lin module base address
+*
+* Application must call this function to take Module to Sleep when Sleep command is received.
+* This function can also be called to forcefully enter Sleep when no activity on BUS.
+*/
+void linEnterSleep(linBASE_t *lin)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+ lin->GCR2 |= 0x00000001U;
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+}
+
+/** @fn void linSoftwareReset(linBASE_t *lin)
+* @brief Perform sofware reset.
+* @param[in] lin - lin module base address
+*
+* Perform software reset of lin module.
+* This function will reset the lin state machine and clear all pending flags.
+* It is required to call this function after a wakeup signal has been sent.
+*/
+void linSoftwareReset(linBASE_t *lin)
+{
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+ lin->GCR1 &= ~0x00000080U;
+ lin->GCR1 |= 0x00000080U;
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+}
+
+/** @fn uint32_t linIsTxReady(linBASE_t *lin)
+* @brief Check if Tx buffer empty
+* @param[in] lin - lin module base address
+*
+* @return The TX ready flag
+*
+* Checks to see if the Tx buffer ready flag is set, returns
+* 0 is flags not set otherwise will return the Tx flag itself.
+*/
+uint32_t linIsTxReady(linBASE_t *lin)
+{
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+ return lin->FLR & LIN_TX_READY;
+}
+
+/** @fn void linSetLength(linBASE_t *lin, uint32_t length)
+* @brief Send Data
+* @param[in] lin - lin module base address
+* @param[in] length - number of data words in bytes. Range: 1-8.
+*
+* Send data response length in bytes.
+*/
+void linSetLength(linBASE_t *lin, uint32_t length)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ lin->LENGTH = length - 1U;
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+}
+
+/** @fn void linSend(linBASE_t *lin, const uint8_t *data)
+* @brief Send Data
+* @param[in] lin - lin module base address
+* @param[in] data - pointer to data to send
+*
+* Send a block of data pointed to by 'data'.
+* The number of data to transmit must be set with 'linSetLength' before.
+*/
+void linSend(linBASE_t *lin, const uint8_t *data)
+{
+ int i;
+ int length = lin->LENGTH;
+ uint8_t *pData = (uint8_t *)data + length;
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ for (i = length; i >= 0; i--)
+ {
+ lin->TDx[i] = *pData--;
+ }
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+/** @fn uint32_t linIsRxReady(linBASE_t *lin)
+* @brief Check if Rx buffer full
+* @param[in] lin - lin module base address
+*
+* @return The Rx ready flag
+*
+* Checks to see if the Rx buffer full flag is set, returns
+* 0 is flags not set otherwise will return the Rx flag itself.
+*/
+uint32_t linIsRxReady(linBASE_t *lin)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ return lin->FLR & LIN_RX_INT;
+}
+
+
+/** @fn uint32_t linTxRxError(linBASE_t *lin)
+* @brief Return Tx and Rx Error flags
+* @param[in] lin - lin module base address
+*
+* @return The Tx and Rx error flags
+*
+* Returns the bit, physical bus, checksum, inconsisten sync field,
+* no response, framing, overun, parity and timeout error flags.
+* It also clears the error flags before returning.
+*/
+uint32_t linTxRxError(linBASE_t *lin)
+{
+ uint32_t status = lin->FLR & (LIN_BE_INT
+ | LIN_PBE_INT
+ | LIN_CE_INT
+ | LIN_ISFE_INT
+ | LIN_NRE_INT
+ | LIN_FE_INT
+ | LIN_OE_INT
+ | LIN_PE_INT
+ | LIN_TOA3WUS_INT
+ | LIN_TOAWUS_INT
+ | LIN_TO_INT);
+
+ lin->FLR = LIN_BE_INT
+ | LIN_PBE_INT
+ | LIN_CE_INT
+ | LIN_ISFE_INT
+ | LIN_NRE_INT
+ | LIN_FE_INT
+ | LIN_OE_INT
+ | LIN_PE_INT
+ | LIN_TOA3WUS_INT
+ | LIN_TOAWUS_INT
+ | LIN_TO_INT;
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+ return status;
+}
+
+
+/** @fn uint32_t linGetIdentifier(linBASE_t *lin)
+* @brief Get last received identifier
+* @param[in] lin - lin module base address
+*
+* @return Identifier
+*
+* Read last received identifier.
+*/
+uint32_t linGetIdentifier(linBASE_t *lin)
+{
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+ return lin->RXID;
+}
+
+
+/** @fn void linGetData(linBASE_t *lin, uint8_t * const data)
+* @brief Read received data
+* @param[in] lin - lin module base address
+* @param[in] data - pointer to data buffer
+*
+* Read a block of bytes and place it into the data buffer pointed to by 'data'.
+*/
+void linGetData(linBASE_t *lin, uint8_t * const data)
+{
+ uint32_t i;
+ uint32_t length = lin->LENGTH;
+ uint8_t *pData = (uint8_t *)data;
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+ for (i = 0U; i <= length; i++)
+ {
+ *pData++ = lin->RDx[i];
+ }
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+}
+
+
+/** @fn void linEnableLoopback(linBASE_t *lin, Loopbacktype_t Loopbacktype)
+* @brief Enable Loopback mode for self test
+* @param[in] lin - lin module base address
+* @param[in] Loopbacktype - Digital or Analog
+*
+* This function enables the Loopback mode for self test.
+*/
+void linEnableLoopback(linBASE_t *lin, Loopbacktype_t Loopbacktype)
+{
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+ /* Clear Loopback incase enbaled already */
+ lin->IODFTCTRL = 0;
+
+ /* Enable Loopback either in Analog or Digital Mode */
+ lin->IODFTCTRL = 0x00000A00
+ | Loopbacktype << 1;
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+}
+
+/** @fn void linDisableLoopback(linBASE_t *lin)
+* @brief Enable Loopback mode for self test
+* @param[in] lin - lin module base address
+*
+* This function disable the Loopback mode.
+*/
+void linDisableLoopback(linBASE_t *lin)
+{
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+ /* Disable Loopback Mode */
+ lin->IODFTCTRL = 0x000005000;
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+}
+
+
+/** @fn linEnableNotification(linBASE_t *lin, uint32_t flags)
+* @brief Enable interrupts
+* @param[in] lin - lin module base address
+* @param[in] flags - Interrupts to be enabled, can be ored value of:
+* LIN_BE_INT - bit error,
+* LIN_PBE_INT - physical bus error,
+* LIN_CE_INT - checksum error,
+* LIN_ISFE_INT - inconsistent sync field error,
+* LIN_NRE_INT - no response error,
+* LIN_FE_INT - framming error,
+* LIN_OE_INT - overrun error,
+* LIN_PE_INT - parity error,
+* LIN_ID_INT - received matching identifier,
+* LIN_RX_INT - receive buffer ready,
+* LIN_TOA3WUS_INT - time out after 3 wakeup signals,
+* LIN_TOAWUS_INT - time out after wakeup signal,
+* LIN_TO_INT - time out signal,
+* LIN_WAKEUP_INT - wakeup,
+* LIN_BREAK_INT - break detect
+*/
+void linEnableNotification(linBASE_t *lin, uint32_t flags)
+{
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ lin->SETINT = flags;
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+}
+
+
+/** @fn linDisableNotification(linBASE_t *lin, uint32_t flags)
+* @brief Disable interrupts
+* @param[in] lin - lin module base address
+* @param[in] flags - Interrupts to be disabled, can be ored value of:
+* LIN_BE_INT - bit error,
+* LIN_PBE_INT - physical bus error,
+* LIN_CE_INT - checksum error,
+* LIN_ISFE_INT - inconsistent sync field error,
+* LIN_NRE_INT - no response error,
+* LIN_FE_INT - framming error,
+* LIN_OE_INT - overrun error,
+* LIN_PE_INT - parity error,
+* LIN_ID_INT - received matching identifier,
+* LIN_RX_INT - receive buffer ready,
+* LIN_TOA3WUS_INT - time out after 3 wakeup signals,
+* LIN_TOAWUS_INT - time out after wakeup signal,
+* LIN_TO_INT - time out signal,
+* LIN_WAKEUP_INT - wakeup,
+* LIN_BREAK_INT - break detect
+*/
+void linDisableNotification(linBASE_t *lin, uint32_t flags)
+{
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+ lin->CLRINT = flags;
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+
+/** @fn void linHighLevelInterrupt(void)
+* @brief Level 0 Interrupt for LIN
+*/
+#pragma INTERRUPT(linHighLevelInterrupt, IRQ)
+
+void linHighLevelInterrupt(void)
+{
+ uint32_t vec = linREG->INTVECT0;
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+ switch (vec)
+ {
+ case 1: linNotification(linREG, LIN_WAKEUP_INT); break;
+ case 2: linNotification(linREG, LIN_ISFE_INT); break;
+ case 3: linNotification(linREG, LIN_PE_INT); break;
+ case 4: linNotification(linREG, LIN_ID_INT); break;
+ case 5: linNotification(linREG, LIN_PBE_INT); break;
+ case 6: linNotification(linREG, LIN_FE_INT); break;
+ case 7: linNotification(linREG, LIN_BREAK_INT); break;
+ case 8: linNotification(linREG, LIN_CE_INT); break;
+ case 9: linNotification(linREG, LIN_OE_INT); break;
+ case 10: linNotification(linREG, LIN_BE_INT); break;
+ case 11: linNotification(linREG, LIN_RX_INT); break;
+ case 13: linNotification(linREG, LIN_NRE_INT); break;
+ case 14: linNotification(linREG, LIN_TOAWUS_INT); break;
+ case 15: linNotification(linREG, LIN_TOA3WUS_INT); break;
+ case 16: linNotification(linREG, LIN_TO_INT); break;
+ default:
+ /* phantom interrupt, perform software reset */
+ linREG->GCR1 &= ~0x00000080U;
+ linREG->GCR1 |= 0x00000080U;
+ break;
+ }
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+}
+
+
+/** @fn void linLowLevelInterrupt(void)
+* @brief Level 1 Interrupt for LIN
+*/
+#pragma INTERRUPT(linLowLevelInterrupt, IRQ)
+
+void linLowLevelInterrupt(void)
+{
+ uint32_t vec = linREG->INTVECT1;
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+ switch (vec)
+ {
+ case 1: linNotification(linREG, LIN_WAKEUP_INT); break;
+ case 2: linNotification(linREG, LIN_ISFE_INT); break;
+ case 3: linNotification(linREG, LIN_PE_INT); break;
+ case 4: linNotification(linREG, LIN_ID_INT); break;
+ case 5: linNotification(linREG, LIN_PBE_INT); break;
+ case 6: linNotification(linREG, LIN_FE_INT); break;
+ case 7: linNotification(linREG, LIN_BREAK_INT); break;
+ case 8: linNotification(linREG, LIN_CE_INT); break;
+ case 9: linNotification(linREG, LIN_OE_INT); break;
+ case 10: linNotification(linREG, LIN_BE_INT); break;
+ case 11: linNotification(linREG, LIN_RX_INT); break;
+ case 13: linNotification(linREG, LIN_NRE_INT); break;
+ case 14: linNotification(linREG, LIN_TOAWUS_INT); break;
+ case 15: linNotification(linREG, LIN_TOA3WUS_INT); break;
+ case 16: linNotification(linREG, LIN_TO_INT); break;
+ default:
+ /* phantom interrupt, perform software reset */
+ linREG->GCR1 &= ~0x00000080U;
+ linREG->GCR1 |= 0x00000080U;
+ break;
+ }
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+}
+
-/**\r
- * \file mdio.c\r
- *\r
- * \brief MDIO APIs.\r
- *\r
- * This file contains the device abstraction layer APIs for MDIO.\r
- */\r
-\r
-/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
- * ALL RIGHTS RESERVED\r
- */\r
-\r
-\r
-#include "sys_common.h"\r
-#include "hw_reg_access.h"\r
-#include "ti_drv_mdio.h"\r
-#include "hw_mdio.h"\r
-\r
-/*******************************************************************************\r
-* INTERNAL MACRO DEFINITIONS\r
-*******************************************************************************/\r
-#define PHY_REG_MASK (0x1Fu)\r
-#define PHY_ADDR_MASK (0x1Fu)\r
-#define PHY_DATA_MASK (0xFFFFu)\r
-#define PHY_REG_SHIFT (21u)\r
-#define PHY_ADDR_SHIFT (16u)\r
-\r
-/*******************************************************************************\r
-* API FUNCTION DEFINITIONS\r
-*******************************************************************************/\r
-\r
-/**\r
- * \brief Reads a PHY register using MDIO.\r
- *\r
- * \param baseAddr Base Address of the MDIO Module Registers.\r
- * \param phyAddr PHY Adress.\r
- * \param regNum Register Number to be read.\r
- * \param dataPtr Pointer where the read value shall be written.\r
- *\r
- * \return status of the read \n\r
- * TRUE - read is successful.\n\r
- * FALSE - read is not acknowledged properly.\r
- *\r
- **/\r
-unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned int phyAddr,\r
- unsigned int regNum, volatile unsigned short *dataPtr)\r
-{\r
- /* Wait till transaction completion if any */\r
- while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);\r
-\r
- HWREG(baseAddr + MDIO_USERACCESS0)\r
- = (MDIO_USERACCESS0_READ | MDIO_USERACCESS0_GO\r
- |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT)\r
- |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT));\r
-\r
- /* wait for command completion */\r
- while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);\r
-\r
- /* Store the data if the read is acknowledged */\r
- if((HWREG(baseAddr + MDIO_USERACCESS0)) & MDIO_USERACCESS0_ACK)\r
- {\r
- *dataPtr = (unsigned short)((HWREG(baseAddr + MDIO_USERACCESS0))\r
- & PHY_DATA_MASK);\r
- return TRUE;\r
- }\r
-\r
- return FALSE;\r
-}\r
-\r
-/**\r
- * \brief Writes a PHY register using MDIO.\r
- *\r
- * \param baseAddr Base Address of the MDIO Module Registers.\r
- * \param phyAddr PHY Adress.\r
- * \param regNum Register Number to be read.\r
- * \param RegVal Value to be written.\r
- *\r
- * \return None\r
- *\r
- **/\r
-void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int phyAddr,\r
- unsigned int regNum, unsigned short RegVal)\r
-{\r
- /* Wait till transaction completion if any */\r
- while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);\r
-\r
- HWREG(baseAddr + MDIO_USERACCESS0) =\r
- (MDIO_USERACCESS0_WRITE\r
- | MDIO_USERACCESS0_GO\r
- |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT)\r
- |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT)\r
- | RegVal);\r
-\r
- /* wait for command completion*/\r
- while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);\r
-}\r
-/**\r
- * \brief Reads the alive status of all PHY connected to this MDIO.\r
- * The bit correponding to the PHY address will be set if the PHY\r
- * is alive.\r
- *\r
- * \param baseAddr Base Address of the MDIO Module Registers.\r
- *\r
- * \return MDIO alive register state\r
- *\r
- **/\r
-unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr)\r
-{\r
- return (HWREG(baseAddr + MDIO_ALIVE));\r
-}\r
-\r
-/**\r
- * \brief Reads the link status of all PHY connected to this MDIO.\r
- * The bit correponding to the PHY address will be set if the PHY\r
- * link is active.\r
- *\r
- * \param baseAddr Base Address of the MDIO Module Registers.\r
- *\r
- * \return MDIO link register state\r
- *\r
- **/\r
-unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr)\r
-{\r
- return (HWREG(baseAddr + MDIO_LINK));\r
-}\r
-\r
-/**\r
- * \brief Initializes the MDIO peripheral. This enables the MDIO state\r
- * machine, uses standard pre-amble and set the clock divider value.\r
- *\r
- * \param baseAddr Base Address of the MDIO Module Registers.\r
- * \param mdioInputFreq The clock input to the MDIO module\r
- * \param mdioOutputFreq The clock output required on the MDIO bus\r
- * \return None\r
- *\r
- **/\r
-#define MDIO_CTRL_ENABLE_m (1 << 30)\r
-#define MDIO_CTRL_CLKDIV_m (0xff)\r
-#define MDIO_HIGHEST_USER_CHANNEL_m (0xf)\r
-#define MDIO_HIGHEST_USER_CHANNEL_sh 24\r
-\r
-void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,\r
- unsigned int mdioOutputFreq)\r
-{\r
- //HWREG(baseAddr + MDIO_CONTROL) = 0x41000020u;\r
-\r
- HWREG(baseAddr + MDIO_CONTROL) = (1 << MDIO_HIGHEST_USER_CHANNEL_sh) |\r
- MDIO_CTRL_ENABLE_m | (0x60 & MDIO_CTRL_CLKDIV_m);\r
-}\r
-\r
-/***************************** End Of File ***********************************/\r
+/**
+ * \file mdio.c
+ *
+ * \brief MDIO APIs.
+ *
+ * This file contains the device abstraction layer APIs for MDIO.
+ */
+
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * ALL RIGHTS RESERVED
+ */
+
+
+#include "sys_common.h"
+#include "hw_reg_access.h"
+#include "ti_drv_mdio.h"
+#include "hw_mdio.h"
+
+/*******************************************************************************
+* INTERNAL MACRO DEFINITIONS
+*******************************************************************************/
+#define PHY_REG_MASK (0x1Fu)
+#define PHY_ADDR_MASK (0x1Fu)
+#define PHY_DATA_MASK (0xFFFFu)
+#define PHY_REG_SHIFT (21u)
+#define PHY_ADDR_SHIFT (16u)
+
+/*******************************************************************************
+* API FUNCTION DEFINITIONS
+*******************************************************************************/
+
+/**
+ * \brief Reads a PHY register using MDIO.
+ *
+ * \param baseAddr Base Address of the MDIO Module Registers.
+ * \param phyAddr PHY Adress.
+ * \param regNum Register Number to be read.
+ * \param dataPtr Pointer where the read value shall be written.
+ *
+ * \return status of the read \n
+ * TRUE - read is successful.\n
+ * FALSE - read is not acknowledged properly.
+ *
+ **/
+unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned int phyAddr,
+ unsigned int regNum, volatile unsigned short *dataPtr)
+{
+ /* Wait till transaction completion if any */
+ while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
+
+ HWREG(baseAddr + MDIO_USERACCESS0)
+ = (MDIO_USERACCESS0_READ | MDIO_USERACCESS0_GO
+ |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT)
+ |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT));
+
+ /* wait for command completion */
+ while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
+
+ /* Store the data if the read is acknowledged */
+ if((HWREG(baseAddr + MDIO_USERACCESS0)) & MDIO_USERACCESS0_ACK)
+ {
+ *dataPtr = (unsigned short)((HWREG(baseAddr + MDIO_USERACCESS0))
+ & PHY_DATA_MASK);
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ * \brief Writes a PHY register using MDIO.
+ *
+ * \param baseAddr Base Address of the MDIO Module Registers.
+ * \param phyAddr PHY Adress.
+ * \param regNum Register Number to be read.
+ * \param RegVal Value to be written.
+ *
+ * \return None
+ *
+ **/
+void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int phyAddr,
+ unsigned int regNum, unsigned short RegVal)
+{
+ /* Wait till transaction completion if any */
+ while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
+
+ HWREG(baseAddr + MDIO_USERACCESS0) =
+ (MDIO_USERACCESS0_WRITE
+ | MDIO_USERACCESS0_GO
+ |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT)
+ |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT)
+ | RegVal);
+
+ /* wait for command completion*/
+ while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
+}
+/**
+ * \brief Reads the alive status of all PHY connected to this MDIO.
+ * The bit correponding to the PHY address will be set if the PHY
+ * is alive.
+ *
+ * \param baseAddr Base Address of the MDIO Module Registers.
+ *
+ * \return MDIO alive register state
+ *
+ **/
+unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr)
+{
+ return (HWREG(baseAddr + MDIO_ALIVE));
+}
+
+/**
+ * \brief Reads the link status of all PHY connected to this MDIO.
+ * The bit correponding to the PHY address will be set if the PHY
+ * link is active.
+ *
+ * \param baseAddr Base Address of the MDIO Module Registers.
+ *
+ * \return MDIO link register state
+ *
+ **/
+unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr)
+{
+ return (HWREG(baseAddr + MDIO_LINK));
+}
+
+/**
+ * \brief Initializes the MDIO peripheral. This enables the MDIO state
+ * machine, uses standard pre-amble and set the clock divider value.
+ *
+ * \param baseAddr Base Address of the MDIO Module Registers.
+ * \param mdioInputFreq The clock input to the MDIO module
+ * \param mdioOutputFreq The clock output required on the MDIO bus
+ * \return None
+ *
+ **/
+#define MDIO_CTRL_ENABLE_m (1 << 30)
+#define MDIO_CTRL_CLKDIV_m (0xff)
+#define MDIO_HIGHEST_USER_CHANNEL_m (0xf)
+#define MDIO_HIGHEST_USER_CHANNEL_sh 24
+
+void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,
+ unsigned int mdioOutputFreq)
+{
+ //HWREG(baseAddr + MDIO_CONTROL) = 0x41000020u;
+
+ HWREG(baseAddr + MDIO_CONTROL) = (1 << MDIO_HIGHEST_USER_CHANNEL_sh) |
+ MDIO_CTRL_ENABLE_m | (0x60 & MDIO_CTRL_CLKDIV_m);
+}
+
+/***************************** End Of File ***********************************/
-/** @file mibspi.c \r
-* @brief MIBSPI Driver Implementation File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-#include "ti_drv_mibspi.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-/* USER CODE END */\r
-\r
-/** @fn void mibspiInit(void)\r
-* @brief Initializes the MIBSPI Driver\r
-*\r
-* This function initializes the MIBSPI module.\r
-*/\r
-void mibspiInit(void)\r
-{\r
-int i ;\r
-\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
-\r
-\r
-\r
- /** @b intalise @b MIBSPI5 */\r
-\r
- /** bring MIBSPI out of reset */\r
- mibspiREG5->GCR0 = 1U;\r
- \r
- /** enable MIBSPI RAM Parity */\r
- mibspiREG5->EDEN = 0x00000005U;\r
-\r
- /** enable MIBSPI5 multibuffered mode and enable buffer RAM */\r
- mibspiREG5->MIBSPIE = 1U;\r
-\r
- /** MIBSPI5 master mode and clock configuration */\r
- mibspiREG5->GCR1 = (1 << 1) /* CLOKMOD */\r
- | 1; /* MASTER */\r
-\r
- /** MIBSPI5 enable pin configuration */\r
- mibspiREG5->ENAHIGHZ = 0; /* ENABLE HIGHZ */\r
-\r
- /** - Delays */\r
- mibspiREG5->DELAY = (0 << 24) /* C2TDELAY */\r
- | (0 << 16) /* T2CDELAY */\r
- | (0 << 8) /* T2EDELAY */\r
- | 0; /* C2EDELAY */\r
-\r
- /** - Data Format 0 */\r
- mibspiREG5->FMT0 = (0 << 24) /* wdelay */\r
- | (0 << 23) /* parity Polarity */\r
- | (0 << 22) /* parity enable */\r
- | (0 << 21) /* wait on enable */\r
- | (0 << 20) /* shift direction */\r
- | (0 << 17) /* clock polarity */\r
- | (0 << 16) /* clock phase */\r
- | (79 << 8) /* baudrate prescale */\r
- | 16; /* data word length */\r
-\r
- /** - Data Format 1 */\r
- mibspiREG5->FMT1 = (0 << 24) /* wdelay */\r
- | (0 << 23) /* parity Polarity */\r
- | (0 << 22) /* parity enable */\r
- | (0 << 21) /* wait on enable */\r
- | (0 << 20) /* shift direction */\r
- | (0 << 17) /* clock polarity */\r
- | (0 << 16) /* clock phase */\r
- | (79 << 8) /* baudrate prescale */\r
- | 16; /* data word length */\r
-\r
- /** - Data Format 2 */\r
- mibspiREG5->FMT2 = (0 << 24) /* wdelay */\r
- | (0 << 23) /* parity Polarity */\r
- | (0 << 22) /* parity enable */\r
- | (0 << 21) /* wait on enable */\r
- | (0 << 20) /* shift direction */\r
- | (0 << 17) /* clock polarity */\r
- | (0 << 16) /* clock phase */\r
- | (79 << 8) /* baudrate prescale */\r
- | 16; /* data word length */\r
-\r
- /** - Data Format 3 */\r
- mibspiREG5->FMT3 = (0 << 24) /* wdelay */\r
- | (0 << 23) /* parity Polarity */\r
- | (0 << 22) /* parity enable */\r
- | (0 << 21) /* wait on enable */\r
- | (0 << 20) /* shift direction */\r
- | (0 << 17) /* clock polarity */\r
- | (0 << 16) /* clock phase */\r
- | (79 << 8) /* baudrate prescale */\r
- | 16; /* data word length */\r
-\r
- /** - wait for buffer inialisation complete before accessing MibSPI registers */\r
- while ((mibspiREG5->BUFINIT) != 0) { /* wait */ } \r
-\r
- /** - inialise transfer groups */\r
- mibspiREG5->TGCTRL[0] = (1 << 30) /* oneshot */\r
- | (0 << 29) /* pcurrent reset */\r
- | (TRG_ALWAYS << 20) /* trigger event */\r
- | (TRG_DISABLED << 16) /* trigger source */\r
- | (0 << 8); /* start buffer */\r
-\r
- mibspiREG5->TGCTRL[1] = (1 << 30) /* oneshot */\r
- | (0 << 29) /* pcurrent reset */\r
- | (TRG_ALWAYS << 20) /* trigger event */\r
- | (TRG_DISABLED << 16) /* trigger source */\r
- | (8 << 8); /* start buffer */\r
-\r
- mibspiREG5->TGCTRL[2] = (1 << 30) /* oneshot */\r
- | (0 << 29) /* pcurrent reset */\r
- | (TRG_ALWAYS << 20) /* trigger event */\r
- | (TRG_DISABLED << 16) /* trigger source */\r
- | ((8+0) << 8); /* start buffer */\r
-\r
- mibspiREG5->TGCTRL[3] = (1 << 30) /* oneshot */\r
- | (0 << 29) /* pcurrent reset */\r
- | (TRG_ALWAYS << 20) /* trigger event */\r
- | (TRG_DISABLED << 16) /* trigger source */\r
- | ((8+0+0) << 8); /* start buffer */\r
-\r
- mibspiREG5->TGCTRL[4] = (1 << 30) /* oneshot */\r
- | (0 << 29) /* pcurrent reset */\r
- | (TRG_ALWAYS << 20) /* trigger event */\r
- | (TRG_DISABLED << 16) /* trigger source */\r
- | ((8+0+0+0) << 8); /* start buffer */\r
-\r
- mibspiREG5->TGCTRL[5] = (1 << 30) /* oneshot */\r
- | (0 << 29) /* pcurrent reset */\r
- | (TRG_ALWAYS << 20) /* trigger event */\r
- | (TRG_DISABLED << 16) /* trigger source */\r
- | ((8+0+0+0+0) << 8); /* start buffer */\r
-\r
- mibspiREG5->TGCTRL[6] = (1 << 30) /* oneshot */\r
- | (0 << 29) /* pcurrent reset */\r
- | (TRG_ALWAYS << 20) /* trigger event */\r
- | (TRG_DISABLED << 16) /* trigger source */\r
- | ((8+0+0+0+0+0) << 8); /* start buffer */\r
-\r
- mibspiREG5->TGCTRL[7] = (1 << 30) /* oneshot */\r
- | (0 << 29) /* pcurrent reset */\r
- | (TRG_ALWAYS << 20) /* trigger event */\r
- | (TRG_DISABLED << 16) /* trigger source */\r
- | ((8+0+0+0+0+0+0) << 8); /* start buffer */\r
-\r
- \r
- mibspiREG5->TGCTRL[8] = 8+0+0+0+0+0+0+0 << 8;\r
-\r
- mibspiREG5->LTGPEND = 8+0+0+0+0+0+0+0-1;\r
-\r
- /** - initalise buffer ram */\r
- { i = 0;\r
-\r
- if (8 > 0)\r
- {\r
- while (i < 8-1)\r
- {\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* hold chip select Based on Lock selection */\r
- | (0 << 11) /* lock transmission */\r
- | (0 << 8) /* data format */\r
- | CS_0; /* chip select */\r
- }\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* chip select hold */\r
- | (0 << 10) /* enable WDELAY */\r
- | (0 << 8) /* data format */\r
- | CS_0; /* chip select */\r
- }\r
- if (0 > 0)\r
- {\r
- while (i < 8+0-1)\r
- {\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* hold chip select Based on Lock selection */\r
- | (0 << 11) /* lock transmission */\r
- | (0 << 8) /* data format */\r
- | CS_1; /* chip select */\r
- }\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* chip select hold */\r
- | (0 << 10) /* enable WDELAY */\r
- | (0 << 8) /* data format */\r
- | CS_1; /* chip select */\r
- }\r
- if (0 > 0)\r
- {\r
- while (i < 8+0+0-1)\r
- {\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* hold chip select Based on Lock selection */\r
- | (0 << 11) /* lock transmission */\r
- | (0 << 8) /* data format */\r
- | CS_2; /* chip select */\r
- }\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* chip select hold */\r
- | (0 << 10) /* enable WDELAY */\r
- | (0 << 8) /* data format */\r
- | CS_2; /* chip select */\r
- }\r
- if (0 > 0)\r
- {\r
- while (i < 8+0+0+0-1)\r
- {\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* hold chip select Based on Lock selection */\r
- | (0 << 11) /* lock transmission */\r
- | (0 << 8) /* data format */\r
- | CS_3; /* chip select */\r
- }\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* chip select hold */\r
- | (0 << 10) /* enable WDELAY */\r
- | (0 << 8) /* data format */\r
- | CS_3; /* chip select */\r
- }\r
- if (0 > 0)\r
- {\r
- while (i < 8+0+0+0+0-1)\r
- {\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* hold chip select Based on Lock selection */\r
- | (0 << 11) /* lock transmission */\r
- | (0 << 8) /* data format */\r
- | CS_4; /* chip select */\r
- }\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* chip select hold */\r
- | (0 << 10) /* enable WDELAY */\r
- | (0 << 8) /* data format */\r
- | CS_4; /* chip select */\r
- }\r
- if (0 > 0)\r
- {\r
- while (i < 8+0+0+0+0+0-1)\r
- {\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* hold chip select Based on Lock selection */\r
- | (0 << 11) /* lock transmission */\r
- | (0 << 8) /* data format */\r
- | CS_5; /* chip select */\r
- }\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* chip select hold */\r
- | (0 << 10) /* enable WDELAY */\r
- | (0 << 8) /* data format */\r
- | CS_5; /* chip select */\r
- }\r
- if (0 > 0)\r
- {\r
- while (i < 8+0+0+0+0+0+0-1)\r
- {\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* hold chip select Based on Lock selection */\r
- | (0 << 11) /* lock transmission */\r
- | (0 << 8) /* data format */\r
- | CS_6; /* chip select */\r
- }\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* chip select hold */\r
- | (0 << 10) /* enable WDELAY */\r
- | (0 << 8) /* data format */\r
- | CS_6; /* chip select */\r
- }\r
- if (0 > 0)\r
- {\r
- while (i < 8+0+0+0+0+0+0+0-1)\r
- {\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* hold chip select Based on Lock selection */\r
- | (0 << 11) /* lock transmission */\r
- | (0 << 8) /* data format */\r
- | CS_7; /* chip select */\r
- }\r
- mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */\r
- | (0 << 12) /* chip select hold */\r
- | (0 << 10) /* enable WDELAY */\r
- | (0 << 8) /* data format */\r
- | CS_7; /* chip select */\r
- }\r
- }\r
-\r
- /** - set interrupt levels */\r
- mibspiREG5->LVL = (0 << 9) /* TXINT */\r
- | (0 << 8) /* RXINT */\r
- | (0 << 6) /* OVRNINT */\r
- | (0 << 4) /* BITERR */\r
- | (0 << 3) /* DESYNC */\r
- | (0 << 2) /* PARERR */\r
- | (0 << 1) /* TIMEOUT */\r
- | (0); /* DLENERR */\r
-\r
- /** - clear any pending interrupts */\r
- mibspiREG5->FLG = 0xFFFFU;\r
-\r
- /** - enable interrupts */\r
- mibspiREG5->INT0 = (0 << 9) /* TXINT */\r
- | (0 << 8) /* RXINT */\r
- | (0 << 6) /* OVRNINT */\r
- | (0 << 4) /* BITERR */\r
- | (0 << 3) /* DESYNC */\r
- | (0 << 2) /* PARERR */\r
- | (0 << 1) /* TIMEOUT */\r
- | (0); /* DLENERR */\r
-\r
- /** @b initalise @b MIBSPI5 @b Port */\r
-\r
- /** - MIBSPI5 Port output values */\r
- mibspiREG5->PCDOUT = 0 /* SCS[0] */\r
- | (0 << 1) /* SCS[1] */\r
- | (0 << 2) /* SCS[2] */\r
- | (0 << 3) /* SCS[3] */\r
- | (0 << 8) /* ENA */\r
- | (0 << 9) /* CLK */\r
- | (0 << 10) /* SIMO */\r
- | (0 << 19)\r
- | (0 << 25) \r
- | (0 << 26) \r
- | (0 << 27)\r
- | (0 << 17) \r
- | (0 << 18)\r
- | (0 << 11); /* SOMI */\r
-\r
- /** - MIBSPI5 Port direction */\r
- mibspiREG5->PCDIR = 1 /* SCS[0] */\r
- | (1 << 1) /* SCS[1] */\r
- | (1 << 2) /* SCS[2] */\r
- | (1 << 3) /* SCS[3] */\r
- | (0 << 8) /* ENA */\r
- | (1 << 9) /* CLK */\r
- | (1 << 10) /* SIMO */\r
- | (0 << 19)\r
- | (0 << 25) \r
- | (0 << 26) \r
- | (0 << 27)\r
- | (0 << 17) \r
- | (0 << 18)\r
- | (0 << 11); /* SOMI */\r
-\r
- /** - MIBSPI5 Port open drain enable */\r
- mibspiREG5->PCPDR = 0 /* SCS[0] */\r
- | (0 << 1) /* SCS[1] */\r
- | (0 << 2) /* SCS[2] */\r
- | (0 << 3) /* SCS[3] */\r
- | (0 << 8) /* ENA */\r
- | (0 << 9) /* CLK */\r
- | (0 << 10) /* SIMO */\r
- | (0 << 19)\r
- | (0 << 25) \r
- | (0 << 26) \r
- | (0 << 27)\r
- | (0 << 17) \r
- | (0 << 18)\r
- | (0 << 11); /* SOMI */\r
-\r
- /** - MIBSPI5 Port pullup / pulldown selection */\r
- mibspiREG5->PCPSL = 1 /* SCS[0] */\r
- | (1 << 1) /* SCS[1] */\r
- | (1 << 2) /* SCS[2] */\r
- | (1 << 3) /* SCS[3] */\r
- | (1 << 8) /* ENA */\r
- | (1 << 9) /* CLK */\r
- | (1 << 10) /* SIMO */\r
- | (1 << 19)\r
- | (1 << 25) \r
- | (1 << 26) \r
- | (1 << 27)\r
- | (1 << 17) \r
- | (1 << 18)\r
- | (1 << 11); /* SOMI */\r
-\r
- /** - MIBSPI5 Port pullup / pulldown enable*/\r
- mibspiREG5->PCDIS = 0 /* SCS[0] */\r
- | (0 << 1) /* SCS[1] */\r
- | (0 << 2) /* SCS[2] */\r
- | (0 << 3) /* SCS[3] */\r
- | (0 << 8) /* ENA */\r
- | (0 << 9) /* CLK */\r
- | (0 << 10) /* SIMO */\r
- | (0 << 19)\r
- | (0 << 25) \r
- | (0 << 26) \r
- | (0 << 27)\r
- | (0 << 17) \r
- | (0 << 18)\r
- | (0 << 11); /* SOMI */\r
-\r
- /* MIBSPI5 set all pins to functional */\r
- mibspiREG5->PCFUN = 1 /* SCS[0] */\r
- | (1 << 1) /* SCS[1] */\r
- | (1 << 2) /* SCS[2] */\r
- | (1 << 3) /* SCS[3] */\r
- | (1 << 8) /* ENA */\r
- | (1 << 9) /* CLK */\r
- | (1 << 10) /* SIMO */\r
- | (1 << 19)\r
- | (1 << 25) \r
- | (1 << 26) \r
- | (1 << 27)\r
- | (0 << 17) \r
- | (0 << 18)\r
- | (1 << 11); /* SOMI */\r
- \r
-\r
-\r
- /** - Finaly start MIBSPI5 */\r
- mibspiREG5->ENA = 1U;\r
-\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-\r
-}\r
-\r
-\r
-/** @fn void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32_t port)\r
-* @brief Change functional behavoiur of pins at runtime.\r
-* @param[in] mibspi - mibspi module base address\r
-* @param[in] port - Value to write to PCFUN register\r
-*\r
-* Change the value of the PCFUN register at runtime, this allows to\r
-* dynaimcaly change the functionality of the MIBSPI pins between functional\r
-* and GIO mode.\r
-*/\r
-void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32_t port)\r
-{\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-\r
- mibspi->PCFUN = port;\r
-\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void mibspiSetData(mibspiBASE_t *mibspi, uint32_t group, uint16_t data[])\r
-* @brief Set Buffer Data\r
-* @param[in] mibspi - Spi module base address\r
-* @param[in] group - Transfer group (0..7)\r
-* @param[in] data - new data for transfer group\r
-*\r
-* This function updates the data for the specified transfer group,\r
-* the length of the data must match the length of the transfer group.\r
-*/\r
-void mibspiSetData(mibspiBASE_t *mibspi, uint32_t group, uint16_t data[])\r
-{\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
-\r
- mibspiRAM_t *ram = mibspi == mibspiREG1 ? mibspiRAM1 : (mibspi == mibspiREG3 ? mibspiRAM3 : mibspiRAM5);\r
- uint32_t start = (mibspi->TGCTRL[group] >> 8) & 0xFF;\r
- uint32_t end = group == 7 ? (mibspi->LTGPEND + 1) : (mibspi->TGCTRL[group+1] >> 8) & 0xFF;\r
-\r
- if (end < start) {end = 128;}\r
-\r
- while (start < end)\r
- {\r
- ram->tx[start].data = *data++;\r
- start++;\r
- }\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void mibspiGetData(mibspiBASE_t *mibspi, uint32_t group, uint16_t data[])\r
-* @brief Retrieves Buffer Data fro receive buffer\r
-* @param[in] mibspi - Spi module base address\r
-* @param[in] group - Transfer group (0..7)\r
-* @param[out] data - pointer to data array\r
-*\r
-* @return error flags from data buffer, if there was a receive error on\r
-* one of the buffers this will be rerflected in the return value.\r
-*\r
-* This function transfers the data from the specified transfer group receve\r
-* buffers to the data array, the length of the data must match the length \r
-* of the transfer group.\r
-*/\r
-uint32_t mibspiGetData(mibspiBASE_t *mibspi, uint32_t group, uint16_t data[])\r
-{\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
-\r
- mibspiRAM_t *ram = mibspi == mibspiREG1 ? mibspiRAM1 : (mibspi == mibspiREG3 ? mibspiRAM3 : mibspiRAM5);\r
- uint32_t start = (mibspi->TGCTRL[group] >> 8) & 0xFF;\r
- uint32_t end = group == 7 ? (mibspi->LTGPEND + 1) : (mibspi->TGCTRL[group+1] >> 8) & 0xFF;\r
- uint32_t flags = 0;\r
-\r
- if (end < start) {end = 128;}\r
-\r
- while (start < end)\r
- {\r
- flags |= ram->rx[start].flags;\r
- *data++ = ram->rx[start].data;\r
- start++;\r
- }\r
-\r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
-\r
- return (flags >> 8) & 0x5F;\r
-}\r
-\r
-\r
-/** @fn void mibspiTransfer(mibspiBASE_t *mibspi, uint32_t group)\r
-* @brief Transmit Transfer Group\r
-* @param[in] mibspi - Spi module base address\r
-* @param[in] group - Transfer group (0..7)\r
-*\r
-* Initiates a transfer for the specified transfer group.\r
-*/\r
-void mibspiTransfer(mibspiBASE_t *mibspi, uint32_t group)\r
-{\r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
-\r
- mibspi->TGCTRL[group] |= 0x80000000;\r
-\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn int mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32_t group)\r
-* @brief Check for Transfer Group Ready\r
-* @param[in] mibspi - Spi module base address\r
-* @param[in] group - Transfer group (0..7)\r
-*\r
-* @return 1 is transfer complete, otherwise 0.\r
-*\r
-* Checks to see if the transfer for the specified transfer group\r
-* has finished.\r
-*/\r
-int mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32_t group)\r
-{\r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
- return (mibspi->INTFLGRDY >> group) & 1;\r
-}\r
-\r
-\r
-/** @fn void mibspiEnableLoopback(mibspiBASE_t *mibspi, Loopbacktype_t Loopbacktype)\r
-* @brief Enable Loopback mode for self test\r
-* @param[in] mibspi - Mibspi module base address\r
-* @param[in] Loopbacktype - Digital or Analog\r
-*\r
-* This function enables the Loopback mode for self test.\r
-*/\r
-void mibspiEnableLoopback(mibspiBASE_t *mibspi, Loopbacktype_t Loopbacktype)\r
-{\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
- \r
- /* Clear Loopback incase enbaled already */\r
- mibspi->IOLPKTSTCR = 0;\r
- \r
- /* Enable Loopback either in Analog or Digital Mode */\r
- mibspi->IOLPKTSTCR = 0x00000A00\r
- | Loopbacktype << 1;\r
- \r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void mibspiDisableLoopback(mibspiBASE_t *mibspi)\r
-* @brief Enable Loopback mode for self test\r
-* @param[in] mibspi - Mibspi module base address\r
-*\r
-* This function disable the Loopback mode.\r
-*/\r
-void mibspiDisableLoopback(mibspiBASE_t *mibspi)\r
-{\r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
- \r
- /* Disable Loopback Mode */\r
- mibspi->IOLPKTSTCR = 0x000005000;\r
- \r
-/* USER CODE BEGIN (16) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32_t group, uint32_t level)\r
-* @brief Enable Transfer Group interrupt\r
-* @param[in] mibspi - Spi module base address\r
-* @param[in] group - Transfer group (0..7)\r
-* @param[in] level - Interrupt level\r
-*\r
-* This function enables the transfer group finished interrupt.\r
-*/\r
-void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32_t group, uint32_t level)\r
-{\r
-/* USER CODE BEGIN (17) */\r
-/* USER CODE END */\r
-\r
- if (level != 0)\r
- {\r
- mibspi->SETINTLVLRDY = 1 << group;\r
- }\r
- else\r
- {\r
- mibspi->CLRINTLVLRDY = 1 << group;\r
- }\r
- mibspi->SETINTENARDY = 1 << group;\r
-\r
-/* USER CODE BEGIN (18) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32_t group)\r
-* @brief Disable Transfer Group interrupt\r
-* @param[in] mibspi - Spi module base address\r
-* @param[in] group - Transfer group (0..7)\r
-*\r
-* This function disables the transfer group finished interrupt.\r
-*/\r
-void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32_t group)\r
-{\r
-/* USER CODE BEGIN (19) */\r
-/* USER CODE END */\r
-\r
- mibspi->CLRINTENARDY = 1 << group;\r
-\r
-/* USER CODE BEGIN (20) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-\r
-/** @fn void mibspi5HighLevelInterrupt(void)\r
-* @brief Level 0 Interrupt for MIBSPI5\r
-*/\r
-#pragma INTERRUPT(mibspi5HighLevelInterrupt, IRQ)\r
-\r
-void mibspi5HighLevelInterrupt(void)\r
-{\r
- uint32_t vec = mibspiREG5->INTVECT0;\r
-\r
-/* USER CODE BEGIN (29) */\r
-/* USER CODE END */\r
-\r
- if (vec > 0x21U)\r
- {\r
- uint32_t flags = mibspiREG5->FLG & (~mibspiREG5->LVL & 0x035F);\r
- mibspiREG5->FLG = flags;\r
- mibspiNotification(mibspiREG5, flags);\r
- }\r
- else\r
- {\r
- mibspiGroupNotification(mibspiREG5, ((vec & 0x3FU) >> 1U) - 1U);\r
- }\r
-/* USER CODE BEGIN (30) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void mibspi5LowLevelInterrupt(void)\r
-* @brief Level 1 Interrupt for MIBSPI5\r
-*/\r
-#pragma INTERRUPT(mibspi5LowLevelInterrupt, IRQ)\r
-\r
-void mibspi5LowLevelInterrupt(void)\r
-{\r
- uint32_t vec = mibspiREG5->INTVECT1;\r
-\r
-/* USER CODE BEGIN (31) */\r
-/* USER CODE END */\r
-\r
- if (vec > 0x21U)\r
- {\r
- uint32_t flags = mibspiREG5->FLG & (mibspiREG5->LVL & 0x035F);\r
- mibspiREG5->FLG = flags;\r
- mibspiNotification(mibspiREG5, flags);\r
- }\r
- else\r
- {\r
- mibspiGroupNotification(mibspiREG5, ((vec & 0x3FU) >> 1U) - 1U);\r
- }\r
-/* USER CODE BEGIN (32) */\r
-/* USER CODE END */\r
-}\r
-\r
+/** @file mibspi.c
+* @brief MIBSPI Driver Implementation File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "ti_drv_mibspi.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void mibspiInit(void)
+* @brief Initializes the MIBSPI Driver
+*
+* This function initializes the MIBSPI module.
+*/
+void mibspiInit(void)
+{
+int i ;
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+
+
+ /** @b intalise @b MIBSPI5 */
+
+ /** bring MIBSPI out of reset */
+ mibspiREG5->GCR0 = 1U;
+
+ /** enable MIBSPI RAM Parity */
+ mibspiREG5->EDEN = 0x00000005U;
+
+ /** enable MIBSPI5 multibuffered mode and enable buffer RAM */
+ mibspiREG5->MIBSPIE = 1U;
+
+ /** MIBSPI5 master mode and clock configuration */
+ mibspiREG5->GCR1 = (1 << 1) /* CLOKMOD */
+ | 1; /* MASTER */
+
+ /** MIBSPI5 enable pin configuration */
+ mibspiREG5->ENAHIGHZ = 0; /* ENABLE HIGHZ */
+
+ /** - Delays */
+ mibspiREG5->DELAY = (0 << 24) /* C2TDELAY */
+ | (0 << 16) /* T2CDELAY */
+ | (0 << 8) /* T2EDELAY */
+ | 0; /* C2EDELAY */
+
+ /** - Data Format 0 */
+ mibspiREG5->FMT0 = (0 << 24) /* wdelay */
+ | (0 << 23) /* parity Polarity */
+ | (0 << 22) /* parity enable */
+ | (0 << 21) /* wait on enable */
+ | (0 << 20) /* shift direction */
+ | (0 << 17) /* clock polarity */
+ | (0 << 16) /* clock phase */
+ | (79 << 8) /* baudrate prescale */
+ | 16; /* data word length */
+
+ /** - Data Format 1 */
+ mibspiREG5->FMT1 = (0 << 24) /* wdelay */
+ | (0 << 23) /* parity Polarity */
+ | (0 << 22) /* parity enable */
+ | (0 << 21) /* wait on enable */
+ | (0 << 20) /* shift direction */
+ | (0 << 17) /* clock polarity */
+ | (0 << 16) /* clock phase */
+ | (79 << 8) /* baudrate prescale */
+ | 16; /* data word length */
+
+ /** - Data Format 2 */
+ mibspiREG5->FMT2 = (0 << 24) /* wdelay */
+ | (0 << 23) /* parity Polarity */
+ | (0 << 22) /* parity enable */
+ | (0 << 21) /* wait on enable */
+ | (0 << 20) /* shift direction */
+ | (0 << 17) /* clock polarity */
+ | (0 << 16) /* clock phase */
+ | (79 << 8) /* baudrate prescale */
+ | 16; /* data word length */
+
+ /** - Data Format 3 */
+ mibspiREG5->FMT3 = (0 << 24) /* wdelay */
+ | (0 << 23) /* parity Polarity */
+ | (0 << 22) /* parity enable */
+ | (0 << 21) /* wait on enable */
+ | (0 << 20) /* shift direction */
+ | (0 << 17) /* clock polarity */
+ | (0 << 16) /* clock phase */
+ | (79 << 8) /* baudrate prescale */
+ | 16; /* data word length */
+
+ /** - wait for buffer inialisation complete before accessing MibSPI registers */
+ while ((mibspiREG5->BUFINIT) != 0) { /* wait */ }
+
+ /** - inialise transfer groups */
+ mibspiREG5->TGCTRL[0] = (1 << 30) /* oneshot */
+ | (0 << 29) /* pcurrent reset */
+ | (TRG_ALWAYS << 20) /* trigger event */
+ | (TRG_DISABLED << 16) /* trigger source */
+ | (0 << 8); /* start buffer */
+
+ mibspiREG5->TGCTRL[1] = (1 << 30) /* oneshot */
+ | (0 << 29) /* pcurrent reset */
+ | (TRG_ALWAYS << 20) /* trigger event */
+ | (TRG_DISABLED << 16) /* trigger source */
+ | (8 << 8); /* start buffer */
+
+ mibspiREG5->TGCTRL[2] = (1 << 30) /* oneshot */
+ | (0 << 29) /* pcurrent reset */
+ | (TRG_ALWAYS << 20) /* trigger event */
+ | (TRG_DISABLED << 16) /* trigger source */
+ | ((8+0) << 8); /* start buffer */
+
+ mibspiREG5->TGCTRL[3] = (1 << 30) /* oneshot */
+ | (0 << 29) /* pcurrent reset */
+ | (TRG_ALWAYS << 20) /* trigger event */
+ | (TRG_DISABLED << 16) /* trigger source */
+ | ((8+0+0) << 8); /* start buffer */
+
+ mibspiREG5->TGCTRL[4] = (1 << 30) /* oneshot */
+ | (0 << 29) /* pcurrent reset */
+ | (TRG_ALWAYS << 20) /* trigger event */
+ | (TRG_DISABLED << 16) /* trigger source */
+ | ((8+0+0+0) << 8); /* start buffer */
+
+ mibspiREG5->TGCTRL[5] = (1 << 30) /* oneshot */
+ | (0 << 29) /* pcurrent reset */
+ | (TRG_ALWAYS << 20) /* trigger event */
+ | (TRG_DISABLED << 16) /* trigger source */
+ | ((8+0+0+0+0) << 8); /* start buffer */
+
+ mibspiREG5->TGCTRL[6] = (1 << 30) /* oneshot */
+ | (0 << 29) /* pcurrent reset */
+ | (TRG_ALWAYS << 20) /* trigger event */
+ | (TRG_DISABLED << 16) /* trigger source */
+ | ((8+0+0+0+0+0) << 8); /* start buffer */
+
+ mibspiREG5->TGCTRL[7] = (1 << 30) /* oneshot */
+ | (0 << 29) /* pcurrent reset */
+ | (TRG_ALWAYS << 20) /* trigger event */
+ | (TRG_DISABLED << 16) /* trigger source */
+ | ((8+0+0+0+0+0+0) << 8); /* start buffer */
+
+
+ mibspiREG5->TGCTRL[8] = 8+0+0+0+0+0+0+0 << 8;
+
+ mibspiREG5->LTGPEND = 8+0+0+0+0+0+0+0-1;
+
+ /** - initalise buffer ram */
+ { i = 0;
+
+ if (8 > 0)
+ {
+ while (i < 8-1)
+ {
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* hold chip select Based on Lock selection */
+ | (0 << 11) /* lock transmission */
+ | (0 << 8) /* data format */
+ | CS_0; /* chip select */
+ }
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* chip select hold */
+ | (0 << 10) /* enable WDELAY */
+ | (0 << 8) /* data format */
+ | CS_0; /* chip select */
+ }
+ if (0 > 0)
+ {
+ while (i < 8+0-1)
+ {
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* hold chip select Based on Lock selection */
+ | (0 << 11) /* lock transmission */
+ | (0 << 8) /* data format */
+ | CS_1; /* chip select */
+ }
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* chip select hold */
+ | (0 << 10) /* enable WDELAY */
+ | (0 << 8) /* data format */
+ | CS_1; /* chip select */
+ }
+ if (0 > 0)
+ {
+ while (i < 8+0+0-1)
+ {
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* hold chip select Based on Lock selection */
+ | (0 << 11) /* lock transmission */
+ | (0 << 8) /* data format */
+ | CS_2; /* chip select */
+ }
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* chip select hold */
+ | (0 << 10) /* enable WDELAY */
+ | (0 << 8) /* data format */
+ | CS_2; /* chip select */
+ }
+ if (0 > 0)
+ {
+ while (i < 8+0+0+0-1)
+ {
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* hold chip select Based on Lock selection */
+ | (0 << 11) /* lock transmission */
+ | (0 << 8) /* data format */
+ | CS_3; /* chip select */
+ }
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* chip select hold */
+ | (0 << 10) /* enable WDELAY */
+ | (0 << 8) /* data format */
+ | CS_3; /* chip select */
+ }
+ if (0 > 0)
+ {
+ while (i < 8+0+0+0+0-1)
+ {
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* hold chip select Based on Lock selection */
+ | (0 << 11) /* lock transmission */
+ | (0 << 8) /* data format */
+ | CS_4; /* chip select */
+ }
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* chip select hold */
+ | (0 << 10) /* enable WDELAY */
+ | (0 << 8) /* data format */
+ | CS_4; /* chip select */
+ }
+ if (0 > 0)
+ {
+ while (i < 8+0+0+0+0+0-1)
+ {
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* hold chip select Based on Lock selection */
+ | (0 << 11) /* lock transmission */
+ | (0 << 8) /* data format */
+ | CS_5; /* chip select */
+ }
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* chip select hold */
+ | (0 << 10) /* enable WDELAY */
+ | (0 << 8) /* data format */
+ | CS_5; /* chip select */
+ }
+ if (0 > 0)
+ {
+ while (i < 8+0+0+0+0+0+0-1)
+ {
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* hold chip select Based on Lock selection */
+ | (0 << 11) /* lock transmission */
+ | (0 << 8) /* data format */
+ | CS_6; /* chip select */
+ }
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* chip select hold */
+ | (0 << 10) /* enable WDELAY */
+ | (0 << 8) /* data format */
+ | CS_6; /* chip select */
+ }
+ if (0 > 0)
+ {
+ while (i < 8+0+0+0+0+0+0+0-1)
+ {
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* hold chip select Based on Lock selection */
+ | (0 << 11) /* lock transmission */
+ | (0 << 8) /* data format */
+ | CS_7; /* chip select */
+ }
+ mibspiRAM5->tx[i++].control = (4 << 13) /* buffer mode */
+ | (0 << 12) /* chip select hold */
+ | (0 << 10) /* enable WDELAY */
+ | (0 << 8) /* data format */
+ | CS_7; /* chip select */
+ }
+ }
+
+ /** - set interrupt levels */
+ mibspiREG5->LVL = (0 << 9) /* TXINT */
+ | (0 << 8) /* RXINT */
+ | (0 << 6) /* OVRNINT */
+ | (0 << 4) /* BITERR */
+ | (0 << 3) /* DESYNC */
+ | (0 << 2) /* PARERR */
+ | (0 << 1) /* TIMEOUT */
+ | (0); /* DLENERR */
+
+ /** - clear any pending interrupts */
+ mibspiREG5->FLG = 0xFFFFU;
+
+ /** - enable interrupts */
+ mibspiREG5->INT0 = (0 << 9) /* TXINT */
+ | (0 << 8) /* RXINT */
+ | (0 << 6) /* OVRNINT */
+ | (0 << 4) /* BITERR */
+ | (0 << 3) /* DESYNC */
+ | (0 << 2) /* PARERR */
+ | (0 << 1) /* TIMEOUT */
+ | (0); /* DLENERR */
+
+ /** @b initalise @b MIBSPI5 @b Port */
+
+ /** - MIBSPI5 Port output values */
+ mibspiREG5->PCDOUT = 0 /* SCS[0] */
+ | (0 << 1) /* SCS[1] */
+ | (0 << 2) /* SCS[2] */
+ | (0 << 3) /* SCS[3] */
+ | (0 << 8) /* ENA */
+ | (0 << 9) /* CLK */
+ | (0 << 10) /* SIMO */
+ | (0 << 19)
+ | (0 << 25)
+ | (0 << 26)
+ | (0 << 27)
+ | (0 << 17)
+ | (0 << 18)
+ | (0 << 11); /* SOMI */
+
+ /** - MIBSPI5 Port direction */
+ mibspiREG5->PCDIR = 1 /* SCS[0] */
+ | (1 << 1) /* SCS[1] */
+ | (1 << 2) /* SCS[2] */
+ | (1 << 3) /* SCS[3] */
+ | (0 << 8) /* ENA */
+ | (1 << 9) /* CLK */
+ | (1 << 10) /* SIMO */
+ | (0 << 19)
+ | (0 << 25)
+ | (0 << 26)
+ | (0 << 27)
+ | (0 << 17)
+ | (0 << 18)
+ | (0 << 11); /* SOMI */
+
+ /** - MIBSPI5 Port open drain enable */
+ mibspiREG5->PCPDR = 0 /* SCS[0] */
+ | (0 << 1) /* SCS[1] */
+ | (0 << 2) /* SCS[2] */
+ | (0 << 3) /* SCS[3] */
+ | (0 << 8) /* ENA */
+ | (0 << 9) /* CLK */
+ | (0 << 10) /* SIMO */
+ | (0 << 19)
+ | (0 << 25)
+ | (0 << 26)
+ | (0 << 27)
+ | (0 << 17)
+ | (0 << 18)
+ | (0 << 11); /* SOMI */
+
+ /** - MIBSPI5 Port pullup / pulldown selection */
+ mibspiREG5->PCPSL = 1 /* SCS[0] */
+ | (1 << 1) /* SCS[1] */
+ | (1 << 2) /* SCS[2] */
+ | (1 << 3) /* SCS[3] */
+ | (1 << 8) /* ENA */
+ | (1 << 9) /* CLK */
+ | (1 << 10) /* SIMO */
+ | (1 << 19)
+ | (1 << 25)
+ | (1 << 26)
+ | (1 << 27)
+ | (1 << 17)
+ | (1 << 18)
+ | (1 << 11); /* SOMI */
+
+ /** - MIBSPI5 Port pullup / pulldown enable*/
+ mibspiREG5->PCDIS = 0 /* SCS[0] */
+ | (0 << 1) /* SCS[1] */
+ | (0 << 2) /* SCS[2] */
+ | (0 << 3) /* SCS[3] */
+ | (0 << 8) /* ENA */
+ | (0 << 9) /* CLK */
+ | (0 << 10) /* SIMO */
+ | (0 << 19)
+ | (0 << 25)
+ | (0 << 26)
+ | (0 << 27)
+ | (0 << 17)
+ | (0 << 18)
+ | (0 << 11); /* SOMI */
+
+ /* MIBSPI5 set all pins to functional */
+ mibspiREG5->PCFUN = 1 /* SCS[0] */
+ | (1 << 1) /* SCS[1] */
+ | (1 << 2) /* SCS[2] */
+ | (1 << 3) /* SCS[3] */
+ | (1 << 8) /* ENA */
+ | (1 << 9) /* CLK */
+ | (1 << 10) /* SIMO */
+ | (1 << 19)
+ | (1 << 25)
+ | (1 << 26)
+ | (1 << 27)
+ | (0 << 17)
+ | (0 << 18)
+ | (1 << 11); /* SOMI */
+
+
+
+ /** - Finaly start MIBSPI5 */
+ mibspiREG5->ENA = 1U;
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+}
+
+
+/** @fn void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32_t port)
+* @brief Change functional behavoiur of pins at runtime.
+* @param[in] mibspi - mibspi module base address
+* @param[in] port - Value to write to PCFUN register
+*
+* Change the value of the PCFUN register at runtime, this allows to
+* dynaimcaly change the functionality of the MIBSPI pins between functional
+* and GIO mode.
+*/
+void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32_t port)
+{
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+ mibspi->PCFUN = port;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+}
+
+
+/** @fn void mibspiSetData(mibspiBASE_t *mibspi, uint32_t group, uint16_t data[])
+* @brief Set Buffer Data
+* @param[in] mibspi - Spi module base address
+* @param[in] group - Transfer group (0..7)
+* @param[in] data - new data for transfer group
+*
+* This function updates the data for the specified transfer group,
+* the length of the data must match the length of the transfer group.
+*/
+void mibspiSetData(mibspiBASE_t *mibspi, uint32_t group, uint16_t data[])
+{
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+ mibspiRAM_t *ram = mibspi == mibspiREG1 ? mibspiRAM1 : (mibspi == mibspiREG3 ? mibspiRAM3 : mibspiRAM5);
+ uint32_t start = (mibspi->TGCTRL[group] >> 8) & 0xFF;
+ uint32_t end = group == 7 ? (mibspi->LTGPEND + 1) : (mibspi->TGCTRL[group+1] >> 8) & 0xFF;
+
+ if (end < start) {end = 128;}
+
+ while (start < end)
+ {
+ ram->tx[start].data = *data++;
+ start++;
+ }
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+
+/** @fn void mibspiGetData(mibspiBASE_t *mibspi, uint32_t group, uint16_t data[])
+* @brief Retrieves Buffer Data fro receive buffer
+* @param[in] mibspi - Spi module base address
+* @param[in] group - Transfer group (0..7)
+* @param[out] data - pointer to data array
+*
+* @return error flags from data buffer, if there was a receive error on
+* one of the buffers this will be rerflected in the return value.
+*
+* This function transfers the data from the specified transfer group receve
+* buffers to the data array, the length of the data must match the length
+* of the transfer group.
+*/
+uint32_t mibspiGetData(mibspiBASE_t *mibspi, uint32_t group, uint16_t data[])
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ mibspiRAM_t *ram = mibspi == mibspiREG1 ? mibspiRAM1 : (mibspi == mibspiREG3 ? mibspiRAM3 : mibspiRAM5);
+ uint32_t start = (mibspi->TGCTRL[group] >> 8) & 0xFF;
+ uint32_t end = group == 7 ? (mibspi->LTGPEND + 1) : (mibspi->TGCTRL[group+1] >> 8) & 0xFF;
+ uint32_t flags = 0;
+
+ if (end < start) {end = 128;}
+
+ while (start < end)
+ {
+ flags |= ram->rx[start].flags;
+ *data++ = ram->rx[start].data;
+ start++;
+ }
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+ return (flags >> 8) & 0x5F;
+}
+
+
+/** @fn void mibspiTransfer(mibspiBASE_t *mibspi, uint32_t group)
+* @brief Transmit Transfer Group
+* @param[in] mibspi - Spi module base address
+* @param[in] group - Transfer group (0..7)
+*
+* Initiates a transfer for the specified transfer group.
+*/
+void mibspiTransfer(mibspiBASE_t *mibspi, uint32_t group)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+ mibspi->TGCTRL[group] |= 0x80000000;
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+}
+
+
+/** @fn int mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32_t group)
+* @brief Check for Transfer Group Ready
+* @param[in] mibspi - Spi module base address
+* @param[in] group - Transfer group (0..7)
+*
+* @return 1 is transfer complete, otherwise 0.
+*
+* Checks to see if the transfer for the specified transfer group
+* has finished.
+*/
+int mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32_t group)
+{
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+ return (mibspi->INTFLGRDY >> group) & 1;
+}
+
+
+/** @fn void mibspiEnableLoopback(mibspiBASE_t *mibspi, Loopbacktype_t Loopbacktype)
+* @brief Enable Loopback mode for self test
+* @param[in] mibspi - Mibspi module base address
+* @param[in] Loopbacktype - Digital or Analog
+*
+* This function enables the Loopback mode for self test.
+*/
+void mibspiEnableLoopback(mibspiBASE_t *mibspi, Loopbacktype_t Loopbacktype)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ /* Clear Loopback incase enbaled already */
+ mibspi->IOLPKTSTCR = 0;
+
+ /* Enable Loopback either in Analog or Digital Mode */
+ mibspi->IOLPKTSTCR = 0x00000A00
+ | Loopbacktype << 1;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+}
+
+/** @fn void mibspiDisableLoopback(mibspiBASE_t *mibspi)
+* @brief Enable Loopback mode for self test
+* @param[in] mibspi - Mibspi module base address
+*
+* This function disable the Loopback mode.
+*/
+void mibspiDisableLoopback(mibspiBASE_t *mibspi)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ /* Disable Loopback Mode */
+ mibspi->IOLPKTSTCR = 0x000005000;
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+}
+
+
+/** @fn void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32_t group, uint32_t level)
+* @brief Enable Transfer Group interrupt
+* @param[in] mibspi - Spi module base address
+* @param[in] group - Transfer group (0..7)
+* @param[in] level - Interrupt level
+*
+* This function enables the transfer group finished interrupt.
+*/
+void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32_t group, uint32_t level)
+{
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ if (level != 0)
+ {
+ mibspi->SETINTLVLRDY = 1 << group;
+ }
+ else
+ {
+ mibspi->CLRINTLVLRDY = 1 << group;
+ }
+ mibspi->SETINTENARDY = 1 << group;
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+
+/** @fn void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32_t group)
+* @brief Disable Transfer Group interrupt
+* @param[in] mibspi - Spi module base address
+* @param[in] group - Transfer group (0..7)
+*
+* This function disables the transfer group finished interrupt.
+*/
+void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32_t group)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ mibspi->CLRINTENARDY = 1 << group;
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+
+
+/** @fn void mibspi5HighLevelInterrupt(void)
+* @brief Level 0 Interrupt for MIBSPI5
+*/
+#pragma INTERRUPT(mibspi5HighLevelInterrupt, IRQ)
+
+void mibspi5HighLevelInterrupt(void)
+{
+ uint32_t vec = mibspiREG5->INTVECT0;
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+ if (vec > 0x21U)
+ {
+ uint32_t flags = mibspiREG5->FLG & (~mibspiREG5->LVL & 0x035F);
+ mibspiREG5->FLG = flags;
+ mibspiNotification(mibspiREG5, flags);
+ }
+ else
+ {
+ mibspiGroupNotification(mibspiREG5, ((vec & 0x3FU) >> 1U) - 1U);
+ }
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+}
+
+
+/** @fn void mibspi5LowLevelInterrupt(void)
+* @brief Level 1 Interrupt for MIBSPI5
+*/
+#pragma INTERRUPT(mibspi5LowLevelInterrupt, IRQ)
+
+void mibspi5LowLevelInterrupt(void)
+{
+ uint32_t vec = mibspiREG5->INTVECT1;
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+ if (vec > 0x21U)
+ {
+ uint32_t flags = mibspiREG5->FLG & (mibspiREG5->LVL & 0x035F);
+ mibspiREG5->FLG = flags;
+ mibspiNotification(mibspiREG5, flags);
+ }
+ else
+ {
+ mibspiGroupNotification(mibspiREG5, ((vec & 0x3FU) >> 1U) - 1U);
+ }
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+}
+
-/** @file sci.c \r
-* @brief SCI Driver Implementation File\r
-* @date 15.Mar.2012\r
-* @version 03.01.00\r
-*\r
-*/\r
-\r
-/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
-\r
-/* USER CODE BEGIN (0) */\r
-/* USER CODE END */\r
-\r
-#include "ti_drv_sci.h"\r
-\r
-/* USER CODE BEGIN (1) */\r
-//#include "cmdproc_io_tisci.h"\r
-//#include "os_queue.h"\r
-\r
-//extern tBuffer outBuffer;\r
-//extern tBuffer inBuffer;\r
-//static uint32_t receiveError;\r
-/* USER CODE END */\r
-/** @struct g_sciTransfer\r
-* @brief Interrupt mode globals\r
-*\r
-*/\r
-struct g_sciTransfer\r
-{\r
- uint32_t mode;\r
- uint32_t length;\r
- uint8_t *data;\r
-} g_sciTransfer[2];\r
-\r
-\r
-/** @fn void sciInit(void)\r
-* @brief Initializes the SCI Driver\r
-*\r
-* This function initializes the SCI module.\r
-*/\r
-void sciInit(void)\r
-{\r
-/* USER CODE BEGIN (2) */\r
-/* USER CODE END */\r
-\r
- /** @b intalise @b SCI */\r
-\r
- /** - bring SCI out of reset */\r
- sciREG->GCR0 = 1U;\r
-\r
- /** - Disable all interrupts */\r
- sciREG->CLRINT = 0xFFFFFFFFU;\r
- sciREG->CLRINTLVL = 0xFFFFFFFFU;\r
-\r
- /** - global control 1 */\r
- sciREG->GCR1 = (1 << 25) /* enable transmit */\r
- | (1 << 24) /* enable receive */\r
- | (1 << 5) /* internal clock (device has no clock pin) */\r
- | ((1-1) << 4) /* number of stop bits */\r
- | (0 << 3) /* even parity, otherwise odd */\r
- | (0 << 2) /* enable parity */\r
- | (1 << 1); /* asynchronous timing mode */\r
-\r
- /** - set baudrate */\r
- sciREG->BAUD = 520; /* baudrate */\r
-\r
- /** - tranmision length */\r
- sciREG->LENGTH = 8 - 1; /* length */\r
-\r
- /** - set SCI pins functional mode */\r
- sciREG->FUN = (1 << 2) /* tx pin */\r
- | (1 << 1) /* rx pin */\r
- | (0); /* clk pin */\r
-\r
- /** - set SCI pins default output value */\r
- sciREG->DOUT = (0 << 2) /* tx pin */\r
- | (0 << 1) /* rx pin */\r
- | (0); /* clk pin */\r
-\r
- /** - set SCI pins output direction */\r
- sciREG->DIR = (1 << 2) /* tx pin */\r
- | (0 << 1) /* rx pin */\r
- | (0); /* clk pin */\r
-\r
- /** - set SCI pins open drain enable */\r
- sciREG->ODR = (0 << 2) /* tx pin */\r
- | (0 << 1) /* rx pin */\r
- | (0); /* clk pin */\r
-\r
- /** - set SCI pins pullup/pulldown enable */\r
- sciREG->PD = (0 << 2) /* tx pin */\r
- | (0 << 1) /* rx pin */\r
- | (0); /* clk pin */\r
-\r
- /** - set SCI pins pullup/pulldown select */\r
- sciREG->PSL = (1 << 2) /* tx pin */\r
- | (1 << 1) /* rx pin */\r
- | (1); /* clk pin */\r
-\r
- /** - set interrupt level */\r
- sciREG->SETINTLVL = (0 << 26) /* Framing error */\r
- | (0 << 25) /* Overrun error */\r
- | (0 << 24) /* Pariry error */\r
- | (0 << 9) /* Receive */\r
- | (0 << 8) /* Transmit */\r
- | (0 << 1) /* Wakeup */\r
- | (0); /* Break detect */\r
-\r
- /** - set interrupt enable */\r
- sciREG->SETINT = (0 << 26) /* Framing error */\r
- | (0 << 25) /* Overrun error */\r
- | (0 << 24) /* Pariry error */\r
- | (1 << 9) /* Receive */\r
- | (0 << 1) /* Wakeup */\r
- | (0); /* Break detect */\r
-\r
- /** - inialise global transfer variables */\r
- g_sciTransfer[0].mode = 1 << 8;\r
- g_sciTransfer[0].length = 0;\r
-\r
- /** - Finaly start SCI */\r
- sciREG->GCR1 |= (1 << 7);\r
-\r
-\r
-/* USER CODE BEGIN (3) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void sciSetFunctional(sciBASE_t *sci, uint32_t port)\r
-* @brief Change functional behavoiur of pins at runtime.\r
-* @param[in] sci - sci module base address\r
-* @param[in] port - Value to write to FUN register\r
-*\r
-* Change the value of the PCFUN register at runtime, this allows to\r
-* dynaimcaly change the functionality of the SCI pins between functional\r
-* and GIO mode.\r
-*/\r
-void sciSetFunctional(sciBASE_t *sci, uint32_t port)\r
-{\r
-/* USER CODE BEGIN (4) */\r
-/* USER CODE END */\r
-\r
- sci->FUN = port;\r
-\r
-/* USER CODE BEGIN (5) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32_t baud)\r
-* @brief Change baudrate at runtime.\r
-* @param[in] sci - sci module base address\r
-* @param[in] baud - baudrate in Hz\r
-*\r
-* Change the SCI baudrate at runtime.\r
-*/\r
-void sciSetBaudrate(sciBASE_t *sci, uint32_t baud)\r
-{\r
- double vclk = 80.000 * 1000000.0;\r
- uint32_t f = sci->GCR1 & 2 ? 16 : 1;\r
-\r
-/* USER CODE BEGIN (6) */\r
-/* USER CODE END */\r
-\r
- sci->BAUD = ((uint32_t)((vclk /(f*baud) + 0.5)) - 1) & 0x00FFFFFF;\r
-\r
-/* USER CODE BEGIN (7) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn int sciIsTxReady(sciBASE_t *sci)\r
-* @brief Check if Tx buffer empty\r
-* @param[in] sci - sci module base address\r
-*\r
-* @return The TX ready flag\r
-*\r
-* Checks to see if the Tx buffer ready flag is set, returns\r
-* 0 is flags not set otherwise will return the Tx flag itself.\r
-*/\r
-int sciIsTxReady(sciBASE_t *sci)\r
-{\r
-/* USER CODE BEGIN (8) */\r
-/* USER CODE END */\r
-\r
- return sci->FLR & SCI_TX_INT;\r
-}\r
-\r
-\r
-/** @fn void sciSendByte(sciBASE_t *sci, uint8_t byte)\r
-* @brief Send Byte\r
-* @param[in] sci - sci module base address\r
-* @param[in] byte - byte to transfer\r
-*\r
-* Sends a single byte in polling mode, will wait in the\r
-* routine until the transmit buffer is empty before sending\r
-* the byte. Use sciIsTxReady to check for Tx buffer empty\r
-* before calling sciSendByte to avoid waiting.\r
-*/\r
-void sciSendByte(sciBASE_t *sci, uint8_t byte)\r
-{\r
-/* USER CODE BEGIN (9) */\r
-/* USER CODE END */\r
-\r
- while ((sci->FLR & SCI_TX_INT) == 0) { /* wait */ };\r
- sci->TD = byte;\r
-\r
-/* USER CODE BEGIN (10) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void sciSend(sciBASE_t *sci, uint32_t length, uint8_t *data)\r
-* @brief Send Data\r
-* @param[in] sci - sci module base address\r
-* @param[in] length - number of data words to transfer\r
-* @param[in] data - pointer to data to send\r
-*\r
-* Send a block of data pointed to by 'data' and 'length' bytes\r
-* long. If interrupts have been enabled the data is sent using\r
-* interrupt mode, otherwise polling mode is used. In interrupt\r
-* mode transmition of the first byte is started and the routine\r
-* returns imediatly, sciSend must not be called again until the\r
-* transfer is complete, when the sciNotification callback will\r
-* be called. In polling mode, sciSend will not return until \r
-* the transfer is complete.\r
-*\r
-* @note if data word is less than 8 bits, then the data must be left\r
-* aligned in the data byte.\r
-*/\r
-void sciSend(sciBASE_t *sci, uint32_t length, uint8_t *data)\r
-{\r
- int index = sci == sciREG ? 0 : 1;\r
-\r
-/* USER CODE BEGIN (11) */\r
-/* USER CODE END */\r
-\r
- if ((g_sciTransfer[index].mode & SCI_TX_INT) != 0)\r
- {\r
- /* we are in interrupt mode */\r
- \r
- g_sciTransfer[index].length = length;\r
- g_sciTransfer[index].data = data;\r
-\r
- /* start transmit by sending first byte */ \r
- sci->TD = *g_sciTransfer[index].data++;\r
- sci->SETINT = SCI_TX_INT;\r
- }\r
- else\r
- {\r
- /* send the data */\r
- while (length-- > 0)\r
- {\r
- while ((sci->FLR & SCI_TX_INT) == 0) { /* wait */ };\r
- sci->TD = *data++;\r
- }\r
- }\r
-\r
-/* USER CODE BEGIN (12) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn int sciIsRxReady(sciBASE_t *sci)\r
-* @brief Check if Rx buffer full\r
-* @param[in] sci - sci module base address\r
-*\r
-* @return The Rx ready flag\r
-*\r
-* Checks to see if the Rx buffer full flag is set, returns\r
-* 0 is flags not set otherwise will return the Rx flag itself.\r
-*/\r
-int sciIsRxReady(sciBASE_t *sci)\r
-{\r
-/* USER CODE BEGIN (13) */\r
-/* USER CODE END */\r
-\r
- return sci->FLR & SCI_RX_INT;\r
-}\r
-\r
-\r
-/** @fn int sciRxError(sciBASE_t *sci)\r
-* @brief Return Rx Error flags\r
-* @param[in] sci - sci module base address\r
-*\r
-* @return The Rx error flags\r
-*\r
-* Returns the Rx framing, overun and parity errors flags,\r
-* also clears the error flags before returning.\r
-*/\r
-int sciRxError(sciBASE_t *sci)\r
-{\r
- int status = sci->FLR & (SCI_FE_INT | SCI_OE_INT |SCI_PE_INT);\r
-\r
-/* USER CODE BEGIN (14) */\r
-/* USER CODE END */\r
-\r
- sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT;\r
- return status;\r
-}\r
-\r
-\r
-/** @fn uint32_t sciReceiveByte(sciBASE_t *sci)\r
-* @brief Receive Byte\r
-* @param[in] sci - sci module base address\r
-*\r
-* @return Received byte\r
-*\r
-* Recieves a single byte in polling mode. If there is\r
-* not a byte in the receive buffer the routine will wait\r
-* until one is received. Use sciIsRxReady to check to\r
-* see if the buffer is full to avoid waiting.\r
-*/\r
-int sciReceiveByte(sciBASE_t *sci)\r
-{\r
-/* USER CODE BEGIN (15) */\r
-/* USER CODE END */\r
-\r
- while ((sci->FLR & SCI_RX_INT) == 0) { /* wait */ };\r
-\r
- return sci->RD;\r
-}\r
-\r
-\r
-/** @fn void sciReceive(sciBASE_t *sci, uint32_t length, uint8_t *data)\r
-* @brief Receive Data\r
-* @param[in] sci - sci module base address\r
-* @param[in] length - number of data words to transfer\r
-* @param[in] data - pointer to data buffer\r
-*\r
-* Receive a block of 'length' bytes long and place it into the \r
-* data buffer pointed to by 'data'. If interrupts have been \r
-* enabled the data is received using interrupt mode, otherwise\r
-* polling mode is used. In interrupt mode receive is setup and\r
-* the routine returns imediatly, sciReceive must not be called \r
-* again until the transfer is complete, when the sciNotification \r
-* callback will be called. In polling mode, sciReceive will not\r
-* return until the transfer is complete.\r
-*/\r
-void sciReceive(sciBASE_t *sci, uint32_t length, uint8_t *data)\r
-{\r
-/* USER CODE BEGIN (16) */\r
- // Delete generated content after user code block!!!\r
- if (sci->SETINT & SCI_RX_INT)\r
- {\r
- /* We are in iterrupt mode, clear error flags */\r
- sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT;\r
-\r
- }\r
- else\r
- { \r
- while (length-- > 0)\r
- {\r
- while ((sci->FLR & SCI_RX_INT) == 0) { /* wait */ };\r
- *data++ = sci->RD;\r
- }\r
- }\r
-/* USER CODE END */\r
-\r
-\r
-/* USER CODE BEGIN (17) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void sciEnableLoopback(sciBASE_t *sci, Loopbacktype_t Loopbacktype)\r
-* @brief Enable Loopback mode for self test\r
-* @param[in] sci - sci module base address\r
-* @param[in] Loopbacktype - Digital or Analog\r
-*\r
-* This function enables the Loopback mode for self test.\r
-*/\r
-void sciEnableLoopback(sciBASE_t *sci, Loopbacktype_t Loopbacktype)\r
-{\r
-/* USER CODE BEGIN (18) */\r
-/* USER CODE END */\r
- \r
- /* Clear Loopback incase enbaled already */\r
- sci->IODFTCTRL = 0;\r
- \r
- /* Enable Loopback either in Analog or Digital Mode */\r
- sci->IODFTCTRL = 0x00000A00\r
- | Loopbacktype << 1;\r
- \r
-/* USER CODE BEGIN (19) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void sciDisableLoopback(sciBASE_t *sci)\r
-* @brief Enable Loopback mode for self test\r
-* @param[in] sci - sci module base address\r
-*\r
-* This function disable the Loopback mode.\r
-*/\r
-void sciDisableLoopback(sciBASE_t *sci)\r
-{\r
-/* USER CODE BEGIN (20) */\r
-/* USER CODE END */\r
- \r
- /* Disable Loopback Mode */\r
- sci->IODFTCTRL = 0x000005000;\r
- \r
-/* USER CODE BEGIN (21) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn sciEnableNotification(sciBASE_t *sci, uint32_t flags)\r
-* @brief Enable interrupts\r
-* @param[in] sci - sci module base address\r
-* @param[in] flags - Interrupts to be enabled, can be ored value of:\r
-* SCI_FE_INT - framming error,\r
-* SCI_OE_INT - overrun error,\r
-* SCI_PE_INT - parity error,\r
-* SCI_RX_INT - receive buffer ready,\r
-* SCI_TX_INT - transmit buffer ready,\r
-* SCI_WAKE_INT - wakeup,\r
-* SCI_BREAK_INT - break detect\r
-*/\r
-void sciEnableNotification(sciBASE_t *sci, uint32_t flags)\r
-{\r
- int index = sci == sciREG ? 0 : 1;\r
-\r
-/* USER CODE BEGIN (22) */\r
-/* USER CODE END */\r
-\r
- g_sciTransfer[index].mode |= (flags & SCI_TX_INT);\r
- sci->SETINT = (flags & ~SCI_TX_INT);\r
-\r
-/* USER CODE BEGIN (23) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn sciDisableNotification(sciBASE_t *sci, uint32_t flags)\r
-* @brief Disable interrupts\r
-* @param[in] sci - sci module base address\r
-* @param[in] flags - Interrupts to be disabled, can be ored value of:\r
-* SCI_FE_INT - framming error,\r
-* SCI_OE_INT - overrun error,\r
-* SCI_PE_INT - parity error,\r
-* SCI_RX_INT - receive buffer ready,\r
-* SCI_TX_INT - transmit buffer ready,\r
-* SCI_WAKE_INT - wakeup,\r
-* SCI_BREAK_INT - break detect\r
-*/\r
-void sciDisableNotification(sciBASE_t *sci, uint32_t flags)\r
-{\r
- int index = sci == sciREG ? 0 : 1;\r
-\r
-/* USER CODE BEGIN (24) */\r
-/* USER CODE END */\r
-\r
- g_sciTransfer[index].mode &= ~(flags & SCI_TX_INT);\r
- sci->CLRINT = (flags & ~SCI_TX_INT);\r
-\r
-/* USER CODE BEGIN (25) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-/** @fn void sciHighLevelInterrupt(void)\r
-* @brief Level 0 Interrupt for SCI\r
-*/\r
-#pragma INTERRUPT(sciHighLevelInterrupt, IRQ)\r
-\r
-void sciHighLevelInterrupt(void)\r
-{\r
- uint32_t vec = sciREG->INTVECT0;\r
-\r
-/* USER CODE BEGIN (26) */\r
- /* FIXME: Move this implementation and header somewhere else.\r
- // Delete generated content after user code block!!!\r
- switch (vec)\r
- {\r
- case 1:\r
- sciNotification(sciREG, SCI_WAKE_INT);\r
- break;\r
- case 3:\r
- sciNotification(sciREG, SCI_PE_INT);\r
- break;\r
- case 6:\r
- sciNotification(sciREG, SCI_FE_INT);\r
- break;\r
- case 7:\r
- sciNotification(sciREG, SCI_BREAK_INT);\r
- break;\r
- case 9:\r
- sciNotification(sciREG, SCI_OE_INT);\r
- break;\r
-\r
- case 11:\r
- // receive\r
- { uint8_t byte = sciREG->RD;\r
- if (xQueueSendFromISR(inBuffer.buf, (void*)&byte, NULL) == errQUEUE_FULL)\r
- receiveError++;\r
- sciNotification(sciREG, SCI_RX_INT);\r
- }\r
- break;\r
-\r
- case 12:\r
- // transmit\r
- {\r
- uint8_t byte = 0;\r
- if (xQueueReceiveFromISR(outBuffer.buf, (uint8_t *)&byte, NULL) == errQUEUE_EMPTY) {\r
- sciREG->CLRINT = SCI_TX_INT;\r
- outBuffer.flags &= ~BUF_TRANSFER_IN_PROGRESS;\r
- }\r
- else {\r
- sciREG->TD = byte;\r
- }\r
- }\r
- break;\r
- default:\r
- // phantom interrupt, clear flags and return\r
- sciREG->FLR = ~sciREG->SETINTLVL & 0x07000303;\r
- break;\r
- }\r
- */\r
-/* USER CODE END */\r
-/* USER CODE BEGIN (27) */\r
-/* USER CODE END */\r
-}\r
-\r
-/** @fn void sciLowLevelInterrupt(void)\r
-* @brief Level 1 Interrupt for SCI\r
-*/\r
-#pragma INTERRUPT(sciLowLevelInterrupt, IRQ)\r
-\r
-void sciLowLevelInterrupt(void)\r
-{\r
- uint32_t vec = sciREG->INTVECT1;\r
-\r
-/* USER CODE BEGIN (28) */\r
-/* USER CODE END */\r
-\r
- switch (vec)\r
- {\r
- case 1:\r
- sciNotification(sciREG, SCI_WAKE_INT);\r
- break;\r
- case 3:\r
- sciNotification(sciREG, SCI_PE_INT);\r
- break;\r
- case 6:\r
- sciNotification(sciREG, SCI_FE_INT);\r
- break;\r
- case 7:\r
- sciNotification(sciREG, SCI_BREAK_INT);\r
- break;\r
- case 9:\r
- sciNotification(sciREG, SCI_OE_INT);\r
- break;\r
-\r
- case 11:\r
- /* receive */\r
- { uint32_t byte = sciREG->RD;\r
-\r
- if (g_sciTransfer[0].length > 0)\r
- {\r
- *g_sciTransfer[0].data++ = byte;\r
- g_sciTransfer[0].length--;\r
- if (g_sciTransfer[0].length == 0)\r
- {\r
- sciNotification(sciREG, SCI_RX_INT);\r
- }\r
- }\r
- }\r
- break;\r
-\r
- case 12:\r
- /* transmit */\r
- if (--g_sciTransfer[0].length > 0)\r
- {\r
- sciREG->TD = *g_sciTransfer[0].data++;\r
- }\r
- else\r
- {\r
- sciREG->CLRINT = SCI_TX_INT;\r
- sciNotification(sciREG, SCI_TX_INT);\r
- }\r
- break;\r
-\r
- default:\r
- /* phantom interrupt, clear flags and return */\r
- sciREG->FLR = sciREG->SETINTLVL & 0x07000303;\r
- break;\r
- }\r
-/* USER CODE BEGIN (29) */\r
-/* USER CODE END */\r
-}\r
-\r
-\r
-\r
+/** @file sci.c
+* @brief SCI Driver Implementation File
+* @date 15.Mar.2012
+* @version 03.01.00
+*
+*/
+
+/* (c) Texas Instruments 2009-2012, All rights reserved. */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "ti_drv_sci.h"
+
+/* USER CODE BEGIN (1) */
+//#include "cmdproc_io_tisci.h"
+//#include "os_queue.h"
+
+//extern tBuffer outBuffer;
+//extern tBuffer inBuffer;
+//static uint32_t receiveError;
+/* USER CODE END */
+/** @struct g_sciTransfer
+* @brief Interrupt mode globals
+*
+*/
+struct g_sciTransfer
+{
+ uint32_t mode;
+ uint32_t length;
+ uint8_t *data;
+} g_sciTransfer[2];
+
+
+/** @fn void sciInit(void)
+* @brief Initializes the SCI Driver
+*
+* This function initializes the SCI module.
+*/
+void sciInit(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+ /** @b intalise @b SCI */
+
+ /** - bring SCI out of reset */
+ sciREG->GCR0 = 1U;
+
+ /** - Disable all interrupts */
+ sciREG->CLRINT = 0xFFFFFFFFU;
+ sciREG->CLRINTLVL = 0xFFFFFFFFU;
+
+ /** - global control 1 */
+ sciREG->GCR1 = (1 << 25) /* enable transmit */
+ | (1 << 24) /* enable receive */
+ | (1 << 5) /* internal clock (device has no clock pin) */
+ | ((1-1) << 4) /* number of stop bits */
+ | (0 << 3) /* even parity, otherwise odd */
+ | (0 << 2) /* enable parity */
+ | (1 << 1); /* asynchronous timing mode */
+
+ /** - set baudrate */
+ sciREG->BAUD = 520; /* baudrate */
+
+ /** - tranmision length */
+ sciREG->LENGTH = 8 - 1; /* length */
+
+ /** - set SCI pins functional mode */
+ sciREG->FUN = (1 << 2) /* tx pin */
+ | (1 << 1) /* rx pin */
+ | (0); /* clk pin */
+
+ /** - set SCI pins default output value */
+ sciREG->DOUT = (0 << 2) /* tx pin */
+ | (0 << 1) /* rx pin */
+ | (0); /* clk pin */
+
+ /** - set SCI pins output direction */
+ sciREG->DIR = (1 << 2) /* tx pin */
+ | (0 << 1) /* rx pin */
+ | (0); /* clk pin */
+
+ /** - set SCI pins open drain enable */
+ sciREG->ODR = (0 << 2) /* tx pin */
+ | (0 << 1) /* rx pin */
+ | (0); /* clk pin */
+
+ /** - set SCI pins pullup/pulldown enable */
+ sciREG->PD = (0 << 2) /* tx pin */
+ | (0 << 1) /* rx pin */
+ | (0); /* clk pin */
+
+ /** - set SCI pins pullup/pulldown select */
+ sciREG->PSL = (1 << 2) /* tx pin */
+ | (1 << 1) /* rx pin */
+ | (1); /* clk pin */
+
+ /** - set interrupt level */
+ sciREG->SETINTLVL = (0 << 26) /* Framing error */
+ | (0 << 25) /* Overrun error */
+ | (0 << 24) /* Pariry error */
+ | (0 << 9) /* Receive */
+ | (0 << 8) /* Transmit */
+ | (0 << 1) /* Wakeup */
+ | (0); /* Break detect */
+
+ /** - set interrupt enable */
+ sciREG->SETINT = (0 << 26) /* Framing error */
+ | (0 << 25) /* Overrun error */
+ | (0 << 24) /* Pariry error */
+ | (1 << 9) /* Receive */
+ | (0 << 1) /* Wakeup */
+ | (0); /* Break detect */
+
+ /** - inialise global transfer variables */
+ g_sciTransfer[0].mode = 1 << 8;
+ g_sciTransfer[0].length = 0;
+
+ /** - Finaly start SCI */
+ sciREG->GCR1 |= (1 << 7);
+
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+}
+
+
+/** @fn void sciSetFunctional(sciBASE_t *sci, uint32_t port)
+* @brief Change functional behavoiur of pins at runtime.
+* @param[in] sci - sci module base address
+* @param[in] port - Value to write to FUN register
+*
+* Change the value of the PCFUN register at runtime, this allows to
+* dynaimcaly change the functionality of the SCI pins between functional
+* and GIO mode.
+*/
+void sciSetFunctional(sciBASE_t *sci, uint32_t port)
+{
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+ sci->FUN = port;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+}
+
+
+/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32_t baud)
+* @brief Change baudrate at runtime.
+* @param[in] sci - sci module base address
+* @param[in] baud - baudrate in Hz
+*
+* Change the SCI baudrate at runtime.
+*/
+void sciSetBaudrate(sciBASE_t *sci, uint32_t baud)
+{
+ double vclk = 80.000 * 1000000.0;
+ uint32_t f = sci->GCR1 & 2 ? 16 : 1;
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+ sci->BAUD = ((uint32_t)((vclk /(f*baud) + 0.5)) - 1) & 0x00FFFFFF;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+
+/** @fn int sciIsTxReady(sciBASE_t *sci)
+* @brief Check if Tx buffer empty
+* @param[in] sci - sci module base address
+*
+* @return The TX ready flag
+*
+* Checks to see if the Tx buffer ready flag is set, returns
+* 0 is flags not set otherwise will return the Tx flag itself.
+*/
+int sciIsTxReady(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ return sci->FLR & SCI_TX_INT;
+}
+
+
+/** @fn void sciSendByte(sciBASE_t *sci, uint8_t byte)
+* @brief Send Byte
+* @param[in] sci - sci module base address
+* @param[in] byte - byte to transfer
+*
+* Sends a single byte in polling mode, will wait in the
+* routine until the transmit buffer is empty before sending
+* the byte. Use sciIsTxReady to check for Tx buffer empty
+* before calling sciSendByte to avoid waiting.
+*/
+void sciSendByte(sciBASE_t *sci, uint8_t byte)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+ while ((sci->FLR & SCI_TX_INT) == 0) { /* wait */ };
+ sci->TD = byte;
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+}
+
+
+/** @fn void sciSend(sciBASE_t *sci, uint32_t length, uint8_t *data)
+* @brief Send Data
+* @param[in] sci - sci module base address
+* @param[in] length - number of data words to transfer
+* @param[in] data - pointer to data to send
+*
+* Send a block of data pointed to by 'data' and 'length' bytes
+* long. If interrupts have been enabled the data is sent using
+* interrupt mode, otherwise polling mode is used. In interrupt
+* mode transmition of the first byte is started and the routine
+* returns imediatly, sciSend must not be called again until the
+* transfer is complete, when the sciNotification callback will
+* be called. In polling mode, sciSend will not return until
+* the transfer is complete.
+*
+* @note if data word is less than 8 bits, then the data must be left
+* aligned in the data byte.
+*/
+void sciSend(sciBASE_t *sci, uint32_t length, uint8_t *data)
+{
+ int index = sci == sciREG ? 0 : 1;
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ if ((g_sciTransfer[index].mode & SCI_TX_INT) != 0)
+ {
+ /* we are in interrupt mode */
+
+ g_sciTransfer[index].length = length;
+ g_sciTransfer[index].data = data;
+
+ /* start transmit by sending first byte */
+ sci->TD = *g_sciTransfer[index].data++;
+ sci->SETINT = SCI_TX_INT;
+ }
+ else
+ {
+ /* send the data */
+ while (length-- > 0)
+ {
+ while ((sci->FLR & SCI_TX_INT) == 0) { /* wait */ };
+ sci->TD = *data++;
+ }
+ }
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+
+/** @fn int sciIsRxReady(sciBASE_t *sci)
+* @brief Check if Rx buffer full
+* @param[in] sci - sci module base address
+*
+* @return The Rx ready flag
+*
+* Checks to see if the Rx buffer full flag is set, returns
+* 0 is flags not set otherwise will return the Rx flag itself.
+*/
+int sciIsRxReady(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ return sci->FLR & SCI_RX_INT;
+}
+
+
+/** @fn int sciRxError(sciBASE_t *sci)
+* @brief Return Rx Error flags
+* @param[in] sci - sci module base address
+*
+* @return The Rx error flags
+*
+* Returns the Rx framing, overun and parity errors flags,
+* also clears the error flags before returning.
+*/
+int sciRxError(sciBASE_t *sci)
+{
+ int status = sci->FLR & (SCI_FE_INT | SCI_OE_INT |SCI_PE_INT);
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+ sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT;
+ return status;
+}
+
+
+/** @fn uint32_t sciReceiveByte(sciBASE_t *sci)
+* @brief Receive Byte
+* @param[in] sci - sci module base address
+*
+* @return Received byte
+*
+* Recieves a single byte in polling mode. If there is
+* not a byte in the receive buffer the routine will wait
+* until one is received. Use sciIsRxReady to check to
+* see if the buffer is full to avoid waiting.
+*/
+int sciReceiveByte(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ while ((sci->FLR & SCI_RX_INT) == 0) { /* wait */ };
+
+ return sci->RD;
+}
+
+
+/** @fn void sciReceive(sciBASE_t *sci, uint32_t length, uint8_t *data)
+* @brief Receive Data
+* @param[in] sci - sci module base address
+* @param[in] length - number of data words to transfer
+* @param[in] data - pointer to data buffer
+*
+* Receive a block of 'length' bytes long and place it into the
+* data buffer pointed to by 'data'. If interrupts have been
+* enabled the data is received using interrupt mode, otherwise
+* polling mode is used. In interrupt mode receive is setup and
+* the routine returns imediatly, sciReceive must not be called
+* again until the transfer is complete, when the sciNotification
+* callback will be called. In polling mode, sciReceive will not
+* return until the transfer is complete.
+*/
+void sciReceive(sciBASE_t *sci, uint32_t length, uint8_t *data)
+{
+/* USER CODE BEGIN (16) */
+ // Delete generated content after user code block!!!
+ if (sci->SETINT & SCI_RX_INT)
+ {
+ /* We are in iterrupt mode, clear error flags */
+ sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT;
+
+ }
+ else
+ {
+ while (length-- > 0)
+ {
+ while ((sci->FLR & SCI_RX_INT) == 0) { /* wait */ };
+ *data++ = sci->RD;
+ }
+ }
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+}
+
+/** @fn void sciEnableLoopback(sciBASE_t *sci, Loopbacktype_t Loopbacktype)
+* @brief Enable Loopback mode for self test
+* @param[in] sci - sci module base address
+* @param[in] Loopbacktype - Digital or Analog
+*
+* This function enables the Loopback mode for self test.
+*/
+void sciEnableLoopback(sciBASE_t *sci, Loopbacktype_t Loopbacktype)
+{
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+ /* Clear Loopback incase enbaled already */
+ sci->IODFTCTRL = 0;
+
+ /* Enable Loopback either in Analog or Digital Mode */
+ sci->IODFTCTRL = 0x00000A00
+ | Loopbacktype << 1;
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+}
+
+/** @fn void sciDisableLoopback(sciBASE_t *sci)
+* @brief Enable Loopback mode for self test
+* @param[in] sci - sci module base address
+*
+* This function disable the Loopback mode.
+*/
+void sciDisableLoopback(sciBASE_t *sci)
+{
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+ /* Disable Loopback Mode */
+ sci->IODFTCTRL = 0x000005000;
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+}
+
+/** @fn sciEnableNotification(sciBASE_t *sci, uint32_t flags)
+* @brief Enable interrupts
+* @param[in] sci - sci module base address
+* @param[in] flags - Interrupts to be enabled, can be ored value of:
+* SCI_FE_INT - framming error,
+* SCI_OE_INT - overrun error,
+* SCI_PE_INT - parity error,
+* SCI_RX_INT - receive buffer ready,
+* SCI_TX_INT - transmit buffer ready,
+* SCI_WAKE_INT - wakeup,
+* SCI_BREAK_INT - break detect
+*/
+void sciEnableNotification(sciBASE_t *sci, uint32_t flags)
+{
+ int index = sci == sciREG ? 0 : 1;
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+ g_sciTransfer[index].mode |= (flags & SCI_TX_INT);
+ sci->SETINT = (flags & ~SCI_TX_INT);
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+}
+
+
+/** @fn sciDisableNotification(sciBASE_t *sci, uint32_t flags)
+* @brief Disable interrupts
+* @param[in] sci - sci module base address
+* @param[in] flags - Interrupts to be disabled, can be ored value of:
+* SCI_FE_INT - framming error,
+* SCI_OE_INT - overrun error,
+* SCI_PE_INT - parity error,
+* SCI_RX_INT - receive buffer ready,
+* SCI_TX_INT - transmit buffer ready,
+* SCI_WAKE_INT - wakeup,
+* SCI_BREAK_INT - break detect
+*/
+void sciDisableNotification(sciBASE_t *sci, uint32_t flags)
+{
+ int index = sci == sciREG ? 0 : 1;
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+ g_sciTransfer[index].mode &= ~(flags & SCI_TX_INT);
+ sci->CLRINT = (flags & ~SCI_TX_INT);
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+}
+
+
+/** @fn void sciHighLevelInterrupt(void)
+* @brief Level 0 Interrupt for SCI
+*/
+#pragma INTERRUPT(sciHighLevelInterrupt, IRQ)
+
+void sciHighLevelInterrupt(void)
+{
+ uint32_t vec = sciREG->INTVECT0;
+
+/* USER CODE BEGIN (26) */
+ /* FIXME: Move this implementation and header somewhere else.
+ // Delete generated content after user code block!!!
+ switch (vec)
+ {
+ case 1:
+ sciNotification(sciREG, SCI_WAKE_INT);
+ break;
+ case 3:
+ sciNotification(sciREG, SCI_PE_INT);
+ break;
+ case 6:
+ sciNotification(sciREG, SCI_FE_INT);
+ break;
+ case 7:
+ sciNotification(sciREG, SCI_BREAK_INT);
+ break;
+ case 9:
+ sciNotification(sciREG, SCI_OE_INT);
+ break;
+
+ case 11:
+ // receive
+ { uint8_t byte = sciREG->RD;
+ if (xQueueSendFromISR(inBuffer.buf, (void*)&byte, NULL) == errQUEUE_FULL)
+ receiveError++;
+ sciNotification(sciREG, SCI_RX_INT);
+ }
+ break;
+
+ case 12:
+ // transmit
+ {
+ uint8_t byte = 0;
+ if (xQueueReceiveFromISR(outBuffer.buf, (uint8_t *)&byte, NULL) == errQUEUE_EMPTY) {
+ sciREG->CLRINT = SCI_TX_INT;
+ outBuffer.flags &= ~BUF_TRANSFER_IN_PROGRESS;
+ }
+ else {
+ sciREG->TD = byte;
+ }
+ }
+ break;
+ default:
+ // phantom interrupt, clear flags and return
+ sciREG->FLR = ~sciREG->SETINTLVL & 0x07000303;
+ break;
+ }
+ */
+/* USER CODE END */
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+}
+
+/** @fn void sciLowLevelInterrupt(void)
+* @brief Level 1 Interrupt for SCI
+*/
+#pragma INTERRUPT(sciLowLevelInterrupt, IRQ)
+
+void sciLowLevelInterrupt(void)
+{
+ uint32_t vec = sciREG->INTVECT1;
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ switch (vec)
+ {
+ case 1:
+ sciNotification(sciREG, SCI_WAKE_INT);
+ break;
+ case 3:
+ sciNotification(sciREG, SCI_PE_INT);
+ break;
+ case 6:
+ sciNotification(sciREG, SCI_FE_INT);
+ break;
+ case 7:
+ sciNotification(sciREG, SCI_BREAK_INT);
+ break;
+ case 9:
+ sciNotification(sciREG, SCI_OE_INT);
+ break;
+
+ case 11:
+ /* receive */
+ { uint32_t byte = sciREG->RD;
+
+ if (g_sciTransfer[0].length > 0)
+ {
+ *g_sciTransfer[0].data++ = byte;
+ g_sciTransfer[0].length--;
+ if (g_sciTransfer[0].length == 0)
+ {
+ sciNotification(sciREG, SCI_RX_INT);
+ }
+ }
+ }
+ break;
+
+ case 12:
+ /* transmit */
+ if (--g_sciTransfer[0].length > 0)
+ {
+ sciREG->TD = *g_sciTransfer[0].data++;
+ }
+ else
+ {
+ sciREG->CLRINT = SCI_TX_INT;
+ sciNotification(sciREG, SCI_TX_INT);
+ }
+ break;
+
+ default:
+ /* phantom interrupt, clear flags and return */
+ sciREG->FLR = sciREG->SETINTLVL & 0x07000303;
+ break;
+ }
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+}
+
+
+
projects / pes-rpp / rpp-lib.git / commitdiff