-/* Copyright (C) 2013 Czech Technical University in Prague
+/**
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * Copyright (C) 2013-2015 Czech Technical University in Prague
+ * All rights reserved.
*
- * Authors:
- * - Carlos Jenkins <carlos@jenkins.co.cr>
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
*
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
*
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * This file is part of the lwIP TCP/IP stack.
*
- * File : eth.c
- * Abstract:
- * Ethernet Communication RPP API implementation file.
+ * Author: Adam Dunkels <adam@sics.se>
+ * Carlos Jenkins <carlos@jenkins.co.cr>
+ * Rostislav Lisovy <lisovy@gmail.com>
+ * Jan Doležal <pm.jenik@gmail.com>
*
- * References:
- * eth.h
- * RPP API documentation.
*/
+/**
+ * Copyright (c) 2010 Texas Instruments Incorporated
+ *
+ * This file is dervied from the "ethernetif.c" skeleton Ethernet network
+ * interface driver for lwIP.
+ *
+ */
#include "rpp/rpp.h"
-#if rppCONFIG_INCLUDE_ETH == 1
+#ifndef FREERTOS_POSIX
+
+/* lwIP headers */
+#include "lwip/init.h"
+#include "lwip/timers.h" /* for DHCP binding in NO_SYS mode */
+#include "lwip/sys.h" /* includes - lwip/opt.h, lwip/err.h, arch/sys_arch.h */
+#include "lwip/tcpip.h" /* includes - lwip/opt.h, lwip/api_msg.h, lwip/netifapi.h, lwip/pbuf.h, lwip/api.h, lwip/sys.h, lwip/timers.h, lwip/netif.h */
+#include "lwip/stats.h" /* includes - lwip/mem.h, lwip/memp.h, lwip/opt.h */
+#include "netif/etharp.h" /* includes - lwip/ip.h, lwip/netif.h, lwip/ip_addr.h, lwip/pbuf.h */
+#include "lwip/def.h"
+#include "lwip/snmp.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "netif/ppp_oe.h"
+/* end - lwIP headers */
+
+#include "drv/digital_io.h"
+#include "sys/sys.h" /* includes - sys/phy_dp83848h.h */
+#include "drv/emac.h"
+#include "os/os.h"
+#include "types.h"
+
+
+/* Number of EMAC Instances */
+#define MAX_EMAC_INSTANCE 1
+
+#define DEFAULT_PHY_ADDR 0x1
+#define FIND_FIRST_PHY_ALIVE 1 /* or use default (phy_address: 1) */
+#define NUM_OF_PHYs 32
+
+/* Size of the Buffer descriptor defined by the EMAC in bytes */
+#define SIZE_OF_DESC 16
+
+/* Channel number used for for RX, TX, unicast, broadcast or damaged frames;
+ * there are different channels for rx and tx operations (i.e. RXCH0 != TXCH0) */
+#define CHANNEL 0
+
+/* take in account oversized frames */
+#define MAX_TRANSFER_UNIT 1500
+
+/* WARNING!
+ * Be very carefull when setting this value. We have to keep in mind
+ * that pbuf_alloc(..., PBUF_POOL) will usualy return a chain of PBUFs
+ * pointing to the statically preallocated buffers (of the same size).
+ * The problem is that if we ask to allocate 300 bytes whereby the size
+ * of the statically preallocated PBUFs (PBUF_POOL_BUFSIZE) is 256, we
+ * will get a chain containing two PBUFs -- one *reporting* its size to
+ * be 256 bytes, the other one 44 bytes.
+ * Everything seems to be just fine however during RX, after we call
+ * netif->input(pbuf, netif) we have to newly allocate the PBUF(s) and
+ * properly set the apropriate BDs. This will however work only if the
+ * number of the freed BDs is the same as the number of the BDs newly
+ * initialized. One possible situation when this may fail is when multiple
+ * non-256 byte sized PBUFs will move near to each other, i.e. 3 BDs:
+ * 256 B, 44 B, 44 B -- 344 bytes will be freed (3 BDs) but the new call
+ * to pbuf_alloc(...) will return a chain comprising only two PBUFs
+ * (256 B, 88 B).
+ * This is the implementation limitation. The PBUF_LEN_MAX should therefore
+ * be multiple of PBUF_POOL_BUFSIZE
+ */
+#define PBUF_LEN_MAX (PBUF_POOL_BUFSIZE * 6)
+
+/* Maximum number of PBUFs preallocated in the driver
+ * init function to be used for the RX
+ */
+#define MAX_RX_PBUF_ALLOC 10
+#define MIN_PKT_LEN 60
+
+/* Define those to better describe the network interface. */
+#define IFNAME0 'e'
+#define IFNAME1 'n'
+/* Time to wait for autonegotiation in ticks. */
+#define TICKS_PHY_AUTONEG 4000
+
+/**
+ * TODO -- not implemented
+ * When cable is connected (link status goes up)
+ * autonegotiation and/or dhcp is started.
+ */
+#define PHY_LINK_MONITOR_INT 0
+
+
+/* Statically allocated structure describing interface state -- one per instance */
+static struct hdkif hdkif_data[MAX_EMAC_INSTANCE];
+
+/* The lwIP network interface structure for the HDK Ethernet MAC. */
+static struct netif hdkNetIF[MAX_EMAC_INSTANCE];
+
+/* RPP startup init indicator */
static boolean_t initialized = FALSE;
+static boolean_t postInitialized = FALSE;
+
+/***testing functions**********************************************/
+boolean_t isPostInitialized()
+{
+ return postInitialized;
+}
+
+uint32_t rpp_eth_phylinkstat(uint32_t instNum)
+{
+ struct hdkif *hdkif = &hdkif_data[instNum];
+ return PHY_link_status_get(hdkif->mdio_base, hdkif->phy_addr, 1);
+}
+#define BYTE_BUFF_SIZE 2
+#define OFFSET_MAC_LETTERS (MAC_BIG_LETTERS ? 'A' : 'a')
+/* puts string of MAC address assigned to EMAC instance reffered by instNum into *mac */
+void rpp_eth_get_macAddrStr(uint32_t instNum, uint8_t *macStr)
+{
+ uint8_t index, outindex = 0;
+ char buff[BYTE_BUFF_SIZE];
+ struct hdkif *hdkif = &hdkif_data[instNum];
+ for(index = 0; index < MAC_ADDR_LEN; index++) {
+ if(index)macStr[outindex++] = ':';
+ buff[0] = (hdkif->mac_addr[(MAC_ADDR_LEN - 1) - index] >> 4);
+ buff[1] = (hdkif->mac_addr[(MAC_ADDR_LEN - 1) - index] & 0xf);
+ macStr[outindex++] = (buff[0]<10) ? (buff[0] + '0') : (buff[0] - '\012' + OFFSET_MAC_LETTERS);
+ macStr[outindex++] = (buff[1]<10) ? (buff[1] + '0') : (buff[1] - '\012' + OFFSET_MAC_LETTERS);
+ }
+ macStr[outindex] = '\0';
+}
+
+/* @param ip will be filled accroding to content of ipstr */
+err_t rpp_eth_stringToIP(ip_addr_t * ip, uint8_t * ipstr)
+{
+ uint8_t charProccessed, index = 0, dotindex = 0xff, tmp = 0, dots = 0, fldEdit = 0;
+ uint32_t ipaddr = 0;
+ for(charProccessed = ipstr[index]; (charProccessed >= '0' && charProccessed <= '9') || charProccessed == '.' ; charProccessed = ipstr[++index])
+ {
+ if(charProccessed == '.')
+ {
+ if(++dotindex == index)
+ {
+ dots = 0;
+ break;
+ }
+ dotindex = index;
+
+ ipaddr = (ipaddr << 8) + tmp;
+
+ dots++;
+ if(dots > 3)break;
+
+ tmp = 0;
+ fldEdit = FALSE;
+ }
+ else
+ {
+ fldEdit = TRUE;
+ tmp = tmp*10 + charProccessed - '0';
+ }
+ }
+ if(dots != 3 || !fldEdit)
+ {
+ /* if unsuccesful, don't modify previous content */
+ return FAILURE;
+ }
+ ipaddr = (ipaddr << 8) + tmp;
+ ip->addr = ipaddr;
+ return SUCCESS;
+}
+
+/* returns number in range 0-65535 where 0 is error */
+uint16_t rpp_eth_portStrToInt(uint8_t *string)
+{
+ uint8_t index;
+ uint16_t portNO = 0;
+ for(index = 0;string[index] != '\0';index++)
+ {
+ if(string[index] < '0' || string[index] > '9')
+ {
+ portNO = 0;
+ break;
+ }
+ portNO = portNO * 10 + string[index] - '0';
+ }
+ return portNO;
+}
+
+struct netif *rpp_eth_get_netif(uint32_t instNum)
+{
+ return &hdkNetIF[instNum];
+}
+
+/***** forward declarations **********************************************/
+
+/*
+ * interface initializes
+ */
+err_t rpp_eth_lwip_init(struct netif *netif);
+
+/*
+ * Initializes hw such as PHY, MDIO, EMAC, EMAC control module
+ *
+ * @return SUCCESS if initialization successful.\n
+ * FAILURE if initialization not successful.
+ */
+err_t rpp_eth_hw_init(struct hdkif *hdkif);
+
+/*
+ * Initializes hw, after lwIP was initialized and
+ * OS was initialized in case OS is used.
+ */
+err_t rpp_eth_hw_init_postInit(struct netif *netif);
+
+/***** utility functions **********************************************/
+
+/*
+* Function to set the MAC address to the interface
+* @param inst_num the instance number
+*
+* @note mac_addr[0] is considered MSB
+*/
+static void hdkif_macaddrset(u32_t inst_num, u8_t *mac_addr)
+{
+ struct hdkif *hdkif;
+ u32_t temp;
+
+ hdkif = &hdkif_data[inst_num];
+
+ /* set MAC hardware address */
+ for (temp = 0; temp < MAC_ADDR_LEN; temp++) {
+ hdkif->mac_addr[temp] = mac_addr[(MAC_ADDR_LEN - 1) - temp];
+ }
+#ifdef DEBUG
+ uint8_t macStr[18];
+ rpp_eth_get_macAddrStr(inst_num, macStr);
+ rpp_debug_printf("Setting MAC... %s\r\n", macStr);
+#endif
+}
+
+/**
+* Function to setup the instance parameters inside the interface
+* @param hdkif
+* @return none.
+*/
+static void hdkif_inst_config(struct hdkif *hdkif)
+{
+ if (hdkif->inst_num == 0)
+ {
+ hdkif->emac_base = EMAC_BASE_m(0);
+ hdkif->emac_ctrl_base = EMAC_CTRL_BASE_m(0);
+ hdkif->emac_ctrl_ram = EMAC_CTRL_RAM_BASE_m(0);
+ hdkif->mdio_base = MDIO_BASE_m(0);
+
+ /* Default address of PHY on "MDIO bus"
+ * (depends on PHY hw configuration)
+ */
+ hdkif->phy_addr = DEFAULT_PHY_ADDR;
+ hdkif->phy_autoneg = PHY_auto_negotiate;
+ hdkif->phy_autoneg_start = PHY_start_auto_negotiate;
+ hdkif->phy_autoneg_is_done = PHY_is_done_auto_negotiate;
+ hdkif->phy_partnerability = PHY_partner_ability_get;
+ }
+}
+
+/***** initializing functions **********************************************/
int8_t rpp_eth_init()
{
- if(initialized) {
- return FAIL;
- }
- initialized = TRUE;
+ unsigned int instNum;
+ int8_t retVal = SUCCESS;
+
+ if (initialized)
+ return FAILURE;
+
+ /* Config each EMAC instance */
+ for (instNum = 0; instNum < MAX_EMAC_INSTANCE; instNum++)
+ {
+ struct hdkif *hdkif = &hdkif_data[instNum];
+
+ hdkif->inst_num = instNum;
+ hdkif_inst_config(hdkif);
+
+ retVal = rpp_eth_hw_init(hdkif);
+ if (retVal != SUCCESS) {
+ rpp_debug_printf("rpp_eth_hw_init: %d", retVal);
+ return FAILURE;
+ }
+ }
+
+ initialized = TRUE;
+ return retVal;
+}
+
+int8_t rpp_eth_init_postInit(uint32_t instNum, uint8_t *macArray)
+{
+ volatile unsigned int dhcpBindWait = 0x3FFFFFFF;
+ struct ip_addr ip_addr;
+ struct ip_addr net_mask;
+ struct ip_addr gw_addr;
+ int8_t retVal = SUCCESS;
+ struct netif *netif = &hdkNetIF[instNum];
+ struct netif *netif_tmp;
+ u8_t mac_addr[MAC_ADDR_LEN] = RPP_MAC_ADDR;
+ struct hdkif *hdkif;
+
+ if (postInitialized)
+ return FAILURE;
+
+ if (macArray == NULL)
+ macArray = mac_addr; /* use default MAC */
+
+ hdkif_macaddrset(instNum, macArray);
+
+#if NO_SYS
+ lwip_init();
+#else
+ /* This can be called only within post OS init */
+
+ /*
+ * calls lwip_init() implicitly, starts lwIP task (thread),
+ * when started function given to tcpip_init is executed first
+ */
+ tcpip_init(NULL, NULL);
+#endif
+
+#if STATIC_IP_ADDRESS
+ ip_addr.addr = htonl(RPP_IP_ADDR);
+ net_mask.addr = htonl(RPP_NETMASK);
+ gw_addr.addr = htonl(RPP_GW);
+#else
+ ip_addr.addr = 0;
+ net_mask.addr = 0;
+ gw_addr.addr = 0;
+#endif
+
+#if NO_SYS
+ /* Add new network interface to lwIP list of ifaces
+ * and initialize netif with specific function
+ */
+ netif_tmp = netif_add(netif, &ip_addr, &net_mask, &gw_addr,
+ &hdkif_data[instNum], rpp_eth_lwip_init,
+ ethernet_input);
+#else
+ netif_tmp = netif_add(netif, &ip_addr, &net_mask, &gw_addr,
+ &hdkif_data[instNum], rpp_eth_lwip_init,
+ tcpip_input);
+#endif
+ if (netif_tmp == NULL)
+ return NETIF_ADD_ERR;
+
+ netif_set_default(netif);
+
+ hdkif = netif->state;
+
+#if !NO_SYS
+ /* Semaphores used to block/unblock RX/TX threads doing the
+ * 'deferred' RX/TX handling -- semgive is callend in RX/TX ISR
+ */
+ vSemaphoreCreateBinary(hdkif->goRX);
+ vSemaphoreCreateBinary(hdkif->goTX);
+
+ xTaskCreate(rpp_eth_recv_raw_thr, "RXHandler", 500, netif, 0, NULL);
+ xTaskCreate(rpp_eth_send_raw_thr, "TXHandler", 500, netif, 0, NULL);
+#endif
+
+ /* If we don't use link int change, then it must be done here */
+#if !PHY_LINK_MONITOR_INT
+ if (rpp_eth_phylinkstat(hdkif->inst_num)) {
+ rpp_debug_printf("cable connected ... setting IP params\r\n");
+
+ #if STATIC_IP_ADDRESS
+ netif_set_up(netif);
+ #elif LWIP_DHCP
+ int ret = dhcp_start(netif);
+ if (ret != ERR_OK) {
+ rpp_debug_printf("dhcp mem err\r\n");
+ return DHCP_MEM_ERR;
+ }
+
+ rpp_debug_printf("binding DHCP\r");
+ while ((netif->dhcp->state != DHCP_BOUND) && (dhcpBindWait--))
+ ; /* FIXME: sys_check_timeouts()*/
+
+ if (!dhcpBindWait)
+ rpp_debug_printf("dhcp binding timeout...\r\n");
+ #else /* FIXME there should be some kind of waiting until IP address is assigned */
+ autoip_start(netif);
+ #endif
+
+ #ifdef DEBUG
+ uint8_t ipString[16]; // FIXME change the functions to use char
+ rpp_eth_getIPDecimalStr(netif->ip_addr, ipString);
+ rpp_debug_printf("Address: %s\n", ipString);
+ rpp_eth_getIPDecimalStr(netif->netmask, ipString);
+ rpp_debug_printf("Netmask: %s\n", ipString);
+ rpp_eth_getIPDecimalStr(netif->gw, ipString);
+ rpp_debug_printf("Gateway: %s\n", ipString);
+ #endif
+
+ } else {
+ rpp_debug_printf("cable not connected\r\n");
+ retVal = PHY_LINK_DOWN;
+ }
+
+#else /* !PHY_LINK_MONITOR_INT */
+ /* Link Status change handled in an interrupt -- NOT IMPLEMENTED */
+
+ /*
+ * Now when we established environment needed for phy link status
+ * change we can allow it. Set PHY number which is monitored for
+ * link changes in MDIO and enable interrupt
+ */
+ HWREG(hdkif->mdio_base + MDIO_USERPHYSEL0) =
+ ((hdkif->phy_addr && 0x1f) | MDIO_USERPHYSEL0_LINKINTENB);
+
+ /* Enable MISC interrupt - link monitoring in EMAC control module */
+ HWREG(hdkif->emac_ctrl_base + EMAC_CTRL_CnMISCEN(0)) |=
+ EMAC_CTRL_MISC_LINKINT0ENB;
+
+#endif /* !PHY_LINK_MONITOR_INT */
+
+ postInitialized = TRUE;
+ return retVal;
+}
+
+err_t rpp_eth_lwip_init(struct netif *netif)
+{
+ struct hdkif *hdkif = netif->state;
+
+#if LWIP_NETIF_HOSTNAME
+ netif->hostname = "rpp";
+#endif
+ netif->state = hdkif;
+
+ netif->name[0] = IFNAME0;
+ netif->name[1] = IFNAME1;
+
+#if !NO_SYS
+ hdkif->waitTicksForPHYAneg = TICKS_PHY_AUTONEG;
+#endif
+
+ /*
+ * Initialize the snmp variables and counters inside the struct netif.
+ * The last argument should be replaced with your link speed, in units
+ * of bits per second.
+ */
+ NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
+
+ /* We directly use etharp_output() here to save a function call.
+ * You can instead declare yo_SKIP_TO_HWur own function an call etharp_output()
+ * from it if you have to do some checks before sending (e.g. if link
+ * is available...)
+ */
+ netif->output = etharp_output;
+ netif->linkoutput = rpp_eth_send;
+
+ return rpp_eth_hw_init_postInit(netif);
+}
+
+#define INIT_ONLY_AFTER_RESET 1 // FIXME Why? Wat? Wut? For future implementation?
+static err_t rpp_eth_hw_init(struct hdkif *hdkif)
+{
+ uint8_t index;
+ uint16_t regContent;
+ uint32_t physAlive;
+
+ /* Deactivate reset pin of PHY */
+ /*
+ * For hw reset of PHY, it is necessary that PIN_NAME_ETHRST is 1us
+ * logical low state, before putting it to logical high
+ */
+#if !INIT_ONLY_AFTER_RESET
+#if NO_SYS
+ /*
+ * Initially used to hw reset of PHY connected to GIO pin.
+ * This means 1us - for 80MHz clock.
+ */
+ index = 80;
+#else /* NO_SYS */
+ /*
+ * Initially used to hw reset of PHY connected to GIO pin
+ * 'rpp project only'; 1us - according to PHY specification.
+ */
+ index = configCPU_CLOCK_HZ/1000000;
+#endif /* NO_SYS */
+ dio_gpio_pin_set_value(*dio_gpio_pin_get_dsc(PIN_NAME_ETHRST, -1), 0);
+ while (index--) ;
+#endif /* !INIT_ONLY_AFTER_RESET */
+ /* we have pull-down resistor, so after reset, we only need to put ETHRST pin to log. high */
+ dio_gpio_pin_set_value(*dio_gpio_pin_get_dsc(DIO_PIN_NAME_ETHRST, -1), 1);
+
+ /*
+ * We have pull-down resistor, so after reset, we only need
+ * to put ETHRST pin to log. high
+ */
+ dio_gpio_pin_set_value(*dio_gpio_pin_get_dsc(DIO_PIN_NAME_ETHRST, -1), 1);
+
+ /* Initialize EMAC control module and EMAC module */
+ EMACInit(hdkif->emac_ctrl_base, hdkif->emac_base);
+ /* Initialize MDIO module (reset) */
+ MDIOInit(hdkif->mdio_base, 0x0, 0x0);
+
+ /*
+ * Try to read random register from defaultPhy to make MDIO fill alive
+ * bit for this one if it returned ACK bit in msg response -- this must
+ * be done, because MDIO has not set alive bit of PHY after that
+ * short time after MDIOInit()
+ */
+ MDIOPhyRegRead(hdkif->mdio_base, hdkif->phy_addr, PHY_BMSR, ®Content);
+
+ /* Find first alive PHY -- or use default if alive */
+ physAlive = MDIOPhyAliveStatusGet(hdkif->mdio_base);
+ if (!(physAlive & (1 << hdkif->phy_addr))) {
+#if FIND_FIRST_PHY_ALIVE
+ for (index = 0; index < NUM_OF_PHYs; index++) {
+ if (physAlive && (1 << index)) {
+ hdkif->phy_addr = index;
+ break;
+ } else {
+ /*
+ * Try to 'wake up' PHY on 'index' address by
+ * reading random register, making MDIO set
+ * alive bit for current PHY
+ */
+ MDIOPhyRegRead(hdkif->mdio_base, index,
+ PHY_BMCR, ®Content);
+
+ /* Get updated register */
+ physAlive = MDIOPhyAliveStatusGet(hdkif->mdio_base);
+ if (physAlive && (1 << index)) {
+ hdkif->phy_addr = index;
+ break;
+ }
+ }
+ }
+
+ if (!physAlive) { /* FIXME je to ok? */
+ rpp_debug_printf("no phy found, phys: %d\n", physAlive);
+ return NO_PHY_ALIVE;
+ }
+#else
+ rpp_debug_printf("default phy not alive\n");
+ return DFLT_PHY_NOT_ALIVE;
+#endif
+ }
+
+ /*
+ * Start autonegotiation and check on completion later or
+ * when complete link register will be updated
+ */
+ hdkif->phy_autoneg_start(hdkif->mdio_base, hdkif->phy_addr,
+ PHY_100BASETXDUPL_m | PHY_100BASETX_m |
+ PHY_10BASETDUPL_m | PHY_10BASET_m);
+
+ /*
+ * TODO: you can implement init of receive flow control somewhere
+ * here if desired - set RXBUFFERFLOWEN in MACCONTROL
+ */
+
+
+ /* Acknowledge EMAC control module RX, TX and MISC interrupts */
+ EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_RX);
+ EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_TX);
+ EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_MISC);
+
+ /* Sets which channel will receive broadcasts */
+ EMACRxBroadCastEnable(hdkif->emac_base, CHANNEL);
+
+ /*
+ * Sets channel where all frames will be copied to --
+ * either with MAC address different from local device address,
+ * either packets with error will be copied; appropriate error
+ * will be set in the frame EOP buffer descriptor
+ */
+ EMACRxPromiscEnable(hdkif->emac_base, CHANNEL);
+
+ /* Enable unicast */
+ EMACRxUnicastSet(hdkif->emac_base, CHANNEL);
+
+ /* Enable TX and RX interrupts in both EMAC module and EMAC control module */
+ EMACTxIntPulseEnable(hdkif->emac_base, hdkif->emac_ctrl_base, 0, CHANNEL);
+ EMACRxIntPulseEnable(hdkif->emac_base, hdkif->emac_ctrl_base, 0, CHANNEL);
+
+ return SUCCESS;
+}
+
+static err_t rpp_eth_hw_init_postInit(struct netif *netif)
+{
+ /* 0x3FFFFFFF is for 80MHz aproximately 13s */
+ volatile unsigned int autonegFinishWait = 0x3FFFFFFF;
+
+ uint16_t regContent;
+ uint32_t num_bd, pbuf_cnt = 0;
+ volatile struct emac_tx_bd *curr_txbd, *last_txbd;
+ volatile struct emac_rx_bd *curr_rxbd, *last_rxbd;
+ struct pbuf *p, *q;
+ struct rxch *rxch;
+ struct txch *txch;
+
+ struct hdkif *hdkif = (struct hdkif *)netif->state;
+
+ rxch = &(hdkif->rxch);
+ txch = &(hdkif->txch);
+
+ rpp_debug_printf("autoneg started -- check on cable if it's connected!\r\n");
+
+ /*
+ * Use the CPPI RAM to store RX/TX Buffer Descriptors (= BD).
+ * 1/2 of CPPI RAM is used for TX BDs, another 1/2 for RX BDs.
+ * All the TX BDs are 'owned' by the software. They are initialized
+ * as a linked-list forming a ring. They are awaiting the application
+ * to append pbuf payload to the them and correctly configure for
+ * actual transmission.
+ * Only such number of RX BDs is configured that the pbufs can be
+ * allocated for (i.e. MAX_RX_PBUF_ALLOC). Pbufs are allocated from
+ * the PBUF_POOL (thus the allocated pbufs might be chained).
+ * Each payload part of a payload is them used to initialize single
+ * RX BD. The RX BDs are then configured to be 'owned' bythe EMAC
+ */
+
+ /*
+ * Initialize the Descriptor Memory For TX and RX
+ * Only Channel 0 is supported for both TX and RX
+ */
+ txch->free_head = (volatile struct emac_tx_bd *)hdkif->emac_ctrl_ram;
+ txch->next_bd_to_process = txch->free_head;
+ txch->active_tail = NULL;
+
+ /* Set the number of descriptors for the channel */
+ /* take half of CPPI ram for TX BDs */
+ num_bd = ((SIZE_EMAC_CTRL_RAM >> 1) / sizeof(struct emac_tx_bd));
+
+ curr_txbd = txch->free_head;
+
+ /* Initialize all the TX buffer Descriptors */
+ while (num_bd--) {
+ curr_txbd->next = curr_txbd + 1;
+ curr_txbd->flags_pktlen = 0;
+ last_txbd = curr_txbd;
+ curr_txbd = curr_txbd->next;
+ }
+ last_txbd->next = txch->free_head;
+ /* curr_txbd now points to the BD that is the first BD
+ * after the last_txbd -- this will be the first RX BD
+ */
+
+ /* Initialize the descriptors for the RX channel */
+ rxch->active_head = (volatile struct emac_rx_bd*)curr_txbd;
+ rxch->free_head = NULL; /* Not used */
+ rxch->freed_pbuf_len = 0;
+
+ num_bd = ((SIZE_EMAC_CTRL_RAM >> 1) / sizeof(struct emac_rx_bd));
+ curr_rxbd = rxch->active_head;
+ last_rxbd = curr_rxbd;
+
+ /* Allocate the pbufs for the maximum count permitted or
+ * till the number of buffer descriptors expire,
+ * whichever is earlier.
+ */
+ while (pbuf_cnt < MAX_RX_PBUF_ALLOC) {
+ /* Sidenote -- remember that the PBUF might be chained */
+ p = pbuf_alloc(PBUF_RAW, PBUF_LEN_MAX, PBUF_POOL);
+ if (p != NULL) {
+ /* Watch out not to excede the number of available BDs */
+ if (((uint32_t)pbuf_clen(p)) <= num_bd) {
+ /* Fill in the BD to reference the allocated pbuf */
+ /* for each PBUF chunk */
+ for (q = p; q != NULL; q = q->next) {
+ curr_rxbd->bufptr = (uint8_t *)q->payload;
+ curr_rxbd->bufoff_len = q->len;
+ curr_rxbd->next = curr_rxbd + 1;
+ curr_rxbd->flags_pktlen = EMAC_DSC_FLAG_OWNER;
+
+ /* Save the pbuf */
+ curr_rxbd->pbuf = q;
+ last_rxbd = curr_rxbd;
+ curr_rxbd = curr_rxbd->next;
+ num_bd--;
+ }
+ } else {
+ /* free the allocated pbuf if no free
+ * descriptors are left */
+ pbuf_free(p);
+ break;
+ }
+ } else {
+ break;
+ }
+ pbuf_cnt++;
+ }
+ if (!pbuf_cnt)
+ rpp_sci_printf("No pbufs attached to RX BD during init\n");
+
+ last_rxbd->next = NULL;
+ rxch->active_tail = last_rxbd;
+
+#ifdef DEBUG
+ num_bd = (((uintptr_t)rxch->active_tail - (uintptr_t)rxch->active_head)
+ / sizeof(struct emac_rx_bd)) + 1;
+ rpp_debug_printf("%d pbuf chains allocated for %d rx buffer descriptors\n",
+ pbuf_cnt, num_bd);
+#endif
+
+ /* Set header descriptor pointers -- this shows EMAC which descriptor
+ * is the first one for writing received frames/packets
+ */
+ EMACRxHdrDescPtrWrite(hdkif->emac_base, (uint32_t)rxch->active_head, CHANNEL);
+
+ /* set MAC address */
+ netif->hwaddr_len = MAC_ADDR_LEN;
+ for (regContent = 0; regContent < MAC_ADDR_LEN; regContent++) {
+ netif->hwaddr[regContent] =
+ hdkif->mac_addr[(MAC_ADDR_LEN - 1) - regContent];
+ }
+
+ /* maximum transfer unit */
+ netif->mtu = MAX_TRANSFER_UNIT;
+
+ /* device capabilities */
+ /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
+ netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+
+
+ /* for flow control frames */
+ EMACMACSrcAddrSet(hdkif->emac_base, hdkif->mac_addr);
+
+ /* Be sure to program all eight MAC address registers -
+ * whether the receive channel is to be enabled or not.
+ */
+ for (regContent = 0; regContent < 8; regContent++) {
+ EMACMACAddrSet(hdkif->emac_base, regContent, hdkif->mac_addr,
+ EMAC_MACADDR_NO_MATCH_NO_FILTER);
+ }
+
+#if !PHY_LINK_MONITOR_INT
+ /* In case we don't use interrupt when phy link status changes,
+ * we need to try to finish autoneg in here
+ */
+ /* wait for autonegotiation to be done or continue, when delay was reached */
+ #if !NO_SYS
+ uint32_t timeToWake = hdkif->waitTicksForPHYAneg + sys_jiffies();
+ while (hdkif->phy_autoneg_is_done(hdkif->mdio_base, hdkif->phy_addr) == FALSE &&
+ timeToWake > sys_jiffies())
+ {
+ vTaskDelay(20);
+ /* XXX: if init is not done at the startup,
+ * but couple days later, this might cause troubles */
+ }
+
+ #else
+ while (hdkif->phy_autoneg_is_done(hdkif->mdio_base, hdkif->phy_addr) == FALSE &&
+ autonegFinishWait--)
+ ; /* wait till aneg done */
+ #endif
+
+ if (hdkif->phy_autoneg_is_done(hdkif->mdio_base, hdkif->phy_addr) != FALSE)
+ rpp_debug_printf("autoneg finished\n");
+ else
+ rpp_debug_printf("autoneg timeout\n");
+
+ /* provide informations retrieved from autoneg to EMAC module */
+ hdkif->phy_partnerability(hdkif->mdio_base, hdkif->phy_addr, ®Content);
+ if (regContent & (PHY_100BASETXDUPL_m | PHY_10BASETDUPL_m)) {
+ EMACDuplexSet(hdkif->emac_base, EMAC_DUPLEX_FULL);
+ /* this is right place to implement transmit flow control if desired --
+ * set TXFLOWEN in MACCONTROL
+ */
+ } else if (regContent & (PHY_100BASETX_m | PHY_10BASET_m)) {
+ EMACDuplexSet(hdkif->emac_base, EMAC_DUPLEX_HALF);
+ } else {
+ rpp_debug_printf("Unknown duplex mode\r\n");
+ return UNKN_DUPLEX_MODE;
+ }
+#endif /* !PHY_LINK_MONITOR_INT */
+
+ /* enable hostpend interrupts in emac module */
+ HWREG(hdkif->emac_base + EMAC_MACINTMASKSET) |=
+ EMAC_MACINTMASKSET_HOSTMASK;
+
+ /* enable hostpend interrupts in emac control module */
+ HWREG(hdkif->emac_ctrl_base + EMAC_CTRL_CnMISCEN(0)) |=
+ EMAC_CTRL_MISC_HOSTPENDENB;
+
+ EMACMIIEnable(hdkif->emac_base);
+ EMACTxEnable(hdkif->emac_base);
+ EMACRxEnable(hdkif->emac_base);
+
+ return SUCCESS;
+}
+
+/* send and receive functions / ISRs ******************************************/
+
+err_t rpp_eth_send(struct netif *netif, struct pbuf *p)
+{
+ err_t retVal = SUCCESS;
+ SYS_ARCH_DECL_PROTECT(lev);
+
+ /**
+ * This entire function must be protected to preserve
+ * the integrity of the transmit pbuf queue.
+ */
+ SYS_ARCH_PROTECT(lev);
+#if !SYS_LIGHTWEIGHT_PROT
+ uint32_t prevProt = (uint32_t) _get_CPSR() & 0x80;
+ _disable_IRQ();
+#endif
- // FIXME: Implement.
- return SUCCESS;
+ /* adjust the packet length if less than minimum required */
+ if (p->tot_len < MIN_PKT_LEN) {
+ p->tot_len = MIN_PKT_LEN;
+ p->len = MIN_PKT_LEN;
+ }
+
+ /**
+ * Bump the reference count on the pbuf to prevent it from being
+ * freed until we are done with it.
+ */
+ pbuf_ref(p);
+
+ /* call the actual transmit function */
+ retVal = rpp_eth_send_raw(netif, p);
+
+ /* Return to prior interrupt state and return. */
+ SYS_ARCH_UNPROTECT(lev);
+#if !SYS_LIGHTWEIGHT_PROT
+ if (!prevProt)
+ _enable_IRQ();
+#endif
+
+ return retVal;
}
+/**
+ * When called from rpp_eth_send(), the 'lev' lock is held
+ */
+static err_t rpp_eth_send_raw(struct netif *netif, struct pbuf *pbuf)
+{
+ struct pbuf *q;
+ struct txch *txch;
+ struct hdkif *hdkif;
+ volatile struct emac_tx_bd *curr_bd;
+ /* Head of the BD chain representing 'active' BDs --
+ * those that are modified/added in this function
+ */
+ volatile struct emac_tx_bd *active_head;
+ /* Same as active_head, but this is the tail of the list */
+ volatile struct emac_tx_bd *active_tail;
+
+ hdkif = (struct hdkif *)netif->state;
+ txch = &(hdkif->txch);
+
+ /* Get the first BD that is unused and will be used for TX */
+ curr_bd = txch->free_head;
+ active_head = curr_bd;
+
+ /* Be sure that the free_head didn't wrap around the chain
+ * of all BDs pointing to the BD being processed by the EMAC
+ * (in such case txch->free_head would be the same as
+ * txch->next_bd_to_process)
+ */
+ while (curr_bd->flags_pktlen & EMAC_DSC_FLAG_OWNER)
+ ;
+
+ /* First 'part' of packet flags */
+ curr_bd->flags_pktlen = pbuf->tot_len |
+ EMAC_DSC_FLAG_SOP |
+ EMAC_DSC_FLAG_OWNER;
+
+ /* Copy pbuf information into TX BDs --
+ * remember that the pbuf for a single packet might be chained!
+ */
+ for (q = pbuf; q != NULL; q = q->next) {
+ curr_bd->bufptr = (uint8_t *)(q->payload);
+ curr_bd->bufoff_len = (q->len) & 0xFFFF;
+
+ active_tail = curr_bd;
+ /* This is an extra field that is not par of the in-HW BD.
+ * This is used when freeing the pbuf after the TX processing
+ * is done in EMAC
+ */
+ curr_bd->pbuf = pbuf;
+
+ curr_bd = curr_bd->next;
+ curr_bd->flags_pktlen = 0x0;
+ }
+ /* Indicate the end of the packet */
+ active_tail->next = NULL;
+ active_tail->flags_pktlen |= EMAC_DSC_FLAG_EOP;
+
+ /* Since we used the txch->free_head as the first BD for our purpose,
+ * set the new free_head just behind the active_tail
+ */
+ txch->free_head = curr_bd;
+
+ /* For the first time, write the HDP with the filled bd */
+ if (txch->active_tail == NULL) {
+ EMACTxHdrDescPtrWrite(hdkif->emac_base,
+ (unsigned int)(active_head), CHANNEL);
+ } else {
+ /* Chain the bd's. If the DMA engine already reached the
+ * end of the chain, the EOQ will be set. In that case,
+ * the HDP shall be written again.
+ */
+ curr_bd = txch->active_tail;
+ curr_bd->next = active_head;
+
+#if 0
+ /* Just a workaround in case "appending" to
+ * the last active BD will not work
+ */
+ while (!(curr_bd->flags_pktlen & EMAC_DSC_FLAG_EOQ))
+ ;
+#endif
+
+ /* We were too slow and the EMAC already read the
+ * 'pNext = NULL' of the former txch->active_tail. In this
+ * case the transmission stopped and we need to write the
+ * pointer to newly added BDs to the TX HDP
+ */
+ if (curr_bd->flags_pktlen & EMAC_DSC_FLAG_EOQ) {
+ /* Writes to TX HDP are allowed only when it is 0 */
+ while (HWREG(hdkif->emac_base + EMAC_TXHDP(CHANNEL)) != 0)
+ ;
+ EMACTxHdrDescPtrWrite(hdkif->emac_base,
+ (unsigned int)(active_head), CHANNEL);
+ }
+ }
+ txch->active_tail = active_tail;
+
+ return SUCCESS;
+}
+
+void rpp_eth_send_raw_thr(void *arg)
+{
+ struct hdkif *hdkif;
+ struct txch *txch;
+ volatile struct emac_tx_bd *curr_bd;
+ volatile struct emac_tx_bd *next_bd_to_process;
+ struct netif *netif = (struct netif*)arg;
+
+ hdkif = netif->state;
+ txch = &(hdkif->txch);
+
+ for (;;) {
+ /* Block if there is nothing to do.
+ * Wake up if an TX interrupt occured.
+ */
+ xSemaphoreTake(hdkif->goTX, portMAX_DELAY);
+
+ next_bd_to_process = txch->next_bd_to_process;
+ curr_bd = next_bd_to_process;
+
+ /* Traverse the list of BDs used for transmission --
+ * stop on the first unused
+ */
+ while (curr_bd->flags_pktlen & EMAC_DSC_FLAG_SOP) {
+ /* Make sure the transmission is over */
+ while (curr_bd->flags_pktlen & EMAC_DSC_FLAG_OWNER)
+ ;
+
+ /* Find the last chunk of the packet */
+ while (!(curr_bd->flags_pktlen & EMAC_DSC_FLAG_EOP))
+ curr_bd = curr_bd->next;
+
+ /* Remove flags for the transmitted BDs */
+ next_bd_to_process->flags_pktlen &= (~EMAC_DSC_FLAG_SOP);
+ curr_bd->flags_pktlen &= (~EMAC_DSC_FLAG_EOP);
+
+ /* Point the txch->next_bd_to_process to the BDs
+ * following the 'last BD belonging to the packet
+ * being processed'
+ */
+ if (curr_bd->next == NULL)
+ txch->next_bd_to_process = txch->free_head;
+ else
+ txch->next_bd_to_process = curr_bd->next;
+
+ /* Ack the Interrupt in the EMAC peripheral */
+ EMACTxCPWrite(hdkif->emac_base, CHANNEL,
+ (uint32_t)curr_bd);
+
+ /* Free the corresponding pbuf
+ * Sidenote: Each fragment of the single packet points
+ * to the same pbuf // FIXME is it true?
+ */
+ pbuf_free(curr_bd->pbuf);
+
+ LINK_STATS_INC(link.xmit);
-#endif /* rppCONFIG_INCLUDE_ETH */
+ /* Move to the next packet */
+ next_bd_to_process = txch->next_bd_to_process;
+ curr_bd = next_bd_to_process;
+ }
+ /* Ack the Interrupt in the EMAC peripheral */
+ EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_TX);
+ //EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_RX); // Proc?
+ /* Enable the interrupt in the VIM */
+ vim_mask_set(TXinterruptVectorNumber);
+ }
+}
+
+void rpp_eth_recv_raw_thr(void *arg)
+{
+ struct hdkif *hdkif;
+ struct rxch *rxch;
+ struct netif *netif = (struct netif*)arg;
+ volatile struct emac_rx_bd *curr_bd;
+ volatile struct emac_rx_bd *curr_tail;
+ volatile struct emac_rx_bd *curr_head;
+ struct pbuf *pbuf;
+ struct pbuf *new_pbuf;
+ struct pbuf *q;
+
+ hdkif = netif->state;
+ rxch = &(hdkif->rxch);
+
+ for (;;) {
+ /* Block if there is nothing to do.
+ * Wake up if an RX interrupt occured.
+ */
+#if 0
+ sys_arch_sem_wait(&(hdkif->goRX), 0);
+#endif
+ xSemaphoreTake(hdkif->goRX, portMAX_DELAY);
+
+ /* Get the bd which contains the earliest filled data */
+ curr_bd = rxch->active_head;
+
+ /* For each valid frame */
+ while (curr_bd->flags_pktlen & EMAC_DSC_FLAG_SOP) {
+ unsigned int total_rx_len;
+ unsigned int processed_rx_len = 0;
+
+ /* Start processing once the packet is released by the EMAC. */
+ while (curr_bd->flags_pktlen & EMAC_DSC_FLAG_OWNER)
+ ;
+
+ pbuf = curr_bd->pbuf;
+ total_rx_len = curr_bd->flags_pktlen & 0xFFFF;
+
+ /* The received frame might be fragmented into muliple
+ * pieces -- each one referenced by a separate BD.
+ * To further process the data, we need to 'make' a
+ * proper PBUF out of it -- that means linking each
+ * buffer together, copy the length information form
+ * the DB to PBUF, calculate the 'tot_len' etc.
+ */
+ for (;;) {
+ q = curr_bd->pbuf;
+ /* Since this pbuf will be freed, we need to
+ * keep track of its size to be able to
+ * allocate it back again
+ */
+ rxch->freed_pbuf_len += q->len;
+
+ /* This is the size of the "received data" not the PBUF */
+ q->tot_len = total_rx_len - processed_rx_len;
+ q->len = curr_bd->bufoff_len & 0xFFFF;
+
+ if (curr_bd->flags_pktlen & EMAC_DSC_FLAG_EOP)
+ break;
+ /*
+ * If we are executing here, it means this
+ * packet is being split over multiple BDs
+ */
+
+ /* chain the pbufs since they belong
+ * to the same packet
+ */
+ q->next = (curr_bd->next)->pbuf;
+
+ processed_rx_len += q->len;
+ curr_bd = curr_bd->next;
+ }
+ /* Close the chain */
+ q->next = NULL;
+
+ LINK_STATS_INC(link.recv);
+
+ /* Process the packet */
+ /* ethernet_input((struct pbuf *)pbuf, netif) */
+ if (netif->input((struct pbuf *)pbuf, netif) != ERR_OK) {
+ LINK_STATS_INC(link.memerr);
+ LINK_STATS_INC(link.drop);
+ }
+
+ /* Acknowledge that this packet is processed */
+ EMACRxCPWrite(hdkif->emac_base, 0, (unsigned int)curr_bd);
+
+ curr_head = rxch->active_head;
+ rxch->active_head = curr_bd->next;
+
+ /* The earlier PBUF chain is freed from the upper layer.
+ * So, we need to allocate a new pbuf chain and update
+ * the descriptors with the PBUF info.
+ * Care should be taken even if the allocation fails.
+ */
+ for (;;) {
+ new_pbuf = pbuf_alloc(PBUF_RAW,
+ rxch->freed_pbuf_len,
+ PBUF_POOL);
+ if (new_pbuf == NULL) {
+ /* Cycle until the pbuf is
+ * succesfully allocated
+ */
+ /* Actively poll to decrease the time
+ * when the RX interrupts are disabled
+ */
+ continue;
+ } else {
+ curr_tail = curr_bd;
+ curr_tail->next = NULL;
+ curr_bd = curr_head;
+
+ q = new_pbuf;
+ curr_bd = curr_head;
+ for (;;) {
+ if (q == NULL)
+ break;
+ if (curr_bd == NULL)
+ break;
+
+ curr_bd->bufptr = (uint8_t *)q->payload;
+ curr_bd->bufoff_len = q->len;
+ curr_bd->flags_pktlen =
+ EMAC_DSC_FLAG_OWNER;
+ curr_bd->pbuf = q;
+
+ rxch->freed_pbuf_len -= q->len;
+ q = q->next;
+ curr_bd = curr_bd->next;
+ }
+
+ /* At this point either the whole pbuf
+ * was used or there are no RX BDs left.
+ * If there is not enough RX BDs to assign
+ * all pbufs in the chain, free the
+ * rest of the pbufs.
+ */
+ if (q != NULL)
+ pbuf_free((struct pbuf *)q);
+
+ /* Add the newly allocated BDs to the
+ * end of the list
+ */
+ rxch->active_tail->next = curr_head;
+ /* Check if the reception has ended.
+ * If the EOQ flag is set, the NULL
+ * pointer is taken by the DMA engine.
+ * So we need to write the RX HDP
+ * with the next descriptor.
+ */
+ if (rxch->active_tail->flags_pktlen &
+ EMAC_DSC_FLAG_EOQ)
+ {
+ /* Writes to RX HDP are allowed
+ * only when it is 0
+ */
+ while (HWREG(hdkif->emac_base +
+ EMAC_RXHDP(CHANNEL)) != 0)
+ ;
+
+ EMACRxHdrDescPtrWrite(
+ hdkif->emac_base,
+ (uint32_t)curr_head,
+ CHANNEL);
+ }
+
+ rxch->active_tail = curr_tail;
+ break;
+ }
+ }
+ curr_bd = rxch->active_head;
+ }
+
+ /* Ack the Interrupt in the EMAC peripheral */
+ EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_RX);
+ //EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_TX);
+ /* Enable the interrupt in the VIM */
+ vim_mask_set(RXinterruptVectorNumber);
+ }
+}
+
+void RxIntHandler(u32_t instNum)
+{
+ vim_mask_clr(RXinterruptVectorNumber);
+ /* Unblock the RX task. */
+ xSemaphoreGiveFromISR(hdkif_data[instNum].goRX, NULL);
+}
+
+void TxIntHandler(u32_t instNum)
+{
+ vim_mask_clr(TXinterruptVectorNumber); /* see sys_startup.c */
+ xSemaphoreGiveFromISR(hdkif_data[instNum].goTX, NULL);
+}
+
+/**
+ * TX err codes:
+ * 0 No error
+ * 1h SOP error; the buffer is the first buffer in a packet,
+ * but the SOP bit is not set in software.
+ * 2h Ownership bit not set in SOP buffer
+ * 3h Zero next buffer descriptor pointer without EOP
+ * 4h Zero buffer pointer
+ * 5h Zero buffer length
+ * 6h Packet length error (sum of buffers is less than packet length)
+ *
+ * RX err codes:
+ * 0 No error
+ * 1h Reserved
+ * 2h Ownership bit not set in SOP buffer
+ * 3h Reserved
+ * 4h Zero buffer pointer
+ */
+boolean_t HostPendErrHandler(void)
+{
+ uint8_t index = MAX_EMAC_INSTANCE;
+ uint8_t errFound = FALSE;
+ uint32_t reg;
+ struct hdkif *hdkif;
+
+ while (index) {
+ hdkif = &hdkif_data[--index];
+
+ if (EMACIntVectorGet(hdkif->emac_base) & EMAC_MACINVECTOR_HOSTPEND)
+ errFound = TRUE;
+ }
+
+ if (!errFound)
+ return FALSE; /* this is not the cause of the interrupt */
+
+ rpp_sci_printk("HOSTPEND err\n");
+ reg = HWREG(hdkif->emac_base + EMAC_MACSTATUS);
+ rpp_sci_printk("TXCHERR: %d at CH: %d\n",
+ ((reg >> EMAC_MACSTATUS_TXERRCODE_SHIFT) & 0x7),
+ ((reg >> EMAC_MACSTATUS_TXERRCH_SHIFT) & 0x7));
+ rpp_sci_printk("RXCHERR: %d at CH: %d\n",
+ ((reg >> EMAC_MACSTATUS_RXERRCODE_SHIFT) & 0x7),
+ ((reg >> EMAC_MACSTATUS_RXERRCH_SHIFT) & 0x7));
+
+ { /* Print out all the RX BDs */
+ struct rxch *rxch;
+ volatile struct emac_rx_bd *curr_bd;
+ rxch = &(hdkif->rxch);
+ int glob_len = 0;
+
+ rpp_sci_printk("rxch->active_head: %p\n", rxch->active_head);
+ rpp_sci_printk("rxch->active_tail: %p\n", rxch->active_tail);
+ rpp_sci_printk("rxch->freed_pbuf_len: %p\n", rxch->freed_pbuf_len);
+ rpp_sci_printk("RXCP: 0x%x\n", *((uint32_t*)(hdkif->emac_base + EMAC_RXCP(0))));
+
+ for (curr_bd = rxch->active_head; curr_bd != 0; curr_bd = curr_bd->next) {
+ glob_len += curr_bd->pbuf->len;
+
+ rpp_sci_printk("[%p: buf: %p buffoff_len: 0x%x "
+ "\tflags: 0x%x pktlen: 0x%x]",
+ curr_bd,
+ curr_bd->bufptr,
+ curr_bd->bufoff_len,
+ (curr_bd->flags_pktlen >> 16) & 0xFFFF,
+ curr_bd->flags_pktlen & 0xFFFF);
+ rpp_sci_printk(" pbuf: tot_len: 0x%x \tlen: 0x%x ref: 0x%x\n",
+ curr_bd->pbuf->tot_len,
+ curr_bd->pbuf->len,
+ curr_bd->pbuf->ref);
+ }
+ rpp_sci_printk("glob_len: %d\n", glob_len);
+ }
+
+ /* no acknowledge - emac module has to be restarted */
+
+ /* this was the reason of interrupt */
+ return TRUE;
+}
+
+#if PHY_LINK_MONITOR_INT
+boolean_t LinkIntHandler(void)
+{
+ uint8_t index = MAX_EMAC_INSTANCE;
+ uint8_t phyFound = FALSE;
+ struct hdkif *hdkif;
+ uint16_t regContent;
+ volatile unsigned int autonegFinishWait = 0xFFFFFFF;
+ volatile unsigned int dhcpBindWait = 0x3FFFFFFF;
+
+ /* check each instance, whether this interrupt was meant for this
+ * function, if not return FALSE so other function may be tried
+ */
+ while (index) {
+ hdkif = &hdkif_data[--index];
+ if ((hdkif->phy_addr ==
+ (HWREG(hdkif->mdio_base + MDIO_USERPHYSEL0) & 0x1f)) &&
+ (EMACIntVectorGet(hdkif->emac_base) &
+ EMAC_MACINVECTOR_LINKINT0))
+ phyFound = TRUE;
+ }
+ if (!phyFound)
+ return FALSE;
+ struct netif *netif = &hdkNetIF[hdkif->inst_num];
+
+ /* we handle here connection of cable after startup, not changes of linkstatus */
+
+ /* wait for autonegotiation to be done */
+#if ONCE_LINK_SETUP
+ while (hdkif->phy_autoneg_is_done(hdkif->mdio_base, hdkif->phy_addr) ==
+ FALSE)
+ ;
+#else /* ONCE_LINK_SETUP */
+ while (hdkif->phy_autoneg_is_done(hdkif->mdio_base, hdkif->phy_addr) ==
+ FALSE & autonegFinishWait--)
+ ;
+#endif /* ONCE_LINK_SETUP */
+
+ /* provide informations retrieved from autoneg to EMAC module */
+ hdkif->phy_partnerability(hdkif->mdio_base, hdkif->phy_addr, ®Content);
+ if (regContent & (PHY_100BASETXDUPL_m | PHY_10BASETDUPL_m)) {
+ EMACDuplexSet(hdkif->emac_base, EMAC_DUPLEX_FULL);
+ /* this is right place to implement transmit flow control
+ * if desired - set TXFLOWEN in MACCONTROL
+ */
+ } else if (regContent & (PHY_100BASETX_m | PHY_10BASET_m)) {
+ EMACDuplexSet(hdkif->emac_base, EMAC_DUPLEX_HALF);
+ } else {
+ /* acknowledge MDIO module */
+ HWREG(hdkif->mdio_base + MDIO_LINKINTRAW) =
+ MDIO_LINKINTMASKED_USERPHY0;
+ HWREG(hdkif->mdio_base + MDIO_LINKINTMASKED) =
+ MDIO_LINKINTMASKED_USERPHY0;
+
+ /* acknowledge EMAC control module by writing
+ * appropriate key to MACEOIVECTOR
+ */
+ EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_MISC);
+ return FALSE;
+ }
+ /* if link is up configure lwip struct netif */
+ if (rpp_eth_phylinkstat(hdkif->inst_num)) {
+#if STATIC_IP_ADDRESS
+ netif_set_up(netif);
+#elif LWIP_DHCP /* STATIC_IP_ADDRESS-LWIP_DHCP */
+ if (dhcp_start(netif) != ERR_OK) { /* XXX: can't be used from ISR (mem_malloc()) */
+ return DHCP_MEM_ERR;
+ }
+#if ONCE_LINK_SETUP
+ while (netif->dhcp->state != DHCP_BOUND)
+ ;
+#else
+ while (netif->dhcp->state != DHCP_BOUND & dhcpBindWait--)
+ ;
+ if (!dhcpBindWait) {
+ /* acknowledge MDIO module */
+ HWREG(hdkif->mdio_base + MDIO_LINKINTRAW) =
+ MDIO_LINKINTMASKED_USERPHY0;
+ HWREG(hdkif->mdio_base + MDIO_LINKINTMASKED) =
+ MDIO_LINKINTMASKED_USERPHY0;
+
+ /* acknowledge EMAC control module by writing
+ * appropriate key to MACEOIVECTOR
+ */
+ EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_MISC);
+ return FALSE;
+ }
+#endif
+#else /* LWIP_DHCP-LWIP_AUTOIP FIXME: there should be some kind of waiting till ip is assigned */
+ autoip_start(netif);
+#endif /* STATIC_IP_ADDRESS-LWIP_DHCP-LWIP_AUTOIP */
+#if ONCE_LINK_SETUP
+ /* turn this interrupt off */
+ HWREG(hdkif->emac_ctrl_base + EMAC_CTRL_CnMISCEN(0)) &=
+ (~EMAC_CTRL_MISC_LINKINT0ENB & 0xf);
+#endif /* ONCE_LINK_SETUP */
+ } else {
+#if ONCE_LINK_SETUP
+ /* acknowledge MDIO module */
+ HWREG(hdkif->mdio_base + MDIO_LINKINTRAW) =
+ MDIO_LINKINTMASKED_USERPHY0;
+ HWREG(hdkif->mdio_base + MDIO_LINKINTMASKED) =
+ MDIO_LINKINTMASKED_USERPHY0;
+
+ /* acknowledge EMAC control module by writing
+ * appropriate key to MACEOIVECTOR
+ */
+ EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_MISC);
+ return FALSE;
+#else
+#if STATIC_IP_ADDRESS
+ netif_set_down(netif);
+#elif LWIP_DHCP /* STATIC_IP_ADDRESS-LWIP_DHCP */
+ dhcp_stop(netif);
+#endif /* STATIC_IP_ADDRESS-LWIP_DHCP-LWIP_AUTOIP */
+#endif
+ }
+
+ /* acknowledge MDIO module */
+ HWREG(hdkif->mdio_base + MDIO_LINKINTRAW) =
+ MDIO_LINKINTMASKED_USERPHY0;
+ HWREG(hdkif->mdio_base + MDIO_LINKINTMASKED) =
+ MDIO_LINKINTMASKED_USERPHY0;
+
+ /* acknowledge EMAC control module by writing appropriate key to MACEOIVECTOR */
+ EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_MISC);
+
+ return TRUE;
+}
+#endif /* PHY_LINK_MONITOR_INT */
+#endif /* FREERTOS_POSIX */
projects / pes-rpp / rpp-lib.git / blobdiff