-/*
- * fr_rms570.c
+/* Copyright (C) 2012-2013 Czech Technical University in Prague
*
- * Created on: 9.7.2013
- * Author: michal
+ * Authors:
+ * - Michal Horn <hornmich@fel.cvut.cz>
+ *
+ * This document contains proprietary information belonging to Czech
+ * Technical University in Prague. Passing on and copying of this
+ * document, and communication of its contents is not permitted
+ * without prior written authorization.
+ *
+ * File : fr_rms570.c
+ *
+ * Abstract:
+ * FlexRay Communication driver for TMS570 source file.
*/
-#include "drv/fr_tms570.h"
+#include "drv/drv.h"
#include "sys/ti_drv_fray.h"
#include "binary.h"
-#include "hal/port_def.h"
+#include "drv/digital_io.h"
+
+/**
+ * The structure maps a RX/TX buffer to a slot in the communication cycle.
+ * Each buffer has its default values, which are defined in buffer_ptr during
+ * initialization. Those values are here for reinitialization of the driver
+ * after HALT or to provide some maximum for reconfiguration functions.
+ */
+typedef struct Fr_slot_buffer_map_st {
+ const Fr_TMS570LS_BufferConfigType *buffer_ptr; /**< Address of a buffer configuration assigned to the slot slot_id */
+ uint16_t slot_id; /**< An ID of the slot in the communication cycle. The value may not be equal to the slot_id value in the buffer configuration, after reconfiguration is done. */
+ uint8_t act_payload; /**< The actual maximum payload, that was set for the buffer by reconfiguration function. The value can be equal or lower than max_payload in buffer_ptr. */
+ uint32_t act_cyc_filter; /**< Actual cycle set filter. */
+ Fr_ChannelType act_ch_filter; /**< Actual channel filter. */
+} Fr_slot_buffer_map_t;
static Std_VersionInfoType Fr_versionInfo = {
- .vendorID = 0x00000001,
- .moduleID = 0x00000002,
- .sw_major_version = 0,
- .sw_minor_version = 1,
- .sw_patch_version = 0
+ .vendorID = 0x00000001,
+ .moduleID = 0x00000002,
+ .sw_major_version = 0,
+ .sw_minor_version = 1,
+ .sw_patch_version = 0
};
/** Prepared spi command */
/** Array of responses for each fray driver */
static uint32_t fray_spi_resp[FRAY_NUM_PORTS];
/** Array of port names to be easily accessible by indexing */
-static const char* fray_port_names[FRAY_NUM_PORTS] = { PORT_NAME_FRAY1, PORT_NAME_FRAY2 };
+static const char *fray_port_names[FRAY_NUM_PORTS] = { DIO_PORT_NAME_FRAY1, DIO_PORT_NAME_FRAY2 };
/** Array of integers, where FlexRay cluster and node configuration
* parameters are stored to be accessible by indexes defined in Fr_GeneralTypes.h.
*/
* Address of the unified structure with complete configuration of
* the FlexRay node (cluster, node, message RAM and buffer configuration)
*/
-static const Fr_ConfigType* Fr_Config;
-/** Array of address of configuration data to each buffer. */
-static const Fr_TMS570LS_BufferConfigType* Fr_BuffersPtrs[FR_MAX_BUFFERS_CNT];
+static const Fr_ConfigType *Fr_Config;
+/** Map of the buffers to their slot ID */
+static Fr_slot_buffer_map_t Fr_buffer_slot_map[FR_MAX_BUFFERS_CNT];
/** Array of flags to determine if the buffer was or was not configured. */
static boolean_t Fr_BuffersConfigured[FR_MAX_BUFFERS_CNT];
/** Array of computed data pointers addresses for each buffer. */
* Comment this line to disable error detection and make function processing
* faster, but more dangerous.
*/
-
#define DET_ACTIVATED
+/**
+ * How much times should be the CC test repeated
+ *
+ * The CC test verifies the values written to the FlexRay configuration registers.
+ */
+uint32_t FrCtrlTestCount = 50;
+
+/**
+ * Fr_PrepareLPdu and Fr_ReconfigLPdu functions enabled
+ *
+ * If the value of this variable is false, the only one API function that is allowed to configure buffers is the Fr_ControllerInit.
+ */
+boolean_t FrBufferReconfig = TRUE;
#ifdef DET_ACTIVATED
/**
static Fr_TMS570LS_DriverState Fr_DrvState = FR_ST_DRV_NOT_INITIALIZED;
#endif
+/**
+ * Create flags according to the index of the buffer, its configuration and node configuration.
+ * Flags created by this function are used in buffer configuration and reconfiguration functions.
+ *
+ * @param[in] buffer_cfg_ptr Address of the buffer configuration parameters
+ * @param[in] index of the buffer to which belong the parameters
+ *
+ * @return Buffer configuration flags. Their definition can be found in fr_tms570.h file as macros with prefixes FRAY_BUF_
+ */
+uint32_t Fr_buffer_config_flags(const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr, uint8_t bufferIndex)
+{
+ uint32_t mode = 0;
+
+ mode = (buffer_cfg_ptr->msgBufferInterrupt == TRUE) ? FRAY_BUF_MBI_EN : FRAY_BUF_MBI_DIS;
+ mode |= (buffer_cfg_ptr->singleTransmit == TRUE) ? FRAY_BUF_TX_MODE_SINGLE : FRAY_BUF_TX_MODE_CONTINUOUS;
+ mode |= (buffer_cfg_ptr->payloadPreambleIndicatorTr == TRUE) ? FRAY_BUF_NM_EN : FRAY_BUF_NM_DIS;
+ mode |= (buffer_cfg_ptr->isTx == TRUE) ? FRAY_BUF_TX : FRAY_BUF_RX;
+ mode |= (buffer_cfg_ptr->channel == FR_CHANNEL_A || buffer_cfg_ptr->channel == FR_CHANNEL_AB) ? FRAY_BUF_CHA_EN : FRAY_BUF_CHA_DIS;
+ mode |= (buffer_cfg_ptr->channel == FR_CHANNEL_B || buffer_cfg_ptr->channel == FR_CHANNEL_AB) ? FRAY_BUF_CHB_EN : FRAY_BUF_CHB_DIS;
+ mode |= (buffer_cfg_ptr->rejectNullFrames == TRUE) ? FRAY_BUF_REJECT_NULL_FRAMES : FRAY_BUF_ACCEPT_NULL_FRAMES;
+ mode |= (buffer_cfg_ptr->rejectStaticSegment == TRUE) ? FRAY_BUF_REJECT_STATIC_SEGMENT : FRAY_BUF_ACCEPT_STATIC_SEGMENT;
+ mode |= FRAY_BUF_TXREQ_DIS;
+ if (bufferIndex == 0 || (bufferIndex == 1 && Fr_Config->msgRAMConfig->syncFramePayloadMultiplexEnabled == TRUE)) { // Buffer 0 is always a key slot, if payload multiplexing is enabled, then buffer 1 serves for key slot as well.
+ if (Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSTARTUP] == 1)
+ mode |= FRAY_BUF_SFI_EN;
+ if (Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSYNC] == 1)
+ mode |= FRAY_BUF_SYNC_EN;
+ }
+ return mode;
+}
+
+/**
+ * Buffer is reconfigurable if it is not assigned to the key slot (slot for
+ * synchronization and startup) and reconfiguration is enabled in ode configuration
+ * parameters.
+ * RX FIFO buffer is never configurable.
+ *
+ * @return -1 if buffer reconfiguration is prohibited, otherwise returns index of the first buffer, which is reconfigurable.
+ */
+int Fr_reconfigurable_buffer_index()
+{
+ int lowest_index = -1;
+
+ if (Fr_Config->msgRAMConfig->secureBuffers == FR_SB_STAT_REC_DISABLED_STAT_TR_DISABLED)
+ lowest_index = frayREG->MRC_UN.MRC_ST.fdb_B8;
+ else if (Fr_Config->msgRAMConfig->secureBuffers == FR_SB_RECONFIG_ENABLED) {
+ if (Fr_Config->nodeConfiguration->pKeySlotUsedForSync == TRUE ||
+ Fr_Config->nodeConfiguration->pSingleSlotEnabled == TRUE
+ ) {
+ if (Fr_Config->msgRAMConfig->syncFramePayloadMultiplexEnabled)
+ lowest_index = 2;
+ else
+ lowest_index = 1;
+ }
+ else
+ lowest_index = 0;
+ }
+ else
+ lowest_index = -1;
+ return lowest_index;
+}
+
/**
* Compute CRC for message RAM header data
*
* @param[in] Fr_LPduPtr Pointer to header data
* @return CRC code
*/
-static int Fr_header_crc_calc(const wrhs *Fr_LPduPtr) {
- unsigned int header;
+static int Fr_header_crc_calc(const wrhs *Fr_LPduPtr)
+{
+ unsigned int header;
- int CrcInit = 0x1A;
- int length = 20;
- int CrcNext;
- unsigned long CrcPoly = 0x385;
- unsigned long CrcReg_X = CrcInit;
- unsigned long header_temp, reg_temp;
+ int CrcInit = 0x1A;
+ int length = 20;
+ int CrcNext;
+ unsigned long CrcPoly = 0x385;
+ unsigned long CrcReg_X = CrcInit;
+ unsigned long header_temp, reg_temp;
- header = ((Fr_LPduPtr->sync & 0x1) << 19) | ((Fr_LPduPtr->sfi & 0x1) << 18);
- header |= ((Fr_LPduPtr->fid & 0x7FF) << 7) | (Fr_LPduPtr->pl & 0x7F);
+ header = ((Fr_LPduPtr->sync & 0x1) << 19) | ((Fr_LPduPtr->sfi & 0x1) << 18);
+ header |= ((Fr_LPduPtr->fid & 0x7FF) << 7) | (Fr_LPduPtr->pl & 0x7F);
- header <<= 11;
- CrcReg_X <<= 21;
- CrcPoly <<= 21;
+ header <<= 11;
+ CrcReg_X <<= 21;
+ CrcPoly <<= 21;
- while(length--) {
- header <<= 1;
- header_temp = header & 0x80000000;
- reg_temp = CrcReg_X & 0x80000000;
+ while (length--) {
+ header <<= 1;
+ header_temp = header & 0x80000000;
+ reg_temp = CrcReg_X & 0x80000000;
- if(header_temp ^ reg_temp){ // Step 1
- CrcNext = 1;
- } else {
- CrcNext = 0;
- }
+ if (header_temp ^ reg_temp) // Step 1
+ CrcNext = 1;
+ else
+ CrcNext = 0;
- CrcReg_X <<= 1; // Step 2
+ CrcReg_X <<= 1; // Step 2
- if(CrcNext) {
- CrcReg_X ^= CrcPoly; // Step 3
- }
- }
+ if (CrcNext)
+ CrcReg_X ^= CrcPoly; // Step 3
+ }
- CrcReg_X >>= 21;
+ CrcReg_X >>= 21;
- return CrcReg_X;
+ return CrcReg_X;
}
/**
* Upper software layers have to read the header and data from RDDS and RDHS registers.
* @param[in] buf_num Number of buffer
*/
-static void Fr_buffer_receive_data_header(uint32_t buf_num) {
- bc read_buffer;
-
- read_buffer.obrs=buf_num; // output buffer number
- read_buffer.rdss=1; // read data section
- read_buffer.rhss=1; // read header section
+static void Fr_buffer_receive_data_header(uint32_t buf_num)
+{
+ bc read_buffer;
- // ensure no transfer in progress on shadow registers
- while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0);
- frayREG->OBCM_UN.OBCM_UL=(((read_buffer.rdss & 0x1) << 1) | (read_buffer.rhss & 0x1));
- frayREG->OBCR_UN.OBCR_UL=((1 << 9) | (read_buffer.obrs & 0x3F)); //req=1, view=0
- // wait for completion on shadow registers
- while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0);
+ read_buffer.obrs = buf_num; // output buffer number
+ read_buffer.rdss = 1; // read data section
+ read_buffer.rhss = 1; // read header section
- frayREG->OBCM_UN.OBCM_UL=(((read_buffer.rdss & 0x1) << 1) | (read_buffer.rhss & 0x1));
- frayREG->OBCR_UN.OBCR_UL=((1 << 8) | (read_buffer.obrs & 0x3F)); //req=0, view=1
+ // ensure no transfer in progress on shadow registers
+ while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0) ;
+ frayREG->OBCM_UN.OBCM_UL = (((read_buffer.rdss & 0x1) << 1) | (read_buffer.rhss & 0x1));
+ frayREG->OBCR_UN.OBCR_UL = ((1 << 9) | (read_buffer.obrs & 0x3F)); //req=1, view=0
+ // wait for completion on shadow registers
+ while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0) ;
+ frayREG->OBCM_UN.OBCM_UL = (((read_buffer.rdss & 0x1) << 1) | (read_buffer.rhss & 0x1));
+ frayREG->OBCR_UN.OBCR_UL = ((1 << 8) | (read_buffer.obrs & 0x3F)); //req=0, view=1
}
/**
*
* @param[in] Fr_LSduPtr Pointer to data structure with input buffer settings
*/
-inline void Fr_transmit_tx_LPdu(const bc *Fr_LSduPtr) {
- // ensure nothing is pending
- while ((frayREG->IBCR_UN.IBCR_UL & 0x0008000) != 0);
- frayREG->IBCM_UN.IBCM_UL=((Fr_LSduPtr->stxrh & 0x1) << 2) | ((Fr_LSduPtr->ldsh & 0x1) << 1) | (Fr_LSduPtr->lhsh & 0x1);
- frayREG->IBCR_UN.IBCR_UL=(Fr_LSduPtr->ibrh & 0x3F);
- // optimization possible for future by not gating like below
- // wait for completion on host registers
- while ((Fr_LSduPtr->ibsyh != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x00008000) != 0));
- // wait for completion on shadow registers
- while ((Fr_LSduPtr->ibsys != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x80000000) != 0));
+inline void Fr_transmit_tx_LPdu(const bc *Fr_LSduPtr)
+{
+ // ensure nothing is pending
+ while ((frayREG->IBCR_UN.IBCR_UL & 0x0008000) != 0) ;
+ frayREG->IBCM_UN.IBCM_UL = ((Fr_LSduPtr->stxrh & 0x1) << 2) | ((Fr_LSduPtr->ldsh & 0x1) << 1) | (Fr_LSduPtr->lhsh & 0x1);
+ frayREG->IBCR_UN.IBCR_UL = (Fr_LSduPtr->ibrh & 0x3F);
+ // optimization possible for future by not gating like below
+ // wait for completion on host registers
+ while ((Fr_LSduPtr->ibsyh != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x00008000) != 0)) ;
+ // wait for completion on shadow registers
+ while ((Fr_LSduPtr->ibsys != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x80000000) != 0)) ;
}
/**
* @param[in] payload Maximum data size in half-word
* @param[in] data_pointer Address of the first word of data in buffer
*/
-static void Fr_config_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer) {
- wrhs Fr_LPdu;
- bc Fr_LSdu;
- int wrhs1;
- int wrhs2;
-
- Fr_LPdu.mbi = (mode&FRAY_BUF_MBI_EN) ? 1 : 0; // message buffer interrupt
- Fr_LPdu.txm = (mode&FRAY_BUF_TX_MODE_CONTINUOUS) ? 0 : 1; // transmission mode(0=continuous mode, 1=single mode)
- Fr_LPdu.ppit = (mode&FRAY_BUF_NM_EN) ? 1 : 0; // network management Enable
- Fr_LPdu.cfg = (mode&FRAY_BUF_TX) ? 1 : 0; // message buffer configuration bit (0=RX, 1 = TX)
- Fr_LPdu.chb = (mode&FRAY_BUF_CHB_EN) ? 1 : 0; // Ch B
- Fr_LPdu.cha = (mode&FRAY_BUF_CHA_EN) ? 1 : 0; // Ch A
- Fr_LPdu.cyc = cyc_filter; // Cycle Filtering Code (no cycle filtering)
- Fr_LPdu.fid = frame_id; // Frame ID
-
- // Write Header Section 2 (WRHS2)
- Fr_LPdu.pl = payload; // Payload Length
-
- // Write Header Section 3 (WRHS3)
- Fr_LPdu.dp = data_pointer; // Pointer to start of data in message RAM
-
- Fr_LPdu.sfi = (mode&FRAY_BUF_SFI_EN) ? 1 : 0; // startup frame indicator
- Fr_LPdu.sync = (mode&FRAY_BUF_SYNC_EN) ? 1 : 0; // sync frame indicator
-
- // Write Header Section 2 (WRHS2)
- Fr_LPdu.crc = (mode&FRAY_BUF_TX) ? Fr_header_crc_calc(&Fr_LPdu) : 0;
-
- // Input buffer configuration
- Fr_LSdu.ibrh = buf_num; // input buffer number
- Fr_LSdu.ibsyh = 1; // check for input buffer busy host
- Fr_LSdu.ibsys = 1; // check for input buffer busy shadow
-
- Fr_LSdu.stxrh= (mode&FRAY_BUF_TXREQ_EN) ? 1 : 0; // set transmission request
- Fr_LSdu.ldsh = 0; // load data section
- Fr_LSdu.lhsh = 1; // load header section
- Fr_LSdu.obrs = 0; // output buffer number
- Fr_LSdu.rdss = 0; // read data section
- Fr_LSdu.rhss = 0; // read header section
-
- wrhs1 = ((Fr_LPdu.mbi) & 0x1) <<29;
- wrhs1 |= (Fr_LPdu.txm & 0x1) << 28;
- wrhs1 |= (Fr_LPdu.ppit & 0x1) << 27;
- wrhs1 |= (Fr_LPdu.cfg & 0x1) << 26;
- wrhs1 |= (Fr_LPdu.chb & 0x1) << 25;
- wrhs1 |= (Fr_LPdu.cha & 0x1) << 24;
- wrhs1 |= (Fr_LPdu.cyc & 0x7F) << 16;
- wrhs1 |= (Fr_LPdu.fid & 0x7FF);
- frayREG->WRHS1_UN.WRHS1_UL = wrhs1;
-
- wrhs2 = ((Fr_LPdu.pl & 0x7F) << 16) | (Fr_LPdu.crc & 0x7FF);
- frayREG->WRHS2_UN.WRHS2_UL = wrhs2;
-
- frayREG->WRHS3_UN.WRHS3_UL = (Fr_LPdu.dp & 0x7FF);
-
- Fr_transmit_tx_LPdu(&Fr_LSdu);
+static void Fr_config_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer)
+{
+ wrhs Fr_LPdu;
+ bc Fr_LSdu;
+ int wrhs1;
+ int wrhs2;
+
+ Fr_LPdu.mbi = (mode&FRAY_BUF_MBI_EN) ? 1 : 0; // message buffer interrupt
+ Fr_LPdu.txm = (mode&FRAY_BUF_TX_MODE_CONTINUOUS) ? 0 : 1; // transmission mode(0=continuous mode, 1=single mode)
+ Fr_LPdu.ppit = (mode&FRAY_BUF_NM_EN) ? 1 : 0; // network management Enable
+ Fr_LPdu.cfg = (mode&FRAY_BUF_TX) ? 1 : 0; // message buffer configuration bit (0=RX, 1 = TX)
+ Fr_LPdu.chb = (mode&FRAY_BUF_CHB_EN) ? 1 : 0; // Ch B
+ Fr_LPdu.cha = (mode&FRAY_BUF_CHA_EN) ? 1 : 0; // Ch A
+ Fr_LPdu.cyc = cyc_filter; // Cycle Filtering Code (no cycle filtering)
+ Fr_LPdu.fid = frame_id; // Frame ID
+
+ // Write Header Section 2 (WRHS2)
+ Fr_LPdu.pl = payload; // Payload Length
+
+ // Write Header Section 3 (WRHS3)
+ Fr_LPdu.dp = data_pointer; // Pointer to start of data in message RAM
+
+ Fr_LPdu.sfi = (mode&FRAY_BUF_SFI_EN) ? 1 : 0; // startup frame indicator
+ Fr_LPdu.sync = (mode&FRAY_BUF_SYNC_EN) ? 1 : 0; // sync frame indicator
+
+ // Write Header Section 2 (WRHS2)
+ Fr_LPdu.crc = (mode&FRAY_BUF_TX) ? Fr_header_crc_calc(&Fr_LPdu) : 0;
+
+ // Input buffer configuration
+ Fr_LSdu.ibrh = buf_num; // input buffer number
+ Fr_LSdu.ibsyh = 1; // check for input buffer busy host
+ Fr_LSdu.ibsys = 1; // check for input buffer busy shadow
+
+ Fr_LSdu.stxrh = (mode&FRAY_BUF_TXREQ_EN) ? 1 : 0; // set transmission request
+ Fr_LSdu.ldsh = 0; // load data section
+ Fr_LSdu.lhsh = 1; // load header section
+ Fr_LSdu.obrs = 0; // output buffer number
+ Fr_LSdu.rdss = 0; // read data section
+ Fr_LSdu.rhss = 0; // read header section
+
+ wrhs1 = ((Fr_LPdu.mbi) & 0x1) <<29;
+ wrhs1 |= (Fr_LPdu.txm & 0x1) << 28;
+ wrhs1 |= (Fr_LPdu.ppit & 0x1) << 27;
+ wrhs1 |= (Fr_LPdu.cfg & 0x1) << 26;
+ wrhs1 |= (Fr_LPdu.chb & 0x1) << 25;
+ wrhs1 |= (Fr_LPdu.cha & 0x1) << 24;
+ wrhs1 |= (Fr_LPdu.cyc & 0x7F) << 16;
+ wrhs1 |= (Fr_LPdu.fid & 0x7FF);
+ frayREG->WRHS1_UN.WRHS1_UL = wrhs1;
+
+ wrhs2 = ((Fr_LPdu.pl & 0x7F) << 16) | (Fr_LPdu.crc & 0x7FF);
+ frayREG->WRHS2_UN.WRHS2_UL = wrhs2;
+
+ frayREG->WRHS3_UN.WRHS3_UL = (Fr_LPdu.dp & 0x7FF);
+
+ Fr_transmit_tx_LPdu(&Fr_LSdu);
}
/**
* @param[in] payload Maximum data size in half-word
* @param[in] data_pointer Address of the first word of data in buffer
*/
-static void Fr_configure_fifo_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer) {
+static void Fr_configure_fifo_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint16_t fidMask, uint32_t payload, uint32_t data_pointer)
+{
frayREG->FRF_UN.FRF_ST.rnf = (mode&FRAY_BUF_REJECT_NULL_FRAMES) ? 1 : 0;
frayREG->FRF_UN.FRF_ST.rss = (mode&FRAY_BUF_REJECT_STATIC_SEGMENT) ? 1 : 0;
frayREG->FRF_UN.FRF_ST.fid_B11 = frame_id;
- frayREG->FRFM_UN.FRFM_ST.mfid_B11 = 0x0;
+ frayREG->FRFM_UN.FRFM_ST.mfid_B11 = fidMask;
frayREG->FRF_UN.FRF_ST.cyf_B7 = cyc_filter;
- if (mode&FRAY_BUF_CHB_EN && mode&FRAY_BUF_CHA_EN) {
+ if (mode&FRAY_BUF_CHB_EN && mode&FRAY_BUF_CHA_EN)
frayREG->FRF_UN.FRF_ST.ch_B2 = 0;
- }
- else if (mode&FRAY_BUF_CHA_EN) {
- frayREG->FRF_UN.FRF_ST.ch_B2 = 3;
- }
- else {
+ else if (mode&FRAY_BUF_CHB_EN)
+ frayREG->FRF_UN.FRF_ST.ch_B2 = 1;
+ else if (mode&FRAY_BUF_CHA_EN)
frayREG->FRF_UN.FRF_ST.ch_B2 = 2;
- }
- frame_id = 0;
+ else
+ frayREG->FRF_UN.FRF_ST.ch_B2 = 3;
Fr_config_buffer(buf_num, mode, cyc_filter, frame_id, payload, data_pointer);
}
* @param[in] buf_num Number of buffer
* @param[in] len Number of words to be loaded from data to buffer
*/
-static void Fr_buffer_transmit_data(uint32_t buf_num) {
- bc write_buffer;
-
- write_buffer.ibrh = buf_num; // input buffer number
- write_buffer.stxrh= 1; // set transmission request
- write_buffer.ldsh = 1; // load data section
- write_buffer.lhsh = 0; // load header section
- write_buffer.ibsys = 0; // check for input buffer busy shadow
- write_buffer.ibsyh = 1; // check for input buffer busy host
- Fr_transmit_tx_LPdu(&write_buffer);
+static void Fr_buffer_transmit_data(uint32_t buf_num)
+{
+ bc write_buffer;
+
+ write_buffer.ibrh = buf_num; // input buffer number
+ write_buffer.stxrh = 1; // set transmission request
+ write_buffer.ldsh = 1; // load data section
+ write_buffer.lhsh = 0; // load header section
+ write_buffer.ibsys = 0; // check for input buffer busy shadow
+ write_buffer.ibsyh = 1; // check for input buffer busy host
+ Fr_transmit_tx_LPdu(&write_buffer);
}
/** @fn wait_for_POC_ready(void)
-* @brief Wait until POC is not busy
-*/
-inline void Fr_wait_for_POC_ready() {
+ * @brief Wait until POC is not busy
+ */
+inline void Fr_wait_for_POC_ready()
+{
// Wait for PBSY bit to clear - POC not busy.
// 1: Signals that the POC is busy and cannot accept a command from the host. CMD(3-0) is locked against write accesses.
- while(((frayREG->SUCC1_UN.SUCC1_UL) & 0x00000080) != 0);
+ while (((frayREG->SUCC1_UN.SUCC1_UL) & 0x00000080) != 0) ;
}
/** @fn clear_msg_ram(void)
-* @brief Clears FRAY message RAMs
-*
-* Send command to POC to set all bits of message RAM to 0.
-* @return SUCCESS or FAILURE when command was not accepted
-*/
-static int Fr_clear_msg_RAM() {
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CLEAR_RAMS;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted) {
- return FAILURE;
- }
- Fr_wait_for_POC_ready();
- return SUCCESS;
+ * @brief Clears FRAY message RAMs
+ *
+ * Send command to POC to set all bits of message RAM to 0.
+ * @return SUCCESS or FAILURE when command was not accepted
+ */
+static int Fr_clear_msg_RAM()
+{
+ Fr_wait_for_POC_ready();
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CLEAR_RAMS;
+ if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
+ return FAILURE;
+ Fr_wait_for_POC_ready();
+ return SUCCESS;
}
*
* @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
*/
-static Std_ReturnType Fr_POC_go_to_config() {
+static Std_ReturnType Fr_POC_go_to_config()
+{
// write SUCC1 configuration
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CONFIG;
- // Check if POC has accepted last command
- if ((frayREG->SUCC1_UN.SUCC1_UL & 0xF) == 0x0)
- return E_NOT_OK;
- // Wait for PBSY bit to clear - POC not busy
- Fr_wait_for_POC_ready();
- return E_OK;
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CONFIG;
+ // Check if POC has accepted last command
+ if ((frayREG->SUCC1_UN.SUCC1_UL & 0xF) == 0x0)
+ return E_NOT_OK;
+ // Wait for PBSY bit to clear - POC not busy
+ Fr_wait_for_POC_ready();
+ return E_OK;
}
/**
*
* @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
*/
-static Std_ReturnType Fr_POC_go_to_ready_from_config() {
- Fr_wait_for_POC_ready();
- // For CHA and CHB network
- if (frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 && frayREG->SUCC1_UN.SUCC1_ST.cchb_B1){
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsa_B1 = 1U;
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsb_B1 = 1U;
- }
- // For CHA network
- else if(frayREG->SUCC1_UN.SUCC1_ST.ccha_B1){
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsa_B1 = 1U;
- }
- // For CHB network
- else if (frayREG->SUCC1_UN.SUCC1_ST.cchb_B1){
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- // Unlock sequence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsb_B1 = 1U;
- }
- else frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
-
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
-
- while ((frayREG->CCSV_UN.CCSV_UL & 0x0000003F) != 0x01)
- ; // Waiting for READY state
- return E_OK;
+static Std_ReturnType Fr_POC_go_to_ready_from_config()
+{
+ Fr_wait_for_POC_ready();
+ // For CHA and CHB network
+ if (frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 && frayREG->SUCC1_UN.SUCC1_ST.cchb_B1) {
+ // Unlock sequence
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
+ // Unlock sequence
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
+ frayREG->SUCC1_UN.SUCC1_ST.mtsa_B1 = 1U;
+ // Unlock sequence
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
+ frayREG->SUCC1_UN.SUCC1_ST.mtsb_B1 = 1U;
+ }
+ // For CHA network
+ else if (frayREG->SUCC1_UN.SUCC1_ST.ccha_B1) {
+ // Unlock sequence
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
+ // Unlock sequence
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
+ frayREG->SUCC1_UN.SUCC1_ST.mtsa_B1 = 1U;
+ }
+ // For CHB network
+ else if (frayREG->SUCC1_UN.SUCC1_ST.cchb_B1) {
+ // Unlock sequence
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
+ // Unlock sequence
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
+ frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
+ frayREG->SUCC1_UN.SUCC1_ST.mtsb_B1 = 1U;
+ }
+ else frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
+
+ if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
+ return E_NOT_OK;
+
+ while ((frayREG->CCSV_UN.CCSV_UL & 0x0000003F) != 0x01)
+ ; // Waiting for READY state
+ return E_OK;
}
/**
*
* @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
*/
-static Std_ReturnType Fr_POC_go_to_ready_from_startup() {
+static Std_ReturnType Fr_POC_go_to_ready_from_startup()
+{
Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- while ((frayREG->CCSV_UN.CCSV_UL & 0x0000003F) != 0x01); // Wait until POC is not in ready state
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
+ if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
+ return E_NOT_OK;
+ while ((frayREG->CCSV_UN.CCSV_UL & 0x0000003F) != 0x01) ; // Wait until POC is not in ready state
Fr_wait_for_POC_ready();
- return E_OK;
+ return E_OK;
}
/**
*
* @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
*/
-static Std_ReturnType Fr_POC_go_to_startup() {
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_RUN;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return (E_NOT_OK);
- Fr_wait_for_POC_ready();
- return (E_OK);
+static Std_ReturnType Fr_POC_go_to_startup()
+{
+ Fr_wait_for_POC_ready();
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_RUN;
+ if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
+ return (E_NOT_OK);
+ Fr_wait_for_POC_ready();
+ return (E_OK);
}
/**
*
* @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
*/
-void Fr_config_cluster_parameters(const Fr_TMS570LS_ClusterConfigType* clusterConfigPtr) {
+void Fr_config_cluster_parameters(const Fr_TMS570LS_ClusterConfigType *clusterConfigPtr)
+{
frayREG->SUCC1_UN.SUCC1_ST.csa_B5 = clusterConfigPtr->gColdStartAttempts;
frayREG->GTUC9_UN.GTUC9_ST.apo_B5 = clusterConfigPtr->gdActionPointOffset;
frayREG->PRTC1_UN.PRTC1_ST.casm_B7 = clusterConfigPtr->gdCASRxLowMax;
frayREG->NEMC_UN.NEMC_ST.nml_B4 = clusterConfigPtr->gNetworkManagementVectorLength;
}
-#define __notInRange(val, min, max) (((val) < (min)) || ((val) > (max)))
+Std_ReturnType Fr_verify_cluster_parameters(const Fr_TMS570LS_ClusterConfigType *clusterConfigPtr)
+{
+ boolean_t error = FALSE;
+
+ error |= frayREG->SUCC1_UN.SUCC1_ST.csa_B5 == clusterConfigPtr->gColdStartAttempts;
+ error |= frayREG->GTUC9_UN.GTUC9_ST.apo_B5 == clusterConfigPtr->gdActionPointOffset;
+ error |= frayREG->PRTC1_UN.PRTC1_ST.casm_B7 == clusterConfigPtr->gdCASRxLowMax;
+ error |= frayREG->GTUC9_UN.GTUC9_ST.dsi_B2 == clusterConfigPtr->gdDynamicSlotIdlePhase;
+ error |= frayREG->GTUC8_UN.GTUC8_ST.msl_B6 == clusterConfigPtr->gdMinislot;
+ error |= frayREG->GTUC9_UN.GTUC9_ST.mapo_B5 == clusterConfigPtr->gdMinislotActionPointOffset;
+ error |= frayREG->GTUC7_UN.GTUC7_ST.ssl_B10 == clusterConfigPtr->gdStaticSlot;
+ error |= frayREG->PRTC1_UN.PRTC1_ST.tsst_B4 == clusterConfigPtr->gdTSSTransmitter;
+ error |= frayREG->PRTC2_UN.PRTC2_ST.rxi_B6 == clusterConfigPtr->gdWakeupSymbolRxIdle;
+ error |= frayREG->PRTC2_UN.PRTC2_ST.rxl_B6 == clusterConfigPtr->gdWakeupSymbolRxLow;
+ error |= frayREG->PRTC1_UN.PRTC1_ST.rxw_B9 == clusterConfigPtr->gdWakeupSymbolRxWindow;
+ error |= frayREG->PRTC2_UN.PRTC2_ST.txi_B8 == clusterConfigPtr->gdWakeupSymbolTxIdle;
+ error |= frayREG->PRTC2_UN.PRTC2_ST.txl_B6 == clusterConfigPtr->gdWakeupSymbolTxLow;
+ error |= frayREG->SUCC2_UN.SUCC2_ST.ltn_B4 == clusterConfigPtr->gListenNoise;
+ error |= frayREG->GTUC2_UN.GTUC2_ST.mpc_B14 == clusterConfigPtr->gMacroPerCycle;
+ error |= frayREG->SUCC3_UN.SUCC3_ST.wcf_B4 == clusterConfigPtr->gMaxWithoutClockCorrectionFatal;
+ error |= frayREG->SUCC3_UN.SUCC3_ST.wcp_B4 == clusterConfigPtr->gMaxWithoutClockCorrectionPassive;
+ error |= frayREG->GTUC8_UN.GTUC8_ST.nms_B13 == clusterConfigPtr->gNumberOfMinislots;
+ error |= frayREG->GTUC7_UN.GTUC7_ST.nss_B10 == clusterConfigPtr->gNumberOfStaticSlots;
+ error |= frayREG->GTUC4_UN.GTUC4_ST.ocs_B14 == clusterConfigPtr->gOffsetCorrectionStart;
+ error |= frayREG->MHDC_UN.MHDC_ST.sfdl_B7 == clusterConfigPtr->gPayloadLengthStatic;
+ error |= frayREG->GTUC2_UN.GTUC2_ST.snm_B4 == clusterConfigPtr->gSyncNodeMax;
+ error |= frayREG->GTUC4_UN.GTUC4_ST.nit_B14 == clusterConfigPtr->gdNIT;
+ error |= frayREG->PRTC1_UN.PRTC1_ST.brp_B2 == clusterConfigPtr->gdSampleClockPeriod;
+ error |= frayREG->NEMC_UN.NEMC_ST.nml_B4 == clusterConfigPtr->gNetworkManagementVectorLength;
+ return (error == FALSE) ? E_OK : E_NOT_OK;
+}
+
+#define __notInRange(val, min, max) (((val) < (min)) || ((val) > (max)))
/**
* @brief Check cluster configuration parameters.
*
* @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
* @param [out] errCode Address where error flags will be stored.
- * We have 26 parameters to check. Every one of them has assigned its bit in this flag.
- * Error flags are defined as macros ERR_PARAM_nameOfParameter.
+ * We have 26 parameters to check. Every one of them has assigned its bit in this flag.
+ * Error flags are defined as macros ERR_PARAM_nameOfParameter.
* @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
*/
-Std_ReturnType Fr_check_cluster_parameters(const Fr_TMS570LS_ClusterConfigType* clusterConfigPtr, uint32_t* errCode) {
+Std_ReturnType Fr_check_cluster_parameters(const Fr_TMS570LS_ClusterConfigType *clusterConfigPtr, uint32_t *errCode)
+{
*errCode = ERR_PARAM_NO_ERROR;
- if (__notInRange(clusterConfigPtr->gColdStartAttempts, 2, 31)) *errCode |= ERR_PARAM_gColdStartAttempts;
- if (__notInRange(clusterConfigPtr->gdActionPointOffset, 1, 63)) *errCode |= ERR_PARAM_gdActionPointOffset;
- if (__notInRange(clusterConfigPtr->gdCASRxLowMax, 67, 99)) *errCode |= ERR_PARAM_gdCASRxLowMax;
- if (clusterConfigPtr->gdDynamicSlotIdlePhase > 2) *errCode |= ERR_PARAM_gdDynamicSlotIdlePhase;
- if (__notInRange(clusterConfigPtr->gdMinislot, 2, 63)) *errCode |= ERR_PARAM_gdMinislot;
- if (__notInRange(clusterConfigPtr->gdMinislotActionPointOffset,
- 1, 31)) *errCode |= ERR_PARAM_gdMinislotActionPointOffset;
- if (__notInRange(clusterConfigPtr->gdStaticSlot, 4, 661)) *errCode |= ERR_PARAM_gdStaticSlot;
- if (__notInRange(clusterConfigPtr->gdTSSTransmitter, 3, 15)) *errCode |= ERR_PARAM_gdTSSTransmitter;
- if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxIdle, 14, 59)) *errCode |= ERR_PARAM_gdWakeupSymbolRxIdle;
- if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxLow, 11, 59)) *errCode |= ERR_PARAM_gdWakeupSymbolRxLow;
+ if (__notInRange(clusterConfigPtr->gColdStartAttempts, 2, 31)) *errCode |= ERR_PARAM_gColdStartAttempts;
+ if (__notInRange(clusterConfigPtr->gdActionPointOffset, 1, 63)) *errCode |= ERR_PARAM_gdActionPointOffset;
+ if (__notInRange(clusterConfigPtr->gdCASRxLowMax, 67, 99)) *errCode |= ERR_PARAM_gdCASRxLowMax;
+ if (clusterConfigPtr->gdDynamicSlotIdlePhase > 2) *errCode |= ERR_PARAM_gdDynamicSlotIdlePhase;
+ if (__notInRange(clusterConfigPtr->gdMinislot, 2, 63)) *errCode |= ERR_PARAM_gdMinislot;
+ if (__notInRange(clusterConfigPtr->gdMinislotActionPointOffset, 1, 31)) *errCode |= ERR_PARAM_gdMinislotActionPointOffset;
+ if (__notInRange(clusterConfigPtr->gdStaticSlot, 4, 661)) *errCode |= ERR_PARAM_gdStaticSlot;
+ if (__notInRange(clusterConfigPtr->gdTSSTransmitter, 3, 15)) *errCode |= ERR_PARAM_gdTSSTransmitter;
+ if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxIdle, 14, 59)) *errCode |= ERR_PARAM_gdWakeupSymbolRxIdle;
+ if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxLow, 11, 59)) *errCode |= ERR_PARAM_gdWakeupSymbolRxLow;
if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxWindow,
- 76, 301)) *errCode |= ERR_PARAM_gdWakeupSymbolRxWindow;
- if (__notInRange(clusterConfigPtr->gdWakeupSymbolTxIdle, 45, 180)) *errCode |= ERR_PARAM_gdWakeupSymbolTxIdle;
- if (__notInRange(clusterConfigPtr->gdWakeupSymbolTxLow, 15, 60)) *errCode |= ERR_PARAM_gdWakeupSymbolTxLow;
- if (__notInRange(clusterConfigPtr->gListenNoise, 2, 16)) *errCode |= ERR_PARAM_gListenNoise;
- if (__notInRange(clusterConfigPtr->gMacroPerCycle, 10, 16000)) *errCode |= ERR_PARAM_gMacroPerCycle;
+ 76, 301)) *errCode |= ERR_PARAM_gdWakeupSymbolRxWindow;
+ if (__notInRange(clusterConfigPtr->gdWakeupSymbolTxIdle, 45, 180)) *errCode |= ERR_PARAM_gdWakeupSymbolTxIdle;
+ if (__notInRange(clusterConfigPtr->gdWakeupSymbolTxLow, 15, 60)) *errCode |= ERR_PARAM_gdWakeupSymbolTxLow;
+ if (__notInRange(clusterConfigPtr->gListenNoise, 2, 16)) *errCode |= ERR_PARAM_gListenNoise;
+ if (__notInRange(clusterConfigPtr->gMacroPerCycle, 10, 16000)) *errCode |= ERR_PARAM_gMacroPerCycle;
if (__notInRange(clusterConfigPtr->gMaxWithoutClockCorrectionFatal,
- clusterConfigPtr->gMaxWithoutClockCorrectionPassive, 15)) *errCode |= ERR_PARAM_gMaxWithoutClockCorrectionFatal;
+ clusterConfigPtr->gMaxWithoutClockCorrectionPassive, 15)) *errCode |= ERR_PARAM_gMaxWithoutClockCorrectionFatal;
if (__notInRange(clusterConfigPtr->gMaxWithoutClockCorrectionPassive,
- 1, 15)) *errCode |= ERR_PARAM_gMaxWithoutClockCorrectionPassive;
- if (clusterConfigPtr->gNumberOfMinislots > 7986) *errCode |= ERR_PARAM_gNumberOfMinislots;
+ 1, 15)) *errCode |= ERR_PARAM_gMaxWithoutClockCorrectionPassive;
+ if (clusterConfigPtr->gNumberOfMinislots > 7986) *errCode |= ERR_PARAM_gNumberOfMinislots;
if (__notInRange(clusterConfigPtr->gNumberOfStaticSlots,
- 2, cStaticSlotIDMax)) *errCode |= ERR_PARAM_gNumberOfStaticSlots;
+ 2, cStaticSlotIDMax)) *errCode |= ERR_PARAM_gNumberOfStaticSlots;
if (__notInRange(clusterConfigPtr->gOffsetCorrectionStart,
- 9, 15999)) *errCode |= ERR_PARAM_gOffsetCorrectionStart;
- if (clusterConfigPtr->gPayloadLengthStatic > cPayloadLengthMax) *errCode |= ERR_PARAM_gPayloadLengthStatic;
- if (__notInRange(clusterConfigPtr->gSyncNodeMax, 2, cSyncNodeMax)) *errCode |= ERR_PARAM_gSyncNodeMax;
- if (__notInRange(clusterConfigPtr->gdNIT, 7, 0x3E7D)) *errCode |= ERR_PARAM_gdNIT;
- if (clusterConfigPtr->gdSampleClockPeriod > 3) *errCode |= ERR_PARAM_gdSampleClockPeriod;
- if (clusterConfigPtr->gNetworkManagementVectorLength > 12) *errCode |= ERR_PARAM_gNetworkManagementVectorLength;
+ 9, 15999)) *errCode |= ERR_PARAM_gOffsetCorrectionStart;
+ if (clusterConfigPtr->gPayloadLengthStatic > cPayloadLengthMax) *errCode |= ERR_PARAM_gPayloadLengthStatic;
+ if (__notInRange(clusterConfigPtr->gSyncNodeMax, 2, cSyncNodeMax)) *errCode |= ERR_PARAM_gSyncNodeMax;
+ if (__notInRange(clusterConfigPtr->gdNIT, 7, 0x3E7D)) *errCode |= ERR_PARAM_gdNIT;
+ if (clusterConfigPtr->gdSampleClockPeriod > 3) *errCode |= ERR_PARAM_gdSampleClockPeriod;
+ if (clusterConfigPtr->gNetworkManagementVectorLength > 12) *errCode |= ERR_PARAM_gNetworkManagementVectorLength;
return (*errCode == 0) ? E_OK : E_NOT_OK;
}
*
* @param [in] nodeConfigPtr Address of structure with node configuration parameters
*/
-void Fr_config_node_parameters(const Fr_TMS570LS_NodeConfigType* nodeConfigPtr) {
+void Fr_config_node_parameters(const Fr_TMS570LS_NodeConfigType *nodeConfigPtr)
+{
frayREG->SUCC1_UN.SUCC1_ST.hcse_B1 = nodeConfigPtr->pAllowHaltDueToClock;
frayREG->SUCC1_UN.SUCC1_ST.pta_B5 = nodeConfigPtr->pAllowPassiveToActive;
if (nodeConfigPtr->pChannels == FR_CHANNEL_AB) {
frayREG->GTUC10_UN.GTUC10_ST.moc_B13 = nodeConfigPtr->pRateCorrectionOut;
frayREG->GTUC10_UN.GTUC10_ST.mrc_B11 = nodeConfigPtr->pOffsetCorrectionOut;
frayREG->SUCC1_UN.SUCC1_ST.tsm_B1 = nodeConfigPtr->pSingleSlotEnabled;
- if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_A) {
+ if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_A)
frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 = 0;
- }
- else if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_B) {
+ else if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_B)
frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 = 1;
- }
frayREG->PRTC1_UN.PRTC1_ST.rwp_B6 = nodeConfigPtr->pWakeupPattern;
frayREG->PRTC1_UN.PRTC1_ST.brp_B2 = nodeConfigPtr->pSamplesPerMicrotick;
+ frayREG->EIR_UN.EIR_UL = 0xFFFFFFFF;
}
+Std_ReturnType Fr_verify_node_parameters(const Fr_TMS570LS_NodeConfigType *nodeConfigPtr)
+{
+ boolean_t error = FALSE;
+
+ error |= frayREG->SUCC1_UN.SUCC1_ST.hcse_B1 == nodeConfigPtr->pAllowHaltDueToClock;
+ error |= frayREG->SUCC1_UN.SUCC1_ST.pta_B5 == nodeConfigPtr->pAllowPassiveToActive;
+ if (nodeConfigPtr->pChannels == FR_CHANNEL_AB) {
+ error |= frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 == 1;
+ error |= frayREG->SUCC1_UN.SUCC1_ST.cchb_B1 == 1;
+ }
+ else if (nodeConfigPtr->pChannels == FR_CHANNEL_A) {
+ error |= frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 == 1;
+ error |= frayREG->SUCC1_UN.SUCC1_ST.cchb_B1 == 0;
+ }
+ else {
+ error |= frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 == 0;
+ error |= frayREG->SUCC1_UN.SUCC1_ST.cchb_B1 == 1;
+ }
+ error |= frayREG->GTUC6_UN.GTUC6_ST.asr_B11 == nodeConfigPtr->pdAcceptedStartupRange;
+ error |= frayREG->GTUC5_UN.GTUC5_ST.cdd_B5 == nodeConfigPtr->pClusterDriftDamping;
+ error |= frayREG->GTUC5_UN.GTUC5_ST.dca_B8 == nodeConfigPtr->pDelayCompensationA;
+ error |= frayREG->GTUC5_UN.GTUC5_ST.dcb_B8 == nodeConfigPtr->pDelayCompensationB;
+ error |= frayREG->GTUC5_UN.GTUC5_ST.dec_B8 == nodeConfigPtr->pDecodingCorrection;
+ error |= frayREG->SUCC2_UN.SUCC2_ST.lt_B21 == nodeConfigPtr->pdListenTimeout;
+ error |= frayREG->GTUC6_UN.GTUC6_ST.mod_B11 == nodeConfigPtr->pdMaxDrift;
+ error |= frayREG->GTUC11_UN.GTUC11_ST.eoc_B3 == nodeConfigPtr->pExternOffsetCorrection;
+ error |= frayREG->GTUC11_UN.GTUC11_ST.erc_B3 == nodeConfigPtr->pExternRateCorrection;
+ error |= frayREG->SUCC1_UN.SUCC1_ST.txst_B1 == nodeConfigPtr->pKeySlotUsedForStartup;
+ error |= frayREG->SUCC1_UN.SUCC1_ST.txsy_B1 == nodeConfigPtr->pKeySlotUsedForSync;
+ error |= frayREG->MHDC_UN.MHDC_ST.slt_B13 == nodeConfigPtr->pLatestTx;
+ error |= frayREG->GTUC3_UN.GTUC3_ST.mioa_B7 == nodeConfigPtr->pMacroInitialOffsetA;
+ error |= frayREG->GTUC3_UN.GTUC3_ST.miob_B7 == nodeConfigPtr->pMacroInitialOffsetB;
+ error |= frayREG->GTUC3_UN.GTUC3_ST.uioa_B8 == nodeConfigPtr->pMicroInitialOffsetA;
+ error |= frayREG->GTUC3_UN.GTUC3_ST.uiob_B8 == nodeConfigPtr->pMicroInitialOffsetB;
+ error |= frayREG->GTUC1_UN.GTUC1_ST.ut_B20 == nodeConfigPtr->pMicroPerCycle;
+ error |= frayREG->GTUC10_UN.GTUC10_ST.moc_B13 == nodeConfigPtr->pRateCorrectionOut;
+ error |= frayREG->GTUC10_UN.GTUC10_ST.mrc_B11 == nodeConfigPtr->pOffsetCorrectionOut;
+ error |= frayREG->SUCC1_UN.SUCC1_ST.tsm_B1 == nodeConfigPtr->pSingleSlotEnabled;
+ if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_A)
+ error |= frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 == 0;
+ else if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_B)
+ error |= frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 == 1;
+ error |= frayREG->PRTC1_UN.PRTC1_ST.rwp_B6 == nodeConfigPtr->pWakeupPattern;
+ error |= frayREG->PRTC1_UN.PRTC1_ST.brp_B2 == nodeConfigPtr->pSamplesPerMicrotick;
+ return (error == FALSE) ? E_OK : E_NOT_OK;
+}
+
+
/**
* @brief Check node configuration parameters.
*
*
* @param [in] nodeConfigPtr Address of structure with node configuration parameters
* @param [out] errCode Address where error flags will be stored.
- * We have 24 parameters to check. Every one of them has assigned its bit in this flag.
- * Error flags are defined as macros ERR_PARAM_nameOfParameter.
+ * We have 24 parameters to check. Every one of them has assigned its bit in this flag.
+ * Error flags are defined as macros ERR_PARAM_nameOfParameter.
* @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
*/
-Std_ReturnType Fr_check_node_parameters(const Fr_TMS570LS_NodeConfigType* nodeConfigPtr, uint32_t* errCode) {
+Std_ReturnType Fr_check_node_parameters(const Fr_TMS570LS_NodeConfigType *nodeConfigPtr, uint32_t *errCode)
+{
*errCode = ERR_PARAM_NO_ERROR;
- if (nodeConfigPtr->pAllowPassiveToActive > 31) *errCode |= ERR_PARAM_pAllowPassiveToActive;
+ if (nodeConfigPtr->pAllowPassiveToActive > 31) *errCode |= ERR_PARAM_pAllowPassiveToActive;
if (nodeConfigPtr->pChannels != FR_CHANNEL_A &&
nodeConfigPtr->pChannels != FR_CHANNEL_B &&
- nodeConfigPtr->pChannels != FR_CHANNEL_AB ) *errCode |= ERR_PARAM_pChannels;
- if (nodeConfigPtr->pdAcceptedStartupRange > 1875) *errCode |= ERR_PARAM_pdAcceptedStartupRange;
- if (nodeConfigPtr->pClusterDriftDamping > 20) *errCode |= ERR_PARAM_pClusterDriftDamping;
- if (nodeConfigPtr->pDelayCompensationA > 200) *errCode |= ERR_PARAM_pDelayCompensationA;
- if (nodeConfigPtr->pDelayCompensationB > 200) *errCode |= ERR_PARAM_pDelayCompensationB;
- if (__notInRange(nodeConfigPtr->pdListenTimeout, 1284, 1283846)) *errCode |= ERR_PARAM_pdListenTimeout;
- if (__notInRange(nodeConfigPtr->pdMaxDrift, 2, 1923)) *errCode |= ERR_PARAM_pdMaxDrift;
- if (nodeConfigPtr->pExternOffsetCorrection > 7) *errCode |= ERR_PARAM_pExternOffsetCorrection;
- if (nodeConfigPtr->pExternRateCorrection > 7) *errCode |= ERR_PARAM_pExternRateCorrection;
+ nodeConfigPtr->pChannels != FR_CHANNEL_AB ) *errCode |= ERR_PARAM_pChannels;
+ if (nodeConfigPtr->pdAcceptedStartupRange > 1875) *errCode |= ERR_PARAM_pdAcceptedStartupRange;
+ if (nodeConfigPtr->pClusterDriftDamping > 20) *errCode |= ERR_PARAM_pClusterDriftDamping;
+ if (nodeConfigPtr->pDelayCompensationA > 200) *errCode |= ERR_PARAM_pDelayCompensationA;
+ if (nodeConfigPtr->pDelayCompensationB > 200) *errCode |= ERR_PARAM_pDelayCompensationB;
+ if (__notInRange(nodeConfigPtr->pdListenTimeout, 1284, 1283846)) *errCode |= ERR_PARAM_pdListenTimeout;
+ if (__notInRange(nodeConfigPtr->pdMaxDrift, 2, 1923)) *errCode |= ERR_PARAM_pdMaxDrift;
+ if (nodeConfigPtr->pExternOffsetCorrection > 7) *errCode |= ERR_PARAM_pExternOffsetCorrection;
+ if (nodeConfigPtr->pExternRateCorrection > 7) *errCode |= ERR_PARAM_pExternRateCorrection;
if (nodeConfigPtr->pKeySlotUsedForStartup == TRUE &&
- nodeConfigPtr->pKeySlotUsedForSync == FALSE) *errCode |= ERR_PARAM_pKeySlotUsedForSync
- | ERR_PARAM_pKeySlotUsedForStartup; // If pKeySlotUsedForStartup is set to true then pKeySlotUsedForSync must also be set to true.
- if (nodeConfigPtr->pLatestTx > 7980) *errCode |= ERR_PARAM_pLatestTx;
- if (__notInRange(nodeConfigPtr->pMacroInitialOffsetA, 2, 68)) *errCode |= ERR_PARAM_pMacroInitialOffsetA;
- if (__notInRange(nodeConfigPtr->pMacroInitialOffsetB, 2, 68)) *errCode |= ERR_PARAM_pMacroInitialOffsetB;
- if (nodeConfigPtr->pMicroInitialOffsetA > 239) *errCode |= ERR_PARAM_pMicroInitialOffsetA;
- if (nodeConfigPtr->pMicroInitialOffsetB > 239) *errCode |= ERR_PARAM_pMicroInitialOffsetB;
+ nodeConfigPtr->pKeySlotUsedForSync == FALSE) *errCode |= ERR_PARAM_pKeySlotUsedForSync
+ | ERR_PARAM_pKeySlotUsedForStartup; // If pKeySlotUsedForStartup is set to true then pKeySlotUsedForSync must also be set to true.
+ if (nodeConfigPtr->pLatestTx > 7980) *errCode |= ERR_PARAM_pLatestTx;
+ if (__notInRange(nodeConfigPtr->pMacroInitialOffsetA, 2, 68)) *errCode |= ERR_PARAM_pMacroInitialOffsetA;
+ if (__notInRange(nodeConfigPtr->pMacroInitialOffsetB, 2, 68)) *errCode |= ERR_PARAM_pMacroInitialOffsetB;
+ if (nodeConfigPtr->pMicroInitialOffsetA > 239) *errCode |= ERR_PARAM_pMicroInitialOffsetA;
+ if (nodeConfigPtr->pMicroInitialOffsetB > 239) *errCode |= ERR_PARAM_pMicroInitialOffsetB;
if (__notInRange(nodeConfigPtr->pMicroPerCycle, 640, 640000)) *errCode |= ERR_PARAM_pMicroPerCycle;
if (__notInRange(nodeConfigPtr->pRateCorrectionOut, 2, 1923)) *errCode |= ERR_PARAM_pRateCorrectionOut;
if (__notInRange(nodeConfigPtr->pOffsetCorrectionOut, 5, 0x3BA2)) *errCode |= ERR_PARAM_pOffsetCorrectionOut;
if (nodeConfigPtr->pWakeupChannel != FR_CHANNEL_A &&
- nodeConfigPtr->pWakeupChannel != FR_CHANNEL_B ) *errCode |= ERR_PARAM_pWakeupChannel;
- if (__notInRange(nodeConfigPtr->pWakeupPattern, 2, 63)) *errCode |= ERR_PARAM_pWakeupPattern;
- if (nodeConfigPtr->pSamplesPerMicrotick > 3) *errCode |= ERR_PARAM_pSamplesPerMicrotick;
- if (__notInRange(nodeConfigPtr->pDecodingCorrection, 0xF, 0x8F)) *errCode |= ERR_PARAM_pDecodingCorrection;
+ nodeConfigPtr->pWakeupChannel != FR_CHANNEL_B ) *errCode |= ERR_PARAM_pWakeupChannel;
+ if (__notInRange(nodeConfigPtr->pWakeupPattern, 2, 63)) *errCode |= ERR_PARAM_pWakeupPattern;
+ if (nodeConfigPtr->pSamplesPerMicrotick > 3) *errCode |= ERR_PARAM_pSamplesPerMicrotick;
+ if (__notInRange(nodeConfigPtr->pDecodingCorrection, 0xF, 0x8F)) *errCode |= ERR_PARAM_pDecodingCorrection;
return (*errCode == 0) ? E_OK : E_NOT_OK;
}
*
* This function checks configuration parameters.
* For FIFO buffers:
- * - All of them have to be RX
- * - All of them have the same payload <= 256B
- * - Same channels active
- * - Same cycle counter filter
- * - not coldstart
- * - not single/auto
- * - not reconfigurable
- * - frame ID can be 0, which means that all messages not received by others buffers are received in FIFO.
+ * - All of them have to be RX
+ * - All of them have the same payload <= 256B
+ * - Same channels active
+ * - Same cycle counter filter
+ * - not coldstart
+ * - not single/auto
+ * - not reconfigurable
+ * - frame ID can be 0, which means that all messages not received by others buffers are received in FIFO.
* For dynamic segment buffers and static segment buffers:
- * - frame ID must not be 0
- * - payload <= 256B
+ * - frame ID must not be 0
+ * - payload <= 256B
* The sum of all configured payloads must be <= 8KB.
*
* @param [in] statBufCfgPtr Address of structure with static buffers configuration parameters
* @param [in] dynBufCnt Number of dynamic buffers to be configured
* @param [in] fifoBufCnt Number of fifo buffers to be configured
* @param [out] errCode Address where error flags will be stored.
- * Flags are defined as ERR_PARAM_BUF.....
+ * Flags are defined as ERR_PARAM_BUF.....
* @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
*/
-Std_ReturnType Fr_check_buffer_parameters(const Fr_TMS570LS_BufferConfigType* statBufCfgPtr, const Fr_TMS570LS_BufferConfigType* dynBufCfgPtr, const Fr_TMS570LS_BufferConfigType* fifoBufCfgPtr,
- uint8_t statBufCnt, uint8_t dynBufCnt, uint8_t fifoBufCnt, uint32_t* errCode) {
+Std_ReturnType Fr_check_buffer_parameters(const Fr_TMS570LS_BufferConfigType *statBufCfgPtr, const Fr_TMS570LS_BufferConfigType *dynBufCfgPtr, const Fr_TMS570LS_BufferConfigType *fifoBufCfgPtr,
+ uint8_t statBufCnt, uint8_t dynBufCnt, uint8_t fifoBufCnt, uint32_t *errCode)
+{
uint32_t payloadTotal = 0;
+
*errCode = ERR_PARAM_NO_ERROR;
- uint8_t fifoPayload;
+ uint8_t fifoPayload, fifoCycleCounterFiltering;
Fr_ChannelType fifoChannels;
- uint8_t fifoCycleCounterFiltering;
- uint8_t i;
+ uint16_t fifoFidMask, fifoSlotId;
+ boolean_t fifoRejNullFr, fifoRejStatFr;
+ const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr = NULL;
/* Check FIFO buffer parameters */
if (fifoBufCnt != 0 && fifoBufCfgPtr != NULL) {
- fifoPayload = fifoBufCfgPtr[0].maxPayload;
fifoChannels = fifoBufCfgPtr[0].channel;
fifoCycleCounterFiltering = fifoBufCfgPtr[0].cycleCounterFiltering;
+ fifoFidMask = fifoBufCfgPtr[0].fidMask;
+ fifoSlotId = fifoBufCfgPtr[0].slotId;
+ fifoPayload = fifoBufCfgPtr[0].maxPayload;
+ fifoRejNullFr = fifoBufCfgPtr[0].rejectNullFrames;
+ fifoRejStatFr = fifoBufCfgPtr[0].rejectStaticSegment;
if (fifoPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFFIFO_PAYLOAD_HIGH;
- for (i = 0; i < fifoBufCnt; i++) {
- if (fifoBufCfgPtr[i].isTx == TRUE) *errCode |= ERR_PARAM_BUFFIFO_NOT_RX;
- if (fifoBufCfgPtr[i].maxPayload != fifoPayload) *errCode |= ERR_PARAM_BUFFIFO_PAYLOAD_DIFFERS;
- if (fifoBufCfgPtr[i].channel != fifoChannels) *errCode |= ERR_PARAM_BUFFIFO_CHANNEL_DIFFERS;
- if (fifoBufCfgPtr[i].cycleCounterFiltering != fifoCycleCounterFiltering) *errCode |= ERR_PARAM_BUFFIFO_CCFILTER_DIFFERS;
- payloadTotal += fifoBufCfgPtr[i].maxPayload;
+ for (buffer_cfg_ptr = &fifoBufCfgPtr[0]; buffer_cfg_ptr < &fifoBufCfgPtr[fifoBufCnt]; buffer_cfg_ptr++) {
+ if (buffer_cfg_ptr->channel != fifoChannels) *errCode |= ERR_PARAM_BUFFIFO_CHANNEL_DIFFERS;
+ if (buffer_cfg_ptr->cycleCounterFiltering != fifoCycleCounterFiltering) *errCode |= ERR_PARAM_BUFFIFO_CCFILTER_DIFFERS;
+ if (buffer_cfg_ptr->fidMask != fifoFidMask) *errCode |= ERR_PARAM_BUFFIFO_FIDMASK_DIFFERS;
+ if (buffer_cfg_ptr->isTx == TRUE) *errCode |= ERR_PARAM_BUFFIFO_NOT_RX;
+ if (buffer_cfg_ptr->maxPayload != fifoPayload) *errCode |= ERR_PARAM_BUFFIFO_PAYLOAD_DIFFERS;
+ if (buffer_cfg_ptr->payloadPreambleIndicatorTr == TRUE) *errCode |= ERR_PARAM_BUFFIFO_PPIT;
+ if (buffer_cfg_ptr->rejectNullFrames != fifoRejNullFr) *errCode |= ERR_PARAM_BUFFIFO_REJNULLFR_DIFFERS;
+ if (buffer_cfg_ptr->rejectStaticSegment != fifoRejStatFr) *errCode |= ERR_PARAM_BUFFIFO_REJSTATFR_DIFFERS;
+ if (buffer_cfg_ptr->slotId != fifoSlotId) *errCode |= ERR_PARAM_BUFFIFO_SLOTID_DIFFERS;
+ payloadTotal += buffer_cfg_ptr->maxPayload;
}
}
- if (dynBufCfgPtr != NULL) {
- for (i = 0; i < dynBufCnt; i++) {
- if (dynBufCfgPtr[i].slotId == 0) *errCode |= ERR_PARAM_BUFDYN_FRAMEID_INVALID;
- if (dynBufCfgPtr[i].maxPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFDYN_PAYLOAD_HIGH;
- if (dynBufCfgPtr[i].channel == FR_CHANNEL_AB) *errCode |= ERR_PARAM_BUFDYN_CHANNELS;
- payloadTotal += dynBufCfgPtr[i].maxPayload;
+ if (dynBufCfgPtr != NULL)
+ for (buffer_cfg_ptr = &dynBufCfgPtr[0]; buffer_cfg_ptr < &dynBufCfgPtr[dynBufCnt]; buffer_cfg_ptr++) {
+ if (buffer_cfg_ptr->slotId == 0) *errCode |= ERR_PARAM_BUFDYN_FRAMEID_INVALID;
+ if (buffer_cfg_ptr->maxPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFDYN_PAYLOAD_HIGH;
+ if (buffer_cfg_ptr->channel == FR_CHANNEL_AB) *errCode |= ERR_PARAM_BUFDYN_CHANNELS;
+ payloadTotal += buffer_cfg_ptr->maxPayload;
}
- }
- if (statBufCfgPtr != NULL) {
- for (i = 0; i < statBufCnt; i++) {
- if (statBufCfgPtr[i].slotId == 0) *errCode |= ERR_PARAM_BUFSTAT_FRAMEID_INVALID;
- if (statBufCfgPtr[i].maxPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFSTAT_PAYLOAD_HIGH;
- payloadTotal += statBufCfgPtr[i].maxPayload;
+ if (statBufCfgPtr != NULL)
+ for (buffer_cfg_ptr = &statBufCfgPtr[0]; buffer_cfg_ptr < &statBufCfgPtr[statBufCnt]; buffer_cfg_ptr++) {
+ if (buffer_cfg_ptr->slotId == 0) *errCode |= ERR_PARAM_BUFSTAT_FRAMEID_INVALID;
+ if (buffer_cfg_ptr->maxPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFSTAT_PAYLOAD_HIGH;
+ payloadTotal += buffer_cfg_ptr->maxPayload;
}
- }
if (payloadTotal > 8192/2) *errCode |= ERR_PARAM_BUF_TOTAL_PAYLOAD_HIGH;
* @param [in] msgRAMConfigPtr Address of structure with message RAM configuration parameters
* @return Number of configured buffers
*/
-uint8_t Fr_config_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig* msgRAMConfigPtr) {
+uint8_t Fr_config_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig *msgRAMConfigPtr)
+{
/* If dynSegmentBufferCount is not 0 then first dynamic buffer = statSegmentBufferCount.
* If dynSegmentBufferCount is 0 then first dynamic buffer is 0x80 (see TMS570LS31x documentation)
*/
- if (msgRAMConfigPtr->dynSegmentBufferCount == 0) {
+ if (msgRAMConfigPtr->dynSegmentBufferCount == 0)
frayREG->MRC_UN.MRC_ST.fdb_B8 = 0x80;
- }
- else {
+ else
frayREG->MRC_UN.MRC_ST.fdb_B8 = msgRAMConfigPtr->statSegmentBufferCount;
- }
/* If fifoBufferCount is not 0 then first fifo buffer = statSegmentBufferCount + dynSegmentBufferCount
* If fifoBufferCount is 0 then first fifo buffer is 0x80 (see TMS570LS31x documentation)
*/
- if (msgRAMConfigPtr->fifoBufferCount == 0) {
+ if (msgRAMConfigPtr->fifoBufferCount == 0)
frayREG->MRC_UN.MRC_ST.ffb_B8 = 0x80;
- }
- else {
+ else
frayREG->MRC_UN.MRC_ST.ffb_B8 = msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount;
- }
/* Last configured buffer = statSegmentBufferCount + dynSegmentBufferCount + fifoBufferCount - 1 */
frayREG->MRC_UN.MRC_ST.lcb_B8 = msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount + msgRAMConfigPtr->fifoBufferCount - 1;
/* Secure buffers setting */
- if (msgRAMConfigPtr->secureBuffers == FR_SB_RECONFIG_ENABLED) {
+ if (msgRAMConfigPtr->secureBuffers == FR_SB_RECONFIG_ENABLED)
frayREG->MRC_UN.MRC_ST.sec_B2 = 0;
- }
- else if (msgRAMConfigPtr->secureBuffers == FR_SB_STAT_REC_DISABLED_STAT_TR_DISABLED) {
+ else if (msgRAMConfigPtr->secureBuffers == FR_SB_STAT_REC_DISABLED_STAT_TR_DISABLED)
frayREG->MRC_UN.MRC_ST.sec_B2 = 1;
- }
- else if (msgRAMConfigPtr->secureBuffers == FR_SB_ALL_REC_DISABLED) {
+ else if (msgRAMConfigPtr->secureBuffers == FR_SB_ALL_REC_DISABLED)
frayREG->MRC_UN.MRC_ST.sec_B2 = 2;
- }
- else {
+ else
frayREG->MRC_UN.MRC_ST.sec_B2 = 3;
- }
/* Sync frame payload multiplex setting */
- if (msgRAMConfigPtr->syncFramePayloadMultiplexEnabled == TRUE) {
+ if (msgRAMConfigPtr->syncFramePayloadMultiplexEnabled == TRUE)
frayREG->MRC_UN.MRC_ST.splm_B1 = 1;
- }
- else {
+ else
frayREG->MRC_UN.MRC_ST.splm_B1 = 0;
- }
return msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount + msgRAMConfigPtr->fifoBufferCount;
}
-#define __notInRange(val, min, max) (((val) < (min)) || ((val) > (max)))
+Std_ReturnType Fr_verify_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig *msgRAMConfigPtr)
+{
+ boolean_t error = FALSE;
+
+ if (msgRAMConfigPtr->dynSegmentBufferCount == 0)
+ error |= frayREG->MRC_UN.MRC_ST.fdb_B8 == 0x80;
+ else
+ error |= frayREG->MRC_UN.MRC_ST.fdb_B8 == msgRAMConfigPtr->statSegmentBufferCount;
+
+ if (msgRAMConfigPtr->fifoBufferCount == 0)
+ error |= frayREG->MRC_UN.MRC_ST.ffb_B8 == 0x80;
+ else
+ error |= frayREG->MRC_UN.MRC_ST.ffb_B8 == msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount;
+
+ error |= frayREG->MRC_UN.MRC_ST.lcb_B8 == msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount + msgRAMConfigPtr->fifoBufferCount - 1;
+ if (msgRAMConfigPtr->secureBuffers == FR_SB_RECONFIG_ENABLED)
+ error |= frayREG->MRC_UN.MRC_ST.sec_B2 == 0;
+ else if (msgRAMConfigPtr->secureBuffers == FR_SB_STAT_REC_DISABLED_STAT_TR_DISABLED)
+ error |= frayREG->MRC_UN.MRC_ST.sec_B2 == 1;
+ else if (msgRAMConfigPtr->secureBuffers == FR_SB_ALL_REC_DISABLED)
+ error |= frayREG->MRC_UN.MRC_ST.sec_B2 == 2;
+ else
+ error |= frayREG->MRC_UN.MRC_ST.sec_B2 == 3;
+
+ if (msgRAMConfigPtr->syncFramePayloadMultiplexEnabled == TRUE)
+ error |= frayREG->MRC_UN.MRC_ST.splm_B1 == 1;
+ else
+ error |= frayREG->MRC_UN.MRC_ST.splm_B1 == 0;
+
+ return (error == FALSE) ? E_OK : E_NOT_OK;
+}
+
+
+#define __notInRange(val, min, max) (((val) < (min)) || ((val) > (max)))
/**
* @brief Check message RAM configuration parameters.
*
* @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
* @param [out] errCode Address where error flags will be stored.
- * Error flags are defined as macros ERR_PARAM_nameOfParameter.
+ * Error flags are defined as macros ERR_PARAM_nameOfParameter.
* @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
*/
-Std_ReturnType Fr_check_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig* msgRAMConfigPtr, uint32_t* errCode) {
+Std_ReturnType Fr_check_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig *msgRAMConfigPtr, uint32_t *errCode)
+{
*errCode = ERR_PARAM_NO_ERROR;
- if (__notInRange(msgRAMConfigPtr->statSegmentBufferCount, 1, 127)) *errCode |= ERR_PARAM_statSegmentBufferCount;
- if (msgRAMConfigPtr->dynSegmentBufferCount >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_dynSegmentBufferCount;
- if (msgRAMConfigPtr->fifoBufferCount >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_fifoBufferCount;
+ if (__notInRange(msgRAMConfigPtr->statSegmentBufferCount, 1, 127)) *errCode |= ERR_PARAM_statSegmentBufferCount;
+ if (msgRAMConfigPtr->dynSegmentBufferCount >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_dynSegmentBufferCount;
+ if (msgRAMConfigPtr->fifoBufferCount >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_fifoBufferCount;
if ((msgRAMConfigPtr->statSegmentBufferCount +
- msgRAMConfigPtr->dynSegmentBufferCount +
- msgRAMConfigPtr->fifoBufferCount) >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_maxBuffLimit;
+ msgRAMConfigPtr->dynSegmentBufferCount +
+ msgRAMConfigPtr->fifoBufferCount) >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_maxBuffLimit;
return (*errCode == 0) ? E_OK : E_NOT_OK;
}
-void Fr_Init(const Fr_ConfigType* Fr_ConfigPtr) {
- uint32_t i;
+/**
+ * @brief Master function to prepare buffers for communication
+ * *
+ * @param [in] Fr_CtrlIdx Index of FlexRay CC within the context of the FlexRay Driver.
+ * @param [in] Fr_LPduIdx This index is used to uniquely identify a FlexRay frame buffer.
+ * @return E_OK: API call finished successfully. E_NOT_OK: API call aborted due to errors.
+ */
+Std_ReturnType Fr_PrepareLPdu_master(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx)
+{
+ uint32_t mode;
+ const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr;
#ifdef DET_ACTIVATED
- if (Fr_ConfigPtr == NULL) {
- return;
+ if (Fr_CtrlIdx != 0)
+ return E_NOT_OK;
+ if (Fr_DrvState < FR_ST_DRV_INITIALIZED)
+ return E_NOT_OK;
+ if (Fr_LPduIdx > FR_MAX_BUFFERS_CNT)
+ return E_NOT_OK;
+
+#endif
+ /* Find the index of the buffer in configuration data array */
+ if (Fr_LPduIdx <= frayREG->MRC_UN.MRC_ST.lcb_B8) {
+ if (Fr_BuffersConfigured[Fr_LPduIdx] == FALSE) { // Buffer was not yet configured
+ buffer_cfg_ptr = Fr_buffer_slot_map[Fr_LPduIdx].buffer_ptr;
+ mode = Fr_buffer_config_flags(buffer_cfg_ptr, Fr_LPduIdx);
+ Fr_MsgRAMDataPtrs[Fr_LPduIdx] = Fr_MsgRAMDataOffset;
+ if (Fr_LPduIdx >= frayREG->MRC_UN.MRC_ST.ffb_B8) // This is RX FIFO buffer
+ Fr_configure_fifo_buffer(Fr_LPduIdx, mode, buffer_cfg_ptr->cycleCounterFiltering, buffer_cfg_ptr->slotId, buffer_cfg_ptr->fidMask, buffer_cfg_ptr->maxPayload, Fr_MsgRAMDataPtrs[Fr_LPduIdx]);
+ else // Static/dynamic segment buffer
+ Fr_config_buffer(Fr_LPduIdx, mode, buffer_cfg_ptr->cycleCounterFiltering, buffer_cfg_ptr->slotId, buffer_cfg_ptr->maxPayload, Fr_MsgRAMDataPtrs[Fr_LPduIdx]);
+ /*
+ * Calculate new address.
+ * Payload contains the number of two-bytes words, Fr_MsgRAMDataPtrs contains addresses of 4B words in message RAM, all msgRAM addresses have
+ * to be 4B aligned.
+ * Offset has to be divided by two each time because payload is in 2B words and msgRAM addresses are in 4B words.
+ */
+ Fr_MsgRAMDataOffset += ((buffer_cfg_ptr->maxPayload)%2U == 0U ? (buffer_cfg_ptr->maxPayload) : ((buffer_cfg_ptr->maxPayload)+1U))/2;
+ Fr_BuffersConfigured[Fr_LPduIdx] = TRUE;
+ }
}
- if (Fr_DrvState != FR_ST_DRV_NOT_INITIALIZED) {
+ return E_OK;
+}
+
+void Fr_Init(const Fr_ConfigType *Fr_ConfigPtr)
+{
+ Fr_slot_buffer_map_t *buffer_slot_map_ptr;
+ uint8_t buffer_last_index;
+ boolean_t *buffers_configured_ptr;
+ const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr;
+
+#ifdef DET_ACTIVATED
+ if (Fr_ConfigPtr == NULL)
return;
- }
+ if (Fr_DrvState != FR_ST_DRV_NOT_INITIALIZED)
+ return;
+
#endif
/* Save pointers for parameters indexed by CIDX indexes
* This array representation is used by Fr_ReadCCConfig function.
/* Store pointers to structures with configuration parameters of buffers
* Reset configured flags for all buffers */
- for (i = 0; i < Fr_ConfigPtr->msgRAMConfig->statSegmentBufferCount; ++i) { // Statis segment buffers
- Fr_BuffersPtrs[i] = &Fr_ConfigPtr->staticBufferConfigs[i];
- Fr_BuffersConfigured[i] = FALSE;
- }
- for (i = 0; i < Fr_ConfigPtr->msgRAMConfig->dynSegmentBufferCount; ++i) { // Dynamic segment buffers
- Fr_BuffersPtrs[i + Fr_ConfigPtr->msgRAMConfig->statSegmentBufferCount] = &Fr_ConfigPtr->dynamicBufferConfigs[i];
- Fr_BuffersConfigured[i + Fr_ConfigPtr->msgRAMConfig->statSegmentBufferCount] = FALSE;
- }
- for (i = 0; i < Fr_ConfigPtr->msgRAMConfig->fifoBufferCount; ++i) { // Fifo buffrers
- Fr_BuffersPtrs[i + Fr_ConfigPtr->msgRAMConfig->statSegmentBufferCount + Fr_ConfigPtr->msgRAMConfig->dynSegmentBufferCount] = &Fr_ConfigPtr->fifoBufferConfigs[i];
- Fr_BuffersConfigured[i + Fr_ConfigPtr->msgRAMConfig->statSegmentBufferCount + Fr_ConfigPtr->msgRAMConfig->dynSegmentBufferCount] = FALSE;
+ buffer_last_index = Fr_ConfigPtr->msgRAMConfig->statSegmentBufferCount;
+ for (buffer_slot_map_ptr = Fr_buffer_slot_map, buffers_configured_ptr = Fr_BuffersConfigured, buffer_cfg_ptr = Fr_ConfigPtr->staticBufferConfigs;
+ buffer_slot_map_ptr < &Fr_buffer_slot_map[buffer_last_index];
+ buffer_slot_map_ptr++, buffers_configured_ptr++, buffer_cfg_ptr++
+ ) { // Static segment buffers
+ buffer_slot_map_ptr->buffer_ptr = buffer_cfg_ptr;
+ buffer_slot_map_ptr->slot_id = buffer_cfg_ptr->slotId;
+ buffer_slot_map_ptr->act_payload = buffer_cfg_ptr->maxPayload;
+ buffer_slot_map_ptr->act_ch_filter = buffer_cfg_ptr->channel;
+ buffer_slot_map_ptr->act_cyc_filter = buffer_cfg_ptr->cycleCounterFiltering;
+ *buffers_configured_ptr = FALSE;
+ }
+ buffer_last_index += Fr_ConfigPtr->msgRAMConfig->dynSegmentBufferCount;
+ for (buffer_cfg_ptr = Fr_ConfigPtr->dynamicBufferConfigs;
+ buffer_slot_map_ptr < &Fr_buffer_slot_map[buffer_last_index];
+ buffer_slot_map_ptr++, buffers_configured_ptr++, buffer_cfg_ptr++
+ ) { // Dynamic segment buffers
+ buffer_slot_map_ptr->buffer_ptr = buffer_cfg_ptr;
+ buffer_slot_map_ptr->slot_id = buffer_cfg_ptr->slotId;
+ buffer_slot_map_ptr->act_payload = buffer_cfg_ptr->maxPayload;
+ buffer_slot_map_ptr->act_ch_filter = buffer_cfg_ptr->channel;
+ buffer_slot_map_ptr->act_cyc_filter = buffer_cfg_ptr->cycleCounterFiltering;
+ *buffers_configured_ptr = FALSE;
+ }
+ buffer_last_index += Fr_ConfigPtr->msgRAMConfig->fifoBufferCount;
+ for (buffer_cfg_ptr = Fr_ConfigPtr->fifoBufferConfigs;
+ buffer_slot_map_ptr < &Fr_buffer_slot_map[buffer_last_index];
+ buffer_slot_map_ptr++, buffers_configured_ptr++, buffer_cfg_ptr++
+ ) { // Fifo buffrers
+ buffer_slot_map_ptr->buffer_ptr = buffer_cfg_ptr;
+ buffer_slot_map_ptr->slot_id = buffer_cfg_ptr->slotId;
+ buffer_slot_map_ptr->act_payload = buffer_cfg_ptr->maxPayload;
+ buffer_slot_map_ptr->act_ch_filter = buffer_cfg_ptr->channel;
+ buffer_slot_map_ptr->act_cyc_filter = buffer_cfg_ptr->cycleCounterFiltering;
+ *buffers_configured_ptr = FALSE;
}
#ifdef DET_ACTIVATED
#endif
}
-Std_ReturnType Fr_ControllerInit(uint8_t Fr_CtrlIdx) {
+Std_ReturnType Fr_ControllerInit(uint8_t Fr_CtrlIdx)
+{
uint32_t errCode = ERR_PARAM_NO_ERROR;
uint32_t i;
uint8_t totalBufferCount;
#ifdef DET_ACTIVATED
- if (Fr_DrvState != FR_ST_DRV_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_DRV_INITIALIZED)
return E_NOT_OK;
- }
+
#endif
/* Switch CC into ‘POC:config’ (from any other POCState) */
- if (Fr_POC_go_to_config() == E_NOT_OK) {
- return E_NOT_OK;
- }
+ while (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_CONFIG)
+ if (Fr_POC_go_to_config() == E_NOT_OK)
+ return E_NOT_OK;
+ /* Now no TX request is pending, no RX is pending, all buffers looks like disabled */
+ /* Disable all interrupts */
+ frayREG->EIES_UN.EIES_UL = 0;
+ frayREG->SIES_UN.SIES_UL = 0;
+ /* Clear all pending interrupts */
+ frayREG->EIR_UN.EIR_UL = 0xFFFFFFFF;
+ frayREG->SIR_UN.SIR_UL = 0xFFFFFFFF;
+ /* Disable all timers */
+ frayREG->T0C_UN.T0C_ST.t0rc_B1 = 0;
+ frayREG->T1C_UN.T1C_ST.t1rc_B1 = 0;
/* Check Cluster config parameters */
- if (Fr_check_cluster_parameters(Fr_Config->clusterConfiguration, &errCode) == E_NOT_OK) {
+ if (Fr_check_cluster_parameters(Fr_Config->clusterConfiguration, &errCode) == E_NOT_OK)
return E_NOT_OK | errCode | FR_INIT_ERR_CLUSTER_CONFIG;
- }
/* Check node config parameters */
- if (Fr_check_node_parameters(Fr_Config->nodeConfiguration, &errCode) == E_NOT_OK) {
+ if (Fr_check_node_parameters(Fr_Config->nodeConfiguration, &errCode) == E_NOT_OK)
return E_NOT_OK | errCode | FR_INIT_ERR_NODE_CONFIG;
- }
/* Check msgRAM config parameters */
- if (Fr_check_msgRAM_parameters(Fr_Config->msgRAMConfig, &errCode) == E_NOT_OK) {
+ if (Fr_check_msgRAM_parameters(Fr_Config->msgRAMConfig, &errCode) == E_NOT_OK)
return E_NOT_OK | errCode | FR_INIT_ERR_MSGRAM_CONFIG;
- }
/* Check buffers parameters */
if (Fr_check_buffer_parameters(Fr_Config->staticBufferConfigs, Fr_Config->dynamicBufferConfigs, Fr_Config->fifoBufferConfigs,
- Fr_Config->msgRAMConfig->statSegmentBufferCount, Fr_Config->msgRAMConfig->dynSegmentBufferCount, Fr_Config->msgRAMConfig->fifoBufferCount, &errCode) == E_NOT_OK) {
+ Fr_Config->msgRAMConfig->statSegmentBufferCount, Fr_Config->msgRAMConfig->dynSegmentBufferCount, Fr_Config->msgRAMConfig->fifoBufferCount, &errCode) == E_NOT_OK)
return E_NOT_OK | errCode | FR_INIT_ERR_BUFFPARAM_CONFIG;
- }
/* Clear message RAM */
- if (Fr_clear_msg_RAM() == FAILURE) {
+ if (Fr_clear_msg_RAM() == FAILURE)
return E_NOT_OK;
- }
/* Configure all FlexRay cluster, node and msgRAM parameters */
Fr_config_cluster_parameters(Fr_Config->clusterConfiguration);
;
totalBufferCount = Fr_config_msgRAM_parameters(Fr_Config->msgRAMConfig);
+
+ /* Repeat the parameter verification procedure */
+ /* FIXME: should be false to activate the test below */
+ boolean_t passed = TRUE;
+ for (i = 0; i < FrCtrlTestCount; i++) {
+ if (Fr_verify_cluster_parameters(Fr_Config->clusterConfiguration) == E_OK &&
+ Fr_verify_node_parameters(Fr_Config->nodeConfiguration) == E_OK &&
+ Fr_verify_msgRAM_parameters(Fr_Config->msgRAMConfig) == E_OK) {
+ passed = TRUE;
+ break;
+ }
+ }
+
Fr_MsgRAMDataStartAddress = totalBufferCount*4U; // First data section after headers sections in message RAM.
Fr_MsgRAMDataOffset = Fr_MsgRAMDataStartAddress;
+
+ /* Reset configured flags and map */
+ for (i = 0; i < totalBufferCount; i++) {
+ Fr_BuffersConfigured[i] = FALSE;
+ Fr_buffer_slot_map[i].slot_id = Fr_buffer_slot_map[i].buffer_ptr->slotId;
+ Fr_buffer_slot_map[i].act_payload = Fr_buffer_slot_map[i].buffer_ptr->maxPayload;
+ Fr_buffer_slot_map[i].act_ch_filter = Fr_buffer_slot_map[i].buffer_ptr->channel;
+ Fr_buffer_slot_map[i].act_cyc_filter = Fr_buffer_slot_map[i].buffer_ptr->cycleCounterFiltering;
+ }
+
/* Configure all transmit/receive resources */
for (i = 0; i < totalBufferCount; i++) {
- if (Fr_PrepareLPdu(Fr_CtrlIdx, Fr_BuffersPtrs[i]->slotId) == E_NOT_OK) {
+ if (Fr_PrepareLPdu_master(Fr_CtrlIdx, i) == E_NOT_OK)
return E_NOT_OK | FR_INIT_ERR_BUFF_CONFIG;
- }
}
+ if (passed == FALSE)
+ return E_NOT_OK;
/* Switch POC to ready state */
- if (Fr_POC_go_to_ready_from_config() == E_NOT_OK) {
+ if (Fr_POC_go_to_ready_from_config() == E_NOT_OK)
return E_NOT_OK;
- }
+ /* Enable all interrupts */
+ frayREG->EIES_UN.EIES_UL = 0xFFFFFFFF;
+ frayREG->SIES_UN.SIES_UL = 0xFFFFFFFF;
+
#ifdef DET_ACTIVATED
Fr_DrvState = FR_ST_CTRL_INITIALIZED;
#endif
return E_OK;
}
-Std_ReturnType Fr_StartCommunication(uint8_t Fr_CtrlIdx) {
+Std_ReturnType Fr_StartCommunication(uint8_t Fr_CtrlIdx)
+{
uint32_t counter;
uint32_t state_value;
uint32_t csa;
+
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState != FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_READY) {
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_READY)
return E_NOT_OK;
- }
+
#endif
// Node is configured as coldstart
- if (Fr_Config->nodeConfiguration->pKeySlotUsedForStartup == TRUE) {
- // Start up loop
- while(1) {
- counter = 0;
- // Try to integrate into an existing network as following coldstarter
- if (Fr_POC_go_to_startup() == E_NOT_OK) {
- return E_NOT_OK | FR_STARTUP_ERR_SW_STUP_FOLLOW; // Switch to run state error
- }
-
- do { // Wait until NORMAL_ACTIVE state or timeout
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- counter++;
- } while ((state_value != FR_POCS_NORMAL_ACTIVE) && (counter < FR_FCS_LISTEN_TIMEOUT));
-
- // No success in integration, try to initiate FlexRay network as leading coldstarter.
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == FR_POCS_INTEGRATION_LISTEN){
- csa = frayREG->CCSV_UN.CCSV_ST.rca_B5;
- if (csa != 0) { // Some cold start attempts remaining
- if (Fr_AllowColdstart(Fr_CtrlIdx) == E_NOT_OK) {
- return E_NOT_OK | FR_STARTUP_ERR_CSINH_DIS; // Cold start inhibit disabled error
- }
- }
- }
- do { // Wait until NORMAL_ACTIVE or INTEGRATION_LISTEN state
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- } while ( (state_value != FR_POCS_NORMAL_ACTIVE) && (state_value != FR_POCS_INTEGRATION_LISTEN));
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == FR_POCS_NORMAL_ACTIVE) // Success, break the start up loop
- break;
- if (Fr_POC_go_to_ready_from_startup() == E_NOT_OK) { // No success. Switch back to READY state
- return E_NOT_OK | FR_STARTUP_ERR_SW_STUP_READY;
- }
- }
+ if (Fr_Config->nodeConfiguration->pKeySlotUsedForStartup == TRUE)
+ // Start up loop
+ while (1) {
+ counter = 0;
+ // Try to integrate into an existing network as following coldstarter
+ if (Fr_POC_go_to_startup() == E_NOT_OK)
+ return E_NOT_OK | FR_STARTUP_ERR_SW_STUP_FOLLOW; // Switch to run state error
+
+ do { // Wait until NORMAL_ACTIVE state or timeout
+ state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
+ counter++;
+ } while ((state_value != FR_POCS_NORMAL_ACTIVE) && (counter < FR_FCS_LISTEN_TIMEOUT));
+
+ // No success in integration, try to initiate FlexRay network as leading coldstarter.
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == FR_POCS_INTEGRATION_LISTEN) {
+ csa = frayREG->CCSV_UN.CCSV_ST.rca_B5;
+ if (csa != 0) // Some cold start attempts remaining
+ if (Fr_AllowColdstart(Fr_CtrlIdx) == E_NOT_OK)
+ return E_NOT_OK | FR_STARTUP_ERR_CSINH_DIS; // Cold start inhibit disabled error
+ }
+ do { // Wait until NORMAL_ACTIVE or INTEGRATION_LISTEN state
+ state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
+ } while ( (state_value != FR_POCS_NORMAL_ACTIVE) && (state_value != FR_POCS_INTEGRATION_LISTEN));
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == FR_POCS_NORMAL_ACTIVE) // Success, break the start up loop
+ break;
+ if (Fr_POC_go_to_ready_from_startup() == E_NOT_OK) // No success. Switch back to READY state
+ return E_NOT_OK | FR_STARTUP_ERR_SW_STUP_READY;
+ }
+ // The node is not coldstarter, try to integrate into an existing network.
+ else {
+ if (Fr_POC_go_to_startup() == E_NOT_OK)
+ return E_NOT_OK | FR_STARTUP_ERR_SW_STUP_AS_NCOLD; // Switching to startup state as non-cold start node
+ else {
+ // Wait until NORMAL_ACTIVE
+ do {
+ state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
+ } while (state_value != FR_POCS_NORMAL_ACTIVE);
+ }
}
- // The node is not coldstarter, try to integrate into an existing network.
- else {
- if(Fr_POC_go_to_startup() == E_NOT_OK) {
- return E_NOT_OK | FR_STARTUP_ERR_SW_STUP_AS_NCOLD; // Switching to startup state as non-cold start node
- }
- else {
- // Wait until NORMAL_ACTIVE
- do {
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- } while (state_value != FR_POCS_NORMAL_ACTIVE);
- }
- }
return E_OK;
}
-Std_ReturnType Fr_AllowColdstart(uint8_t Fr_CtrlIdx) {
+Std_ReturnType Fr_AllowColdstart(uint8_t Fr_CtrlIdx)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
+
#endif
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_ALLOW_COLDSTART;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- Fr_wait_for_POC_ready();
- return E_OK;
+ Fr_wait_for_POC_ready();
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_ALLOW_COLDSTART;
+ if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
+ return E_NOT_OK;
+ Fr_wait_for_POC_ready();
+ return E_OK;
}
-Std_ReturnType Fr_AllSlots(uint8_t Fr_CtrlIdx) {
+Std_ReturnType Fr_AllSlots(uint8_t Fr_CtrlIdx)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
+ return E_NOT_OK;
+
#endif
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_ALL_SLOTS;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- Fr_wait_for_POC_ready();
- return E_OK;
+ Fr_wait_for_POC_ready();
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_ALL_SLOTS;
+ if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
+ return E_NOT_OK;
+ Fr_wait_for_POC_ready();
+ return E_OK;
}
-// TODO: Create functions to switch POC from HALT to Default_config->Config->Ready state, to be able start communicating again.
-Std_ReturnType Fr_HaltCommunication(uint8_t Fr_CtrlIdx) {
+Std_ReturnType Fr_HaltCommunication(uint8_t Fr_CtrlIdx)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
+ return E_NOT_OK;
+
#endif
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_HALT;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- Fr_wait_for_POC_ready();
+ Fr_wait_for_POC_ready();
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_HALT;
+ if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
+ return E_NOT_OK;
+ Fr_wait_for_POC_ready();
return E_OK;
}
-Std_ReturnType Fr_AbortCommunication(uint8_t Fr_CtrlIdx) {
+Std_ReturnType Fr_AbortCommunication(uint8_t Fr_CtrlIdx)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
+
#endif
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_FREEZE;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- Fr_wait_for_POC_ready();
+ Fr_wait_for_POC_ready();
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_FREEZE;
+ if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
+ return E_NOT_OK;
+ Fr_wait_for_POC_ready();
return E_OK;
}
-Std_ReturnType Fr_SendWUP(uint8_t Fr_CtrlIdx) {
+Std_ReturnType Fr_SendWUP(uint8_t Fr_CtrlIdx)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_READY)
+ return E_NOT_OK;
+
#endif
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_WAKEUP;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return E_NOT_OK;
- Fr_wait_for_POC_ready();
+ Fr_wait_for_POC_ready();
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_WAKEUP;
+ if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
+ return E_NOT_OK;
+ Fr_wait_for_POC_ready();
return E_OK;
}
-Std_ReturnType Fr_SetWakeupChannel(uint8_t Fr_CtrlIdx, Fr_ChannelType Fr_ChnlIdx) {
+Std_ReturnType Fr_SetWakeupChannel(uint8_t Fr_CtrlIdx, Fr_ChannelType Fr_ChnlIdx)
+{
Std_ReturnType retVal = E_OK;
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_ChnlIdx == FR_CHANNEL_AB) {
+ if (Fr_ChnlIdx == FR_CHANNEL_AB)
return E_NOT_OK;
- }
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_READY) {
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_READY)
return E_NOT_OK;
- }
+
#endif
- if (Fr_POC_go_to_config() == E_NOT_OK) {
+ if (Fr_POC_go_to_config() == E_NOT_OK)
return E_NOT_OK;
- }
if (Fr_ChnlIdx == FR_CHANNEL_A) {
frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 = 0;
retVal = E_OK;
frayREG->SUCC1_UN.SUCC1_ST.wucs_B1 = 1;
retVal = E_OK;
}
- else {
+ else
retVal = E_NOT_OK;
- }
- if (Fr_POC_go_to_ready_from_config() == E_NOT_OK) {
+ if (Fr_POC_go_to_ready_from_config() == E_NOT_OK)
retVal = E_NOT_OK;
- }
return retVal;
}
-Std_ReturnType Fr_GetPOCStatus(uint8_t Fr_CtrlIdx, Fr_POCStatusType* Fr_POCStatusPtr) {
+Std_ReturnType Fr_GetPOCStatus(uint8_t Fr_CtrlIdx, Fr_POCStatusType *Fr_POCStatusPtr)
+{
+ static const Fr_SlotModeType slot_mode[4] = {FR_SLOTMODE_KEYSLOT, FR_SLOTMODE_INVALID, FR_SLOTMODE_ALL_PENDING, FR_SLOTMODE_ALL};
+ static const Fr_ErrorModeType error_mode[4] = {FR_ERRORMODE_ACTIVE, FR_ERRORMODE_PASSIVE, FR_ERRORMODE_COMM_HALT, FR_ERRORMODE_INVALID};
+ static const Fr_POCStateType poc_state[9] = {
+ FR_POCSTATE_DEFAULT_CONFIG, FR_POCSTATE_READY, FR_POCSTATE_NORMAL_ACTIVE, FR_POCSTATE_NORMAL_PASSIVE,
+ FR_POCSTATE_HALT, FR_POCSTATE_MONITOR, FR_POCSTATE_LOOPBACK, FR_POCSTATE_INVALID, FR_POCSTATE_CONFIG
+ };
+ static const Fr_WakeupStatusType wup_state[8] = {
+ FR_WAKEUP_UNDEFINED, FR_WAKEUP_RECEIVED_HEADER, FR_WAKEUP_RECEIVED_WUP, FR_WAKEUP_COLLISION_HEADER,
+ FR_WAKEUP_COLLISION_WUP, FR_WAKEUP_COLLISION_UNKNOWN, FR_WAKEUP_TRANSMITTED, FR_WAKEUP_INVALID
+ };
+ static const Fr_StartupStateType startup_state[11] = {
+ FR_STARTUP_PREPARE, FR_STARTUP_COLDSTART_LISTEN, FR_STARTUP_COLDSTART_COLLISION_RESOLUTION,
+ FR_STARTUP_COLDSTART_CONSISTENCY_CHECK, FR_STARTUP_COLDSTART_GAP, FR_STARTUP_COLDSTART_JOIN, FR_STARTUP_INTEGRATION_COLDSTART_CHECK,
+ FR_STARTUP_INTEGRATION_LISTEN, FR_STARTUP_INTEGRATION_CONSISTENCY_CHECK, FR_STARTUP_INITIALIZE_SCHEDULE, FR_STARTUP_ABORT
+ };
+
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_POCStatusPtr == NULL) {
+ if (Fr_POCStatusPtr == NULL)
return E_NOT_OK;
- }
+
#endif
- /* Slot mode detection */
- switch (frayREG->CCSV_UN.CCSV_ST.slm_B2) {
- case 0x0: /* SINGLE */
- Fr_POCStatusPtr->SlotMode = FR_SLOTMODE_KEYSLOT;
- break;
- case 0x2: /* ALL PENDING */
- Fr_POCStatusPtr->SlotMode = FR_SLOTMODE_ALL_PENDING;
- break;
- case 0x3: /* ALL */
- Fr_POCStatusPtr->SlotMode = FR_SLOTMODE_ALL;
- break;
- default:
- return E_NOT_OK;
- }
- /* Freeze request detection */
- Fr_POCStatusPtr->Freeze = (frayREG->CCSV_UN.CCSV_ST.fsi_B1 == 1) ? TRUE : FALSE;
- /* Halt request detection */
- Fr_POCStatusPtr->CHIHaltRequest = (frayREG->CCSV_UN.CCSV_ST.hrq_B1 == 1) ? TRUE : FALSE;
- /* Coldstart noise detection */
- Fr_POCStatusPtr->ColdstartNoise = (frayREG->CCSV_UN.CCSV_ST.csni_B1 == 1) ? TRUE : FALSE;
- /* Coldstart noise detection */
- Fr_POCStatusPtr->ColdstartNoise = (frayREG->CCSV_UN.CCSV_ST.csni_B1 == 1) ? TRUE : FALSE;
- /* Error mode detection */
- switch (frayREG->CCEV_UN.CCEV_ST.errm_B2) {
- case 0x0: /* ACTIVE */
- Fr_POCStatusPtr->ErrorMode = FR_ERRORMODE_ACTIVE;
- break;
- case 0x1: /* PASSIVE */
- Fr_POCStatusPtr->ErrorMode = FR_ERRORMODE_PASSIVE;
- break;
- case 0x2: /* COMM_HALT */
- Fr_POCStatusPtr->ErrorMode = FR_ERRORMODE_COMM_HALT;
- break;
- default:
- return E_NOT_OK;
- }
+ Fr_POCStatusPtr->SlotMode = slot_mode[frayREG->CCSV_UN.CCSV_ST.slm_B2]; /* Slot mode detection */
+ Fr_POCStatusPtr->Freeze = (frayREG->CCSV_UN.CCSV_ST.fsi_B1 == 1) ? TRUE : FALSE; /* Freeze request detection */
+ Fr_POCStatusPtr->CHIHaltRequest = (frayREG->CCSV_UN.CCSV_ST.hrq_B1 == 1) ? TRUE : FALSE; /* Halt request detection */
+ Fr_POCStatusPtr->ColdstartNoise = (frayREG->CCSV_UN.CCSV_ST.csni_B1 == 1) ? TRUE : FALSE; /* Coldstart noise detection */
+ Fr_POCStatusPtr->ColdstartNoise = (frayREG->CCSV_UN.CCSV_ST.csni_B1 == 1) ? TRUE : FALSE; /* Coldstart noise detection */
+ Fr_POCStatusPtr->ErrorMode = error_mode[frayREG->CCEV_UN.CCEV_ST.errm_B2]; /* Error mode detection */
+
/* POC state detection */
- switch (frayREG->CCSV_UN.CCSV_ST.pocs_B6) {
- case FR_POCS_ABORT_STARTUP:
- case FR_POCS_COLDSTART_COLLISION_RESOLUTION:
- case FR_POCS_COLDSTART_CONSISTENCY_CHECK:
- case FR_POCS_COLDSTART_GAP:
- case FR_POCS_COLDSTART_JOIN:
- case FR_POCS_COLDSTART_LISTEN:
- case FR_POCS_INITIALIZE_SCHEDULE:
- case FR_POCS_INTEGRATION_COLDSTART_CHECK:
- case FR_POCS_INTEGRATION_CONSISTENCY_CHECK:
- case FR_POCS_INTEGRATION_LISTEN:
- case FR_POCS_STARTUP_PREPARE:
- Fr_POCStatusPtr->State = FR_POCSTATE_STARTUP;
- break;
- case FR_POCS_CONFIG:
- Fr_POCStatusPtr->State = FR_POCSTATE_CONFIG;
- break;
- case FR_POCS_DEFAULT_CONFIG:
- Fr_POCStatusPtr->State = FR_POCSTATE_DEFAULT_CONFIG;
- break;
- case FR_POCS_HALT:
- Fr_POCStatusPtr->State = FR_POCSTATE_HALT;
- break;
- case FR_POCS_LOOPBACK:
- Fr_POCStatusPtr->State = FR_POCSTATE_LOOPBACK;
- break;
- case FR_POCS_MONITOR_MODE:
- Fr_POCStatusPtr->State = FR_POCSTATE_MONITOR;
- break;
- case FR_POCS_NORMAL_ACTIVE:
- Fr_POCStatusPtr->State = FR_POCSTATE_NORMAL_ACTIVE;
- break;
- case FR_POCS_NORMAL_PASSIVE:
- Fr_POCStatusPtr->State = FR_POCSTATE_NORMAL_PASSIVE;
- break;
- case FR_POCS_READY:
- Fr_POCStatusPtr->State = FR_POCSTATE_READY;
- break;
- case FR_POCS_WAKEUP_DETECT:
- case FR_POCS_WAKEUP_LISTEN:
- case FR_POCS_WAKEUP_SEND:
- case FR_POCS_WAKEUP_STANDBY:
+ /* Startup substate detection */
+ uint16_t pocs = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
+ Fr_POCStatusPtr->StartupState = FR_STARTUP_UNDEFINED;
+ if (pocs > FR_POCSTATE_DEFAULT_CONFIG && pocs <= FR_POCSTATE_MONITOR)
+ Fr_POCStatusPtr->State = poc_state[pocs];
+ else if (pocs >= FR_POCSTATE_LOOPBACK && pocs <= FR_POCSTATE_CONFIG)
+ Fr_POCStatusPtr->State = poc_state[pocs-7];
+ else if (pocs >= FR_POCS_WAKEUP_STANDBY && pocs <= FR_POCS_WAKEUP_DETECT)
Fr_POCStatusPtr->State = FR_POCSTATE_WAKEUP;
- break;
- default:
- return E_NOT_OK;
+ else if (pocs >= FR_POCS_STARTUP_PREPARE && pocs <= FR_POCS_ABORT_STARTUP) {
+ Fr_POCStatusPtr->State = FR_POCSTATE_STARTUP;
+ Fr_POCStatusPtr->StartupState = startup_state[frayREG->CCSV_UN.CCSV_ST.pocs_B6 - FR_POCS_STARTUP_PREPARE];
}
+ else
+ Fr_POCStatusPtr->State = FR_POCSTATE_INVALID;
+
/* Wakeup substate detection */
- switch (frayREG->CCSV_UN.CCSV_ST.wsv_B3) {
- case FR_WSV_COLLISION_HEADER:
- Fr_POCStatusPtr->WakeupStatus = FR_WAKEUP_COLLISION_HEADER;
- break;
- case FR_WSV_COLLISION_UNKNOWN:
- Fr_POCStatusPtr->WakeupStatus = FR_WAKEUP_COLLISION_UNKNOWN;
- break;
- case FR_WSV_COLLISION_WUP:
- Fr_POCStatusPtr->WakeupStatus = FR_WAKEUP_COLLISION_WUP;
- break;
- case FR_WSV_RECEIVED_HEADER:
- Fr_POCStatusPtr->WakeupStatus = FR_WAKEUP_RECEIVED_HEADER;
- break;
- case FR_WSV_RECEIVED_WUP:
- Fr_POCStatusPtr->WakeupStatus = FR_WAKEUP_RECEIVED_WUP;
- break;
- case FR_WSV_TRANSMITTED:
- Fr_POCStatusPtr->WakeupStatus = FR_WAKEUP_TRANSMITTED;
- break;
- case FR_WSV_UNDEFINED:
- Fr_POCStatusPtr->WakeupStatus = FR_WAKEUP_UNDEFINED;
- break;
- default:
- return E_NOT_OK;
- }
- /* Startup substate detection */
- switch (frayREG->CCSV_UN.CCSV_ST.pocs_B6) {
- case FR_POCS_ABORT_STARTUP:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_ABORT;
- break;
- case FR_POCS_COLDSTART_COLLISION_RESOLUTION:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_COLDSTART_COLLISION_RESOLUTION;
- break;
- case FR_POCS_COLDSTART_CONSISTENCY_CHECK:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_COLDSTART_CONSISTENCY_CHECK;
- break;
- case FR_POCS_COLDSTART_GAP:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_COLDSTART_GAP;
- break;
- case FR_POCS_COLDSTART_JOIN:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_COLDSTART_JOIN;
- break;
- case FR_POCS_COLDSTART_LISTEN:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_COLDSTART_LISTEN;
- break;
- case FR_POCS_INITIALIZE_SCHEDULE:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_INITIALIZE_SCHEDULE;
- break;
- case FR_POCS_INTEGRATION_COLDSTART_CHECK:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_INTEGRATION_COLDSTART_CHECK;
- break;
- case FR_POCS_INTEGRATION_CONSISTENCY_CHECK:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_INTEGRATION_CONSISTENCY_CHECK;
- break;
- case FR_POCS_INTEGRATION_LISTEN:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_INTEGRATION_LISTEN;
- break;
- case FR_POCS_STARTUP_PREPARE:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_PREPARE;
- break;
- default:
- Fr_POCStatusPtr->StartupState = FR_STARTUP_UNDEFINED;
- break;
- }
+ Fr_POCStatusPtr->WakeupStatus = wup_state[frayREG->CCSV_UN.CCSV_ST.wsv_B3];
+
return E_OK;
}
-Std_ReturnType Fr_TransmitTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, const uint8_t* Fr_LSduPtr, uint8_t Fr_LSduLength) {
- uint32_t byte, word, buffer, index, bufferIndex;
+Std_ReturnType Fr_TransmitTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, const uint8_t *Fr_LSduPtr, uint8_t Fr_LSduLength)
+{
+ uint32_t word, buffer, index, mode;
+ uint8_t actualPayload = (Fr_LSduLength+1)/2;
+ Fr_TMS570LS_BufferConfigType tmp_buffer;
+
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_LPduIdx > cSlotIDMax) {
+ if (Fr_LPduIdx > FR_MAX_BUFFERS_CNT)
return E_NOT_OK;
- }
- if (Fr_LSduPtr == NULL) {
+ if (Fr_LSduPtr == NULL)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
#endif
/* Find the index of the buffer in configuration data array */
- for (bufferIndex = 0; bufferIndex < FR_MAX_BUFFERS_CNT; bufferIndex++) {
- if (Fr_BuffersPtrs[bufferIndex]->slotId == Fr_LPduIdx) {
- if (Fr_BuffersConfigured[bufferIndex] == TRUE && Fr_BuffersPtrs[bufferIndex]->isTx == TRUE) { // Buffer was configured already and is TX
- for (word = 0; word < (Fr_LSduLength+3)/4; word++) {
- buffer = 0;
- for (byte = 0; byte < 4; byte++) {
- index = word*4+byte;
- if (index < Fr_LSduLength) {
- buffer |= Fr_LSduPtr[index] << byte*8;
- }
- }
- frayREG->WRDS[word] = buffer;
- }
- Fr_buffer_transmit_data(bufferIndex);
- return E_OK;
+ if (Fr_LPduIdx <= frayREG->MRC_UN.MRC_ST.lcb_B8) {
+ if (Fr_BuffersConfigured[Fr_LPduIdx] == TRUE && Fr_buffer_slot_map[Fr_LPduIdx].buffer_ptr->isTx == TRUE) { // Buffer was configured already and is TX
+ memset((void *)frayREG->WRDS, 0, sizeof(frayREG->WRDS));
+ if (Fr_LPduIdx >= frayREG->MRC_UN.MRC_ST.fdb_B8) { // It is a dynamic segment buffer, reconfigure its payload to match with Fr_LSduLength
+ if (actualPayload > Fr_buffer_slot_map[Fr_LPduIdx].act_payload)
+ actualPayload = Fr_buffer_slot_map[Fr_LPduIdx].act_payload;
+ // Reconfigure buffer to send just the minimum possible payload
+ tmp_buffer = *Fr_buffer_slot_map[Fr_LPduIdx].buffer_ptr;
+ tmp_buffer.channel = Fr_buffer_slot_map[Fr_LPduIdx].act_ch_filter;
+ tmp_buffer.cycleCounterFiltering = Fr_buffer_slot_map[Fr_LPduIdx].act_cyc_filter;
+ tmp_buffer.slotId = Fr_buffer_slot_map[Fr_LPduIdx].slot_id;
+ tmp_buffer.maxPayload = actualPayload;
+ mode = Fr_buffer_config_flags(&tmp_buffer, Fr_LPduIdx);
+ Fr_config_buffer(Fr_LPduIdx, mode, tmp_buffer.cycleCounterFiltering, tmp_buffer.slotId, tmp_buffer.maxPayload, Fr_MsgRAMDataPtrs[Fr_LPduIdx]);
+
}
+ for (word = 0; word < (Fr_LSduLength+3)/4; word++) {
+ index = word*4;
+ buffer = Fr_LSduPtr[index++];
+ buffer |= (index < Fr_LSduLength) ? Fr_LSduPtr[index++] << 8 : 0;
+ buffer |= (index < Fr_LSduLength) ? Fr_LSduPtr[index++] << 16 : 0;
+ buffer |= (index < Fr_LSduLength) ? Fr_LSduPtr[index++] << 24 : 0;
+ frayREG->WRDS[word] = buffer;
+ }
+ Fr_buffer_transmit_data(Fr_LPduIdx);
+ return E_OK;
}
}
return E_NOT_OK;
}
-Std_ReturnType Fr_CancelTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx) {
- uint8_t i;
+/* Fr_LPduIdx should be buffer index, not slot number */
+Std_ReturnType Fr_CancelTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx)
+{
uint8_t mode;
+ const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr;
+
#ifdef DET_ACTIVATED
- boolean_t canceled = FALSE;
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_LPduIdx > cSlotIDMax) {
+ if (Fr_LPduIdx > FR_MAX_BUFFERS_CNT)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_Config->msgRAMConfig->secureBuffers != FR_SB_RECONFIG_ENABLED) {
+ if (Fr_Config->msgRAMConfig->secureBuffers != FR_SB_RECONFIG_ENABLED)
return E_NOT_OK;
- }
+
#endif
/* If bit IBCM.STXR in the input buffer command mask register is set (STXR = 1), the transmission request
/*
* Write the same configuration into buffer headers with TXREQ disabled.
*/
-
- for (i = 0; i < FR_MAX_BUFFERS_CNT; i++) {
- if (Fr_BuffersPtrs[i]->slotId == Fr_LPduIdx) { // Next occurence of the frame ID found, index retreived into i.
- if (Fr_BuffersConfigured[i] == TRUE) { // Buffer was already configured
- if (i == 0) {
- if (Fr_Config->nodeConfiguration->pKeySlotUsedForSync == TRUE ||
- Fr_Config->nodeConfiguration->pSingleSlotEnabled == TRUE
- ) {
- continue; // The first buffer is used for synchronization and can not be reconfigured.
- }
-
- }
- else if (i == 1) {
- if (Fr_Config->nodeConfiguration->pKeySlotUsedForSync == TRUE &&
- Fr_Config->msgRAMConfig->syncFramePayloadMultiplexEnabled == TRUE) {
- continue; // Sync frame payload multiplexing is enabled and the second buffer is used for synchronization and can not be reconfigured.
- }
- }
- mode = (Fr_BuffersPtrs[i]->singleTransmit == TRUE) ? FRAY_BUF_MBI_EN : FRAY_BUF_MBI_DIS;
- mode |= (Fr_BuffersPtrs[i]->singleTransmit == TRUE) ? FRAY_BUF_TX_MODE_SINGLE : FRAY_BUF_TX_MODE_CONTINUOUS;
- mode |= (Fr_BuffersPtrs[i]->payloadPreambleIndicatorTr == TRUE) ? FRAY_BUF_NM_EN : FRAY_BUF_NM_DIS;
- mode |= (Fr_BuffersPtrs[i]->isTx == TRUE) ? FRAY_BUF_TX : FRAY_BUF_RX;
- mode |= (Fr_BuffersPtrs[i]->channel == FR_CHANNEL_A || Fr_BuffersPtrs[i]->channel == FR_CHANNEL_AB) ? FRAY_BUF_CHA_EN : FRAY_BUF_CHA_DIS;
- mode |= (Fr_BuffersPtrs[i]->channel == FR_CHANNEL_B || Fr_BuffersPtrs[i]->channel == FR_CHANNEL_AB) ? FRAY_BUF_CHB_EN : FRAY_BUF_CHB_DIS;
- mode |= (Fr_BuffersPtrs[i]->rejectNullFrames == TRUE) ? FRAY_BUF_REJECT_NULL_FRAMES : FRAY_BUF_ACCEPT_NULL_FRAMES;
- mode |= (Fr_BuffersPtrs[i]->rejectStaticSegment == TRUE) ? FRAY_BUF_REJECT_STATIC_SEGMENT : FRAY_BUF_ACCEPT_STATIC_SEGMENT;
- mode |= FRAY_BUF_TXREQ_DIS;
- if (Fr_BuffersPtrs[i]->isTx == TRUE) {
- Fr_config_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
-#ifdef DET_ACTIVATED
- canceled = TRUE;
-#endif
- }
+ /* No buffer searching, just tests */
+ if (Fr_LPduIdx <= frayREG->MRC_UN.MRC_ST.lcb_B8) {
+ if (Fr_BuffersConfigured[Fr_LPduIdx] == TRUE) { // Buffer was already configured
+ buffer_cfg_ptr = Fr_buffer_slot_map[Fr_LPduIdx].buffer_ptr;
+ mode = Fr_buffer_config_flags(buffer_cfg_ptr, Fr_LPduIdx);
+ if (buffer_cfg_ptr->isTx == TRUE) {
+ Fr_config_buffer(Fr_LPduIdx, mode, buffer_cfg_ptr->cycleCounterFiltering, buffer_cfg_ptr->slotId, buffer_cfg_ptr->maxPayload, Fr_MsgRAMDataPtrs[Fr_LPduIdx]);
+ return E_OK;
}
}
}
-
-#ifdef DET_ACTIVATED
- return (canceled == TRUE) ? E_OK : E_NOT_OK;
-#else
- return E_OK;
-#endif
+ return E_NOT_OK;
}
-Std_ReturnType Fr_ReceiveRxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint8_t* Fr_LSduPtr, Fr_RxLPduStatusType* Fr_LPduStatusPtr, uint8_t* Fr_LSduLengthPtr) {
- volatile unsigned long * ndat[4] = {&frayREG->NDAT1_UN.NDAT1_UL, &frayREG->NDAT2_UN.NDAT2_UL, &frayREG->NDAT3_UN.NDAT3_UL, &frayREG->NDAT4_UN.NDAT4_UL};
+Std_ReturnType Fr_ReceiveRxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint8_t *Fr_LSduPtr, Fr_RxLPduStatusType *Fr_LPduStatusPtr, uint8_t *Fr_LSduLengthPtr)
+{
+ volatile unsigned long *ndat[4] = {&frayREG->NDAT1_UN.NDAT1_UL, &frayREG->NDAT2_UN.NDAT2_UL, &frayREG->NDAT3_UN.NDAT3_UL, &frayREG->NDAT4_UN.NDAT4_UL};
uint32_t bufferIndex;
- uint8_t halfWord;
+ uint8_t word, byte;
+ boolean_t bufferFound = FALSE;
+ const Fr_TMS570LS_BufferConfigType *buffer_cfg_ptr;
+
+ #define fifo_not_empty (frayREG->FSR_UN.FSR_ST.rfne_B1 == 1) // Macro that makes the code more readable, is undefined at the end of the function
+
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_LPduIdx > cSlotIDMax) {
+ if (Fr_LPduIdx > FR_MAX_BUFFERS_CNT)
return E_NOT_OK;
- }
- if (Fr_LSduPtr == NULL) {
+ if (Fr_LSduPtr == NULL)
return E_NOT_OK;
- }
- if (Fr_LPduStatusPtr == NULL) {
+ if (Fr_LPduStatusPtr == NULL)
return E_NOT_OK;
- }
- if (Fr_LSduLengthPtr == NULL) {
+ if (Fr_LSduLengthPtr == NULL)
return E_NOT_OK;
- }
+
#endif
/* Find the index of the buffer in configuration data array */
*Fr_LSduLengthPtr = 0;
*Fr_LPduStatusPtr = FR_NOT_RECEIVED;
- for (bufferIndex = 0; bufferIndex < FR_MAX_BUFFERS_CNT; bufferIndex++) {
- if (Fr_BuffersPtrs[bufferIndex]->slotId == Fr_LPduIdx) {
- if (Fr_BuffersConfigured[bufferIndex] == TRUE) { // Buffer was configured already
- /*
- * Determine if buffer is FIFO or standard static or dynamic buffer.
- * For FIFO:
- * - Pop data and header into an output buffer.
- * - Detect if more data is available in the FIFO and set Fr_LPduStatusPtr.
- * - Store loaded payload from header of the output buffer.
- * - Copy data from the output buffer to the Fr_LSduPtr address.
- * For S/D buffer:
- * - Check New Data flag, if no new data received, return.
- * - Load received data and header into the output buffer.
- * - Store loaded payload from header of the output buffer.
- * - Copy data from the output buffer to the Fr_LSduPtr address.
- */
- // FIXME: Receiving for FID rejection filter other than zero is not working. Why?
- if (bufferIndex >= frayREG->MRC_UN.MRC_ST.ffb_B8 && frayREG->FSR_UN.FSR_ST.rfne_B1 == 1) { // This is RX FIFO buffer and it is not empty
- Fr_buffer_receive_data_header(frayREG->MRC_UN.MRC_ST.ffb_B8); // Consume first element from FIFO
- if (frayREG->FSR_UN.FSR_ST.rfne_B1 == 1) { // FIFO not empty after last pop
- *Fr_LPduStatusPtr = FR_RECEIVED_MORE_DATA_AVAILABLE;
- }
- else { // FIFO empty after last pop
- *Fr_LPduStatusPtr = FR_RECEIVED;
- }
- }
- else { // Static/dynamic segment buffer
- if (*ndat[bufferIndex/32] & (0x1 << bufferIndex%32)) { // New data received
- Fr_buffer_receive_data_header(bufferIndex); // Read data and header into output buffer
- *Fr_LPduStatusPtr = FR_RECEIVED;
- }
- else { // No new data received
- return E_OK;
- }
- }
- /*
- * Copy data from output register into address from parameter Fr_LSduPtr.
- * Data in the output register are 32b words,
- * Data in Fr_LSduPtr are 8b words.
- */
- *Fr_LSduLengthPtr = frayREG->RDHS2_UN.RDHS2_ST.plr_B7*2; // Number of bytes copied into Fr_LSduPtr
- for (halfWord = 0; halfWord < frayREG->RDHS2_UN.RDHS2_ST.plr_B7; halfWord++) {
- if (halfWord%2 == 0) {
- Fr_LSduPtr[halfWord*2] = frayREG->RDDS[halfWord/2] & 0xFF;
- Fr_LSduPtr[halfWord*2+1] = (frayREG->RDDS[halfWord/2] & 0xFF00) >> 8;
- }
- else {
- Fr_LSduPtr[halfWord*2] = (frayREG->RDDS[halfWord/2] & 0xFF0000) >> 16;
- Fr_LSduPtr[halfWord*2+1] = (frayREG->RDDS[halfWord/2] & 0xFF000000) >> 24;
- }
- }
- return E_OK;
+
+ /*
+ * Try to find new message in static and dynamic segment buffers at first:
+ * - Check New Data flag, if no new data received, return.
+ * - Load received data and header into the output buffer.
+ * - Store loaded payload from header of the output buffer.
+ * - Copy data from the output buffer to the Fr_LSduPtr address.
+ * If no new message has been retrieved, there is possibility that
+ * RX FIFO buffer has received it (for example when static or dynamic
+ * segment buffers has rejection filter for channel A, but FIFO for channel B).
+ * - Check if the Fr_LPduIdx can be accepted by the RX FIFO (FID combined with the mask.
+ * - Check if the FIFO is not empty
+ * - Pop data and header into an output buffer.
+ * - Detect if more data is available in the FIFO and set Fr_LPduStatusPtr.
+ * - Store loaded payload from header of the output buffer.
+ * - Copy data from the output buffer to the Fr_LSduPtr address.
+ */
+ if (Fr_LPduIdx < frayREG->MRC_UN.MRC_ST.ffb_B8) {
+ if (Fr_BuffersConfigured[Fr_LPduIdx] == TRUE) { // Buffer was configured already
+ bufferFound = TRUE;
+ if (*ndat[Fr_LPduIdx/32] & (0x1 << Fr_LPduIdx%32)) { // New data received
+ Fr_buffer_receive_data_header(Fr_LPduIdx); // Read data and header into output buffer
+ *Fr_LPduStatusPtr = FR_RECEIVED;
}
- else { // Accessing buffer which was not yet configured.
- return E_NOT_OK;
+ }
+ }
+
+ if (*Fr_LPduStatusPtr == FR_NOT_RECEIVED && Fr_BuffersConfigured[Fr_LPduIdx] == TRUE) { // No message was received, try the FIFO.
+ bufferIndex = frayREG->MRC_UN.MRC_ST.ffb_B8;
+ buffer_cfg_ptr = Fr_buffer_slot_map[bufferIndex].buffer_ptr;
+ if ((Fr_LPduIdx & (~buffer_cfg_ptr->fidMask)) != (buffer_cfg_ptr->slotId & (~buffer_cfg_ptr->fidMask)) ) {
+ bufferFound = TRUE;
+ if (fifo_not_empty) { // The RX FIFO buffer is not empty
+ Fr_buffer_receive_data_header(bufferIndex); // Consume first element from FIFO
+ if (fifo_not_empty) // FIFO not empty after last pop
+ *Fr_LPduStatusPtr = FR_RECEIVED_MORE_DATA_AVAILABLE;
+ else // FIFO empty after last pop
+ *Fr_LPduStatusPtr = FR_RECEIVED;
}
}
}
- return E_NOT_OK; // No buffer with Fr_LPduIdx was found.
+
+ /*
+ * Copy data from output register into address from parameter Fr_LSduPtr.
+ * Data in the output register are 32b words,
+ * Data in Fr_LSduPtr are 8b words.
+ */
+ *Fr_LSduLengthPtr = frayREG->RDHS2_UN.RDHS2_ST.plr_B7*2; // Number of bytes copied into Fr_LSduPtr
+ for (byte = 0, word = 0; word < (*Fr_LSduLengthPtr+3)/4; word++) {
+ Fr_LSduPtr[byte] = (byte < *Fr_LSduLengthPtr) ? frayREG->RDDS[word] & 0xFF : 0;
+ byte++;
+ Fr_LSduPtr[byte] = (byte < *Fr_LSduLengthPtr) ? (frayREG->RDDS[word] & 0xFF00) >> 8 : 0;
+ byte++;
+ Fr_LSduPtr[byte] = (byte < *Fr_LSduLengthPtr) ? (frayREG->RDDS[word] & 0xFF0000) >> 16 : 0;
+ byte++;
+ Fr_LSduPtr[byte] = (byte < *Fr_LSduLengthPtr) ? (frayREG->RDDS[word] & 0xFF000000) >> 24 : 0;
+ byte++;
+ }
+
+ return (bufferFound == TRUE) ? E_OK : E_NOT_OK;
+ #undef fifo_not_empty
}
-Std_ReturnType Fr_CheckTxLPduStatus(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, Fr_TxLPduStatusType* Fr_TxLPduStatusPtr) {
- volatile unsigned long * txrq[4] = {&frayREG->TXRQ1_UN.TXRQ1_UL, &frayREG->TXRQ2_UN.TXRQ2_UL, &frayREG->TXRQ3_UN.TXRQ3_UL, &frayREG->TXRQ4_UN.TXRQ4_UL};
- uint8_t bufferIndex;
+Std_ReturnType Fr_CheckTxLPduStatus(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, Fr_TxLPduStatusType *Fr_TxLPduStatusPtr)
+{
+ volatile unsigned long *txrq[4] = {&frayREG->TXRQ1_UN.TXRQ1_UL, &frayREG->TXRQ2_UN.TXRQ2_UL, &frayREG->TXRQ3_UN.TXRQ3_UL, &frayREG->TXRQ4_UN.TXRQ4_UL};
+
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_LPduIdx > cSlotIDMax) {
+ if (Fr_LPduIdx > FR_MAX_BUFFERS_CNT)
return E_NOT_OK;
- }
- if (Fr_TxLPduStatusPtr == NULL) {
+ if (Fr_TxLPduStatusPtr == NULL)
return E_NOT_OK;
- }
+
#endif
- for (bufferIndex = 0; bufferIndex < FR_MAX_BUFFERS_CNT; bufferIndex++) {
- if (Fr_BuffersPtrs[bufferIndex]->slotId == Fr_LPduIdx) {
- if (Fr_BuffersConfigured[bufferIndex] == TRUE) { // Buffer was configured already
- if (Fr_BuffersPtrs[bufferIndex]->isTx == TRUE) {
- if (*txrq[bufferIndex/32] & (0x1 << bufferIndex%32)) { // Transmit request is pending
- *Fr_TxLPduStatusPtr = FR_NOT_TRANSMITTED;
- }
- else {
- *Fr_TxLPduStatusPtr = FR_TRANSMITTED;
- }
- break;
- }
+ if (Fr_LPduIdx <= frayREG->MRC_UN.MRC_ST.lcb_B8) {
+ if (Fr_BuffersConfigured[Fr_LPduIdx] == TRUE) { // Buffer was configured already
+ if (Fr_buffer_slot_map[Fr_LPduIdx].buffer_ptr->isTx == TRUE) {
+ if (*txrq[Fr_LPduIdx/32] & (0x1 << Fr_LPduIdx%32)) // Transmit request is pending
+ *Fr_TxLPduStatusPtr = FR_NOT_TRANSMITTED;
+ else
+ *Fr_TxLPduStatusPtr = FR_TRANSMITTED;
}
}
}
+
return E_OK;
}
-Std_ReturnType Fr_PrepareLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx) {
- uint32_t i;
+Std_ReturnType Fr_PrepareLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx)
+{
+ if (FrBufferReconfig == TRUE)
+ return Fr_PrepareLPdu_master(Fr_CtrlIdx, Fr_LPduIdx);
+ else
+ return E_NOT_OK;
+}
+
+Std_ReturnType Fr_ReconfigLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint16_t Fr_FrameId, Fr_ChannelType Fr_ChnlIdx, uint8_t Fr_CycleRepetition, uint8_t Fr_CycleOffset, uint8_t Fr_PayloadLength, uint16_t Fr_HeaderCRC)
+{
+ if (FrBufferReconfig == FALSE)
+ return E_NOT_OK;
+
+ int lowest_index = 0;
+ uint8_t highest_index = frayREG->MRC_UN.MRC_ST.ffb_B8;
uint32_t mode;
+ Fr_TMS570LS_BufferConfigType buffer_cfg;
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ boolean_t reconfigured = FALSE;
+ boolean_t is_pow2;
+ uint8_t pow2;
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_DRV_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_LPduIdx > cSlotIDMax) {
+ if (Fr_CycleOffset >= Fr_CycleRepetition)
return E_NOT_OK;
+ for (pow2 = 1, is_pow2 = FALSE; pow2 < 128; pow2 *= 2) {
+ if (Fr_CycleRepetition == pow2) {
+ is_pow2 = TRUE;
+ break;
+ }
}
+ if (!is_pow2)
+ return E_NOT_OK;
+
+#endif
+ lowest_index = Fr_reconfigurable_buffer_index();
+ if (lowest_index == -1)
+ return E_NOT_OK | ERR_PARAM_RECONFIG_NOT_ALLOWED;
+ if (Fr_FrameId == 0)
+ return E_NOT_OK | ERR_PARAM_INVALID_FRAME_ID;
+ if (Fr_FrameId > Fr_Config->clusterConfiguration->gNumberOfStaticSlots &&
+ Fr_ChnlIdx == FR_CHANNEL_AB)
+ return E_NOT_OK | ERR_PARAM_INVALID_CHANNEL;
+ uint8_t payload_in_hw = (Fr_PayloadLength+1)/2;
+ uint32_t cycle_filter = Fr_CycleRepetition+Fr_CycleOffset;
+
+ /* No buffer searching, just tests */
+ if (Fr_LPduIdx < highest_index) {
+ if (Fr_BuffersConfigured[Fr_LPduIdx] == TRUE) { // Buffer was configured already
+ buffer_cfg = *Fr_buffer_slot_map[Fr_LPduIdx].buffer_ptr;
+ buffer_cfg.channel = Fr_ChnlIdx;
+ buffer_cfg.cycleCounterFiltering = cycle_filter;
+ buffer_cfg.slotId = Fr_FrameId;
+ buffer_cfg.maxPayload = payload_in_hw;
+ if (buffer_cfg.maxPayload > Fr_buffer_slot_map[Fr_LPduIdx].buffer_ptr->maxPayload)
+ return E_NOT_OK | ERR_PARAM_PAYLOAD_TOO_BIG;
+ Fr_buffer_slot_map[Fr_LPduIdx].act_payload = payload_in_hw;
+ Fr_buffer_slot_map[Fr_LPduIdx].slot_id = Fr_FrameId;
+ Fr_buffer_slot_map[Fr_LPduIdx].act_ch_filter = Fr_ChnlIdx;
+ Fr_buffer_slot_map[Fr_LPduIdx].act_cyc_filter = cycle_filter;
+ mode = Fr_buffer_config_flags(&buffer_cfg, Fr_LPduIdx);
+ Fr_config_buffer(Fr_LPduIdx, mode, buffer_cfg.cycleCounterFiltering, buffer_cfg.slotId, buffer_cfg.maxPayload, Fr_MsgRAMDataPtrs[Fr_LPduIdx]);
+#ifdef DET_ACTIVATED
+ reconfigured = TRUE;
#endif
- /* Find the index of the buffer in configuration data array */
- for (i = 0; i < FR_MAX_BUFFERS_CNT; i++) {
- if (Fr_BuffersPtrs[i]->slotId == Fr_LPduIdx) { // Next occurrence of the frame ID found, index retrieved into i.
- if (Fr_BuffersConfigured[i] == FALSE) { // Buffer was not yet configured
- mode = (Fr_BuffersPtrs[i]->msgBufferInterrupt == TRUE) ? FRAY_BUF_MBI_EN : FRAY_BUF_MBI_DIS;
- mode |= (Fr_BuffersPtrs[i]->singleTransmit == TRUE) ? FRAY_BUF_TX_MODE_SINGLE : FRAY_BUF_TX_MODE_CONTINUOUS;
- mode |= (Fr_BuffersPtrs[i]->payloadPreambleIndicatorTr == TRUE) ? FRAY_BUF_NM_EN : FRAY_BUF_NM_DIS;
- mode |= (Fr_BuffersPtrs[i]->isTx == TRUE) ? FRAY_BUF_TX : FRAY_BUF_RX;
- mode |= (Fr_BuffersPtrs[i]->channel == FR_CHANNEL_A || Fr_BuffersPtrs[i]->channel == FR_CHANNEL_AB) ? FRAY_BUF_CHA_EN : FRAY_BUF_CHA_DIS;
- mode |= (Fr_BuffersPtrs[i]->channel == FR_CHANNEL_B || Fr_BuffersPtrs[i]->channel == FR_CHANNEL_AB) ? FRAY_BUF_CHB_EN : FRAY_BUF_CHB_DIS;
- mode |= (Fr_BuffersPtrs[i]->rejectNullFrames == TRUE) ? FRAY_BUF_REJECT_NULL_FRAMES : FRAY_BUF_ACCEPT_NULL_FRAMES;
- mode |= (Fr_BuffersPtrs[i]->rejectStaticSegment == TRUE) ? FRAY_BUF_REJECT_STATIC_SEGMENT : FRAY_BUF_ACCEPT_STATIC_SEGMENT;
- mode |= FRAY_BUF_TXREQ_DIS;
- if (i == 0 || (i == 1 && Fr_Config->msgRAMConfig->syncFramePayloadMultiplexEnabled == TRUE)) { // Buffer 0 is always a key slot, if payload multiplexing is enabled, then buffer 1 serves for key slot as well.
- if (Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSTARTUP] == 1) {
- mode |= FRAY_BUF_SFI_EN;
- }
- if (Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSYNC] == 1) {
- mode |= FRAY_BUF_SYNC_EN;
- }
- }
- Fr_MsgRAMDataPtrs[i] = Fr_MsgRAMDataOffset;
- if (i >= frayREG->MRC_UN.MRC_ST.ffb_B8) { // This is RX FIFO buffer
- Fr_configure_fifo_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
- }
- else { // Static/dynamic segment buffer
- Fr_config_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
- }
- /*
- * Calculate new address.
- * Payload contains the number of two-bytes words, Fr_MsgRAMDataPtrs contains addresses of 4B words in message RAM, all msgRAM addresses have
- * to be 4B aligned.
- * Offset has to be divided by two each time because payload is in 2B words and msgRAM addresses are in 4B words.
- */
- Fr_MsgRAMDataOffset += ((Fr_BuffersPtrs[i]->maxPayload)%2U == 0U ? (Fr_BuffersPtrs[i]->maxPayload) : ((Fr_BuffersPtrs[i]->maxPayload)+1U))/2;
- Fr_BuffersConfigured[i] = TRUE;
- }
}
+
}
- return E_OK;
-}
-Std_ReturnType Fr_ReconfigLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint16_t Fr_FrameId, Fr_ChannelType Fr_ChnlIdx, uint8_t Fr_CycleRepetition, uint8_t Fr_CycleOffset, uint8_t Fr_PayloadLength, uint16_t Fr_HeaderCRC) {
- /* TODO: Implement */
+#ifdef DET_ACTIVATED
+ if (reconfigured == FALSE)
+ return E_NOT_OK | ERR_PARAM_NO_BUFFER_FOUND;
+#endif
return E_OK;
}
-Std_ReturnType Fr_DisableLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx) {
+Std_ReturnType Fr_DisableLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx)
+{
+ if (FrBufferReconfig == FALSE)
+ return E_NOT_OK;
+
uint8_t bufferIndexLimit;
- uint8_t i;
uint8_t mode;
+ int lowest_index;
#ifdef DET_ACTIVATED
- boolean_t disabled = FALSE;
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_LPduIdx > cSlotIDMax) {
+ if (Fr_LPduIdx > FR_MAX_BUFFERS_CNT)
return E_NOT_OK;
- }
- if (Fr_Config->msgRAMConfig->secureBuffers != FR_SB_RECONFIG_ENABLED) {
+ if (Fr_Config->msgRAMConfig->secureBuffers != FR_SB_RECONFIG_ENABLED)
return E_NOT_OK;
- }
+
#endif
/* Determine reconfigurable buffers from the data in MRC.SET bits */
switch (frayREG->MRC_UN.MRC_ST.sec_B2) {
bufferIndexLimit = frayREG->MRC_UN.MRC_ST.fdb_B8;
break;
default:
- return E_OK; // No reconfiguration enabled
+ return E_OK; // No reconfiguration enabled
}
/* Find the index of the buffer in configuration data array */
- for (i = 0; i < FR_MAX_BUFFERS_CNT; i++) {
- if (Fr_BuffersPtrs[i]->slotId == Fr_LPduIdx) { // Next occurrence of the frame ID found, index retrieved into i.
- if (Fr_BuffersConfigured[i] == TRUE) { // Buffer was not yet configured
- if (i == 0) {
- if (Fr_Config->nodeConfiguration->pKeySlotUsedForSync == TRUE ||
- Fr_Config->nodeConfiguration->pSingleSlotEnabled == TRUE
- ) {
- continue; // The first buffer is used for synchronization and can not be reconfigured.
- }
-
- }
- else if (i == 1) {
- if (Fr_Config->nodeConfiguration->pKeySlotUsedForSync == TRUE &&
- Fr_Config->msgRAMConfig->syncFramePayloadMultiplexEnabled == TRUE) {
- continue; // Sync frame payload multiplexing is enabled and the second buffer is used for synchronization and can not be reconfigured.
- }
- }
- if (i < bufferIndexLimit) { // Buffer is reconfigurable, reset its configuration registers.
- mode = 0;
- Fr_MsgRAMDataPtrs[i] = 0;
- Fr_BuffersConfigured[i] = FALSE;
- Fr_config_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
-#ifdef DET_ACTIVATED
- disabled = TRUE;
-#endif
- }
+ if (Fr_LPduIdx <= frayREG->MRC_UN.MRC_ST.lcb_B8) {
+ if (Fr_BuffersConfigured[Fr_LPduIdx] == TRUE) { // Buffer was not yet configured
+ lowest_index = Fr_reconfigurable_buffer_index();
+ if (lowest_index == -1) // Reconfiguration disabled
+ return E_NOT_OK;
+ if (Fr_LPduIdx < lowest_index)
+ return E_NOT_OK;
+ if (Fr_LPduIdx < bufferIndexLimit) { // Buffer is reconfigurable, reset its configuration registers.
+ mode = 0;
+ Fr_MsgRAMDataPtrs[Fr_LPduIdx] = 0;
+ Fr_BuffersConfigured[Fr_LPduIdx] = FALSE;
+ Fr_config_buffer(Fr_LPduIdx, mode, Fr_buffer_slot_map[Fr_LPduIdx].buffer_ptr->cycleCounterFiltering,
+ Fr_buffer_slot_map[Fr_LPduIdx].buffer_ptr->slotId,
+ Fr_buffer_slot_map[Fr_LPduIdx].buffer_ptr->maxPayload,
+ Fr_MsgRAMDataPtrs[Fr_LPduIdx]);
+ return E_OK;
}
}
}
-#ifdef DET_ACTIVATED
- return (disabled == TRUE) ? E_OK : E_NOT_OK;
-#else
- return E_OK;
-#endif
+ return E_NOT_OK;
}
-Std_ReturnType Fr_GetGlobalTime(uint8_t Fr_CtrlIdx, uint8_t* Fr_CyclePtr, uint16_t* Fr_MacroTickPtr) {
+Std_ReturnType Fr_GetGlobalTime(uint8_t Fr_CtrlIdx, uint8_t *Fr_CyclePtr, uint16_t *Fr_MacroTickPtr)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_CyclePtr == NULL) {
+ if (Fr_CyclePtr == NULL)
return E_NOT_OK;
- }
- if (Fr_MacroTickPtr == NULL) {
+ if (Fr_MacroTickPtr == NULL)
return E_NOT_OK;
- }
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
+ return E_NOT_OK;
+
#endif
uint32_t time = frayREG->MTCCV_UN.MTCCV_UL;
*Fr_CyclePtr = __mfld2val(MTCCV_CCV_MSK, time);
static inline uint32_t swap32(uint32_t x)
{
- return (x & 0x000000ff) << 24 |
- (x & 0x0000ff00) << 8 |
- (x & 0x00ff0000) >> 8 |
- (x & 0xff000000) >> 24;
+ return (x & 0x000000ff) << 24 |
+ (x & 0x0000ff00) << 8 |
+ (x & 0x00ff0000) >> 8 |
+ (x & 0xff000000) >> 24;
}
-Std_ReturnType Fr_GetNmVector(uint8_t Fr_CtrlIdx, uint8_t* Fr_NmVectorPtr) {
+Std_ReturnType Fr_GetNmVector(uint8_t Fr_CtrlIdx, uint8_t *Fr_NmVectorPtr)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_NmVectorPtr == NULL) {
+ if (Fr_NmVectorPtr == NULL)
return E_NOT_OK;
- }
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
+ return E_NOT_OK;
+
#endif
- *((uint32_t*)(Fr_NmVectorPtr+0)) = swap32(frayREG->NMV1_UN.NMV1_UL);
- *((uint32_t*)(Fr_NmVectorPtr+4)) = swap32(frayREG->NMV2_UN.NMV2_UL);
- *((uint32_t*)(Fr_NmVectorPtr+8)) = swap32(frayREG->NMV3_UL);
+ *((uint32_t *)(Fr_NmVectorPtr+0)) = swap32(frayREG->NMV1_UN.NMV1_UL);
+ *((uint32_t *)(Fr_NmVectorPtr+4)) = swap32(frayREG->NMV2_UN.NMV2_UL);
+ *((uint32_t *)(Fr_NmVectorPtr+8)) = swap32(frayREG->NMV3_UL);
return E_OK;
}
-Std_ReturnType Fr_GetNumOfStartupFrames(uint8_t Fr_CtrlIdx, uint8_t* Fr_NumOfStartupFramesPtr) {
+Std_ReturnType Fr_GetNumOfStartupFrames(uint8_t Fr_CtrlIdx, uint8_t *Fr_NumOfStartupFramesPtr)
+{
/* TODO: Implement - can not find this information in the datasheet */
return E_OK;
}
-Std_ReturnType Fr_GetChannelStatus(uint8_t Fr_CtrlIdx, uint16_t* Fr_ChannelAStatusPtr, uint16_t* Fr_ChannelBStatusPtr) {
+Std_ReturnType Fr_GetChannelStatus(uint8_t Fr_CtrlIdx, uint16_t *Fr_ChannelAStatusPtr, uint16_t *Fr_ChannelBStatusPtr)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_ChannelAStatusPtr == NULL) {
+ if (Fr_ChannelAStatusPtr == NULL)
return E_NOT_OK;
- }
- if (Fr_ChannelBStatusPtr == NULL) {
+ if (Fr_ChannelBStatusPtr == NULL)
return E_NOT_OK;
- }
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
+ return E_NOT_OK;
+
#endif
*Fr_ChannelAStatusPtr = 0;
*Fr_ChannelBStatusPtr = 0;
return E_OK;
}
-Std_ReturnType Fr_GetClockCorrection(uint8_t Fr_CtrlIdx, int16_t* Fr_RateCorrectionPtr, int32_t* Fr_OffsetCorrectionPtr) {
+Std_ReturnType Fr_GetClockCorrection(uint8_t Fr_CtrlIdx, int16_t *Fr_RateCorrectionPtr, int32_t *Fr_OffsetCorrectionPtr)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_RateCorrectionPtr == NULL) {
+ if (Fr_RateCorrectionPtr == NULL)
return E_NOT_OK;
- }
- if (Fr_OffsetCorrectionPtr == NULL) {
+ if (Fr_OffsetCorrectionPtr == NULL)
return E_NOT_OK;
- }
+
#endif
*Fr_RateCorrectionPtr = frayREG->RCV_UN.RCV_ST.rcv_B12;
*Fr_OffsetCorrectionPtr = frayREG->OCV_UN.OCV_ST.ocv_B14;
return E_OK;
}
-Std_ReturnType Fr_GetSyncFrameList(uint8_t Fr_CtrlIdx, uint8_t Fr_ListSize, uint16_t* Fr_ChannelAEvenListPtr, uint16_t* Fr_ChannelBEvenListPtr, uint16_t* Fr_ChannelAOddListPtr, uint16_t* Fr_ChannelBOddListPtr) {
+Std_ReturnType Fr_GetSyncFrameList(uint8_t Fr_CtrlIdx, uint8_t Fr_ListSize, uint16_t *Fr_ChannelAEvenListPtr, uint16_t *Fr_ChannelBEvenListPtr, uint16_t *Fr_ChannelAOddListPtr, uint16_t *Fr_ChannelBOddListPtr)
+{
uint32_t esid;
uint32_t osid;
uint8_t i;
+
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_ChannelAEvenListPtr == NULL) {
+ if (Fr_ChannelAEvenListPtr == NULL)
return E_NOT_OK;
- }
- if (Fr_ChannelBEvenListPtr == NULL) {
+ if (Fr_ChannelBEvenListPtr == NULL)
return E_NOT_OK;
- }
- if (Fr_ChannelAOddListPtr == NULL) {
+ if (Fr_ChannelAOddListPtr == NULL)
return E_NOT_OK;
- }
- if (Fr_ChannelBOddListPtr == NULL) {
+ if (Fr_ChannelBOddListPtr == NULL)
return E_NOT_OK;
- }
+
#endif
- if (Fr_ListSize > FR_MAX_SYNC_FRAME_LIST_SIZE) { // Limit list size to 15
+ if (Fr_ListSize > FR_MAX_SYNC_FRAME_LIST_SIZE) // Limit list size to 15
Fr_ListSize = FR_MAX_SYNC_FRAME_LIST_SIZE;
- }
for (i = 0; i < Fr_ListSize; i++) {
esid = frayREG->ESID_UL[i];
return E_OK;
}
-Std_ReturnType Fr_GetWakeupRxStatus(uint8_t Fr_CtrlIdx, uint8_t* Fr_WakeupRxStatusPtr) {
+Std_ReturnType Fr_GetWakeupRxStatus(uint8_t Fr_CtrlIdx, uint8_t *Fr_WakeupRxStatusPtr)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_WakeupRxStatusPtr == NULL) {
+ if (Fr_WakeupRxStatusPtr == NULL)
return E_NOT_OK;
- }
+
#endif
*Fr_WakeupRxStatusPtr = 0;
return E_OK;
}
-Std_ReturnType Fr_SetAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, uint8_t Fr_Cycle, uint16_t Fr_Offset) {
+Std_ReturnType Fr_SetAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, uint8_t Fr_Cycle, uint16_t Fr_Offset)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_AbsTimerIdx > 1) {
+ if (Fr_AbsTimerIdx > 1)
return E_NOT_OK;
- }
- if (Fr_Offset > Fr_Config->clusterConfiguration->gMacroPerCycle) {
+ if (Fr_Offset > Fr_Config->clusterConfiguration->gMacroPerCycle)
return E_NOT_OK;
- }
- if (Fr_Cycle & 0x80) {
+ if (Fr_Cycle & 0x80)
return E_NOT_OK;
- }
+ if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_ACTIVE && frayREG->CCSV_UN.CCSV_ST.pocs_B6 != FR_POCS_NORMAL_PASSIVE)
+ return E_NOT_OK;
+
#endif
if (Fr_AbsTimerIdx == 0) {
frayREG->T0C_UN.T0C_ST.t0rc_B1 = 0;
frayREG->T0C_UN.T0C_ST.t0ms_B1 = 1;
frayREG->T0C_UN.T0C_ST.t0cc_B7 = Fr_Cycle;
frayREG->T0C_UN.T0C_ST.t0mo_B14 = Fr_Offset;
- frayREG->SIR_UN.SIR_ST.ti0_B1 = 1; // Reset interrupt
+ frayREG->SIR_UN.SIR_ST.ti0_B1 = 1; // Reset interrupt
frayREG->T0C_UN.T0C_ST.t0rc_B1 = 1;
}
else if (Fr_AbsTimerIdx == 1) {
frayREG->T1C_UN.T1C_ST.t1rc_B1 = 0;
frayREG->T1C_UN.T1C_ST.t1ms_B1 = 1;
frayREG->T1C_UN.T1C_ST.t1mc_B14 = Fr_Cycle*Fr_Config->clusterConfiguration->gMacroPerCycle+Fr_Offset;
- frayREG->SIR_UN.SIR_ST.ti1_B1 = 1;// Reset interrupt
+ frayREG->SIR_UN.SIR_ST.ti1_B1 = 1; // Reset interrupt
frayREG->T1C_UN.T1C_ST.t1rc_B1 = 1;
}
- else {
+ else
return E_NOT_OK;
- }
-
return E_OK;
}
-Std_ReturnType Fr_CancelAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
+Std_ReturnType Fr_CancelAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_AbsTimerIdx > 1) {
+ if (Fr_AbsTimerIdx > 1)
return E_NOT_OK;
- }
+
#endif
- if (Fr_AbsTimerIdx == 0) {
+ if (Fr_AbsTimerIdx == 0)
frayREG->T0C_UN.T0C_ST.t0rc_B1 = 0;
- }
- else if (Fr_AbsTimerIdx == 1) {
+ else if (Fr_AbsTimerIdx == 1)
frayREG->T1C_UN.T1C_ST.t1rc_B1 = 0;
- }
- else {
+ else
return E_NOT_OK;
- }
return E_OK;
}
-Std_ReturnType Fr_EnableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
+Std_ReturnType Fr_EnableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_AbsTimerIdx > 1) {
+ if (Fr_AbsTimerIdx > 1)
return E_NOT_OK;
- }
+
#endif
frayREG->ILE_UN.ILE_ST.eint0_B1 = 1;
- if (Fr_AbsTimerIdx == 0) {
+ if (Fr_AbsTimerIdx == 0)
frayREG->SIES_UN.SIES_ST.ti0e_B1 = 1;
- }
- else if (Fr_AbsTimerIdx == 1) {
+ else if (Fr_AbsTimerIdx == 1)
frayREG->SIES_UN.SIES_ST.ti0e_B1 = 1;
- }
- else {
+ else
return E_NOT_OK;
- }
return E_OK;
}
-Std_ReturnType Fr_AckAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
+Std_ReturnType Fr_AckAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_AbsTimerIdx > 1) {
+ if (Fr_AbsTimerIdx > 1)
return E_NOT_OK;
- }
+
#endif
- if (Fr_AbsTimerIdx == 0) {
+ if (Fr_AbsTimerIdx == 0)
frayREG->SIR_UN.SIR_ST.ti0_B1 = 1;
- }
- else if (Fr_AbsTimerIdx == 1) {
+ else if (Fr_AbsTimerIdx == 1)
frayREG->SIR_UN.SIR_ST.ti1_B1 = 1;
- }
- else {
+ else
return E_NOT_OK;
- }
return E_OK;
}
-Std_ReturnType Fr_DisableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
+Std_ReturnType Fr_DisableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_AbsTimerIdx > 1) {
+ if (Fr_AbsTimerIdx > 1)
return E_NOT_OK;
- }
+
#endif
- if (Fr_AbsTimerIdx == 0) {
+ if (Fr_AbsTimerIdx == 0)
frayREG->SIER_UN.SIER_ST.ti0e_B1 = 1;
- }
- else if (Fr_AbsTimerIdx == 1) {
+ else if (Fr_AbsTimerIdx == 1)
frayREG->SIER_UN.SIER_ST.ti0e_B1 = 1;
- }
- else {
+ else
return E_NOT_OK;
- }
return E_OK;
}
-Std_ReturnType Fr_GetAbsoluteTimerIRQStatus(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, boolean_t* Fr_IRQStatusPtr) {
+Std_ReturnType Fr_GetAbsoluteTimerIRQStatus(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, boolean_t *Fr_IRQStatusPtr)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
- if (Fr_AbsTimerIdx > 1) {
+ if (Fr_AbsTimerIdx > 1)
return E_NOT_OK;
- }
- if (Fr_IRQStatusPtr == NULL) {
+ if (Fr_IRQStatusPtr == NULL)
return E_NOT_OK;
- }
+
#endif
- if (Fr_AbsTimerIdx == 0) {
+ if (Fr_AbsTimerIdx == 0)
*Fr_IRQStatusPtr = (frayREG->SIR_UN.SIR_ST.ti0_B1 == 1) ? TRUE : FALSE;
- }
- else if (Fr_AbsTimerIdx == 1) {
+ else if (Fr_AbsTimerIdx == 1)
*Fr_IRQStatusPtr = (frayREG->SIR_UN.SIR_ST.ti1_B1 == 1) ? TRUE : FALSE;
- }
- else {
+ else
return E_NOT_OK;
- }
return E_OK;
}
-void Fr_GetVersionInfo(Std_VersionInfoType* VersioninfoPtr) {
+void Fr_GetVersionInfo(Std_VersionInfoType *VersioninfoPtr)
+{
#ifdef DET_ACTIVATED
- if (VersioninfoPtr == NULL) {
+ if (VersioninfoPtr == NULL)
return;
- }
+
#endif
VersioninfoPtr->vendorID = Fr_versionInfo.vendorID;
VersioninfoPtr->moduleID = Fr_versionInfo.moduleID;
VersioninfoPtr->sw_major_version = Fr_versionInfo.sw_major_version;
- VersioninfoPtr->sw_minor_version= Fr_versionInfo.sw_minor_version;
- VersioninfoPtr->sw_patch_version= Fr_versionInfo.sw_patch_version;
+ VersioninfoPtr->sw_minor_version = Fr_versionInfo.sw_minor_version;
+ VersioninfoPtr->sw_patch_version = Fr_versionInfo.sw_patch_version;
}
-Std_ReturnType Fr_ReadCCConfig( uint8_t Fr_CtrlIdx, uint8_t Fr_ConfigParamIdx, uint32_t* Fr_ConfigParamValuePtr) {
+Std_ReturnType Fr_ReadCCConfig( uint8_t Fr_CtrlIdx, uint8_t Fr_ConfigParamIdx, uint32_t *Fr_ConfigParamValuePtr)
+{
#ifdef DET_ACTIVATED
- if (Fr_CtrlIdx != 0) {
+ if (Fr_CtrlIdx != 0)
return E_NOT_OK;
- }
- if (Fr_ConfigParamIdx >= FR_CIDX_CNT) {
+ if (Fr_ConfigParamIdx >= FR_CIDX_CNT)
return E_NOT_OK;
- }
- if (Fr_ConfigParamValuePtr == NULL) {
+ if (Fr_ConfigParamValuePtr == NULL)
return E_NOT_OK;
- }
- if (Fr_DrvState != FR_ST_CTRL_INITIALIZED) {
+ if (Fr_DrvState < FR_ST_CTRL_INITIALIZED)
return E_NOT_OK;
- }
+
#endif
*Fr_ConfigParamValuePtr = Fr_ConfigParPtrs[Fr_ConfigParamIdx];
return E_OK;
}
-int Fr_spi_transfer(uint8_t port) {
- uint32_t commands[2];
- port_desc_t* desc;
+int Fr_spi_transfer(uint8_t port)
+{
+ uint32_t commands[2];
+ dio_port_desc_t *desc;
- if (port > FRAY_NUM_PORTS) return -1;
- desc = hal_port_get_dsc(fray_port_names[port], -1);
- fray_spi_cmd_sh = fray_spi_cmd;
- commands[0] = (fray_spi_cmd_sh & 0xFF00) >> 8;
- commands[1] = (fray_spi_cmd_sh & 0xFF);
+ if (port > FRAY_NUM_PORTS) return -1;
+ desc = dio_port_get_dsc(fray_port_names[port], -1);
+ fray_spi_cmd_sh = fray_spi_cmd;
+ commands[0] = (fray_spi_cmd_sh & 0xFF00) >> 8;
+ commands[1] = (fray_spi_cmd_sh & 0xFF);
- fray_spi_resp[port] = desc->port_setfnc_ptr(desc->config, desc->numValues, commands);
- return 0;
+ fray_spi_resp[port] = desc->port_setfnc_ptr(desc->config, desc->numValues, commands);
+ return 0;
}
-int Fr_spi_response(uint8_t port) {
- if (port > FRAY_NUM_PORTS) return -1;
- return fray_spi_resp[port];
+int Fr_spi_response(uint8_t port)
+{
+ if (port > FRAY_NUM_PORTS) return -1;
+ return fray_spi_resp[port];
}
-int Fr_spi_get_cmd(uint8_t port) {
- if (port > FRAY_NUM_PORTS) return -1;
- return fray_spi_cmd;
+int Fr_spi_get_cmd(uint8_t port)
+{
+ if (port > FRAY_NUM_PORTS) return -1;
+ return fray_spi_cmd;
}
projects / pes-rpp / rpp-lib.git / blobdiff