1 /* Copyright (C) 2013 Czech Technical University in Prague
4 * - Carlos Jenkins <carlos@jenkins.co.cr>
5 * - Michal Horn <hornmich@fel.cvut.cz>
7 * This document contains proprietary information belonging to Czech
8 * Technical University in Prague. Passing on and copying of this
9 * document, and communication of its contents is not permitted
10 * without prior written authorization.
14 * FlexRay Communication RPP API implementation file.
18 * RPP API documentation.
24 #ifndef FREERTOS_POSIX
30 static rpp_fr_state_t rpp_fr_state = RPP_FR_NOT_INITIALIZED; /**< Stores the actual state of the FlexRay module */
32 /* AUTOSAR-like API */
34 int8_t rpp_fr_init_driver(const Fr_ConfigType* config_ptr, uint32_t* error) {
35 if (rpp_fr_state >= RPP_FR_DRV_INITIALIZED)
37 #if rppCONFIG_DRV == 1
41 rpp_fr_state = RPP_FR_DRV_INITIALIZED;
45 int8_t rpp_fr_init_controller(uint8_t ctrl, uint32_t* error) {
46 Std_ReturnType retVal = ERR_PARAM_NO_ERROR;
47 if (rpp_fr_state == RPP_FR_DRV_INITIALIZED ||
48 rpp_fr_state == RPP_FR_HALTED ||
49 rpp_fr_state == RPP_FR_ABORTED) {
50 retVal = Fr_ControllerInit(ctrl);
52 rpp_fr_state = RPP_FR_CTR_INITIALIZED;
63 int8_t rpp_fr_start_communication(uint8_t ctrl, uint32_t* error) {
64 Std_ReturnType retVal = ERR_PARAM_NO_ERROR;
65 if (rpp_fr_state == RPP_FR_CTR_INITIALIZED) {
66 retVal = Fr_StartCommunication(ctrl);
68 rpp_fr_state = RPP_FR_RUNNING;
79 int8_t rpp_fr_all_slots(uint8_t ctrl) {
80 if (rpp_fr_state == RPP_FR_RUNNING && Fr_AllSlots(ctrl) & E_OK) {
86 int8_t rpp_fr_halt_communication(uint8_t ctrl) {
87 if (rpp_fr_state == RPP_FR_RUNNING && Fr_HaltCommunication(ctrl) & E_OK) {
88 rpp_fr_state = RPP_FR_HALTED;
94 int8_t rpp_fr_abort_communication(uint8_t ctrl) {
95 if (rpp_fr_state == RPP_FR_RUNNING && Fr_AbortCommunication(ctrl) & E_OK) {
96 rpp_fr_state = RPP_FR_ABORTED;
102 int8_t rpp_fr_send_wup(uint8_t ctrl) {
103 if (rpp_fr_state == RPP_FR_CTR_INITIALIZED && Fr_SendWUP(ctrl) & E_OK) {
109 int8_t rpp_fr_set_wu_channel(uint8_t ctrl, Fr_ChannelType channel) {
110 if (rpp_fr_state >= RPP_FR_CTR_INITIALIZED && Fr_SetWakeupChannel(ctrl, channel) & E_OK) {
116 int8_t rpp_fr_get_poc_status(uint8_t ctrl, Fr_POCStatusType* poc_status_ptr) {
117 if (rpp_fr_state >= RPP_FR_DRV_INITIALIZED && Fr_GetPOCStatus(ctrl, poc_status_ptr) & E_OK) {
123 int8_t rpp_fr_transmit_lpdu(uint8_t ctrl, uint16_t lpdu_idx, const uint8_t* lsdu, uint8_t lsdu_length) {
124 if (rpp_fr_state == RPP_FR_RUNNING && Fr_TransmitTxLPdu(ctrl, lpdu_idx, lsdu, lsdu_length) & E_OK) {
130 int8_t rpp_fr_cancel_transmit_lpdu(uint8_t ctrl, uint16_t lpdu_idx) {
131 if (rpp_fr_state == RPP_FR_RUNNING && Fr_CancelTxLPdu(ctrl, lpdu_idx) & E_OK) {
137 int8_t rpp_fr_receive_lpdu(uint8_t ctrl, uint16_t lpdu_idx, uint8_t* lsdu, Fr_RxLPduStatusType* lpdu_status, uint8_t* lsdu_length) {
138 if (rpp_fr_state == RPP_FR_RUNNING && Fr_ReceiveRxLPdu(ctrl, lpdu_idx, lsdu, lpdu_status, lsdu_length) & E_OK) {
144 int8_t rpp_fr_check_tx_lpdu_status(uint8_t ctrl, uint16_t lpdu_idx, Fr_TxLPduStatusType* lpdu_status) {
145 if (rpp_fr_state == RPP_FR_RUNNING && Fr_CheckTxLPduStatus(ctrl, lpdu_idx, lpdu_status) & E_OK) {
151 int8_t rpp_fr_reconfigure_lpdu(uint8_t ctrl, uint16_t lpdu_idx, uint16_t frame_id, Fr_ChannelType channel, uint8_t cycle_set, uint8_t cycle_offset, uint8_t payload, uint16_t header_crc) {
152 if (rpp_fr_state >= RPP_FR_CTR_INITIALIZED && Fr_ReconfigLPdu(ctrl, lpdu_idx, frame_id, channel, cycle_set, cycle_offset, payload, header_crc) & E_OK) {
158 int8_t rpp_fr_disable_lpdu(uint8_t ctrl, uint16_t lpdu_idx) {
159 if (rpp_fr_state == RPP_FR_RUNNING && Fr_DisableLPdu(ctrl, lpdu_idx) & E_OK) {
165 int8_t rpp_fr_get_global_time(uint8_t ctrl, uint8_t* cycle, uint16_t* macroticks) {
166 if (rpp_fr_state >= RPP_FR_CTR_INITIALIZED && Fr_GetGlobalTime(ctrl, cycle, macroticks) & E_OK) {
172 int8_t rpp_fr_get_network_management_vector(uint8_t ctrl, uint8_t* nm_vector) {
173 if (rpp_fr_state >= RPP_FR_CTR_INITIALIZED && Fr_GetNmVector(ctrl, nm_vector) & E_OK) {
179 int8_t rpp_fr_get_channel_status(uint8_t ctrl, uint16_t* channel_a_status, uint16_t* channel_b_status) {
180 if (rpp_fr_state >= RPP_FR_CTR_INITIALIZED && Fr_GetChannelStatus(ctrl, channel_a_status, channel_b_status) & E_OK) {
186 int8_t rpp_fr_get_clock_correction(uint8_t ctrl, int16_t* rate_correction, int32_t* offset_correction) {
187 if (rpp_fr_state >= RPP_FR_RUNNING && Fr_GetClockCorrection(ctrl, rate_correction, offset_correction) & E_OK) {
193 int8_t rpp_fr_get_sync_frame_list(uint8_t ctrl, uint8_t list_size, uint16_t* channel_a_even_list, uint16_t* channel_b_even_list, uint16_t* channel_a_odd_list, uint16_t* channel_b_odd_list) {
194 if (rpp_fr_state >= RPP_FR_RUNNING && Fr_GetSyncFrameList(ctrl, list_size, channel_a_even_list, channel_b_even_list, channel_a_odd_list, channel_b_odd_list) & E_OK) {
200 int8_t rpp_fr_get_wakeup_rx_status(uint8_t ctrl, uint8_t* status) {
201 if (rpp_fr_state >= RPP_FR_DRV_INITIALIZED && Fr_GetWakeupRxStatus(ctrl, status) & E_OK) {
207 int8_t rpp_fr_set_timer(uint8_t ctrl, uint8_t timer_idx, uint8_t cycle_set, uint16_t offset_threshold) {
208 if (rpp_fr_state == RPP_FR_RUNNING && Fr_SetAbsoluteTimer(ctrl, timer_idx, cycle_set, offset_threshold) & E_OK) {
214 int8_t rpp_fr_cancel_timer(uint8_t ctrl, uint8_t timer_idx) {
215 if (rpp_fr_state == RPP_FR_RUNNING && Fr_CancelAbsoluteTimer(ctrl, timer_idx) & E_OK) {
221 int8_t rpp_fr_clear_timer_irq(uint8_t ctrl, uint8_t timer_idx) {
222 if (rpp_fr_state >= RPP_FR_DRV_INITIALIZED && Fr_AckAbsoluteTimerIRQ(ctrl, timer_idx) & E_OK) {
228 int8_t rpp_fr_get_timer_irq_status(uint8_t ctrl, uint8_t timer_idx, boolean_t* irq_pending) {
229 if (rpp_fr_state >= RPP_FR_DRV_INITIALIZED && Fr_GetAbsoluteTimerIRQStatus(ctrl, timer_idx, irq_pending) & E_OK) {
235 int8_t rpp_fr_get_driver_version(Std_VersionInfoType* version) {
236 Fr_GetVersionInfo(version);
240 int8_t rpp_fr_read_com_ctrl_config(uint8_t ctrl, uint8_t param_idx, uint32_t* param_value) {
241 if (Fr_ReadCCConfig(ctrl, param_idx, param_value) & E_OK) {
246 #endif /* FREERTOS_POSIX */