2 * @brief PINMUX Register Layer Header File
9 * - Interface Prototypes
11 * which are relevant for the PINMUX driver.
15 * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
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49 #ifndef __REG_PINMUX_H__
50 #define __REG_PINMUX_H__
56 /* IOMM Revision and Boot Register */
57 #define REVISION_REG (*(volatile uint32_t *)0xFFFFEA00U)
58 #define ENDIAN_REG (*(volatile uint32_t *)0xFFFFEA20U)
60 /* IOMM Error and Fault Registers */
61 /** @struct iommErrFault
62 * @brief IOMM Error and Fault Register Definition
64 * This structure is used to access the IOMM Error and Fault registers.
66 typedef volatile struct iommErrFault
68 uint32_t ERR_RAW_STATUS_REG; /* Error Raw Status / Set Register */
69 uint32_t ERR_ENABLED_STATUS_REG; /* Error Enabled Status / Clear Register */
70 uint32_t ERR_ENABLE_REG; /* Error Signaling Enable Register */
71 uint32_t ERR_ENABLE_CLR_REG; /* Error Signaling Enable Clear Register */
72 uint32_t rsvd; /* Reserved */
73 uint32_t FAULT_ADDRESS_REG; /* Fault Address Register */
74 uint32_t FAULT_STATUS_REG; /* Fault Status Register */
75 uint32_t FAULT_CLEAR_REG; /* Fault Clear Register */
77 /* Pinmux Register Frame Definition */
78 /** @struct pinMuxKicker
79 * @brief Pin Muxing Kicker Register Definition
81 * This structure is used to access the Pin Muxing Kicker registers.
83 typedef volatile struct pinMuxKicker
85 uint32_t KICKER0; /* kicker 0 register */
86 uint32_t KICKER1; /* kicker 1 register */
89 /** @struct pinMuxBase
90 * @brief PINMUX Register Definition
92 * This structure is used to access the PINMUX module registers.
94 /** @typedef pinMuxBASE_t
95 * @brief PINMUX Register Frame Type Definition
97 * This type is used to access the PINMUX Registers.
99 typedef volatile struct pinMuxBase
101 uint32_t PINMMR0; /**< 0xEB10 Pin Mux 0 register*/
102 uint32_t PINMMR1; /**< 0xEB14 Pin Mux 1 register*/
103 uint32_t PINMMR2; /**< 0xEB18 Pin Mux 2 register*/
104 uint32_t PINMMR3; /**< 0xEB1C Pin Mux 3 register*/
105 uint32_t PINMMR4; /**< 0xEB20 Pin Mux 4 register*/
106 uint32_t PINMMR5; /**< 0xEB24 Pin Mux 5 register*/
107 uint32_t PINMMR6; /**< 0xEB28 Pin Mux 6 register*/
108 uint32_t PINMMR7; /**< 0xEB2C Pin Mux 7 register*/
109 uint32_t PINMMR8; /**< 0xEB30 Pin Mux 8 register*/
110 uint32_t PINMMR9; /**< 0xEB34 Pin Mux 9 register*/
111 uint32_t PINMMR10; /**< 0xEB38 Pin Mux 10 register*/
112 uint32_t PINMMR11; /**< 0xEB3C Pin Mux 11 register*/
113 uint32_t PINMMR12; /**< 0xEB40 Pin Mux 12 register*/
114 uint32_t PINMMR13; /**< 0xEB44 Pin Mux 13 register*/
115 uint32_t PINMMR14; /**< 0xEB48 Pin Mux 14 register*/
116 uint32_t PINMMR15; /**< 0xEB4C Pin Mux 15 register*/
117 uint32_t PINMMR16; /**< 0xEB50 Pin Mux 16 register*/
118 uint32_t PINMMR17; /**< 0xEB54 Pin Mux 17 register*/
119 uint32_t PINMMR18; /**< 0xEB58 Pin Mux 18 register*/
120 uint32_t PINMMR19; /**< 0xEB5C Pin Mux 19 register*/
121 uint32_t PINMMR20; /**< 0xEB60 Pin Mux 20 register*/
122 uint32_t PINMMR21; /**< 0xEB64 Pin Mux 21 register*/
123 uint32_t PINMMR22; /**< 0xEB68 Pin Mux 22 register*/
124 uint32_t PINMMR23; /**< 0xEB6C Pin Mux 23 register*/
125 uint32_t PINMMR24; /**< 0xEB70 Pin Mux 24 register*/
126 uint32_t PINMMR25; /**< 0xEB74 Pin Mux 25 register*/
127 uint32_t PINMMR26; /**< 0xEB78 Pin Mux 26 register*/
128 uint32_t PINMMR27; /**< 0xEB7C Pin Mux 27 register*/
129 uint32_t PINMMR28; /**< 0xEB80 Pin Mux 28 register*/
130 uint32_t PINMMR29; /**< 0xEB84 Pin Mux 29 register*/
131 uint32_t PINMMR30; /**< 0xEB88 Pin Mux 30 register*/
132 uint32_t PINMMR31; /**< 0xEB8C Pin Mux 31 register*/
133 uint32_t PINMMR32; /**< 0xEB90 Pin Mux 32 register*/
134 uint32_t PINMMR33; /**< 0xEB94 Pin Mux 33 register*/
135 uint32_t PINMMR34; /**< 0xEB98 Pin Mux 34 register*/
136 uint32_t PINMMR35; /**< 0xEB9C Pin Mux 35 register*/
137 uint32_t PINMMR36; /**< 0xEBA0 Pin Mux 36 register*/
138 uint32_t PINMMR37; /**< 0xEBA4 Pin Mux 37 register*/
139 uint32_t PINMMR38; /**< 0xEBA8 Pin Mux 38 register*/
140 uint32_t PINMMR39; /**< 0xEBAC Pin Mux 39 register*/
141 uint32_t PINMMR40; /**< 0xEBB0 Pin Mux 40 register*/
142 uint32_t PINMMR41; /**< 0xEBB4 Pin Mux 41 register*/
143 uint32_t PINMMR42; /**< 0xEBB8 Pin Mux 42 register*/
144 uint32_t PINMMR43; /**< 0xEBBC Pin Mux 43 register*/
145 uint32_t PINMMR44; /**< 0xEBC0 Pin Mux 44 register*/
146 uint32_t PINMMR45; /**< 0xEBC4 Pin Mux 45 register*/
147 uint32_t PINMMR46; /**< 0xEBC8 Pin Mux 46 register*/
148 uint32_t PINMMR47; /**< 0xEBCC Pin Mux 47 register*/
153 /** @def iommErrFaultReg
154 * @brief IOMM Error Fault Register Frame Pointer
156 * This pointer is used to control IOMM Error and Fault across the device.
158 #define iommErrFaultReg ((iommErrFault_t *) 0xFFFFEAE0U)
161 * @brief Pin Muxing Kicker Register Frame Pointer
163 * This pointer is used to enable and disable muxing across the device.
165 #define kickerReg ((pinMuxKICKER_t *) 0xFFFFEA38U)
168 * @brief Pin Muxing Control Register Frame Pointer
170 * This pointer is used to set the muxing registers across the device.
172 #define pinMuxReg ((pinMuxBASE_t *) 0xFFFFEB10U)