3 * @file spi_resp_transl.h
5 * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
7 * @author Michal Horn <hornmich@fel.cvut.cz>
13 //#include "sys_common.h"
14 //#include "drv_spi.h"
15 #include "ul/ul_list.h"
17 #include "sys/cpu_def.h"
20 #define SPI_CTRL_WAKE_RQ 1
22 /* ------------------------------------------------------------------------- */
24 #define SPI_MSG_FINISHED 0x040
25 #define SPI_MSG_ABORT 0x020
26 #define SPI_MSG_FAIL 0x010
28 #define SPI_BR_FORMAT0 1000000 /**< Clock rate for data format 0 in Hz. */
29 #define SPI_BR_FORMAT1 1000000 /**< Clock rate for data format 0 in Hz. */
30 #define SPI_BR_FORMAT2 1000000 /**< Clock rate for data format 0 in Hz. */
31 #define SPI_BR_FORMAT3 1000000 /**< Clock rate for data format 0 in Hz. */
36 typedef int (spi_ctrl_fnc_t)(struct spi_drv *ifc, int ctrl, void *p);
38 typedef struct spi_msg_head {
39 uint16_t flags; // message flags
40 uint16_t addr; // message destination address -- used as index into the "address translation table"*/
42 //uint16_t size_mode; // message frame len and mode
43 uint16_t rq_len; // requested transfer length
44 const uint8_t *tx_buf; // pointer to TX data
45 uint8_t *rx_buf; // pointer to RX data
48 //struct spi_drv *ifc;
49 int (*callback)(struct spi_drv *ifc, int code, struct spi_msg_head *msg); // Called when whole transfer is finished
50 long private; // If set -- msg is processed by HW
53 typedef struct spi_drv {
54 uint16_t flags; // Flags
56 ul_list_head_t rq_queue; // Queue containing MSG requests to process
57 spi_msg_head_t *msg_act; // MSG being actually processed
58 spi_ctrl_fnc_t *ctrl_fnc; // Device dependent function responsible for sending data
62 /* ------------------------------------------------------------------------- */
64 typedef unsigned long spi_isr_lock_level_t;
65 #define spi_isr_lock save_and_cli
66 #define spi_isr_unlock restore_flags
68 /* ------------------------------------------------------------------------- */
70 #define spi_compat_REG2 ((spiBASE_compat_t *)0xFFF7F600U)
71 #define spi_compat_REG4 ((spiBASE_compat_t *)0xFFF7FA00U)
72 #define mibspi_compat_REG1 ((spiBASE_compat_t *)0xFFF7F400U)
73 #define mibspi_compat_REG3 ((spiBASE_compat_t *)0xFFF7F800U)
74 #define mibspi_compat_REG5 ((spiBASE_compat_t *)0xFFF7FC00U) /* NOT USED ON RPP BOARD */
77 #define SPI_FLG_TXINT_m (1 << 9)
78 #define SPI_FLG_RXINT_m (1 << 8)
80 #define SPI_INT0_TXINTENA_m (1 << 9)
81 #define SPI_INT0_RXINTENA_m (1 << 8)
83 #define SPI_DAT1_CSHOLD_m (1 << 28)
85 /* Used as CSNR in DATA1 reg */
103 typedef volatile struct spiBase {
104 uint32_t GCR0; /**< 0x0000: Global Control 0 */
105 #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
106 uint32_t GCR1 : 8U; /**< 0x0007: Global Control 1 */
107 uint32_t PD : 1U; /**< 0x0006: Power down bit */
109 uint32_t LB : 1U; /**< 0x0005: Loop back bit */
111 uint32_t ENA : 1U; /**< 0x0004: SPI Enable bit */
113 uint32_t INT0 : 16U; /**< 0x000A: Interrupt Enable bits */
114 uint32_t DMAREQEN : 1U; /**< 0x0009: DMA Request enable */
116 uint32_t ENAHIGHZ : 1U; /**< 0x0008: Enable HIGHZ outputs */
120 uint32_t ENA : 1U; /**< 0x0004: SPI Enable bit */
122 uint32_t LB : 1U; /**< 0x0005: Loop back bit */
124 uint32_t PD : 1U; /**< 0x0006: Power down bit */
125 uint32_t GCR1 : 8U; /**< 0x0007: Global Control 1 */
127 uint32_t ENAHIGHZ : 1U; /**< 0x0008: Enable HIGHZ outputs */
129 uint32_t DMAREQEN : 1U; /**< 0x0009: DMA Request enable */
130 uint32_t INT0 : 16U; /**< 0x000A: Interrupt Enable bits */
132 uint32_t LVL; /**< 0x000C: Interrupt Level */
133 #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
134 uint32_t FLG : 16U; /**< 0x0012: Interrupt flags */
136 uint32_t BUFINIT : 1U; /**< 0x0010: Buffer initialization active flag */
140 uint32_t BUFINIT : 1U; /**< 0x0010: Buffer initialization active flag */
142 uint32_t FLG : 16U; /**< 0x0012: Interrupt flags */
144 uint32_t PCFUN; /**< 0x0014: Function Pin Enable */
145 uint32_t PCDIR; /**< 0x0018: Pin Direction */
146 uint32_t PCDIN; /**< 0x001C: Pin Input Latch */
147 uint32_t PCDOUT; /**< 0x0020: Pin Output Latch */
148 uint32_t PCSET; /**< 0x0024: Output Pin Set */
149 uint32_t PCCLR; /**< 0x0028: Output Pin Clr */
150 uint32_t PCPDR; /**< 0x002C: Open Drain Output Enable */
151 uint32_t PCDIS; /**< 0x0030: Pullup/Pulldown Disable */
152 uint32_t PCPSL; /**< 0x0034: Pullup/Pulldown Selection */
153 uint32_t DAT0; /**< 0x0038: Transmit Data */
154 uint32_t DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
155 uint32_t BUF; /**< 0x0040: Receive Buffer */
156 uint32_t EMU; /**< 0x0044: Emulation Receive Buffer */
157 uint32_t DELAY; /**< 0x0048: Delays */
158 uint32_t CSDEF; /**< 0x004C: Default Chip Select */
159 uint32_t FMT0; /**< 0x0050: Data Format 0 */
160 uint32_t FMT1; /**< 0x0054: Data Format 1 */
161 uint32_t FMT2; /**< 0x0058: Data Format 2 */
162 uint32_t FMT3; /**< 0x005C: Data Format 3 */
163 uint32_t INTVECT0; /**< 0x0060: Interrupt Vector 0 */
164 uint32_t INTVECT1; /**< 0x0064: Interrupt Vector 1 */
165 uint32_t SRSEL; /**< 0x0068: Slew Rate Select */
167 uint32_t PMCTRL; /**< 0x006C: Parallel Mode Control */
168 #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
169 uint32_t MIBSPIE : 16U; /**< 0x0072: MibSPI Enable */
170 uint32_t RAMACCESS : 16U; /**< 0x0070: RX Ram Write Access Enable */
172 uint32_t RAMACCESS : 16U; /**< 0x0070: RX Ram Write Access Enable */
173 uint32_t MIBSPIE : 16U; /**< 0x0072: MibSPI Enable */
176 uint32_t RESERVED[48U]; /**< 0x006C to 0x0130: Reserved */
177 uint32_t IOLPKTSTCR; /**< 0x0134: IO loopback */
181 /* SPI devices connected to SPI interface */
182 typedef struct spi_dev {
183 unsigned int cs; /* Combination of CS (+GPIO CS) necessary to enable the device */
184 unsigned char dfsel; /* Data word format */
185 unsigned char wdel; /* Enable the delay counter at the end of the current transaction */
186 unsigned char cshold; /* Chip select hold mode */
187 unsigned int dlen; /* Data len needed for one complete transfer */
191 typedef struct spi_tms570_drv {
193 spiBASE_compat_t *spi; /* Base Reg. for SPI device register array */
194 unsigned txcnt; /* No. of transfered bytes for msg_act */
195 unsigned rxcnt; /* No. of received bytes for msg_act */
196 spi_dev_t *spi_devs; /* Pointer to table holding information about SPI devices bound to the interface */
197 uint32_t transfer_ctrl; /* Transfer configuration -- upper 16 bits of SPIDAT1 register */
200 //extern spi_tms570_drv_t spi_tms570_ifcs[4];
201 //extern spi_dev_t spi_devs[];
202 int spi_tms570_init(void);
204 spi_drv_t *spi_find_drv(char *name, int number);
207 #endif /* _MYSPI_H_ */