8 #include "drv/fr_tms570.h"
9 #include "sys/ti_drv_fray.h"
12 Std_VersionInfoType Fr_versionInfo = {
13 .vendorID = 0x00000001,
14 .moduleID = 0x00000002,
15 .sw_major_version = 0,
16 .sw_minor_version = 1,
20 const uint32_t* Fr_ConfigParPtrs[FR_CIDX_CNT];
21 const Fr_ConfigType* Fr_Config;
22 Fr_POCStatusType Fr_POCStatus;
24 boolean_t Fr_Initialized = FALSE;
27 /** @fn wait_for_POC_ready(void)
28 * @brief Wait until POC is not busy
30 void Fr_wait_for_POC_ready() {
31 // Wait for PBSY bit to clear - POC not busy.
32 // 1: Signals that the POC is busy and cannot accept a command from the host. CMD(3-0) is locked against write accesses.
33 while(((frayREG->SUCC1_UN.SUCC1_UL) & 0x00000080) != 0);
37 * @brief Switch POC to config state from any other state
39 * After command to switch into config state is passed into CHI,
40 * the response is checked and if POC has reacted on the command,
41 * the function is waiting until POC is ready
43 * @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
45 Std_ReturnType Fr_POC_go_to_config() {
46 // write SUCC1 configuration
47 frayREG->SUCC1_UN.SUCC1_UL = 0x0F1FFB00 | CMD_CONFIG;
48 // Check if POC has accepted last command
49 if ((frayREG->SUCC1_UN.SUCC1_UL & 0xF) == 0x0)
51 // Wait for PBSY bit to clear - POC not busy
52 Fr_wait_for_POC_ready();
57 * @brief Copy cluster config parameters into FlexRay configuration registers.
59 * This function does not check values ranges. This is a responsibility of higher
60 * layers. Cluster configuration parameters are copied from data structure
61 * into right bit position in configuration registers.
63 * @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
65 void Fr_config_cluster_parameters(const Fr_TMS570LS_ClusterConfigType* clusterConfigPtr) {
66 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CSA_MSK , frayREG->SUCC1_UN.SUCC1_UL, clusterConfigPtr->gColdStartAttempts);
67 frayREG->GTUC9_UN.GTUC9_UL = __insval2mfld(GTUC9_APO_MSK , frayREG->GTUC9_UN.GTUC9_UL, clusterConfigPtr->gdActionPointOffset);
68 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_CASM_MSK, frayREG->PRTC1_UN.PRTC1_UL, clusterConfigPtr->gdCASRxLowMax);
69 frayREG->GTUC9_UN.GTUC9_UL = __insval2mfld(GTUC9_DSI_MSK , frayREG->GTUC9_UN.GTUC9_UL, clusterConfigPtr->gdDynamicSlotIdlePhase);
70 frayREG->GTUC8_UN.GTUC8_UL = __insval2mfld(GTUC8_MSL_MSK , frayREG->GTUC8_UN.GTUC8_UL, clusterConfigPtr->gdMinislot);
71 frayREG->GTUC9_UN.GTUC9_UL = __insval2mfld(GTUC9_MAPO_MSK, frayREG->GTUC9_UN.GTUC9_UL, clusterConfigPtr->gdMinislotActionPointOffset);
72 frayREG->GTUC7_UN.GTUC7_UL = __insval2mfld(GTUC7_SSL_MSK , frayREG->GTUC7_UN.GTUC7_UL, clusterConfigPtr->gdStaticSlot);
73 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_TSST_MSK, frayREG->PRTC1_UN.PRTC1_UL, clusterConfigPtr->gdTSSTransmitter);
74 frayREG->PRTC2_UN.PRTC2_UL = __insval2mfld(PRTC2_RXI_MSK , frayREG->PRTC2_UN.PRTC2_UL, clusterConfigPtr->gdWakeupSymbolRxIdle);
75 frayREG->PRTC2_UN.PRTC2_UL = __insval2mfld(PRTC2_RXL_MSK , frayREG->PRTC2_UN.PRTC2_UL, clusterConfigPtr->gdWakeupSymbolRxLow);
76 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_RXW_MSK , frayREG->PRTC1_UN.PRTC1_UL, clusterConfigPtr->gdWakeupSymbolRxWindow);
77 frayREG->PRTC2_UN.PRTC2_UL = __insval2mfld(PRTC2_TXI_MSK , frayREG->PRTC2_UN.PRTC2_UL, clusterConfigPtr->gdWakeupSymbolTxIdle);
78 frayREG->PRTC2_UN.PRTC2_UL = __insval2mfld(PRTC2_TXL_MSK , frayREG->PRTC2_UN.PRTC2_UL, clusterConfigPtr->gdWakeupSymbolTxLow);
79 frayREG->SUCC2_UN.SUCC2_UL = __insval2mfld(SUCC2_LTN_MSK , frayREG->SUCC2_UN.SUCC2_UL, clusterConfigPtr->gListenNoise);
80 frayREG->GTUC2_UN.GTUC2_UL = __insval2mfld(GTUC2_MPC_MSK , frayREG->GTUC2_UN.GTUC2_UL, clusterConfigPtr->gMacroPerCycle);
81 frayREG->SUCC3_UN.SUCC3_UL = __insval2mfld(SUCC3_WCF_MSK , frayREG->SUCC3_UN.SUCC3_UL, clusterConfigPtr->gMaxWithoutClockCorrectionFatal);
82 frayREG->SUCC3_UN.SUCC3_UL = __insval2mfld(SUCC3_WCP_MSK , frayREG->SUCC3_UN.SUCC3_UL, clusterConfigPtr->gMaxWithoutClockCorrectionPassive);
83 frayREG->GTUC8_UN.GTUC8_UL = __insval2mfld(GTUC8_NMS_MSK , frayREG->GTUC8_UN.GTUC8_UL, clusterConfigPtr->gNumberOfMinislots);
84 frayREG->GTUC7_UN.GTUC7_UL = __insval2mfld(GTUC7_NSS_MSK , frayREG->GTUC7_UN.GTUC7_UL, clusterConfigPtr->gNumberOfStaticSlots);
85 frayREG->GTUC4_UN.GTUC4_UL = __insval2mfld(GTUC4_OCS_MSK , frayREG->GTUC4_UN.GTUC4_UL, clusterConfigPtr->gOffsetCorrectionStart);
86 frayREG->MHDC_UN.MHDC_UL = __insval2mfld(MHDC_SFDL_MSK , frayREG->MHDC_UN.MHDC_UL , clusterConfigPtr->gPayloadLengthStatic);
87 frayREG->GTUC2_UN.GTUC2_UL = __insval2mfld(GTUC2_SNM_MSK , frayREG->GTUC2_UN.GTUC2_UL, clusterConfigPtr->gSyncNodeMax);
89 frayREG->GTUC4_UN.GTUC4_UL = __insval2mfld(GTUC4_NIT_MSK , frayREG->GTUC4_UN.GTUC4_UL, clusterConfigPtr->gdNIT);
90 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_BRP_MSK , frayREG->PRTC1_UN.PRTC1_UL, clusterConfigPtr->gdSampleClockPeriod);
91 frayREG->NEMC_UN.NEMC_UL = __insval2mfld(NEMC_NML_MSK , frayREG->NEMC_UN.NEMC_UL , clusterConfigPtr->gNetworkManagementVectorLength);
94 #define __notInRange(val, min, max) (((val) < (min)) || ((val) > (max)))
97 * @brief Check cluster configuration parameters.
99 * This function checks values of the cluster configuration parameters,
100 * if they are in ranges noted in FlexRay specification.
102 * @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
103 * @param [out] errCode Address where error flags will be stored.
104 * We have 26 parameters to check. Every one of them has assigned its bit in this flag.
105 * Error flags are defined as macros ERR_PARAM_nameOfParameter.
106 * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
108 Std_ReturnType Fr_check_cluster_parameters(const Fr_TMS570LS_ClusterConfigType* clusterConfigPtr, uint32_t* errCode) {
109 *errCode = ERR_PARAM_NO_ERROR;
111 if (__notInRange(clusterConfigPtr->gColdStartAttempts, 2, 31)) *errCode |= ERR_PARAM_gColdStartAttempts;
112 if (__notInRange(clusterConfigPtr->gdActionPointOffset, 1, 63)) *errCode |= ERR_PARAM_gdActionPointOffset;
113 if (__notInRange(clusterConfigPtr->gdCASRxLowMax, 67, 99)) *errCode |= ERR_PARAM_gdCASRxLowMax;
114 if (clusterConfigPtr->gdDynamicSlotIdlePhase > 2) *errCode |= ERR_PARAM_gdDynamicSlotIdlePhase;
115 if (__notInRange(clusterConfigPtr->gdMinislot, 2, 63)) *errCode |= ERR_PARAM_gdMinislot;
116 if (__notInRange(clusterConfigPtr->gdMinislotActionPointOffset,
117 1, 31)) *errCode |= ERR_PARAM_gdMinislotActionPointOffset;
118 if (__notInRange(clusterConfigPtr->gdStaticSlot, 4, 661)) *errCode |= ERR_PARAM_gdStaticSlot;
119 if (__notInRange(clusterConfigPtr->gdTSSTransmitter, 3, 15)) *errCode |= ERR_PARAM_gdTSSTransmitter;
120 if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxIdle, 14, 59)) *errCode |= ERR_PARAM_gdWakeupSymbolRxIdle;
121 if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxLow, 11, 59)) *errCode |= ERR_PARAM_gdWakeupSymbolRxLow;
122 if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxWindow,
123 76, 301)) *errCode |= ERR_PARAM_gdWakeupSymbolRxWindow;
124 if (__notInRange(clusterConfigPtr->gdWakeupSymbolTxIdle, 45, 180)) *errCode |= ERR_PARAM_gdWakeupSymbolTxIdle;
125 if (__notInRange(clusterConfigPtr->gdWakeupSymbolTxLow, 15, 60)) *errCode |= ERR_PARAM_gdWakeupSymbolTxLow;
126 if (__notInRange(clusterConfigPtr->gListenNoise, 2, 16)) *errCode |= ERR_PARAM_gListenNoise;
127 if (__notInRange(clusterConfigPtr->gMacroPerCycle, 10, 16000)) *errCode |= ERR_PARAM_gMacroPerCycle;
128 if (__notInRange(clusterConfigPtr->gMaxWithoutClockCorrectionFatal,
129 clusterConfigPtr->gMaxWithoutClockCorrectionPassive, 15)) *errCode |= ERR_PARAM_gMaxWithoutClockCorrectionFatal;
130 if (__notInRange(clusterConfigPtr->gMaxWithoutClockCorrectionPassive,
131 1, 15)) *errCode |= ERR_PARAM_gMaxWithoutClockCorrectionPassive;
132 if (clusterConfigPtr->gNumberOfMinislots > 7986) *errCode |= ERR_PARAM_gNumberOfMinislots;
133 if (__notInRange(clusterConfigPtr->gNumberOfStaticSlots,
134 2, cStaticSlotIDMax)) *errCode |= ERR_PARAM_gNumberOfStaticSlots;
135 if (__notInRange(clusterConfigPtr->gOffsetCorrectionStart,
136 9, 15999)) *errCode |= ERR_PARAM_gOffsetCorrectionStart;
137 if (clusterConfigPtr->gPayloadLengthStatic > cPayloadLengthMax) *errCode |= ERR_PARAM_gPayloadLengthStatic;
138 if (__notInRange(clusterConfigPtr->gSyncNodeMax, 2, cSyncNodeMax)) *errCode |= ERR_PARAM_gSyncNodeMax;
139 if (__notInRange(clusterConfigPtr->gdNIT, 2, 805)) *errCode |= ERR_PARAM_gdNIT;
140 if (clusterConfigPtr->gdSampleClockPeriod > 2) *errCode |= ERR_PARAM_gdSampleClockPeriod;
141 if (clusterConfigPtr->gNetworkManagementVectorLength > 12) *errCode |= ERR_PARAM_gNetworkManagementVectorLength;
143 return (*errCode == 0) ? E_OK : E_NOT_OK;
147 * @brief Copy node config parameters into FlexRay configuration registers.
149 * This function does not check values ranges. This is a responsibility of higher
150 * layers. Node configuration parameters are copied from data structure
151 * into right bit position in configuration registers.
153 * @param [in] nodeConfigPtr Address of structure with node configuration parameters
155 void Fr_config_node_parameters(const Fr_TMS570LS_NodeConfigType* nodeConfigPtr) {
156 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_HCSE_MSK, frayREG->SUCC1_UN.SUCC1_UL, nodeConfigPtr->pAllowHaltDueToClock);
157 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_PTA_MSK, frayREG->SUCC1_UN.SUCC1_UL, nodeConfigPtr->pAllowPassiveToActive);
158 if (nodeConfigPtr->pChannels == FR_CHANNEL_AB) {
159 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHA_MSK, frayREG->SUCC1_UN.SUCC1_UL, 1);
160 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHB_MSK, frayREG->SUCC1_UN.SUCC1_UL, 1);
163 else if (nodeConfigPtr->pChannels == FR_CHANNEL_A) {
164 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHA_MSK, frayREG->SUCC1_UN.SUCC1_UL, 1);
165 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHB_MSK, frayREG->SUCC1_UN.SUCC1_UL, 0);
168 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHA_MSK, frayREG->SUCC1_UN.SUCC1_UL, 0);
169 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHB_MSK, frayREG->SUCC1_UN.SUCC1_UL, 1);
171 frayREG->GTUC6_UN.GTUC6_UL = __insval2mfld(GTUC6_ASR_MSK , frayREG->GTUC6_UN.GTUC6_UL , nodeConfigPtr->pdAcceptedStartupRange);
172 frayREG->GTUC5_UN.GTUC5_UL = __insval2mfld(GTUC5_CDD_MSK , frayREG->GTUC5_UN.GTUC5_UL , nodeConfigPtr->pClusterDriftDamping);
173 frayREG->GTUC5_UN.GTUC5_UL = __insval2mfld(GTUC5_DCA_MSK , frayREG->GTUC5_UN.GTUC5_UL , nodeConfigPtr->pDelayCompensationA);
174 frayREG->GTUC5_UN.GTUC5_UL = __insval2mfld(GTUC5_DCB_MSK , frayREG->GTUC5_UN.GTUC5_UL , nodeConfigPtr->pDelayCompensationB);
175 frayREG->SUCC2_UN.SUCC2_UL = __insval2mfld(SUCC2_LT_MSK , frayREG->SUCC2_UN.SUCC2_UL , nodeConfigPtr->pdListenTimeout);
176 frayREG->GTUC6_UN.GTUC6_UL = __insval2mfld(GTUC6_MOD_MSK , frayREG->GTUC6_UN.GTUC6_UL , nodeConfigPtr->pdMaxDrift);
177 frayREG->GTUC11_UN.GTUC11_UL = __insval2mfld(GTUC11_EOC_MSK, frayREG->GTUC11_UN.GTUC11_UL, nodeConfigPtr->pExternOffsetCorrection);
178 frayREG->GTUC11_UN.GTUC11_UL = __insval2mfld(GTUC11_ERC_MSK, frayREG->GTUC11_UN.GTUC11_UL, nodeConfigPtr->pExternRateCorrection);
179 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_TXST_MSK, frayREG->SUCC1_UN.SUCC1_UL , nodeConfigPtr->pKeySlotUsedForStartup);
180 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_TXSY_MSK, frayREG->SUCC1_UN.SUCC1_UL , nodeConfigPtr->pKeySlotUsedForSync);
181 frayREG->MHDC_UN.MHDC_UL = __insval2mfld(MHDC_SLT_MSK , frayREG->MHDC_UN.MHDC_UL , nodeConfigPtr->pLatestTx);
182 frayREG->GTUC3_UN.GTUC3_UL = __insval2mfld(GTUC3_MIOA_MSK, frayREG->GTUC3_UN.GTUC3_UL , nodeConfigPtr->pMacroInitialOffsetA);
183 frayREG->GTUC3_UN.GTUC3_UL = __insval2mfld(GTUC3_MIOB_MSK, frayREG->GTUC3_UN.GTUC3_UL , nodeConfigPtr->pMacroInitialOffsetB);
184 frayREG->GTUC3_UN.GTUC3_UL = __insval2mfld(GTUC3_UIOA_MSK, frayREG->GTUC3_UN.GTUC3_UL , nodeConfigPtr->pMicroInitialOffsetA);
185 frayREG->GTUC3_UN.GTUC3_UL = __insval2mfld(GTUC3_UIOB_MSK, frayREG->GTUC3_UN.GTUC3_UL , nodeConfigPtr->pMicroInitialOffsetB);
186 frayREG->GTUC1_UN.GTUC1_UL = __insval2mfld(GTUC1_UT_MSK , frayREG->GTUC1_UN.GTUC1_UL , nodeConfigPtr->pMicroPerCycle);
187 frayREG->GTUC10_UN.GTUC10_UL = __insval2mfld(GTUC10_MOC_MSK, frayREG->GTUC10_UN.GTUC10_UL, nodeConfigPtr->pRateCorrectionOut);
188 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_TSM_MSK , frayREG->SUCC1_UN.SUCC1_UL , nodeConfigPtr->pSingleSlotEnabled);
189 if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_A) {
190 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_WUCS_MSK, frayREG->SUCC1_UN.SUCC1_UL, 0);
192 else if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_B) {
193 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_WUCS_MSK, frayREG->SUCC1_UN.SUCC1_UL, 1);
195 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_RWP_MSK, frayREG->PRTC1_UN.PRTC1_UL, nodeConfigPtr->pWakeupPattern);
196 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_BRP_MSK, frayREG->PRTC1_UN.PRTC1_UL, nodeConfigPtr->pSamplesPerMicrotick);
201 * @brief Check node configuration parameters.
203 * This function checks values of the node configuration parameters,
204 * if they are in ranges noted in FlexRay specification.
206 * @param [in] nodeConfigPtr Address of structure with node configuration parameters
207 * @param [out] errCode Address where error flags will be stored.
208 * We have 24 parameters to check. Every one of them has assigned its bit in this flag.
209 * Error flags are defined as macros ERR_PARAM_nameOfParameter.
210 * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
212 Std_ReturnType Fr_check_node_parameters(const Fr_TMS570LS_NodeConfigType* nodeConfigPtr, uint32_t* errCode) {
213 *errCode = ERR_PARAM_NO_ERROR;
215 if (nodeConfigPtr->pAllowPassiveToActive > 31) *errCode |= ERR_PARAM_pAllowPassiveToActive;
216 if (nodeConfigPtr->pChannels != FR_CHANNEL_A &&
217 nodeConfigPtr->pChannels != FR_CHANNEL_B &&
218 nodeConfigPtr->pChannels != FR_CHANNEL_AB ) *errCode |= ERR_PARAM_pChannels;
219 if (nodeConfigPtr->pdAcceptedStartupRange > 1875) *errCode |= ERR_PARAM_pdAcceptedStartupRange;
220 if (nodeConfigPtr->pClusterDriftDamping > 20) *errCode |= ERR_PARAM_pClusterDriftDamping;
221 if (nodeConfigPtr->pDelayCompensationA > 200) *errCode |= ERR_PARAM_pDelayCompensationA;
222 if (nodeConfigPtr->pDelayCompensationB > 200) *errCode |= ERR_PARAM_pDelayCompensationB;
223 if (__notInRange(nodeConfigPtr->pdListenTimeout, 1284, 1283846)) *errCode |= ERR_PARAM_pdListenTimeout;
224 if (__notInRange(nodeConfigPtr->pdMaxDrift, 2, 1923)) *errCode |= ERR_PARAM_pdMaxDrift;
225 if (nodeConfigPtr->pExternOffsetCorrection > 7) *errCode |= ERR_PARAM_pExternOffsetCorrection;
226 if (nodeConfigPtr->pExternRateCorrection > 7) *errCode |= ERR_PARAM_pExternRateCorrection;
227 if (nodeConfigPtr->pKeySlotUsedForStartup == TRUE &&
228 nodeConfigPtr->pKeySlotUsedForSync == FALSE) *errCode |= ERR_PARAM_pKeySlotUsedForSync
229 | ERR_PARAM_pKeySlotUsedForStartup; // If pKeySlotUsedForStartup is set to true then pKeySlotUsedForSync must also be set to true.
230 if (nodeConfigPtr->pLatestTx > 7980) *errCode |= ERR_PARAM_pLatestTx;
231 if (__notInRange(nodeConfigPtr->pMacroInitialOffsetA, 2, 68)) *errCode |= ERR_PARAM_pMacroInitialOffsetA;
232 if (__notInRange(nodeConfigPtr->pMacroInitialOffsetB, 2, 68)) *errCode |= ERR_PARAM_pMacroInitialOffsetB;
233 if (nodeConfigPtr->pMicroInitialOffsetA > 239) *errCode |= ERR_PARAM_pMicroInitialOffsetA;
234 if (nodeConfigPtr->pMicroInitialOffsetB > 239) *errCode |= ERR_PARAM_pMicroInitialOffsetB;
235 if (__notInRange(nodeConfigPtr->pMicroPerCycle, 640, 640000)) *errCode |= ERR_PARAM_pMicroPerCycle;
236 if (__notInRange(nodeConfigPtr->pRateCorrectionOut, 2, 1923)) *errCode |= ERR_PARAM_pRateCorrectionOut;
237 if (nodeConfigPtr->pWakeupChannel != FR_CHANNEL_A &&
238 nodeConfigPtr->pWakeupChannel != FR_CHANNEL_B ) *errCode |= ERR_PARAM_pWakeupChannel;
239 if (__notInRange(nodeConfigPtr->pWakeupPattern, 2, 63)) *errCode |= ERR_PARAM_pWakeupPattern;
240 if (nodeConfigPtr->pSamplesPerMicrotick != 1 &&
241 nodeConfigPtr->pSamplesPerMicrotick != 2 &&
242 nodeConfigPtr->pSamplesPerMicrotick != 4 ) *errCode |= ERR_PARAM_pSamplesPerMicrotick;
244 return (*errCode == 0) ? E_OK : E_NOT_OK;
248 * @brief Check Configuration parameters for all buffers
250 * This function checks configuration parameters.
252 * - All of them have to be RX
253 * - All of them have the same payload <= 256B
254 * - Same channels active
255 * - Same cycle counter filter
258 * - not reconfigurable
259 * - frame ID can be 0, which means that all messages not received by others buffers are received in FIFO.
260 * For dynamic segment buffers and static segment buffers:
261 * - frame ID must not be 0
263 * The sum of all configured payloads must be <= 8KB.
265 * @param [in] statBufCfgPtr Address of structure with static buffers configuration parameters
266 * @param [in] dynBufCfgPtr Address of structure with dynamic buffers configuration parameters
267 * @param [in] fifoBufCfgPtr Address of structure with fifo buffers configuration parameters
268 * @param [in] statBufCnt Number of static buffers to be configured
269 * @param [in] dynBufCnt Number of dynamic buffers to be configured
270 * @param [in] fifoBufCnt Number of fifo buffers to be configured
271 * @param [out] errCode Address where error flags will be stored.
272 * Flags are defined as ERR_PARAM_BUF.....
273 * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
275 Std_ReturnType Fr_check_buffer_parameters(const Fr_TMS570LS_BufferConfigType* statBufCfgPtr, const Fr_TMS570LS_BufferConfigType* dynBufCfgPtr, const Fr_TMS570LS_BufferConfigType* fifoBufCfgPtr,
276 uint8_t statBufCnt, uint8_t dynBufCnt, uint8_t fifoBufCnt, uint32_t* errCode) {
277 uint32_t payloadTotal = 0;
278 *errCode = ERR_PARAM_NO_ERROR;
280 Fr_ChannelType fifoChannels;
281 uint8_t fifoCycleCounterFiltering;
284 /* Check FIFO buffer parameters */
285 fifoPayload = fifoBufCfgPtr[0].maxPayload;
286 fifoChannels = fifoBufCfgPtr[0].channel;
287 fifoCycleCounterFiltering = fifoBufCfgPtr[0].cycleCounterFiltering;
288 if (fifoBufCnt != 0 && fifoPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFFIFO_PAYLOAD_HIGH;
289 for (i = 0; i < fifoBufCnt; i++) {
290 if (fifoBufCfgPtr[i].isTx == TRUE) *errCode |= ERR_PARAM_BUFFIFO_NOT_RX;
291 if (fifoBufCfgPtr[i].maxPayload != fifoPayload) *errCode |= ERR_PARAM_BUFFIFO_PAYLOAD_DIFFERS;
292 if (fifoBufCfgPtr[i].channel != fifoChannels) *errCode |= ERR_PARAM_BUFFIFO_CHANNEL_DIFFERS;
293 if (fifoBufCfgPtr[i].cycleCounterFiltering != fifoCycleCounterFiltering) *errCode |= ERR_PARAM_BUFFIFO_CCFILTER_DIFFERS;
294 payloadTotal += fifoBufCfgPtr[i].maxPayload;
297 for (i = 0; i < dynBufCnt; i++) {
298 if (dynBufCfgPtr[i].slotId == 0) *errCode |= ERR_PARAM_BUFDYN_FRAMEID_INVALID;
299 if (dynBufCfgPtr[i].maxPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFDYN_PAYLOAD_HIGH;
300 payloadTotal += dynBufCfgPtr[i].maxPayload;
303 for (i = 0; i < statBufCnt; i++) {
304 if (statBufCfgPtr[i].slotId == 0) *errCode |= ERR_PARAM_BUFSTAT_FRAMEID_INVALID;
305 if (statBufCfgPtr[i].maxPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFSTAT_PAYLOAD_HIGH;
306 payloadTotal += statBufCfgPtr[i].maxPayload;
309 if (payloadTotal > 8192/2) *errCode |= ERR_PARAM_BUF_TOTAL_PAYLOAD_HIGH;
311 return (*errCode == 0) ? E_OK : E_NOT_OK;
315 * @brief Compute and set message RAM config parameters into FlexRay configuration registers.
317 * This function does not check values ranges. This is a responsibility of other functions.
318 * Message RAM configuration parameters are computed from data in the structure and
319 * written into right bit position in configuration registers.
321 * @param [in] msgRAMConfigPtr Address of structure with message RAM configuration parameters
323 void Fr_config_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig* msgRAMConfigPtr) {
324 /* If dynSegmentBufferCount is not 0 then first dynamic buffer = statSegmentBufferCount.
325 * If dynSegmentBufferCount is 0 then first dynamic buffer is 0x80 (see TMS570LS31x documentation)
327 if (msgRAMConfigPtr->dynSegmentBufferCount == 0) {
328 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_FDB_MSK, frayREG->MRC_UN.MRC_UL, 0x80);
331 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_FDB_MSK, frayREG->MRC_UN.MRC_UL, msgRAMConfigPtr->statSegmentBufferCount);
333 /* If fifoBufferCount is not 0 then first fifo buffer = statSegmentBufferCount + dynSegmentBufferCount
334 * If fifoBufferCount is 0 then first fifo buffer is 0x80 (see TMS570LS31x documentation)
336 if (msgRAMConfigPtr->fifoBufferCount == 0) {
337 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_FFB_MSK, frayREG->MRC_UN.MRC_UL, 0x80);
340 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_FFB_MSK, frayREG->MRC_UN.MRC_UL, msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount);
342 /* Last configured buffer = statSegmentBufferCount + dynSegmentBufferCount + fifoBufferCount - 1 */
343 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_LCB_MSK, frayREG->MRC_UN.MRC_UL, msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount + msgRAMConfigPtr->fifoBufferCount - 1);
345 /* Secure buffers setting */
346 if (msgRAMConfigPtr->secureBuffers == FR_SB_RECONFIG_ENABLED) {
347 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SEC_MSK, frayREG->MRC_UN.MRC_UL, 0);
349 else if (msgRAMConfigPtr->secureBuffers == FR_SB_STAT_REC_DISABLED_STAT_TR_DISABLED) {
350 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SEC_MSK, frayREG->MRC_UN.MRC_UL, 1);
352 else if (msgRAMConfigPtr->secureBuffers == FR_SB_ALL_REC_DISABLED) {
353 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SEC_MSK, frayREG->MRC_UN.MRC_UL, 2);
356 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SEC_MSK, frayREG->MRC_UN.MRC_UL, 3);
359 /* Sync frame payload multiplex setting */
360 if (msgRAMConfigPtr->syncFramePayloadMultiplexEnabled == TRUE) {
361 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SPLM_MSK, frayREG->MRC_UN.MRC_UL, 1);
364 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SPLM_MSK, frayREG->MRC_UN.MRC_UL, 0);
368 #define __notInRange(val, min, max) (((val) < (min)) || ((val) > (max)))
371 * @brief Check message RAM configuration parameters.
373 * This function checks values of the message RAM configuration parameters.
374 * FlexRay implementation in TMS570 can have up to 128 buffers configured, so
375 * the sum of all values buffer count must not exceed this ceiling.
378 * @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
379 * @param [out] errCode Address where error flags will be stored.
380 * Error flags are defined as macros ERR_PARAM_nameOfParameter.
381 * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
383 Std_ReturnType Fr_check_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig* msgRAMConfigPtr, uint32_t* errCode) {
384 *errCode = ERR_PARAM_NO_ERROR;
386 if (__notInRange(msgRAMConfigPtr->statSegmentBufferCount, 1, 127)) *errCode |= ERR_PARAM_statSegmentBufferCount;
387 if (msgRAMConfigPtr->dynSegmentBufferCount >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_dynSegmentBufferCount;
388 if (msgRAMConfigPtr->fifoBufferCount >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_fifoBufferCount;
389 if ((msgRAMConfigPtr->statSegmentBufferCount +
390 msgRAMConfigPtr->dynSegmentBufferCount +
391 msgRAMConfigPtr->fifoBufferCount) >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_maxBuffLimit;
393 return (*errCode == 0) ? E_OK : E_NOT_OK;
396 void Fr_Init(const Fr_ConfigType* Fr_ConfigPtr) {
398 if (Fr_ConfigPtr == NULL) {
402 /* Save pointers for parameters indexed by CIDX indexes
403 * This array representation is used by Fr_ReadCCConfig function.
404 * Parameter thet are not configurable in tms570 FlexRay implementation
407 Fr_ConfigParPtrs[FR_CIDX_GDCYCLE] = NULL;
408 Fr_ConfigParPtrs[FR_CIDX_PMICROPERCYCLE] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pMicroPerCycle;
409 Fr_ConfigParPtrs[FR_CIDX_PDLISTENTIMEOUT] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gMacroPerCycle;
410 Fr_ConfigParPtrs[FR_CIDX_GDMACROTICK] = NULL;
411 Fr_ConfigParPtrs[FR_CIDX_GNUMBEROFMINISLOTS] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gNumberOfMinislots;
412 Fr_ConfigParPtrs[FR_CIDX_GNUMBEROFSTATICSLOTS] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gNumberOfStaticSlots;
413 Fr_ConfigParPtrs[FR_CIDX_GDNIT] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdNIT;
414 Fr_ConfigParPtrs[FR_CIDX_GDSTATICSLOT] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdNIT;
415 Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPRXWINDOW] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdWakeupSymbolRxWindow;
416 Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTID] = NULL;
417 Fr_ConfigParPtrs[FR_CIDX_PLATESTTX] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pLatestTx;
418 Fr_ConfigParPtrs[FR_CIDX_POFFSETCORRECTIONOUT] = NULL;
419 Fr_ConfigParPtrs[FR_CIDX_POFFSETCORRECTIONSTART] = NULL;
420 Fr_ConfigParPtrs[FR_CIDX_PRATECORRECTIONOUT] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pRateCorrectionOut;
421 Fr_ConfigParPtrs[FR_CIDX_PSECONDKEYSLOTID] = NULL;
422 Fr_ConfigParPtrs[FR_CIDX_PDACCEPTEDSTARTUPRANGE] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pdAcceptedStartupRange;
423 Fr_ConfigParPtrs[FR_CIDX_GCOLDSTARTATTEMPTS] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gColdStartAttempts;
424 Fr_ConfigParPtrs[FR_CIDX_GCYCLECOUNTMAX] = NULL;
425 Fr_ConfigParPtrs[FR_CIDX_GLISTENNOISE] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gListenNoise;
426 Fr_ConfigParPtrs[FR_CIDX_GMAXWITHOUTCLOCKCORRECTFATAL] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gMaxWithoutClockCorrectionFatal;
427 Fr_ConfigParPtrs[FR_CIDX_GMAXWITHOUTCLOCKCORRECTPASSIVE] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gMaxWithoutClockCorrectionPassive;
428 Fr_ConfigParPtrs[FR_CIDX_GNETWORKMANAGEMENTVECTORLENGTH] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gNetworkManagementVectorLength;
429 Fr_ConfigParPtrs[FR_CIDX_GPAYLOADLENGTHSTATIC] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gPayloadLengthStatic;
430 Fr_ConfigParPtrs[FR_CIDX_GSYNCFRAMEIDCOUNTMAX] = NULL;
431 Fr_ConfigParPtrs[FR_CIDX_GDACTIONPOINTOFFSET] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdActionPointOffset;
432 Fr_ConfigParPtrs[FR_CIDX_GDBIT] = NULL;
433 Fr_ConfigParPtrs[FR_CIDX_GDCASRXLOWMAX] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdCASRxLowMax;
434 Fr_ConfigParPtrs[FR_CIDX_GDDYNAMICSLOTIDLEPHASE] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdDynamicSlotIdlePhase;
435 Fr_ConfigParPtrs[FR_CIDX_GDMINISLOTACTIONPOINTOFFSET] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdMinislotActionPointOffset;
436 Fr_ConfigParPtrs[FR_CIDX_GDMINISLOT] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdMinislot;
437 Fr_ConfigParPtrs[FR_CIDX_GDSAMPLECLOCKPERIOD] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdSampleClockPeriod;
438 Fr_ConfigParPtrs[FR_CIDX_GDSYMBOLWINDOW] = NULL;
439 Fr_ConfigParPtrs[FR_CIDX_GDSYMBOLWINDOWACTIONPOINTOFFSET] = NULL;
440 Fr_ConfigParPtrs[FR_CIDX_GDTSSTRANSMITTER] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdTSSTransmitter;
441 Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPRXIDLE] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdWakeupSymbolRxIdle;
442 Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPRXLOW] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdWakeupSymbolRxLow;
443 Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPTXACTIVE] = NULL;
444 Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPTXIDLE] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdWakeupSymbolTxIdle;
445 Fr_ConfigParPtrs[FR_CIDX_PALLOWPASSIVETOACTIVE] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pAllowPassiveToActive;
446 Fr_ConfigParPtrs[FR_CIDX_PCHANNELS] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pChannels;
447 Fr_ConfigParPtrs[FR_CIDX_PCLUSTERDRIFTDAMPING] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pClusterDriftDamping;
448 Fr_ConfigParPtrs[FR_CIDX_PDECODINGCORRECTION] = NULL;
449 Fr_ConfigParPtrs[FR_CIDX_PDELAYCOMPENSATIONA] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pDelayCompensationA;
450 Fr_ConfigParPtrs[FR_CIDX_PDELAYCOMPENSATIONB] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pDelayCompensationB;
451 Fr_ConfigParPtrs[FR_CIDX_PMACROINITIALOFFSETA] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pMacroInitialOffsetA;
452 Fr_ConfigParPtrs[FR_CIDX_PMACROINITIALOFFSETB] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pMacroInitialOffsetB;
453 Fr_ConfigParPtrs[FR_CIDX_PMICROINITIALOFFSETA] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pMicroInitialOffsetA;
454 Fr_ConfigParPtrs[FR_CIDX_PMICROINITIALOFFSETB] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pMicroInitialOffsetB;
455 Fr_ConfigParPtrs[FR_CIDX_PPAYLOADLENGTHDYNMAX] = NULL;
456 Fr_ConfigParPtrs[FR_CIDX_PSAMPLESPERMICROTICK] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pSamplesPerMicrotick;
457 Fr_ConfigParPtrs[FR_CIDX_PWAKEUPCHANNEL] =(const uint32_t*) &Fr_ConfigPtr->nodeConfiguration.pWakeupChannel;
458 Fr_ConfigParPtrs[FR_CIDX_PWAKEUPPATTERN] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pWakeupPattern;
459 Fr_ConfigParPtrs[FR_CIDX_PDMICROTICK] = NULL;
460 Fr_ConfigParPtrs[FR_CIDX_GDIGNOREAFTERTX] = NULL;
461 Fr_ConfigParPtrs[FR_CIDX_PALLOWHALTDUETOCLOCK] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pAllowHaltDueToClock;
462 Fr_ConfigParPtrs[FR_CIDX_PEXTERNALSYNC] = NULL;
463 Fr_ConfigParPtrs[FR_CIDX_PFALLBACKINTERNAL] = NULL;
464 Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTONLYENABLED] = NULL;
465 Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSTARTUP] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pKeySlotUsedForStartup;
466 Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSYNC] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pKeySlotUsedForSync;
467 Fr_ConfigParPtrs[FR_CIDX_PNMVECTOREARLYUPDATE] = NULL;
468 Fr_ConfigParPtrs[FR_CIDX_PTWOKEYSLOTMODE] = NULL;
470 /* Store whole configuration address
471 * This structured representation is used by other function in API.
473 Fr_Config = Fr_ConfigPtr;
475 /* Set some default POC state values */
476 Fr_POCStatus.WakeupStatus = FR_WAKEUP_UNDEFINED;
477 Fr_POCStatus.State = FR_POCSTATE_DEFAULT_CONFIG;
478 Fr_POCStatus.StartupState = FR_STARTUP_UNDEFINED;
479 Fr_POCStatus.SlotMode = FR_SLOTMODE_ALL;
480 Fr_POCStatus.Freeze = FALSE;
481 Fr_POCStatus.ErrorMode = FR_ERRORMODE_ACTIVE;
482 Fr_POCStatus.ColdstartNoise = FALSE;
483 Fr_POCStatus.CHIReadyRequest = FALSE;
484 Fr_POCStatus.CHIHaltRequest = FALSE;
487 Fr_Initialized = TRUE;
491 Std_ReturnType Fr_ControllerInit(uint8_t Fr_CtrlIdx) {
492 uint32_t errCode = ERR_PARAM_NO_ERROR;
493 /* Switch CC into ‘POC:config’ (from any other POCState) */
494 if (Fr_POC_go_to_config() == E_NOT_OK) {
498 /* Configure all FlexRay cluster and node parameters */
499 if (Fr_check_cluster_parameters(&Fr_Config->clusterConfiguration, &errCode) == E_NOT_OK) {
500 return E_NOT_OK | errCode | FR_INIT_ERR_CLUSTER_CONFIG;
502 if (Fr_check_node_parameters(&Fr_Config->nodeConfiguration, &errCode) == E_NOT_OK) {
503 return E_NOT_OK | errCode | FR_INIT_ERR_NODE_CONFIG;
505 Fr_config_cluster_parameters(&Fr_Config->clusterConfiguration);
506 Fr_config_node_parameters(&Fr_Config->nodeConfiguration);
508 /* Configure all transmit/receive resources */
512 //The function Fr_ControllerInit shall ensure that no transmission requests are pending
514 //The function Fr_ControllerInit shall ensure that no reception indications are pending.
516 //The function Fr_ControllerInit shall ensure that no interrupts are pending.
518 //The function Fr_ControllerInit shall ensure that all timers are disabled.
520 //The function Fr_ControllerInit shall disable all LPdus which are dynamically reconfigurable
522 /*If the function Fr_ControllerInit detects errors while testing the
523 CC (CC test), then it shall repeat the test procedure a configurable number
524 (FrCtrlTestCount) of times. If all tests fail, then it calls Dem_ReportErrorStatus
525 (FrDemCtrlTestResultRef,
526 DEM_EVENT_STATUS_FAILED)
530 The CC test as described in SWS_Fr_00147 shall verify (read
531 back and compare to reference values held in the configuration) that the node and
532 cluster FlexRay parameters were written properly into the FlexRay CC.
536 Std_ReturnType Fr_StartCommunication(uint8_t Fr_CtrlIdx) {
540 Std_ReturnType Fr_AllowColdstart(uint8_t Fr_CtrlIdx) {
544 Std_ReturnType Fr_AllSlots(uint8_t Fr_CtrlIdx) {
548 Std_ReturnType Fr_HaltCommunication(uint8_t Fr_CtrlIdx) {
552 Std_ReturnType Fr_AbortCommunication(uint8_t Fr_CtrlIdx) {
556 Std_ReturnType Fr_SendWUP(uint8_t Fr_CtrlIdx) {
560 Std_ReturnType Fr_SetWakeupChannel(uint8_t Fr_CtrlIdx, Fr_ChannelType Fr_ChnlIdx) {
564 Std_ReturnType Fr_GetPOCStatus(uint8_t Fr_CtrlIdx, Fr_POCStatusType* Fr_POCStatusPtr) {
568 Std_ReturnType Fr_TransmitTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, const uint8_t* Fr_LSduPtr, uint8_t Fr_LSduLength) {
572 Std_ReturnType Fr_CancelTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx) {
576 Std_ReturnType Fr_ReceiveRxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint8_t* Fr_LSduPtr, Fr_RxLPduStatusType* Fr_LPduStatusPtr, uint8_t* Fr_LSduLengthPtr) {
580 Std_ReturnType Fr_CheckTxLPduStatus(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, Fr_TxLPduStatusType* Fr_TxLPduStatusPtr) {
584 Std_ReturnType Fr_PrepareLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx) {
588 Std_ReturnType Fr_ReconfigLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint16_t Fr_FrameId, Fr_ChannelType Fr_ChnlIdx, uint8_t Fr_CycleRepetition, uint8_t Fr_CycleOffset, uint8_t Fr_PayloadLength, uint16_t Fr_HeaderCRC) {
592 Std_ReturnType Fr_DisableLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx) {
596 Std_ReturnType Fr_GetGlobalTime(uint8_t Fr_CtrlIdx, uint8_t* Fr_CyclePtr, uint16_t* Fr_MacroTickPtr) {
600 Std_ReturnType Fr_GetNmVector(uint8_t Fr_CtrlIdx, uint8_t* Fr_NmVectorPtr) {
604 Std_ReturnType Fr_GetNumOfStartupFrames(uint8_t Fr_CtrlIdx, uint8_t* Fr_NumOfStartupFramesPtr) {
608 Std_ReturnType Fr_GetChannelStatus(uint8_t Fr_CtrlIdx, uint16_t* Fr_ChannelAStatusPtr, uint16_t* Fr_ChannelBStatusPtr) {
612 Std_ReturnType Fr_GetClockCorrection(uint8_t Fr_CtrlIdx, int16_t* Fr_RateCorrectionPtr, int32_t* Fr_OffsetCorrectionPtr) {
616 Std_ReturnType Fr_GetSyncFrameList(uint8_t Fr_CtrlIdx, uint8_t Fr_ListSize, uint16_t* Fr_ChannelAEvenListPtr, uint16_t* Fr_ChannelBEvenListPtr, uint16_t* Fr_ChannelAOddListPtr, uint16_t* Fr_ChannelBOddListPtr) {
620 Std_ReturnType Fr_GetWakeupRxStatus(uint8_t Fr_CtrlIdx, uint8_t* Fr_WakeupRxStatusPtr) {
624 Std_ReturnType Fr_SetAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, uint8_t Fr_Cycle, uint16_t Fr_Offset) {
628 Std_ReturnType Fr_CancelAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
632 Std_ReturnType Fr_EnableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
637 Std_ReturnType Fr_AckAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
641 Std_ReturnType Fr_DisableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
645 Std_ReturnType Fr_GetAbsoluteTimerIRQStatus(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, boolean_t* Fr_IRQStatusPtr) {
649 void Fr_GetVersionInfo(Std_VersionInfoType* VersioninfoPtr) {
651 if (VersioninfoPtr == NULL) {
655 VersioninfoPtr->vendorID = Fr_versionInfo.vendorID;
656 VersioninfoPtr->moduleID = Fr_versionInfo.moduleID;
657 VersioninfoPtr->sw_major_version = Fr_versionInfo.sw_major_version;
658 VersioninfoPtr->sw_minor_version= Fr_versionInfo.sw_minor_version;
659 VersioninfoPtr->sw_patch_version= Fr_versionInfo.sw_patch_version;
662 Std_ReturnType Fr_ReadCCConfig( uint8_t Fr_CtrlIdx, uint8_t Fr_ConfigParamIdx, uint32_t* Fr_ConfigParamValuePtr) {
664 if (Fr_CtrlIdx != 0) {
667 if (Fr_ConfigParamIdx >= FR_CIDX_CNT) {
670 if (Fr_ConfigParamValuePtr >= NULL) {
673 if (Fr_Initialized != TRUE) {
678 Fr_ConfigParamValuePtr = (uint32_t*)Fr_ConfigParPtrs[Fr_ConfigParamIdx];