1 /* Copyright (C) 2013 Czech Technical University in Prague
4 * - Carlos Jenkins <carlos@jenkins.co.cr>
6 * This document contains proprietary information belonging to Czech
7 * Technical University in Prague. Passing on and copying of this
8 * document, and communication of its contents is not permitted
9 * without prior written authorization.
13 * Digital Input RPP API implementation file.
17 * RPP API documentation.
23 #if rppCONFIG_DRV == 1
27 static boolean_t initialized = FALSE;
35 #if rppCONFIG_DRV == 1
45 int8_t rpp_din_ref(uint16_t ref_a, uint16_t ref_b)
47 if((ref_a > 4095) || (ref_b > 4095)) {
51 #if rppCONFIG_DRV == 1
52 drv_din_ref(ref_a, ref_b);
58 // Check for configuration changes to avoid SPI overhead
59 static boolean_t config_changed = FALSE;
61 // All cached values are 16 bits in the form [SG7,...,SG0][SP7,...,SP0]
62 static uint16_t pull_cache = 0x0; /* 0 - pull-down, 1 - pull-up */
63 static uint16_t active_cache = 0x0; /* 0 - tri-state, 1 - active */
64 static uint16_t can_wake_cache = 0x0;
66 static boolean_t check_pin_busy(uint8_t pin) {
67 if (rpp_irc1_enabled && (pin == 10 || pin == 11))
69 if (rpp_irc2_enabled && (pin == 14 || pin == 15))
74 int8_t rpp_din_setup(uint8_t pin, boolean_t pull_up,
75 boolean_t active, boolean_t can_wake)
82 // Check programmable feature
83 if(!pull_up && (pin > 7)) {
87 // Check blockade of specific pins
88 if (check_pin_busy(pin))
93 bit_set(pull_cache, pin);
95 bit_clear(pull_cache, pin);
99 bit_set(active_cache, pin);
101 bit_clear(active_cache, pin);
105 bit_set(can_wake_cache, pin);
107 bit_clear(can_wake_cache, pin);
110 config_changed = TRUE;
115 static uint16_t in_cache = 0x0;
117 int8_t rpp_din_get(uint8_t pin)
124 // Check blockade of specific pins
125 if (check_pin_busy(pin))
129 if(is_bit_set(in_cache, pin)) {
135 int8_t rpp_din_get_tr(uint8_t pin)
138 if(pin < 8 || pin > 15) {
142 // Check blockade of specific pins
143 if (check_pin_busy(pin))
147 #if rppCONFIG_DRV == 1
148 if (drv_din_get_varthr(pin) == 1) {
157 static uint16_t diag_cache = 0x0;
159 int8_t rpp_din_diag(uint8_t pin)
166 // Check blockade of specific pins
167 if (check_pin_busy(pin))
171 if(is_bit_set(diag_cache, pin)) {
178 * pouzivat din_mod s pouzivanim enumu
180 int8_t rpp_din_update()
182 #if rppCONFIG_DRV == 1
189 din_set_reg(DIN_RESET_CMD, 0, 0);
190 //rpp_sci_printf("din_reset()\r\n");
193 // In DRV logic is inverted:
194 // DRV: 1 - set pin as switch-to-battery. RPP: 0 - pull-down.
195 // DRV: 0 - set pin as switch-to-ground. RPP: 1 - pull-up.
196 sp = (~pull_cache) & 0xFF;
197 din_set_reg(DIN_SETTINGS_CMD, 0xffff, sp);
198 //rpp_sci_printf("din_set_pr(%X)\r\n", sp);
200 // Set state type, active or tri-stated.
201 // In DRV logic is inverted:
202 // DRV: 1 - tri-state. RPP: 0 - tri-state.
203 // DRV: 0 - active. RPP: 1 - active.
204 sp = ((~active_cache) ) & 0xFF;
205 sg = ((~active_cache) >> 8) & 0xFF;
206 din_set_reg(DIN_TRI_STATE_CMD_YES, 0xffff, sp);
207 din_set_reg(DIN_TRI_STATE_CMD_NO, 0xffff, sg);
208 //rpp_sci_printf("din_set_stat(%X, %X)\r\n", sp, sg);
210 // Set wake / interrupt.
211 // IN DRV logic is not inverted.
212 // DRV: 1 - can wake. RPP: 1 - can wake.
213 // DRV: 0 - interrupt disabled. RPP: 0 - interrupt disabled.
214 sp = (can_wake_cache ) & 0xFF;
215 sg = (can_wake_cache >> 8) & 0xFF;
217 din_set_reg(DIN_WAKE_UP_CMD_ENB, 0xffff, sp);
218 din_set_reg(DIN_WAKE_UP_CMD_DIS, 0xffff, sg);
219 //rpp_sci_printf("din_set_int(%X, %X)\r\n", sp, sg);
221 // Mark configuration as commited
222 config_changed = FALSE;
225 // Update cached values
226 din_set_reg(DIN_SWITCH_STATUS_CMD, 0, 0);
227 in_cache = din_get_val_word();
229 // FIXME: Implement. Dummy assign for now.
230 diag_cache = in_cache;
232 if(diag_cache != in_cache) {
236 UNUSED(config_changed);