2 * @brief PINMUX Driver Implementation File
8 /* (c) Texas Instruments 2009-2012, All rights reserved. */
12 #include "sys/sys_pinmux.h"
14 #define PINMUX_SET(REG, BALLID, MUX) \
15 pinMuxReg->PINMUX##REG = (pinMuxReg->PINMUX##REG & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX)
17 #define PINMUX_GATE_EMIF_CLK_ENABLE \
18 pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GATE_EMIF_CLK_MASK) | PINMUX_GATE_EMIF_CLK
20 #define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \
21 (pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state))
23 #define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \
24 pinMuxReg->PINMUX30 = (pinMuxReg->PINMUX30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)
26 #define PINMUX_ETHERNET_SELECT(interface) \
27 pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)
31 /* Enable Pin Muxing */
32 kickerReg->KICKER0 = 0x83E70B13;
33 kickerReg->KICKER1 = 0x95A4F1E0;
35 pinMuxReg->PINMUX0 = PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0;
37 pinMuxReg->PINMUX1 = PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_EMIF_DATA_4 | PINMUX_BALL_F5_EMIF_DATA_5;
39 pinMuxReg->PINMUX2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_EMIF_DATA_6 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
41 pinMuxReg->PINMUX3 = PINMUX_BALL_K5_EMIF_DATA_7 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_EMIF_DATA_8;
43 pinMuxReg->PINMUX4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_EMIF_DATA_9 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
45 pinMuxReg->PINMUX5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_EMIF_DATA_10;
47 pinMuxReg->PINMUX6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_EMIF_DATA_11 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_EMIF_DATA_12;
49 pinMuxReg->PINMUX7 = PINMUX_BALL_R6_EMIF_DATA_13 | PINMUX_BALL_W3_SCIRX | PINMUX_BALL_R7_EMIF_DATA_14;
51 pinMuxReg->PINMUX8 = PINMUX_BALL_N2_SCITX | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_EMIF_DATA_15;
53 pinMuxReg->PINMUX9 = ((~(pinMuxReg->PINMUX9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_V10_GIOB_2;
55 pinMuxReg->PINMUX10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_EMIF_DATA_3 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_EMIF_DATA_2;
57 pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_HET1_24;
59 pinMuxReg->PINMUX12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_EMIF_DATA_0 | PINMUX_BALL_H18_MIBSPI5NENA;
61 pinMuxReg->PINMUX13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
63 pinMuxReg->PINMUX14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
65 pinMuxReg->PINMUX15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
67 pinMuxReg->PINMUX16 = PINMUX_BALL_E13_EMIF_BA_0 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_EMIF_nOE;
69 pinMuxReg->PINMUX17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_EMIF_nDQM_1 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_EMIF_ADDR_5;
71 pinMuxReg->PINMUX18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
73 pinMuxReg->PINMUX19 = PINMUX_BALL_E8_EMIF_ADDR_4 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_E7_EMIF_ADDR_3;
75 pinMuxReg->PINMUX20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_C9_EMIF_ADDR_11;
77 pinMuxReg->PINMUX21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
79 pinMuxReg->PINMUX22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_EMIF_ADDR_2;
81 pinMuxReg->PINMUX23 = ((~(pinMuxReg->PINMUX5 >> 1U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMUX5 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMUX5 >> 17U) & 0x00000001U ) << 24U) | PINMUX_BALL_C6_EMIF_ADDR_8;
83 pinMuxReg->PINMUX24 = ((~(pinMuxReg->PINMUX4 >> 17U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMUX4 >> 25U) & 0x00000001U ) << 8U) | PINMUX_BALL_A13_HET1_17 | PINMUX_BALL_B13_HET1_19;
85 pinMuxReg->PINMUX25 = PINMUX_BALL_H4_HET1_21 | PINMUX_BALL_J4_HET1_23 | PINMUX_BALL_M3_HET1_25 | PINMUX_BALL_B2_HET1_27;
87 pinMuxReg->PINMUX26 = PINMUX_BALL_A3_HET1_29 | PINMUX_BALL_J17_HET1_31 | PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
89 pinMuxReg->PINMUX27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
91 pinMuxReg->PINMUX28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
93 pinMuxReg->PINMUX29 = PINMUX_BALL_D3_SPI2NENA;
95 PINMUX_GATE_EMIF_CLK_ENABLE;
96 PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
97 PINMUX_ALT_ADC_TRIGGER_SELECT(1);
98 PINMUX_ETHERNET_SELECT(RMII);
100 /* Disable Pin Muxing */
101 kickerReg->KICKER0 = 0x00000000U;
102 kickerReg->KICKER1 = 0x00000000U;
104 /* Bit 31 of register GPREG1 is used to gate off the
105 EMIF module outputs */
106 systemREG1->GPREG1 |= 0x80000;
110 * This function explicitly enable/disable HET2 inputs for IRC module
111 * Parameters: irc - IRC number
112 * 1 for IRC is connected to DIN10 and DIN11
113 * 2 for IRC is connected to DIN14 and DIN15
114 * enable - TRUE for IRC, FALSE for normal usage as digital inputs
116 void setMuxForIRC(int8_t irc, boolean_t enable) {
118 /* Enable Pin Muxing */
119 kickerReg->KICKER0 = 0x83E70B13;
120 kickerReg->KICKER1 = 0x95A4F1E0;
124 case 1: // set DIN10 and DIN11 to HET2
125 PINMUX_SET(2,C1,HET2_0);
126 PINMUX_SET(2,E1,HET2_2);
128 case 2: // set DIN14 and DIN15 to HET2
129 PINMUX_SET(3,H3,HET2_4);
130 PINMUX_SET(4,M1,HET2_6);
135 case 1: // set DIN10 and DIN11 back from HET2
136 PINMUX_SET(2,C1,GIOA_2);
137 PINMUX_SET(2,E1,GIOA_3);
139 case 2: // set DIN14 and DIN15 back from HET2
140 PINMUX_SET(3,H3,GIOA_6);
141 PINMUX_SET(4,M1,GIOA_7);
148 /* Disable Pin Muxing */
149 kickerReg->KICKER0 = 0x00000000;
150 kickerReg->KICKER1 = 0x00000000;