1 /** @file sys_startup.c
2 * @brief Startup Source File
13 * which are relevant for the Startup.
16 /* (c) Texas Instruments 2009-2012, All rights reserved. */
21 #include "sys/system.h"
22 #include "sys/sys_vim.h"
23 #include "sys/sys_core.h"
24 #include "sys/sys_selftest.h"
25 #include "sys/ti_drv_esm.h"
28 #define MDIOMiscInt phantomInterrupt
29 #define EMACCore0RxIsr phantomInterrupt
30 #define EMACCore0TxIsr phantomInterrupt
33 /* Type Definitions */
35 typedef void (*handler_fptr)(const uint8_t *in, uint8_t *out);
37 /* External Functions */
38 #pragma WEAK(__TI_Handler_Table_Base)
39 #pragma WEAK(__TI_Handler_Table_Limit)
40 #pragma WEAK(__TI_CINIT_Base)
41 #pragma WEAK(__TI_CINIT_Limit)
43 extern uint32_t __TI_Handler_Table_Base;
44 extern uint32_t __TI_Handler_Table_Limit;
45 extern uint32_t __TI_CINIT_Base;
46 extern uint32_t __TI_CINIT_Limit;
47 extern uint32_t __TI_PINIT_Base;
48 extern uint32_t __TI_PINIT_Limit;
49 extern uint32_t * __binit__;
51 extern void main(void);
52 extern void exit(void);
53 /* Functions from library */
54 extern void __TI_auto_init(void);
55 extern void muxInit(void);
57 /* Vim Ram Definition */
59 * @brief Vim Ram Definition
61 * This type is used to access the Vim Ram.
64 * @brief Vim Ram Type Definition
66 * This type is used to access the Vim Ram.
68 typedef volatile struct vimRam
70 t_isrFuncPTR ISR[VIM_CHANNELS + 1];
73 #define vimRAM ((vimRAM_t *)0xFFF82000U)
75 static const t_isrFuncPTR s_vim_init[] =
78 &esmHighInterrupt, // 0
80 #if FREERTOS_VERSION_NUMBER_MAYOR == 7 && \
81 FREERTOS_VERSION_NUMBER_MINOR == 0 && \
82 FREERTOS_VERSION_NUMBER_REV == 2
83 &vPreemptiveTick, // FreeRTOS 7.0.2
85 &vPortPreemptiveTick, // FreeRTOS 7.4.0 and 7.4.2
89 &phantomInterrupt, // 5
94 &phantomInterrupt, // 10
97 /*#if serialLine == scilinREG
98 &sciHighLevelinterrupt,
100 &linHighLevelInterrupt,
103 &sciHighLevelInterrupt,
105 &adc1Group1Interrupt, // 15
110 &phantomInterrupt, // 20
111 &vPortYeildWithinAPI, // Software interrupt
115 &phantomInterrupt, // 25
120 &phantomInterrupt, // 30
125 &phantomInterrupt, // 35
130 &phantomInterrupt, // 40
135 &phantomInterrupt, // 45
140 &phantomInterrupt, // 50
141 &adc2Group1Interrupt,
145 &phantomInterrupt, // 55
150 &phantomInterrupt, // 60
154 &sciHighLevelInterrupt,
155 &phantomInterrupt, // 65
160 &phantomInterrupt, // 70
165 &phantomInterrupt, // 75
166 &phantomInterrupt, //MDIOMiscInt
167 &phantomInterrupt, //EMACCore0TxIsr
169 &phantomInterrupt, //EMACCore0RxIsr
170 &phantomInterrupt, // 80
175 &phantomInterrupt, // 85
180 &phantomInterrupt, // 90
185 &phantomInterrupt, // 95
190 &phantomInterrupt, // 100
221 /** @fn void _errata_CORTEXR4_66_(void)
222 * @brief Work Around for Errata CORTEX-R4#66
224 * This function Disable out-of-order completion for divide
225 * instructions in Auxiliary Control register.
227 void _errata_CORTEXR4_66_(void);
229 /** @fn void _errata_CORTEXR4_57_(void)
230 * @brief Work Around for Errata CORTEX-R4#57
232 * Disable out-of-order single-precision floating point
233 * multiply-accumulate instruction completion.
235 void _errata_CORTEXR4_57_(void);
238 /* Startup Routine */
240 #pragma INTERRUPT(_c_int00, RESET)
244 /* Initialize Core Registers to avoid CCM Error */
245 _coreInitRegisters_();
247 /* Initialize Stack Pointers */
248 _coreInitStackPointer_();
250 /* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
252 * Errata Description:
253 * The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on
255 * Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register
257 if (DEVICE_ID_REV == 0x802AAD05)
259 _esmCcmErrorsClear_();
262 /* Enable CPU Event Export */
263 /* This allows the CPU to signal any single-bit or double-bit errors detected
264 * by its ECC logic for accesses to program flash or data RAM.
266 _coreEnableEventBusExport_();
268 /* Enable response to ECC errors indicated by CPU for accesses to flash */
269 /*flashWREG->FEDACCTRL1 = 0x000A060A;*/
271 /* Enable CPU ECC checking for ATCM (flash accesses) */
272 /*_coreEnableFlashEcc_();*/
274 /* Reset handler: the following instructions read from the system exception status register
275 * to identify the cause of the CPU reset.
278 /* check for power-on reset condition */
279 if ((SYS_EXCEPTION & POWERON_RESET) != 0)
281 /* clear all reset status flags */
282 SYS_EXCEPTION = 0xFFFF;
283 /* Workaround for Errata CORTEXR4 66 */
284 _errata_CORTEXR4_66_();
285 /* Workaround for Errata CORTEXR4 57 */
286 _errata_CORTEXR4_57_();
287 /* continue with normal start-up sequence */
289 else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0)
291 /* Reset caused due to oscillator failure.
292 Add user code here to handle oscillator failure */
294 else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0 )
297 * 1) windowed watchdog violation - Add user code here to handle watchdog violation.
298 * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
300 /* Check the WatchDog Status register */
301 if(WATCHDOG_STATUS != 0U)
303 /* Add user code here to handle watchdog violation. */
304 /* Clear the Watchdog reset flag in Exception Status register */
305 SYS_EXCEPTION = WATCHDOG_RESET;
309 /* Clear the ICEPICK reset flag in Exception Status register */
310 SYS_EXCEPTION = ICEPICK_RESET;
313 else if ((SYS_EXCEPTION & CPU_RESET) !=0 )
315 /* Reset caused due to CPU reset.
316 CPU reset can be caused by CPU self-test completion, or
317 by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
318 /* clear all reset status flags */
319 SYS_EXCEPTION = CPU_RESET;
321 else if ((SYS_EXCEPTION & SW_RESET) != 0)
323 /* Reset caused due to software reset.
324 Add user code to handle software reset. */
328 /* Reset caused by nRST being driven low externally.
329 Add user code to handle external reset. */
332 /* Check if there were ESM group3 errors during power-up.
333 * These could occur during eFuse auto-load or during reads from flash OTP
334 * during power-up. Device operation is not reliable and not recommended
336 * An ESM group3 error only drives the nERROR pin low. An external circuit
337 * that monitors the nERROR pin must take the appropriate action to ensure that
338 * the system is placed in a safe state, as determined by the application.
340 if (esmREG->ESTATUS1[2])
345 /* Initialize System - Clock, Flash settings with Efuse self check */
348 /* Workaround for Errata PBIST#4 */
351 /* Run a diagnostic check on the memory self-test controller.
352 * This function chooses a RAM test algorithm and runs it on an on-chip ROM.
353 * The memory self-test is expected to fail. The function ensures that the PBIST controller
354 * is capable of detecting and indicating a memory self-test failure.
358 /* Run PBIST on STC ROM */
359 pbistRun((uint32_t)STC_ROM_PBIST_RAM_GROUP,
360 ((uint32_t)PBIST_TripleReadSlow | (uint32_t)PBIST_TripleReadFast));
362 /* Wait for PBIST for STC ROM to be completed */
363 while(!pbistIsTestCompleted());
365 /* Check if PBIST on STC ROM passed the self-test */
366 if( pbistIsTestPassed() != TRUE)
368 /* PBIST and STC ROM failed the self-test.
369 * Need custom handler to check the memory failure
370 * and to take the appropriate next step.
376 /* Run PBIST on PBIST ROM */
377 pbistRun((uint32_t)PBIST_ROM_PBIST_RAM_GROUP,
378 ((uint32_t)PBIST_TripleReadSlow | (uint32_t)PBIST_TripleReadFast));
380 /* Wait for PBIST for PBIST ROM to be completed */
381 while(!pbistIsTestCompleted());
383 /* Check if PBIST ROM passed the self-test */
384 if( pbistIsTestPassed() != TRUE)
386 /* PBIST and STC ROM failed the self-test.
387 * Need custom handler to check the memory failure
388 * and to take the appropriate next step.
395 /* Disable RAM ECC before doing PBIST for Main RAM */
396 _coreDisableRamEcc_();
398 /* Run PBIST on CPU RAM.
399 * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
400 * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
403 pbistRun(0x08300020, /* ESRAM Single Port PBIST */
406 /* Wait for PBIST for CPU RAM to be completed */
407 while(!pbistIsTestCompleted());
409 /* Check if CPU RAM passed the self-test */
410 if( pbistIsTestPassed() != TRUE)
412 /* CPU RAM failed the self-test.
413 * Need custom handler to check the memory failure
414 * and to take the appropriate next step.
419 /* Disable PBIST clocks and disable memory self-test mode */
422 /* Initialize CPU RAM.
423 * This function uses the system module's hardware for auto-initialization of memories and their
424 * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
425 * Hence the value 0x1 passed to the function.
426 * This function will initialize the entire CPU RAM and the corresponding ECC locations.
430 /* Enable ECC checking for TCRAM accesses.
431 * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
433 _coreEnableRamEcc_();
435 /* Start PBIST on all dual-port memories */
436 pbistRun( 0x00000000 /* EMAC Dual Port PBIST */
437 | 0x00000000 /* USB Dual Port PBIST for RMx / Reserved for TMS570x */
438 | 0x00000800 /* DMA Dual Port PBIST */
439 | 0x00000200 /* VIM Dual Port PBIST */
440 | 0x00000040 /* MIBSPI1 Dual Port PBIST */
441 | 0x00000080 /* MIBSPI3 Dual Port PBIST */
442 | 0x00000100 /* MIBSPI5 Dual Port PBIST */
443 | 0x00000004 /* CAN1 Dual Port PBIST */
444 | 0x00000008 /* CAN2 Dual Port PBIST */
445 | 0x00000010 /* CAN3 Dual Port PBIST */
446 | 0x00000400 /* ADC1 Dual Port PBIST */
447 | 0x00020000 /* ADC2 Dual Port PBIST */
448 | 0x00001000 /* HET1 Dual Port PBIST */
449 | 0x00040000 /* HET2 Dual Port PBIST */
450 | 0x00002000 /* HTU1 Dual Port PBIST */
451 | 0x00080000 /* HTU2 Dual Port PBIST */
452 | 0x00004000 /* RTP Dual Port PBIST */
453 | 0x00000000 /* FTU Dual Port PBIST for TMS570x / Reserved for RMx */
454 | 0x00008000 /* FRAY Dual Port PBIST for TMS570x / Reserved for RMx */
455 , PBIST_March13N_DP);
457 /* Test the CPU ECC mechanism for RAM accesses.
458 * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
459 * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
460 * in the ECC causes a data abort exception. The data abort handler is written to look for
461 * deliberately caused exception and to return the code execution to the instruction
462 * following the one that caused the abort.
465 tcram1REG->RAMCTRL &= ~(0x00000100); /* disable writes to ECC RAM */
466 tcram2REG->RAMCTRL &= ~(0x00000100);
469 tcram1REG->RAMCTRL &= ~(0x00000100); /* disable writes to ECC RAM */
470 tcram2REG->RAMCTRL &= ~(0x00000100);
472 /* Test the CPU ECC mechanism for Flash accesses.
473 * The checkFlashECC function uses the flash interface module's diagnostic mode 7
474 * to create single-bit and double-bit errors in CPU accesses to the flash. A double-bit
475 * error on reading from flash causes a data abort exception.
476 * The data abort handler is written to look for deliberately caused exception and
477 * to return the code execution to the instruction following the one that was aborted.
482 flashWREG->FDIAGCTRL = 0x000A0007; */ /* disable flash diagnostic mode */
484 /* Wait for PBIST for CPU RAM to be completed */
485 while(!pbistIsTestCompleted());
487 /* Check if CPU RAM passed the self-test */
488 if( pbistIsTestPassed() != TRUE)
490 /* CPU RAM failed the self-test.
491 * Need custom handler to check the memory failure
492 * and to take the appropriate next step.
498 /* Disable PBIST clocks and disable memory self-test mode */
501 /* Release the MibSPI1 modules from local reset.
502 * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
504 mibspiREG1->GCR0 = 0x1;
506 /* Release the MibSPI3 modules from local reset.
507 * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
509 mibspiREG3->GCR0 = 0x1;
511 /* Release the MibSPI5 modules from local reset.
512 * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
514 mibspiREG5->GCR0 = 0x1;
516 /* Enable parity on selected RAMs */
519 /* Initialize all on-chip SRAMs except for MibSPIx RAMs
520 * The MibSPIx modules have their own auto-initialization mechanism which is triggered
521 * as soon as the modules are brought out of local reset.
523 /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
525 memoryInit( 1 << 1 /* DMA Memory Init */
526 | 1 << 2 /* VIM Memory Init */
527 | 1 << 5 /* CAN1 Memory Init */
528 | 1 << 6 /* CAN2 Memory Init */
529 | 1 << 10 /* CAN3 Memory Init */
530 | 1 << 8 /* ADC1 Memory Init */
531 | 1 << 14 /* ADC2 Memory Init */
532 | 1 << 3 /* HET1 Memory Init */
533 | 1 << 4 /* HTU1 Memory Init */
534 | 1 << 15 /* HET2 Memory Init */
535 | 1 << 16 /* HTU2 Memory Init */
536 | 1 << 13); /* Reserved for RMx Family / FTU Memory Init for TMS570x Family */
541 /* Test the parity protection mechanism for peripheral RAMs
542 * The following memories have parity protection that needs to be checked:
543 * VIM, DMA, ADC1, ADC2, NHET1, NHET2, HTU1, HTU2, FlexRay, FTU,
544 * MibSPI1, MibSPI3, MibSPI5, DCAN1, DCAN2, DCAN3 based on user selection
546 /* Test the parity protection mechanism for peripheral RAMs
547 NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
548 Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
564 while (mibspiREG1->BUFINIT); /* wait for MibSPI1 RAM to complete initialization */
565 while (mibspiREG3->BUFINIT); /* wait for MibSPI3 RAM to complete initialization */
566 while (mibspiREG5->BUFINIT); /* wait for MibSPI5 RAM to complete initialization */
568 mibspi1ParityCheck();
569 mibspi3ParityCheck();
570 mibspi5ParityCheck();
572 /* Initialize VIM table */
576 for (i = 0; i < (VIM_CHANNELS + 1); i++)
578 vimRAM->ISR[i] = s_vim_init[i];
582 /* set IRQ/FIQ priorities */
583 vimREG->FIRQPR0 = SYS_FIQ
616 vimREG->FIRQPR1 = SYS_IRQ
650 vimREG->FIRQPR2 = SYS_IRQ
662 | (SYS_IRQ << 12U) // MDIOMiscInt
663 | (SYS_IRQ << 13U) // EMAC
665 | (SYS_IRQ << 15U) // EMAC
683 vimREG->FIRQPR3 = SYS_IRQ
717 /* enable interrupts */
718 vimREG->REQMASKSET0 = 1U
751 vimREG->REQMASKSET1 = 0U
784 vimREG->REQMASKSET2 = 1U
796 | (1U << 12U) // MDIOMiscInt
797 | (1U << 13U) // EMACCore0TxIsr
799 | (1U << 15U) // EMACCore0RxIsr
817 vimREG->REQMASKSET3 = 0U
850 /* Configure system response to error conditions signaled to the ESM group1 */
851 /* This function can be configured from the ESM tab of HALCoGen */
854 /* initialize copy table */
857 /* call the application */