2 * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
3 * Copyright (C) 2013-2015 Czech Technical University in Prague
6 * Redistribution and use in source and binary forms, with or without modification,
7 * are permitted provided that the following conditions are met:
9 * 1. Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
20 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
22 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
28 * This file is part of the lwIP TCP/IP stack.
30 * Author: Adam Dunkels <adam@sics.se>
31 * Carlos Jenkins <carlos@jenkins.co.cr>
32 * Rostislav Lisovy <lisovy@gmail.com>
33 * Jan Doležal <pm.jenik@gmail.com>
38 * Copyright (c) 2010 Texas Instruments Incorporated
40 * This file is dervied from the "ethernetif.c" skeleton Ethernet network
41 * interface driver for lwIP.
47 #ifndef FREERTOS_POSIX
50 #include "lwip/init.h"
51 #include "lwip/timers.h" /* for DHCP binding in NO_SYS mode */
52 #include "lwip/sys.h" /* includes - lwip/opt.h, lwip/err.h, arch/sys_arch.h */
53 #include "lwip/tcpip.h" /* includes - lwip/opt.h, lwip/api_msg.h, lwip/netifapi.h, lwip/pbuf.h, lwip/api.h, lwip/sys.h, lwip/timers.h, lwip/netif.h */
54 #include "lwip/stats.h" /* includes - lwip/mem.h, lwip/memp.h, lwip/opt.h */
55 #include "netif/etharp.h" /* includes - lwip/ip.h, lwip/netif.h, lwip/ip_addr.h, lwip/pbuf.h */
57 #include "lwip/snmp.h"
58 #include "lwip/dhcp.h"
59 #include "lwip/autoip.h"
60 #include "netif/ppp_oe.h"
61 /* end - lwIP headers */
64 #include "sys/sys.h" /* includes - sys/phy_dp83848h.h */
70 /* Number of EMAC Instances */
71 #define MAX_EMAC_INSTANCE 1
73 #define DEFAULT_PHY_ADDR 0x1
74 #define FIND_FIRST_PHY_ALIVE 1 /* or use default (phy_address: 1) */
75 #define NUM_OF_PHYs 32
77 /* Size of the Buffer descriptor defined by the EMAC in bytes */
78 #define SIZE_OF_DESC 16
80 /* Channel number used for for RX, TX, unicast, broadcast or damaged frames;
81 * there are different channels for rx and tx operations (i.e. RXCH0 != TXCH0) */
84 /* take in account oversized frames */
85 #define MAX_TRANSFER_UNIT 1500
88 * Be very carefull when setting this value. We have to keep in mind
89 * that pbuf_alloc(..., PBUF_POOL) will usualy return a chain of PBUFs
90 * pointing to the statically preallocated buffers (of the same size).
91 * The problem is that if we ask to allocate 300 bytes whereby the size
92 * of the statically preallocated PBUFs (PBUF_POOL_BUFSIZE) is 256, we
93 * will get a chain containing two PBUFs -- one *reporting* its size to
94 * be 256 bytes, the other one 44 bytes.
95 * Everything seems to be just fine however during RX, after we call
96 * netif->input(pbuf, netif) we have to newly allocate the PBUF(s) and
97 * properly set the apropriate BDs. This will however work only if the
98 * number of the freed BDs is the same as the number of the BDs newly
99 * initialized. One possible situation when this may fail is when multiple
100 * non-256 byte sized PBUFs will move near to each other, i.e. 3 BDs:
101 * 256 B, 44 B, 44 B -- 344 bytes will be freed (3 BDs) but the new call
102 * to pbuf_alloc(...) will return a chain comprising only two PBUFs
104 * This is the implementation limitation. The PBUF_LEN_MAX should therefore
105 * be multiple of PBUF_POOL_BUFSIZE
107 #define PBUF_LEN_MAX (PBUF_POOL_BUFSIZE * 6)
109 /* Maximum number of PBUFs preallocated in the driver
110 * init function to be used for the RX
112 #define MAX_RX_PBUF_ALLOC 10
113 #define MIN_PKT_LEN 60
115 /* Define those to better describe the network interface. */
119 /* Time to wait for autonegotiation in ticks. */
120 #define TICKS_PHY_AUTONEG 4000
123 * TODO -- not implemented
124 * When cable is connected (link status goes up)
125 * autonegotiation and/or dhcp is started.
127 #define PHY_LINK_MONITOR_INT 0
130 /* Statically allocated structure describing interface state -- one per instance */
131 static struct hdkif hdkif_data[MAX_EMAC_INSTANCE];
133 /* The lwIP network interface structure for the HDK Ethernet MAC. */
134 static struct netif hdkNetIF[MAX_EMAC_INSTANCE];
136 /* RPP startup init indicator */
137 static boolean_t initialized = FALSE;
138 static boolean_t postInitialized = FALSE;
140 /***testing functions**********************************************/
141 boolean_t isPostInitialized()
143 return postInitialized;
146 uint32_t rpp_eth_phylinkstat(uint32_t instNum)
148 struct hdkif *hdkif = &hdkif_data[instNum];
150 return PHY_link_status_get(hdkif->mdio_base, hdkif->phy_addr, 1);
153 #define BYTE_BUFF_SIZE 2
154 #define OFFSET_MAC_LETTERS (MAC_BIG_LETTERS ? 'A' : 'a')
155 /* puts string of MAC address assigned to EMAC instance reffered by instNum into *mac */
156 void rpp_eth_get_macAddrStr(uint32_t instNum, uint8_t *macStr)
158 uint8_t index, outindex = 0;
159 char buff[BYTE_BUFF_SIZE];
160 struct hdkif *hdkif = &hdkif_data[instNum];
161 for(index = 0; index < MAC_ADDR_LEN; index++) {
162 if(index)macStr[outindex++] = ':';
163 buff[0] = (hdkif->mac_addr[(MAC_ADDR_LEN - 1) - index] >> 4);
164 buff[1] = (hdkif->mac_addr[(MAC_ADDR_LEN - 1) - index] & 0xf);
165 macStr[outindex++] = (buff[0]<10) ? (buff[0] + '0') : (buff[0] - '\012' + OFFSET_MAC_LETTERS);
166 macStr[outindex++] = (buff[1]<10) ? (buff[1] + '0') : (buff[1] - '\012' + OFFSET_MAC_LETTERS);
168 macStr[outindex] = '\0';
171 /* @param ip will be filled accroding to content of ipstr */
172 err_t rpp_eth_stringToIP(ip_addr_t * ip, uint8_t * ipstr)
174 uint8_t charProccessed, index = 0, dotindex = 0xff, tmp = 0, dots = 0, fldEdit = 0;
176 for(charProccessed = ipstr[index]; (charProccessed >= '0' && charProccessed <= '9') || charProccessed == '.' ; charProccessed = ipstr[++index])
178 if(charProccessed == '.')
180 if(++dotindex == index)
187 ipaddr = (ipaddr << 8) + tmp;
198 tmp = tmp*10 + charProccessed - '0';
201 if(dots != 3 || !fldEdit)
203 /* if unsuccesful, don't modify previous content */
206 ipaddr = (ipaddr << 8) + tmp;
211 /* returns number in range 0-65535 where 0 is error */
212 uint16_t rpp_eth_portStrToInt(uint8_t *string)
216 for(index = 0;string[index] != '\0';index++)
218 if(string[index] < '0' || string[index] > '9')
223 portNO = portNO * 10 + string[index] - '0';
228 struct netif *rpp_eth_get_netif(uint32_t instNum)
230 return &hdkNetIF[instNum];
233 /***** forward declarations **********************************************/
236 * interface initializes
238 err_t rpp_eth_lwip_init(struct netif *netif);
241 * Initializes hw such as PHY, MDIO, EMAC, EMAC control module
243 * @return SUCCESS if initialization successful.\n
244 * FAILURE if initialization not successful.
246 err_t rpp_eth_hw_init(struct hdkif *hdkif);
249 * Initializes hw, after lwIP was initialized and
250 * OS was initialized in case OS is used.
252 err_t rpp_eth_hw_init_postInit(struct netif *netif);
254 /***** utility functions **********************************************/
257 * Function to set the MAC address to the interface
258 * @param inst_num the instance number
260 * @note mac_addr[0] is considered MSB
262 static void hdkif_macaddrset(u32_t inst_num, u8_t *mac_addr)
267 hdkif = &hdkif_data[inst_num];
269 /* set MAC hardware address */
270 for (temp = 0; temp < MAC_ADDR_LEN; temp++) {
271 hdkif->mac_addr[temp] = mac_addr[(MAC_ADDR_LEN - 1) - temp];
275 rpp_eth_get_macAddrStr(inst_num, macStr);
276 rpp_debug_printf("Setting MAC... %s\r\n", macStr);
281 * Function to setup the instance parameters inside the interface
285 static void hdkif_inst_config(struct hdkif *hdkif)
287 if (hdkif->inst_num == 0) {
288 hdkif->emac_base = EMAC_BASE_m(0);
289 hdkif->emac_ctrl_base = EMAC_CTRL_BASE_m(0);
290 hdkif->emac_ctrl_ram = EMAC_CTRL_RAM_BASE_m(0);
291 hdkif->mdio_base = MDIO_BASE_m(0);
293 /* Default address of PHY on "MDIO bus"
294 * (depends on PHY hw configuration)
296 hdkif->phy_addr = DEFAULT_PHY_ADDR;
297 hdkif->phy_autoneg = PHY_auto_negotiate;
298 hdkif->phy_autoneg_start = PHY_start_auto_negotiate;
299 hdkif->phy_autoneg_is_done = PHY_is_done_auto_negotiate;
300 hdkif->phy_partnerability = PHY_partner_ability_get;
304 /***** initializing functions **********************************************/
305 int8_t rpp_eth_init()
307 unsigned int instNum;
308 int8_t retVal = SUCCESS;
313 /* Config each EMAC instance */
314 for (instNum = 0; instNum < MAX_EMAC_INSTANCE; instNum++) {
315 struct hdkif *hdkif = &hdkif_data[instNum];
317 hdkif->inst_num = instNum;
318 hdkif_inst_config(hdkif);
320 retVal = rpp_eth_hw_init(hdkif);
321 if (retVal != SUCCESS) {
322 rpp_debug_printf("rpp_eth_hw_init: %d", retVal);
331 int8_t rpp_eth_init_postInit(uint32_t instNum, uint8_t *macArray)
333 volatile unsigned int dhcpBindWait = 0x3FFFFFFF;
334 struct ip_addr ip_addr;
335 struct ip_addr net_mask;
336 struct ip_addr gw_addr;
337 int8_t retVal = SUCCESS;
338 struct netif *netif = &hdkNetIF[instNum];
339 struct netif *netif_tmp;
340 u8_t mac_addr[MAC_ADDR_LEN] = RPP_MAC_ADDR;
346 if (macArray == NULL)
347 macArray = mac_addr; /* use default MAC */
349 hdkif_macaddrset(instNum, macArray);
354 /* This can be called only within post OS init */
357 * calls lwip_init() implicitly, starts lwIP task (thread),
358 * when started function given to tcpip_init is executed first
360 tcpip_init(NULL, NULL);
363 #if STATIC_IP_ADDRESS
364 ip_addr.addr = htonl(RPP_IP_ADDR);
365 net_mask.addr = htonl(RPP_NETMASK);
366 gw_addr.addr = htonl(RPP_GW);
374 /* Add new network interface to lwIP list of ifaces
375 * and initialize netif with specific function
377 netif_tmp = netif_add(netif, &ip_addr, &net_mask, &gw_addr,
378 &hdkif_data[instNum], rpp_eth_lwip_init,
381 netif_tmp = netif_add(netif, &ip_addr, &net_mask, &gw_addr,
382 &hdkif_data[instNum], rpp_eth_lwip_init,
385 if (netif_tmp == NULL)
386 return NETIF_ADD_ERR;
388 netif_set_default(netif);
390 hdkif = netif->state;
393 /* Semaphores used to block/unblock RX/TX threads doing the
394 * 'deferred' RX/TX handling -- semgive is callend in RX/TX ISR
396 vSemaphoreCreateBinary(hdkif->goRX);
397 vSemaphoreCreateBinary(hdkif->goTX);
399 xTaskCreate(rpp_eth_recv_raw_thr, "RXHandler", 500, netif, 0, NULL);
400 xTaskCreate(rpp_eth_send_raw_thr, "TXHandler", 500, netif, 0, NULL);
403 /* If we don't use link int change, then it must be done here */
404 #if !PHY_LINK_MONITOR_INT
405 if (rpp_eth_phylinkstat(hdkif->inst_num)) {
406 rpp_debug_printf("cable connected ... setting IP params\r\n");
408 #if STATIC_IP_ADDRESS
411 int ret = dhcp_start(netif);
413 rpp_debug_printf("dhcp mem err\r\n");
417 rpp_debug_printf("binding DHCP\r");
418 while ((netif->dhcp->state != DHCP_BOUND) && (dhcpBindWait--))
419 ; /* FIXME: sys_check_timeouts()*/
422 rpp_debug_printf("dhcp binding timeout...\r\n");
423 #else /* FIXME there should be some kind of waiting until IP address is assigned */
428 uint8_t ipString[16]; // FIXME change the functions to use char
429 rpp_eth_getIPDecimalStr(netif->ip_addr, ipString);
430 rpp_debug_printf("Address: %s\n", ipString);
431 rpp_eth_getIPDecimalStr(netif->netmask, ipString);
432 rpp_debug_printf("Netmask: %s\n", ipString);
433 rpp_eth_getIPDecimalStr(netif->gw, ipString);
434 rpp_debug_printf("Gateway: %s\n", ipString);
438 rpp_debug_printf("cable not connected\r\n");
439 retVal = PHY_LINK_DOWN;
442 #else /* !PHY_LINK_MONITOR_INT */
443 /* Link Status change handled in an interrupt -- NOT IMPLEMENTED */
446 * Now when we established environment needed for phy link status
447 * change we can allow it. Set PHY number which is monitored for
448 * link changes in MDIO and enable interrupt
450 HWREG(hdkif->mdio_base + MDIO_USERPHYSEL0) =
451 ((hdkif->phy_addr && 0x1f) | MDIO_USERPHYSEL0_LINKINTENB);
453 /* Enable MISC interrupt - link monitoring in EMAC control module */
454 HWREG(hdkif->emac_ctrl_base + EMAC_CTRL_CnMISCEN(0)) |=
455 EMAC_CTRL_MISC_LINKINT0ENB;
457 #endif /* !PHY_LINK_MONITOR_INT */
459 postInitialized = TRUE;
463 err_t rpp_eth_lwip_init(struct netif *netif)
465 struct hdkif *hdkif = netif->state;
467 #if LWIP_NETIF_HOSTNAME
468 netif->hostname = "rpp";
470 netif->state = hdkif;
472 netif->name[0] = IFNAME0;
473 netif->name[1] = IFNAME1;
476 hdkif->waitTicksForPHYAneg = TICKS_PHY_AUTONEG;
480 * Initialize the snmp variables and counters inside the struct netif.
481 * The last argument should be replaced with your link speed, in units
482 * of bits per second.
484 NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
486 /* We directly use etharp_output() here to save a function call.
487 * You can instead declare yo_SKIP_TO_HWur own function an call etharp_output()
488 * from it if you have to do some checks before sending (e.g. if link
491 netif->output = etharp_output;
492 netif->linkoutput = rpp_eth_send;
494 return rpp_eth_hw_init_postInit(netif);
497 #define INIT_ONLY_AFTER_RESET 1 // FIXME Why? Wat? Wut? For future implementation?
498 static err_t rpp_eth_hw_init(struct hdkif *hdkif)
504 /* Deactivate reset pin of PHY */
506 * For hw reset of PHY, it is necessary that PIN_NAME_ETHRST is 1us
507 * logical low state, before putting it to logical high
509 #if !INIT_ONLY_AFTER_RESET
512 * Initially used to hw reset of PHY connected to GIO pin.
513 * This means 1us - for 80MHz clock.
518 * Initially used to hw reset of PHY connected to GIO pin
519 * 'rpp project only'; 1us - according to PHY specification.
521 index = configCPU_CLOCK_HZ/1000000;
523 dio_pin_set(*dio_gpio_pin_get_dsc(PIN_NAME_ETHRST, -1), 0);
525 #endif /* !INIT_ONLY_AFTER_RESET */
527 * We have pull-down resistor, so after reset, we only need
528 * to put ETHRST pin to log. high
530 gio_set(PIN_ETHRST, 1);
532 /* Initialize EMAC control module and EMAC module */
533 EMACInit(hdkif->emac_ctrl_base, hdkif->emac_base);
534 /* Initialize MDIO module (reset) */
535 MDIOInit(hdkif->mdio_base, 0x0, 0x0);
538 * Try to read random register from defaultPhy to make MDIO fill alive
539 * bit for this one if it returned ACK bit in msg response -- this must
540 * be done, because MDIO has not set alive bit of PHY after that
541 * short time after MDIOInit()
543 MDIOPhyRegRead(hdkif->mdio_base, hdkif->phy_addr, PHY_BMSR, ®Content);
545 /* Find first alive PHY -- or use default if alive */
546 physAlive = MDIOPhyAliveStatusGet(hdkif->mdio_base);
547 if (!(physAlive & (1 << hdkif->phy_addr))) {
548 #if FIND_FIRST_PHY_ALIVE
549 for (index = 0; index < NUM_OF_PHYs; index++) {
550 if (physAlive && (1 << index)) {
551 hdkif->phy_addr = index;
555 * Try to 'wake up' PHY on 'index' address by
556 * reading random register, making MDIO set
557 * alive bit for current PHY
559 MDIOPhyRegRead(hdkif->mdio_base, index,
560 PHY_BMCR, ®Content);
562 /* Get updated register */
563 physAlive = MDIOPhyAliveStatusGet(hdkif->mdio_base);
564 if (physAlive && (1 << index)) {
565 hdkif->phy_addr = index;
571 if (!physAlive) { /* FIXME je to ok? */
572 rpp_debug_printf("no phy found, phys: %d\n", physAlive);
576 rpp_debug_printf("default phy not alive\n");
577 return DFLT_PHY_NOT_ALIVE;
582 * Start autonegotiation and check on completion later or
583 * when complete link register will be updated
585 hdkif->phy_autoneg_start(hdkif->mdio_base, hdkif->phy_addr,
586 PHY_100BASETXDUPL_m | PHY_100BASETX_m |
587 PHY_10BASETDUPL_m | PHY_10BASET_m);
590 * TODO: you can implement init of receive flow control somewhere
591 * here if desired - set RXBUFFERFLOWEN in MACCONTROL
595 /* Acknowledge EMAC control module RX, TX and MISC interrupts */
596 EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_RX);
597 EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_TX);
598 EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_MISC);
600 /* Sets which channel will receive broadcasts */
601 EMACRxBroadCastEnable(hdkif->emac_base, CHANNEL);
604 * Sets channel where all frames will be copied to --
605 * either with MAC address different from local device address,
606 * either packets with error will be copied; appropriate error
607 * will be set in the frame EOP buffer descriptor
609 EMACRxPromiscEnable(hdkif->emac_base, CHANNEL);
612 EMACRxUnicastSet(hdkif->emac_base, CHANNEL);
614 /* Enable TX and RX interrupts in both EMAC module and EMAC control module */
615 EMACTxIntPulseEnable(hdkif->emac_base, hdkif->emac_ctrl_base, 0, CHANNEL);
616 EMACRxIntPulseEnable(hdkif->emac_base, hdkif->emac_ctrl_base, 0, CHANNEL);
621 static err_t rpp_eth_hw_init_postInit(struct netif *netif)
623 /* 0x3FFFFFFF is for 80MHz aproximately 13s */
624 volatile unsigned int autonegFinishWait = 0x3FFFFFFF;
627 uint32_t num_bd, pbuf_cnt = 0;
628 volatile struct emac_tx_bd *curr_txbd, *last_txbd;
629 volatile struct emac_rx_bd *curr_rxbd, *last_rxbd;
634 struct hdkif *hdkif = (struct hdkif *)netif->state;
636 rxch = &(hdkif->rxch);
637 txch = &(hdkif->txch);
639 rpp_debug_printf("autoneg started -- check on cable if it's connected!\r\n");
642 * Use the CPPI RAM to store RX/TX Buffer Descriptors (= BD).
643 * 1/2 of CPPI RAM is used for TX BDs, another 1/2 for RX BDs.
644 * All the TX BDs are 'owned' by the software. They are initialized
645 * as a linked-list forming a ring. They are awaiting the application
646 * to append pbuf payload to the them and correctly configure for
647 * actual transmission.
648 * Only such number of RX BDs is configured that the pbufs can be
649 * allocated for (i.e. MAX_RX_PBUF_ALLOC). Pbufs are allocated from
650 * the PBUF_POOL (thus the allocated pbufs might be chained).
651 * Each payload part of a payload is them used to initialize single
652 * RX BD. The RX BDs are then configured to be 'owned' bythe EMAC
656 * Initialize the Descriptor Memory For TX and RX
657 * Only Channel 0 is supported for both TX and RX
659 txch->free_head = (volatile struct emac_tx_bd *)hdkif->emac_ctrl_ram;
660 txch->next_bd_to_process = txch->free_head;
661 txch->active_tail = NULL;
663 /* Set the number of descriptors for the channel */
664 /* take half of CPPI ram for TX BDs */
665 num_bd = ((SIZE_EMAC_CTRL_RAM >> 1) / sizeof(struct emac_tx_bd));
667 curr_txbd = txch->free_head;
669 /* Initialize all the TX buffer Descriptors */
671 curr_txbd->next = curr_txbd + 1;
672 curr_txbd->flags_pktlen = 0;
673 last_txbd = curr_txbd;
674 curr_txbd = curr_txbd->next;
676 last_txbd->next = txch->free_head;
677 /* curr_txbd now points to the BD that is the first BD
678 * after the last_txbd -- this will be the first RX BD
681 /* Initialize the descriptors for the RX channel */
682 rxch->active_head = (volatile struct emac_rx_bd*)curr_txbd;
683 rxch->free_head = NULL; /* Not used */
684 rxch->freed_pbuf_len = 0;
686 num_bd = ((SIZE_EMAC_CTRL_RAM >> 1) / sizeof(struct emac_rx_bd));
687 curr_rxbd = rxch->active_head;
688 last_rxbd = curr_rxbd;
690 /* Allocate the pbufs for the maximum count permitted or
691 * till the number of buffer descriptors expire,
692 * whichever is earlier.
694 while (pbuf_cnt < MAX_RX_PBUF_ALLOC) {
695 /* Sidenote -- remember that the PBUF might be chained */
696 p = pbuf_alloc(PBUF_RAW, PBUF_LEN_MAX, PBUF_POOL);
698 /* Watch out not to excede the number of available BDs */
699 if (((uint32_t)pbuf_clen(p)) <= num_bd) {
700 /* Fill in the BD to reference the allocated pbuf */
701 /* for each PBUF chunk */
702 for (q = p; q != NULL; q = q->next) {
703 curr_rxbd->bufptr = (uint8_t *)q->payload;
704 curr_rxbd->bufoff_len = q->len;
705 curr_rxbd->next = curr_rxbd + 1;
706 curr_rxbd->flags_pktlen = EMAC_DSC_FLAG_OWNER;
710 last_rxbd = curr_rxbd;
711 curr_rxbd = curr_rxbd->next;
715 /* free the allocated pbuf if no free
716 * descriptors are left */
726 rpp_sci_printf("No pbufs attached to RX BD during init\n");
728 last_rxbd->next = NULL;
729 rxch->active_tail = last_rxbd;
732 num_bd = (((uintptr_t)rxch->active_tail - (uintptr_t)rxch->active_head)
733 / sizeof(struct emac_rx_bd)) + 1;
734 rpp_debug_printf("%d pbuf chains allocated for %d rx buffer descriptors\n",
738 /* Set header descriptor pointers -- this shows EMAC which descriptor
739 * is the first one for writing received frames/packets
741 EMACRxHdrDescPtrWrite(hdkif->emac_base, (uint32_t)rxch->active_head, CHANNEL);
743 /* set MAC address */
744 netif->hwaddr_len = MAC_ADDR_LEN;
745 for (regContent = 0; regContent < MAC_ADDR_LEN; regContent++) {
746 netif->hwaddr[regContent] =
747 hdkif->mac_addr[(MAC_ADDR_LEN - 1) - regContent];
750 /* maximum transfer unit */
751 netif->mtu = MAX_TRANSFER_UNIT;
753 /* device capabilities */
754 /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
755 netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
758 /* for flow control frames */
759 EMACMACSrcAddrSet(hdkif->emac_base, hdkif->mac_addr);
761 /* Be sure to program all eight MAC address registers -
762 * whether the receive channel is to be enabled or not.
764 for (regContent = 0; regContent < 8; regContent++) {
765 EMACMACAddrSet(hdkif->emac_base, regContent, hdkif->mac_addr,
766 EMAC_MACADDR_NO_MATCH_NO_FILTER);
769 #if !PHY_LINK_MONITOR_INT
770 /* In case we don't use interrupt when phy link status changes,
771 * we need to try to finish autoneg in here
773 /* wait for autonegotiation to be done or continue, when delay was reached */
775 uint32_t timeToWake = hdkif->waitTicksForPHYAneg + sys_jiffies();
776 while (hdkif->phy_autoneg_is_done(hdkif->mdio_base, hdkif->phy_addr) == FALSE &&
777 timeToWake > sys_jiffies())
780 /* XXX: if init is not done at the startup,
781 * but couple days later, this might cause troubles */
785 while (hdkif->phy_autoneg_is_done(hdkif->mdio_base, hdkif->phy_addr) == FALSE &&
787 ; /* wait till aneg done */
790 if (hdkif->phy_autoneg_is_done(hdkif->mdio_base, hdkif->phy_addr) != FALSE)
791 rpp_debug_printf("autoneg finished\n");
793 rpp_debug_printf("autoneg timeout\n");
795 /* provide informations retrieved from autoneg to EMAC module */
796 hdkif->phy_partnerability(hdkif->mdio_base, hdkif->phy_addr, ®Content);
797 if (regContent & (PHY_100BASETXDUPL_m | PHY_10BASETDUPL_m)) {
798 EMACDuplexSet(hdkif->emac_base, EMAC_DUPLEX_FULL);
799 /* this is right place to implement transmit flow control if desired --
800 * set TXFLOWEN in MACCONTROL
802 } else if (regContent & (PHY_100BASETX_m | PHY_10BASET_m)) {
803 EMACDuplexSet(hdkif->emac_base, EMAC_DUPLEX_HALF);
805 rpp_debug_printf("Unknown duplex mode\r\n");
806 return UNKN_DUPLEX_MODE;
808 #endif /* !PHY_LINK_MONITOR_INT */
810 /* enable hostpend interrupts in emac module */
811 HWREG(hdkif->emac_base + EMAC_MACINTMASKSET) |=
812 EMAC_MACINTMASKSET_HOSTMASK;
814 /* enable hostpend interrupts in emac control module */
815 HWREG(hdkif->emac_ctrl_base + EMAC_CTRL_CnMISCEN(0)) |=
816 EMAC_CTRL_MISC_HOSTPENDENB;
818 EMACMIIEnable(hdkif->emac_base);
819 EMACTxEnable(hdkif->emac_base);
820 EMACRxEnable(hdkif->emac_base);
825 /* send and receive functions / ISRs ******************************************/
827 err_t rpp_eth_send(struct netif *netif, struct pbuf *p)
829 err_t retVal = SUCCESS;
831 SYS_ARCH_DECL_PROTECT(lev);
834 * This entire function must be protected to preserve
835 * the integrity of the transmit pbuf queue.
837 SYS_ARCH_PROTECT(lev);
838 #if !SYS_LIGHTWEIGHT_PROT
839 uint32_t prevProt = (uint32_t) _get_CPSR() & 0x80;
843 /* adjust the packet length if less than minimum required */
844 if (p->tot_len < MIN_PKT_LEN) {
845 p->tot_len = MIN_PKT_LEN;
846 p->len = MIN_PKT_LEN;
850 * Bump the reference count on the pbuf to prevent it from being
851 * freed until we are done with it.
855 /* call the actual transmit function */
856 retVal = rpp_eth_send_raw(netif, p);
858 /* Return to prior interrupt state and return. */
859 SYS_ARCH_UNPROTECT(lev);
860 #if !SYS_LIGHTWEIGHT_PROT
869 * When called from rpp_eth_send(), the 'lev' lock is held
871 static err_t rpp_eth_send_raw(struct netif *netif, struct pbuf *pbuf)
876 volatile struct emac_tx_bd *curr_bd;
877 /* Head of the BD chain representing 'active' BDs --
878 * those that are modified/added in this function
880 volatile struct emac_tx_bd *active_head;
881 /* Same as active_head, but this is the tail of the list */
882 volatile struct emac_tx_bd *active_tail;
884 hdkif = (struct hdkif *)netif->state;
885 txch = &(hdkif->txch);
887 /* Get the first BD that is unused and will be used for TX */
888 curr_bd = txch->free_head;
889 active_head = curr_bd;
891 /* Be sure that the free_head didn't wrap around the chain
892 * of all BDs pointing to the BD being processed by the EMAC
893 * (in such case txch->free_head would be the same as
894 * txch->next_bd_to_process)
896 while (curr_bd->flags_pktlen & EMAC_DSC_FLAG_OWNER)
899 /* First 'part' of packet flags */
900 curr_bd->flags_pktlen = pbuf->tot_len |
904 /* Copy pbuf information into TX BDs --
905 * remember that the pbuf for a single packet might be chained!
907 for (q = pbuf; q != NULL; q = q->next) {
908 curr_bd->bufptr = (uint8_t *)(q->payload);
909 curr_bd->bufoff_len = (q->len) & 0xFFFF;
911 active_tail = curr_bd;
912 /* This is an extra field that is not par of the in-HW BD.
913 * This is used when freeing the pbuf after the TX processing
916 curr_bd->pbuf = pbuf;
918 curr_bd = curr_bd->next;
919 curr_bd->flags_pktlen = 0x0;
921 /* Indicate the end of the packet */
922 active_tail->next = NULL;
923 active_tail->flags_pktlen |= EMAC_DSC_FLAG_EOP;
925 /* Since we used the txch->free_head as the first BD for our purpose,
926 * set the new free_head just behind the active_tail
928 txch->free_head = curr_bd;
930 /* For the first time, write the HDP with the filled bd */
931 if (txch->active_tail == NULL) {
932 EMACTxHdrDescPtrWrite(hdkif->emac_base,
933 (unsigned int)(active_head), CHANNEL);
935 /* Chain the bd's. If the DMA engine already reached the
936 * end of the chain, the EOQ will be set. In that case,
937 * the HDP shall be written again.
939 curr_bd = txch->active_tail;
940 curr_bd->next = active_head;
943 /* Just a workaround in case "appending" to
944 * the last active BD will not work
946 while (!(curr_bd->flags_pktlen & EMAC_DSC_FLAG_EOQ))
950 /* We were too slow and the EMAC already read the
951 * 'pNext = NULL' of the former txch->active_tail. In this
952 * case the transmission stopped and we need to write the
953 * pointer to newly added BDs to the TX HDP
955 if (curr_bd->flags_pktlen & EMAC_DSC_FLAG_EOQ) {
956 /* Writes to TX HDP are allowed only when it is 0 */
957 while (HWREG(hdkif->emac_base + EMAC_TXHDP(CHANNEL)) != 0)
959 EMACTxHdrDescPtrWrite(hdkif->emac_base,
960 (unsigned int)(active_head), CHANNEL);
963 txch->active_tail = active_tail;
968 void rpp_eth_send_raw_thr(void *arg)
972 volatile struct emac_tx_bd *curr_bd;
973 volatile struct emac_tx_bd *next_bd_to_process;
974 struct netif *netif = (struct netif*)arg;
976 hdkif = netif->state;
977 txch = &(hdkif->txch);
980 /* Block if there is nothing to do.
981 * Wake up if an TX interrupt occured.
983 xSemaphoreTake(hdkif->goTX, portMAX_DELAY);
985 next_bd_to_process = txch->next_bd_to_process;
986 curr_bd = next_bd_to_process;
988 /* Traverse the list of BDs used for transmission --
989 * stop on the first unused
991 while (curr_bd->flags_pktlen & EMAC_DSC_FLAG_SOP) {
992 /* Make sure the transmission is over */
993 while (curr_bd->flags_pktlen & EMAC_DSC_FLAG_OWNER)
996 /* Find the last chunk of the packet */
997 while (!(curr_bd->flags_pktlen & EMAC_DSC_FLAG_EOP))
998 curr_bd = curr_bd->next;
1000 /* Remove flags for the transmitted BDs */
1001 next_bd_to_process->flags_pktlen &= (~EMAC_DSC_FLAG_SOP);
1002 curr_bd->flags_pktlen &= (~EMAC_DSC_FLAG_EOP);
1004 /* Point the txch->next_bd_to_process to the BDs
1005 * following the 'last BD belonging to the packet
1008 if (curr_bd->next == NULL)
1009 txch->next_bd_to_process = txch->free_head;
1011 txch->next_bd_to_process = curr_bd->next;
1013 /* Ack the Interrupt in the EMAC peripheral */
1014 EMACTxCPWrite(hdkif->emac_base, CHANNEL,
1017 /* Free the corresponding pbuf
1018 * Sidenote: Each fragment of the single packet points
1019 * to the same pbuf // FIXME is it true?
1021 pbuf_free(curr_bd->pbuf);
1023 LINK_STATS_INC(link.xmit);
1025 /* Move to the next packet */
1026 next_bd_to_process = txch->next_bd_to_process;
1027 curr_bd = next_bd_to_process;
1030 /* Ack the Interrupt in the EMAC peripheral */
1031 EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_TX);
1032 //EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_RX); // Proc?
1033 /* Enable the interrupt in the VIM */
1034 vim_mask_set(TXinterruptVectorNumber);
1038 void rpp_eth_recv_raw_thr(void *arg)
1040 struct hdkif *hdkif;
1042 struct netif *netif = (struct netif*)arg;
1043 volatile struct emac_rx_bd *curr_bd;
1044 volatile struct emac_rx_bd *curr_tail;
1045 volatile struct emac_rx_bd *curr_head;
1047 struct pbuf *new_pbuf;
1050 hdkif = netif->state;
1051 rxch = &(hdkif->rxch);
1054 /* Block if there is nothing to do.
1055 * Wake up if an RX interrupt occured.
1058 sys_arch_sem_wait(&(hdkif->goRX), 0);
1060 xSemaphoreTake(hdkif->goRX, portMAX_DELAY);
1062 /* Get the bd which contains the earliest filled data */
1063 curr_bd = rxch->active_head;
1065 /* For each valid frame */
1066 while (curr_bd->flags_pktlen & EMAC_DSC_FLAG_SOP) {
1067 unsigned int total_rx_len;
1068 unsigned int processed_rx_len = 0;
1070 /* Start processing once the packet is released by the EMAC. */
1071 while (curr_bd->flags_pktlen & EMAC_DSC_FLAG_OWNER)
1074 pbuf = curr_bd->pbuf;
1075 total_rx_len = curr_bd->flags_pktlen & 0xFFFF;
1077 /* The received frame might be fragmented into muliple
1078 * pieces -- each one referenced by a separate BD.
1079 * To further process the data, we need to 'make' a
1080 * proper PBUF out of it -- that means linking each
1081 * buffer together, copy the length information form
1082 * the DB to PBUF, calculate the 'tot_len' etc.
1086 /* Since this pbuf will be freed, we need to
1087 * keep track of its size to be able to
1088 * allocate it back again
1090 rxch->freed_pbuf_len += q->len;
1092 /* This is the size of the "received data" not the PBUF */
1093 q->tot_len = total_rx_len - processed_rx_len;
1094 q->len = curr_bd->bufoff_len & 0xFFFF;
1096 if (curr_bd->flags_pktlen & EMAC_DSC_FLAG_EOP)
1099 * If we are executing here, it means this
1100 * packet is being split over multiple BDs
1103 /* chain the pbufs since they belong
1104 * to the same packet
1106 q->next = (curr_bd->next)->pbuf;
1108 processed_rx_len += q->len;
1109 curr_bd = curr_bd->next;
1111 /* Close the chain */
1114 LINK_STATS_INC(link.recv);
1116 /* Process the packet */
1117 /* ethernet_input((struct pbuf *)pbuf, netif) */
1118 if (netif->input((struct pbuf *)pbuf, netif) != ERR_OK) {
1119 LINK_STATS_INC(link.memerr);
1120 LINK_STATS_INC(link.drop);
1123 /* Acknowledge that this packet is processed */
1124 EMACRxCPWrite(hdkif->emac_base, 0, (unsigned int)curr_bd);
1126 curr_head = rxch->active_head;
1127 rxch->active_head = curr_bd->next;
1129 /* The earlier PBUF chain is freed from the upper layer.
1130 * So, we need to allocate a new pbuf chain and update
1131 * the descriptors with the PBUF info.
1132 * Care should be taken even if the allocation fails.
1135 new_pbuf = pbuf_alloc(PBUF_RAW,
1136 rxch->freed_pbuf_len,
1138 if (new_pbuf == NULL) {
1139 /* Cycle until the pbuf is
1140 * succesfully allocated
1142 /* Actively poll to decrease the time
1143 * when the RX interrupts are disabled
1147 curr_tail = curr_bd;
1148 curr_tail->next = NULL;
1149 curr_bd = curr_head;
1152 curr_bd = curr_head;
1156 if (curr_bd == NULL)
1159 curr_bd->bufptr = (uint8_t *)q->payload;
1160 curr_bd->bufoff_len = q->len;
1161 curr_bd->flags_pktlen =
1162 EMAC_DSC_FLAG_OWNER;
1165 rxch->freed_pbuf_len -= q->len;
1167 curr_bd = curr_bd->next;
1170 /* At this point either the whole pbuf
1171 * was used or there are no RX BDs left.
1172 * If there is not enough RX BDs to assign
1173 * all pbufs in the chain, free the
1174 * rest of the pbufs.
1177 pbuf_free((struct pbuf *)q);
1179 /* Add the newly allocated BDs to the
1182 rxch->active_tail->next = curr_head;
1183 /* Check if the reception has ended.
1184 * If the EOQ flag is set, the NULL
1185 * pointer is taken by the DMA engine.
1186 * So we need to write the RX HDP
1187 * with the next descriptor.
1189 if (rxch->active_tail->flags_pktlen &
1192 /* Writes to RX HDP are allowed
1195 while (HWREG(hdkif->emac_base +
1196 EMAC_RXHDP(CHANNEL)) != 0)
1199 EMACRxHdrDescPtrWrite(
1201 (uint32_t)curr_head,
1205 rxch->active_tail = curr_tail;
1209 curr_bd = rxch->active_head;
1212 /* Ack the Interrupt in the EMAC peripheral */
1213 EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_RX);
1214 //EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_TX);
1215 /* Enable the interrupt in the VIM */
1216 vim_mask_set(RXinterruptVectorNumber);
1220 void RxIntHandler(u32_t instNum)
1222 vim_mask_clr(RXinterruptVectorNumber);
1223 /* Unblock the RX task. */
1224 xSemaphoreGiveFromISR(hdkif_data[instNum].goRX, NULL);
1227 void TxIntHandler(u32_t instNum)
1229 vim_mask_clr(TXinterruptVectorNumber); /* see sys_startup.c */
1230 xSemaphoreGiveFromISR(hdkif_data[instNum].goTX, NULL);
1236 * 1h SOP error; the buffer is the first buffer in a packet,
1237 * but the SOP bit is not set in software.
1238 * 2h Ownership bit not set in SOP buffer
1239 * 3h Zero next buffer descriptor pointer without EOP
1240 * 4h Zero buffer pointer
1241 * 5h Zero buffer length
1242 * 6h Packet length error (sum of buffers is less than packet length)
1247 * 2h Ownership bit not set in SOP buffer
1249 * 4h Zero buffer pointer
1251 boolean_t HostPendErrHandler(void)
1253 uint8_t index = MAX_EMAC_INSTANCE;
1254 uint8_t errFound = FALSE;
1256 struct hdkif *hdkif;
1259 hdkif = &hdkif_data[--index];
1261 if (EMACIntVectorGet(hdkif->emac_base) & EMAC_MACINVECTOR_HOSTPEND)
1266 return FALSE; /* this is not the cause of the interrupt */
1268 rpp_sci_printk("HOSTPEND err\n");
1269 reg = HWREG(hdkif->emac_base + EMAC_MACSTATUS);
1270 rpp_sci_printk("TXCHERR: %d at CH: %d\n",
1271 ((reg >> EMAC_MACSTATUS_TXERRCODE_SHIFT) & 0x7),
1272 ((reg >> EMAC_MACSTATUS_TXERRCH_SHIFT) & 0x7));
1273 rpp_sci_printk("RXCHERR: %d at CH: %d\n",
1274 ((reg >> EMAC_MACSTATUS_RXERRCODE_SHIFT) & 0x7),
1275 ((reg >> EMAC_MACSTATUS_RXERRCH_SHIFT) & 0x7));
1277 { /* Print out all the RX BDs */
1279 volatile struct emac_rx_bd *curr_bd;
1280 rxch = &(hdkif->rxch);
1283 rpp_sci_printk("rxch->active_head: %p\n", rxch->active_head);
1284 rpp_sci_printk("rxch->active_tail: %p\n", rxch->active_tail);
1285 rpp_sci_printk("rxch->freed_pbuf_len: %p\n", rxch->freed_pbuf_len);
1286 rpp_sci_printk("RXCP: 0x%x\n", *((uint32_t*)(hdkif->emac_base + EMAC_RXCP(0))));
1288 for (curr_bd = rxch->active_head; curr_bd != 0; curr_bd = curr_bd->next) {
1289 glob_len += curr_bd->pbuf->len;
1291 rpp_sci_printk("[%p: buf: %p buffoff_len: 0x%x "
1292 "\tflags: 0x%x pktlen: 0x%x]",
1295 curr_bd->bufoff_len,
1296 (curr_bd->flags_pktlen >> 16) & 0xFFFF,
1297 curr_bd->flags_pktlen & 0xFFFF);
1298 rpp_sci_printk(" pbuf: tot_len: 0x%x \tlen: 0x%x ref: 0x%x\n",
1299 curr_bd->pbuf->tot_len,
1301 curr_bd->pbuf->ref);
1303 rpp_sci_printk("glob_len: %d\n", glob_len);
1306 /* no acknowledge - emac module has to be restarted */
1308 /* this was the reason of interrupt */
1312 #if PHY_LINK_MONITOR_INT
1313 boolean_t LinkIntHandler(void)
1315 uint8_t index = MAX_EMAC_INSTANCE;
1316 uint8_t phyFound = FALSE;
1317 struct hdkif *hdkif;
1318 uint16_t regContent;
1319 volatile unsigned int autonegFinishWait = 0xFFFFFFF;
1320 volatile unsigned int dhcpBindWait = 0x3FFFFFFF;
1322 /* check each instance, whether this interrupt was meant for this
1323 * function, if not return FALSE so other function may be tried
1326 hdkif = &hdkif_data[--index];
1327 if ((hdkif->phy_addr ==
1328 (HWREG(hdkif->mdio_base + MDIO_USERPHYSEL0) & 0x1f)) &&
1329 (EMACIntVectorGet(hdkif->emac_base) &
1330 EMAC_MACINVECTOR_LINKINT0))
1335 struct netif *netif = &hdkNetIF[hdkif->inst_num];
1337 /* we handle here connection of cable after startup, not changes of linkstatus */
1339 /* wait for autonegotiation to be done */
1341 while (hdkif->phy_autoneg_is_done(hdkif->mdio_base, hdkif->phy_addr) ==
1344 #else /* ONCE_LINK_SETUP */
1345 while (hdkif->phy_autoneg_is_done(hdkif->mdio_base, hdkif->phy_addr) ==
1346 FALSE & autonegFinishWait--)
1348 #endif /* ONCE_LINK_SETUP */
1350 /* provide informations retrieved from autoneg to EMAC module */
1351 hdkif->phy_partnerability(hdkif->mdio_base, hdkif->phy_addr, ®Content);
1352 if (regContent & (PHY_100BASETXDUPL_m | PHY_10BASETDUPL_m)) {
1353 EMACDuplexSet(hdkif->emac_base, EMAC_DUPLEX_FULL);
1354 /* this is right place to implement transmit flow control
1355 * if desired - set TXFLOWEN in MACCONTROL
1357 } else if (regContent & (PHY_100BASETX_m | PHY_10BASET_m)) {
1358 EMACDuplexSet(hdkif->emac_base, EMAC_DUPLEX_HALF);
1360 /* acknowledge MDIO module */
1361 HWREG(hdkif->mdio_base + MDIO_LINKINTRAW) =
1362 MDIO_LINKINTMASKED_USERPHY0;
1363 HWREG(hdkif->mdio_base + MDIO_LINKINTMASKED) =
1364 MDIO_LINKINTMASKED_USERPHY0;
1366 /* acknowledge EMAC control module by writing
1367 * appropriate key to MACEOIVECTOR
1369 EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_MISC);
1372 /* if link is up configure lwip struct netif */
1373 if (rpp_eth_phylinkstat(hdkif->inst_num)) {
1374 #if STATIC_IP_ADDRESS
1375 netif_set_up(netif);
1376 #elif LWIP_DHCP /* STATIC_IP_ADDRESS-LWIP_DHCP */
1377 if (dhcp_start(netif) != ERR_OK) /* XXX: can't be used from ISR (mem_malloc()) */
1378 return DHCP_MEM_ERR;
1381 while (netif->dhcp->state != DHCP_BOUND)
1384 while (netif->dhcp->state != DHCP_BOUND & dhcpBindWait--)
1386 if (!dhcpBindWait) {
1387 /* acknowledge MDIO module */
1388 HWREG(hdkif->mdio_base + MDIO_LINKINTRAW) =
1389 MDIO_LINKINTMASKED_USERPHY0;
1390 HWREG(hdkif->mdio_base + MDIO_LINKINTMASKED) =
1391 MDIO_LINKINTMASKED_USERPHY0;
1393 /* acknowledge EMAC control module by writing
1394 * appropriate key to MACEOIVECTOR
1396 EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_MISC);
1400 #else /* LWIP_DHCP-LWIP_AUTOIP FIXME: there should be some kind of waiting till ip is assigned */
1401 autoip_start(netif);
1402 #endif /* STATIC_IP_ADDRESS-LWIP_DHCP-LWIP_AUTOIP */
1404 /* turn this interrupt off */
1405 HWREG(hdkif->emac_ctrl_base + EMAC_CTRL_CnMISCEN(0)) &=
1406 (~EMAC_CTRL_MISC_LINKINT0ENB & 0xf);
1407 #endif /* ONCE_LINK_SETUP */
1410 /* acknowledge MDIO module */
1411 HWREG(hdkif->mdio_base + MDIO_LINKINTRAW) =
1412 MDIO_LINKINTMASKED_USERPHY0;
1413 HWREG(hdkif->mdio_base + MDIO_LINKINTMASKED) =
1414 MDIO_LINKINTMASKED_USERPHY0;
1416 /* acknowledge EMAC control module by writing
1417 * appropriate key to MACEOIVECTOR
1419 EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_MISC);
1422 #if STATIC_IP_ADDRESS
1423 netif_set_down(netif);
1424 #elif LWIP_DHCP /* STATIC_IP_ADDRESS-LWIP_DHCP */
1426 #endif /* STATIC_IP_ADDRESS-LWIP_DHCP-LWIP_AUTOIP */
1430 /* acknowledge MDIO module */
1431 HWREG(hdkif->mdio_base + MDIO_LINKINTRAW) =
1432 MDIO_LINKINTMASKED_USERPHY0;
1433 HWREG(hdkif->mdio_base + MDIO_LINKINTMASKED) =
1434 MDIO_LINKINTMASKED_USERPHY0;
1436 /* acknowledge EMAC control module by writing appropriate key to MACEOIVECTOR */
1437 EMACCoreIntAck(hdkif->emac_base, EMAC_INT_CORE0_MISC);
1441 #endif /* PHY_LINK_MONITOR_INT */
1442 #endif /* FREERTOS_POSIX */