2 * @brief ADC Driver Header File
9 * - Interface Prototypes
11 * which are relevant for the ADC driver.
19 /* ADC General Definitions */
22 * @brief Alias name for ADC event group
24 * @note This value should be used for API argument @a group
29 * @brief Alias name for ADC group 1
31 * @note This value should be used for API argument @a group
36 * @brief Alias name for ADC group 2
38 * @note This value should be used for API argument @a group
42 /** @enum adcResolution
43 * @brief Alias names for data resolution
44 * This enumeration is used to provide alias names for the data resolution:
52 ADC_12_BIT = 0x00000000, /**< Alias for 12 bit data resolution */
53 ADC_10_BIT = 0x00000100, /**< Alias for 10 bit data resolution */
54 ADC_8_BIT = 0x00000200 /**< Alias for 8 bit data resolution */
57 /** @enum adcFiFoStatus
58 * @brief Alias names for FiFo status
59 * This enumeration is used to provide alias names for the current FiFo states:
62 * - FiFo overflow occured
67 ADC_FIFO_IS_NOT_FULL = 0, /**< Alias for FiFo is not full */
68 ADC_FIFO_IS_FULL = 1, /**< Alias for FiFo is full */
69 ADC_FIFO_OVERFLOW = 3 /**< Alias for FiFo overflow occured */
72 /** @enum adcConversionStatus
73 * @brief Alias names for conversion status
74 * This enumeration is used to provide alias names for the current conversion states:
75 * - Conversion is not finished
76 * - Conversion is finished
79 enum adcConversionStatus
81 ADC_CONVERSION_IS_NOT_FINISHED = 0, /**< Alias for current conversion is not finished */
82 ADC_CONVERSION_IS_FINISHED = 8 /**< Alias for current conversion is finished */
85 /** @enum adc1HwTriggerSource
86 * @brief Alias names for hardware trigger source
87 * This enumeration is used to provide alias names for the hardware trigger sources:
90 enum adc1HwTriggerSource
92 ADC1_EVENT = 0, /**< Alias for event pin */
93 ADC1_HET1_8 = 1, /**< Alias for HET1 pin 8 */
94 ADC1_HET1_10 = 2, /**< Alias for HET1 pin 10 */
95 ADC1_RTI_COMP0 = 3, /**< Alias for RTI compare 0 match */
96 ADC1_HET1_12 = 4, /**< Alias for HET1 pin 12 */
97 ADC1_HET1_14 = 5, /**< Alias for HET1 pin 14 */
98 ADC1_GIOB0 = 6, /**< Alias for GIO port b pin 0 */
99 ADC1_GIOB1 = 7, /**< Alias for GIO port b pin 1 */
101 ADC1_HET2_5 = 1, /**< Alias for HET2 pin 5 */
102 ADC1_HET1_27 = 2, /**< Alias for HET1 pin 27 */
103 ADC1_HET1_17 = 4, /**< Alias for HET1 pin 17 */
104 ADC1_HET1_19 = 5, /**< Alias for HET1 pin 19 */
105 ADC1_HET1_11 = 6, /**< Alias for HET1 pin 11 */
106 ADC1_HET2_13 = 7, /**< Alias for HET2 pin 13 */
108 ADC1_EPWM_B = 1, /**< Alias for B Signal EPWM */
109 ADC1_EPWM_A1 = 3, /**< Alias for A1 Signal EPWM */
110 ADC1_HET2_1 = 5, /**< Alias for HET2 pin 1 */
111 ADC1_EPWM_A2 = 6, /**< Alias for A2 Signal EPWM */
112 ADC1_EPWM_AB = 7 /**< Alias for AB Signal EPWM */
116 /** @enum adc2HwTriggerSource
117 * @brief Alias names for hardware trigger source
118 * This enumeration is used to provide alias names for the hardware trigger sources:
121 enum adc2HwTriggerSource
123 ADC2_EVENT = 0, /**< Alias for event pin */
124 ADC2_HET1_8 = 1, /**< Alias for HET1 pin 8 */
125 ADC2_HET1_10 = 2, /**< Alias for HET1 pin 10 */
126 ADC2_RTI_COMP0 = 3, /**< Alias for RTI compare 0 match */
127 ADC2_HET1_12 = 4, /**< Alias for HET1 pin 12 */
128 ADC2_HET1_14 = 5, /**< Alias for HET1 pin 14 */
129 ADC2_GIOB0 = 6, /**< Alias for GIO port b pin 0 */
130 ADC2_GIOB1 = 7, /**< Alias for GIO port b pin 1 */
131 ADC2_HET2_5 = 1, /**< Alias for HET2 pin 5 */
132 ADC2_HET1_27 = 2, /**< Alias for HET1 pin 27 */
133 ADC2_HET1_17 = 4, /**< Alias for HET1 pin 17 */
134 ADC2_HET1_19 = 5, /**< Alias for HET1 pin 19 */
135 ADC2_HET1_11 = 6, /**< Alias for HET1 pin 11 */
136 ADC2_HET2_13 = 7, /**< Alias for HET2 pin 13 */
138 ADC2_EPWM_B = 1, /**< Alias for B Signal EPWM */
139 ADC2_EPWM_A1 = 3, /**< Alias for A1 Signal EPWM */
140 ADC2_HET2_1 = 5, /**< Alias for HET2 pin 1 */
141 ADC2_EPWM_A2 = 6, /**< Alias for A2 Signal EPWM */
142 ADC2_EPWM_AB = 7 /**< Alias for AB Signal EPWM */
147 * @brief ADC Conversion data structure
149 * This type is used to pass adc conversion data.
151 /** @typedef adcData_t
152 * @brief ADC Data Type Definition
154 typedef struct adcData
156 uint32_t id; /**< Channel/Pin Id */
157 uint16_t value; /**< Conversion data value */
161 * @brief ADC Register Frame Definition
163 * This type is used to access the ADC Registers.
165 /** @typedef adcBASE_t
166 * @brief ADC Register Frame Type Definition
168 * This type is used to access the ADC Registers.
170 typedef volatile struct adcBase
172 uint32_t RSTCR; /**< 0x0000: Reset control register */
173 uint32_t OPMODECR; /**< 0x0004: Operating mode control register */
174 uint32_t CLOCKCR; /**< 0x0008: Clock control register */
175 uint32_t CALCR; /**< 0x000C: Calibration control register */
176 uint32_t GxMODECR[3U]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */
177 uint32_t G0SRC; /**< 0x001C: Group 0 trigger source control register */
178 uint32_t G1SRC; /**< 0x0020: Group 1 trigger source control register */
179 uint32_t G2SRC; /**< 0x0024: Group 2 trigger source control register */
180 uint32_t GxINTENA[3U]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register */
181 uint32_t GxINTFLG[3U]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */
182 uint32_t GxINTCR[3U]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */
183 uint32_t G0DMACR; /**< 0x004C: Group 0 DMA control register */
184 uint32_t G1DMACR; /**< 0x0050: Group 1 DMA control register */
185 uint32_t G2DMACR; /**< 0x0054: Group 2 DMA control register */
186 uint32_t BNDCR; /**< 0x0058: Buffer boundary control register */
187 #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
188 uint32_t BNDEND : 16U; /**< 0x005C: Buffer boundary end register */
189 uint32_t BUFINIT : 16U; /**< 0x005C: Buffer initialization register */
191 uint32_t BUFINIT : 16U; /**< 0x005C: Buffer initialization register */
192 uint32_t BNDEND : 16U; /**< 0x005C: Buffer boundary end register */
194 uint32_t G0SAMP; /**< 0x0060: Group 0 sample window register */
195 uint32_t G1SAMP; /**< 0x0064: Group 1 sample window register */
196 uint32_t G2SAMP; /**< 0x0068: Group 2 sample window register */
197 uint32_t G0SR; /**< 0x006C: Group 0 status register */
198 uint32_t G1SR; /**< 0x0070: Group 1 status register */
199 uint32_t G2SR; /**< 0x0074: Group 2 status register */
200 uint32_t GxSEL[3U]; /**< 0x0078-0x007C: Group 0-2 channel select register */
201 uint32_t CALR; /**< 0x0084: Calibration register */
202 uint32_t SMSTATE; /**< 0x0088: State machine state register */
203 uint32_t LASTCONV; /**< 0x008C: Last conversion register */
206 uint32_t BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */
207 uint32_t BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */
208 uint32_t BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */
209 uint32_t BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */
210 uint32_t BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */
211 uint32_t BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */
212 uint32_t BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */
213 uint32_t BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */
215 uint32_t G0EMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */
216 uint32_t G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */
217 uint32_t G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */
218 uint32_t EVTDIR; /**< 0x00FC: Event pin direction register */
219 uint32_t EVTOUT; /**< 0x0100: Event pin digital output register */
220 uint32_t EVTIN; /**< 0x0104: Event pin digital input register */
221 uint32_t EVTSET; /**< 0x0108: Event pin set register */
222 uint32_t EVTCLR; /**< 0x010C: Event pin clear register */
223 uint32_t EVTPDR; /**< 0x0110: Event pin open drain register */
224 uint32_t EVTDIS; /**< 0x0114: Event pin pull disable register */
225 uint32_t EVTPSEL; /**< 0x0118: Event pin pull select register */
226 uint32_t G0SAMPDISEN; /**< 0x011C: Group 0 sample discharge register */
227 uint32_t G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */
228 uint32_t G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */
229 uint32_t MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */
230 uint32_t MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */
231 uint32_t MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */
232 uint32_t MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */
233 uint32_t MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */
234 uint32_t MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */
235 uint32_t MAGINTCR4; /**< 0x0140: Magnitude interrupt control register 4 */
236 uint32_t MAGINT4MASK; /**< 0x0144: Magnitude interrupt mask register 4 */
237 uint32_t MAGINTCR5; /**< 0x0148: Magnitude interrupt control register 5 */
238 uint32_t MAGINT5MASK; /**< 0x014C: Magnitude interrupt mask register 5 */
239 uint32_t MAGINTCR6; /**< 0x0150: Magnitude interrupt control register 6 */
240 uint32_t MAGINT6MASK; /**< 0x0154: Magnitude interrupt mask register 6 */
241 uint32_t MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */
242 uint32_t MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */
243 uint32_t MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */
244 uint32_t MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */
245 uint32_t GxFIFORESETCR[3U]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register */
246 uint32_t G0RAMADDR; /**< 0x0174: Group 0 RAM pointer register */
247 uint32_t G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */
248 uint32_t G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */
249 uint32_t PARCR; /**< 0x0180: Parity control register */
250 uint32_t PARADDR; /**< 0x0184: Parity error address register */
251 uint32_t PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */
256 * @brief ADC1 Register Frame Pointer
258 * This pointer is used by the ADC driver to access the ADC1 registers.
260 #define adcREG1 ((adcBASE_t *)0xFFF7C000U)
263 * @brief ADC2 Register Frame Pointer
265 * This pointer is used by the ADC driver to access the ADC2 registers.
267 #define adcREG2 ((adcBASE_t *)0xFFF7C200U)
270 * @brief ADC1 RAM Pointer
272 * This pointer is used by the ADC driver to access the ADC1 RAM.
274 #define adcRAM1 (*(unsigned int *)0xFF3E0000U)
277 * @brief ADC2 RAM Pointer
279 * This pointer is used by the ADC driver to access the ADC2 RAM.
281 #define adcRAM2 (*(unsigned int *)0xFF3A0000U)
284 * @brief ADC1 Parity RAM Pointer
286 * This pointer is used by the ADC driver to access the ADC1 Parity RAM.
288 #define adcPARRAM1 (*(unsigned int *)(0xFF3E0000U + 0x1000))
291 * @brief ADC2 Parity RAM Pointer
293 * This pointer is used by the ADC driver to access the ADC2 Parity RAM.
295 #define adcPARRAM2 (*(unsigned int *)(0xFF3A0000U + 0x1000))
297 /* ADC Interface Functions */
300 void adcStartConversion(adcBASE_t *adc, uint32_t group);
301 void adcStopConversion(adcBASE_t *adc, uint32_t group);
302 void adcResetFiFo(adcBASE_t *adc, uint32_t group);
303 uint32_t adcGetData(adcBASE_t *adc, uint32_t group, adcData_t *data);
304 uint32_t adcIsFifoFull(adcBASE_t *adc, uint32_t group);
305 uint32_t adcIsConversionComplete(adcBASE_t *adc, uint32_t group);
306 void adcEnableNotification(adcBASE_t *adc, uint32_t group);
307 void adcDisableNotification(adcBASE_t *adc, uint32_t group);
308 void adcCalibration(adcBASE_t *adc);
309 uint32_t adcMidPointCalibration(adcBASE_t *adc);
311 /** @fn void adcNotification(adcBASE_t *adc, uint32_t group)
312 * @brief Group notification
313 * @param[in] adc Pointer to ADC node:
314 * - adcREG1: ADC1 module pointer
315 * - adcREG2: ADC2 module pointer
316 * @param[in] group number of ADC node:
317 * - adcGROUP0: ADC event group
318 * - adcGROUP1: ADC group 1
319 * - adcGROUP2: ADC group 2
321 * @note This function has to be provide by the user.
323 void adcNotification(adcBASE_t *adc, uint32_t group);