8 #include "drv/fr_tms570.h"
9 #include "sys/ti_drv_fray.h"
13 Std_VersionInfoType Fr_versionInfo = {
14 .vendorID = 0x00000001,
15 .moduleID = 0x00000002,
16 .sw_major_version = 0,
17 .sw_minor_version = 1,
21 const uint32_t* Fr_ConfigParPtrs[FR_CIDX_CNT];
22 const Fr_ConfigType* Fr_Config;
23 const Fr_TMS570LS_BufferConfigType* Fr_BuffersPtrs[FR_MAX_BUFFERS_CNT]; /** < Array of address of configuration data to each buffer. */
24 boolean_t Fr_BuffersConfigured[FR_MAX_BUFFERS_CNT]; /**< Array of flags to determine if the buffer was or was not configured. */
25 int Fr_MsgRAMDataPtrs[FR_MAX_BUFFERS_CNT]; /**< Array of computed data pointers addresses for each buffer. */
26 uint32_t Fr_MsgRAMDataOffset; /**< Address of the next free position in message RAM, which can be assigned to configured buffer. Addresses 32b words. */
27 uint32_t Fr_MsgRAMDataStartAddress; /**< Address of the first free position in message RAM, which can be assigned to the first configured buffer. Addresses 32b words. */
28 Fr_POCStatusType Fr_POCStatus;
30 boolean_t Fr_Initialized = FALSE;
33 /** @fn wait_for_POC_ready(void)
34 * @brief Wait until POC is not busy
36 void Fr_wait_for_POC_ready() {
37 // Wait for PBSY bit to clear - POC not busy.
38 // 1: Signals that the POC is busy and cannot accept a command from the host. CMD(3-0) is locked against write accesses.
39 while(((frayREG->SUCC1_UN.SUCC1_UL) & 0x00000080) != 0);
43 * @brief Switch POC to config state from any other state
45 * After command to switch into config state is passed into CHI,
46 * the response is checked and if POC has reacted on the command,
47 * the function is waiting until POC is ready
49 * @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
51 Std_ReturnType Fr_POC_go_to_config() {
52 // write SUCC1 configuration
53 frayREG->SUCC1_UN.SUCC1_UL = 0x0F1FFB00 | CMD_CONFIG;
54 // Check if POC has accepted last command
55 if ((frayREG->SUCC1_UN.SUCC1_UL & 0xF) == 0x0)
57 // Wait for PBSY bit to clear - POC not busy
58 Fr_wait_for_POC_ready();
63 * @brief Copy cluster config parameters into FlexRay configuration registers.
65 * This function does not check values ranges. This is a responsibility of higher
66 * layers. Cluster configuration parameters are copied from data structure
67 * into right bit position in configuration registers.
69 * @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
71 void Fr_config_cluster_parameters(const Fr_TMS570LS_ClusterConfigType* clusterConfigPtr) {
72 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CSA_MSK , frayREG->SUCC1_UN.SUCC1_UL, clusterConfigPtr->gColdStartAttempts);
73 frayREG->GTUC9_UN.GTUC9_UL = __insval2mfld(GTUC9_APO_MSK , frayREG->GTUC9_UN.GTUC9_UL, clusterConfigPtr->gdActionPointOffset);
74 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_CASM_MSK, frayREG->PRTC1_UN.PRTC1_UL, clusterConfigPtr->gdCASRxLowMax);
75 frayREG->GTUC9_UN.GTUC9_UL = __insval2mfld(GTUC9_DSI_MSK , frayREG->GTUC9_UN.GTUC9_UL, clusterConfigPtr->gdDynamicSlotIdlePhase);
76 frayREG->GTUC8_UN.GTUC8_UL = __insval2mfld(GTUC8_MSL_MSK , frayREG->GTUC8_UN.GTUC8_UL, clusterConfigPtr->gdMinislot);
77 frayREG->GTUC9_UN.GTUC9_UL = __insval2mfld(GTUC9_MAPO_MSK, frayREG->GTUC9_UN.GTUC9_UL, clusterConfigPtr->gdMinislotActionPointOffset);
78 frayREG->GTUC7_UN.GTUC7_UL = __insval2mfld(GTUC7_SSL_MSK , frayREG->GTUC7_UN.GTUC7_UL, clusterConfigPtr->gdStaticSlot);
79 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_TSST_MSK, frayREG->PRTC1_UN.PRTC1_UL, clusterConfigPtr->gdTSSTransmitter);
80 frayREG->PRTC2_UN.PRTC2_UL = __insval2mfld(PRTC2_RXI_MSK , frayREG->PRTC2_UN.PRTC2_UL, clusterConfigPtr->gdWakeupSymbolRxIdle);
81 frayREG->PRTC2_UN.PRTC2_UL = __insval2mfld(PRTC2_RXL_MSK , frayREG->PRTC2_UN.PRTC2_UL, clusterConfigPtr->gdWakeupSymbolRxLow);
82 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_RXW_MSK , frayREG->PRTC1_UN.PRTC1_UL, clusterConfigPtr->gdWakeupSymbolRxWindow);
83 frayREG->PRTC2_UN.PRTC2_UL = __insval2mfld(PRTC2_TXI_MSK , frayREG->PRTC2_UN.PRTC2_UL, clusterConfigPtr->gdWakeupSymbolTxIdle);
84 frayREG->PRTC2_UN.PRTC2_UL = __insval2mfld(PRTC2_TXL_MSK , frayREG->PRTC2_UN.PRTC2_UL, clusterConfigPtr->gdWakeupSymbolTxLow);
85 frayREG->SUCC2_UN.SUCC2_UL = __insval2mfld(SUCC2_LTN_MSK , frayREG->SUCC2_UN.SUCC2_UL, clusterConfigPtr->gListenNoise);
86 frayREG->GTUC2_UN.GTUC2_UL = __insval2mfld(GTUC2_MPC_MSK , frayREG->GTUC2_UN.GTUC2_UL, clusterConfigPtr->gMacroPerCycle);
87 frayREG->SUCC3_UN.SUCC3_UL = __insval2mfld(SUCC3_WCF_MSK , frayREG->SUCC3_UN.SUCC3_UL, clusterConfigPtr->gMaxWithoutClockCorrectionFatal);
88 frayREG->SUCC3_UN.SUCC3_UL = __insval2mfld(SUCC3_WCP_MSK , frayREG->SUCC3_UN.SUCC3_UL, clusterConfigPtr->gMaxWithoutClockCorrectionPassive);
89 frayREG->GTUC8_UN.GTUC8_UL = __insval2mfld(GTUC8_NMS_MSK , frayREG->GTUC8_UN.GTUC8_UL, clusterConfigPtr->gNumberOfMinislots);
90 frayREG->GTUC7_UN.GTUC7_UL = __insval2mfld(GTUC7_NSS_MSK , frayREG->GTUC7_UN.GTUC7_UL, clusterConfigPtr->gNumberOfStaticSlots);
91 frayREG->GTUC4_UN.GTUC4_UL = __insval2mfld(GTUC4_OCS_MSK , frayREG->GTUC4_UN.GTUC4_UL, clusterConfigPtr->gOffsetCorrectionStart);
92 frayREG->MHDC_UN.MHDC_UL = __insval2mfld(MHDC_SFDL_MSK , frayREG->MHDC_UN.MHDC_UL , clusterConfigPtr->gPayloadLengthStatic);
93 frayREG->GTUC2_UN.GTUC2_UL = __insval2mfld(GTUC2_SNM_MSK , frayREG->GTUC2_UN.GTUC2_UL, clusterConfigPtr->gSyncNodeMax);
95 frayREG->GTUC4_UN.GTUC4_UL = __insval2mfld(GTUC4_NIT_MSK , frayREG->GTUC4_UN.GTUC4_UL, clusterConfigPtr->gdNIT);
96 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_BRP_MSK , frayREG->PRTC1_UN.PRTC1_UL, clusterConfigPtr->gdSampleClockPeriod);
97 frayREG->NEMC_UN.NEMC_UL = __insval2mfld(NEMC_NML_MSK , frayREG->NEMC_UN.NEMC_UL , clusterConfigPtr->gNetworkManagementVectorLength);
100 #define __notInRange(val, min, max) (((val) < (min)) || ((val) > (max)))
103 * @brief Check cluster configuration parameters.
105 * This function checks values of the cluster configuration parameters,
106 * if they are in ranges noted in FlexRay specification.
108 * @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
109 * @param [out] errCode Address where error flags will be stored.
110 * We have 26 parameters to check. Every one of them has assigned its bit in this flag.
111 * Error flags are defined as macros ERR_PARAM_nameOfParameter.
112 * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
114 Std_ReturnType Fr_check_cluster_parameters(const Fr_TMS570LS_ClusterConfigType* clusterConfigPtr, uint32_t* errCode) {
115 *errCode = ERR_PARAM_NO_ERROR;
117 if (__notInRange(clusterConfigPtr->gColdStartAttempts, 2, 31)) *errCode |= ERR_PARAM_gColdStartAttempts;
118 if (__notInRange(clusterConfigPtr->gdActionPointOffset, 1, 63)) *errCode |= ERR_PARAM_gdActionPointOffset;
119 if (__notInRange(clusterConfigPtr->gdCASRxLowMax, 67, 99)) *errCode |= ERR_PARAM_gdCASRxLowMax;
120 if (clusterConfigPtr->gdDynamicSlotIdlePhase > 2) *errCode |= ERR_PARAM_gdDynamicSlotIdlePhase;
121 if (__notInRange(clusterConfigPtr->gdMinislot, 2, 63)) *errCode |= ERR_PARAM_gdMinislot;
122 if (__notInRange(clusterConfigPtr->gdMinislotActionPointOffset,
123 1, 31)) *errCode |= ERR_PARAM_gdMinislotActionPointOffset;
124 if (__notInRange(clusterConfigPtr->gdStaticSlot, 4, 661)) *errCode |= ERR_PARAM_gdStaticSlot;
125 if (__notInRange(clusterConfigPtr->gdTSSTransmitter, 3, 15)) *errCode |= ERR_PARAM_gdTSSTransmitter;
126 if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxIdle, 14, 59)) *errCode |= ERR_PARAM_gdWakeupSymbolRxIdle;
127 if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxLow, 11, 59)) *errCode |= ERR_PARAM_gdWakeupSymbolRxLow;
128 if (__notInRange(clusterConfigPtr->gdWakeupSymbolRxWindow,
129 76, 301)) *errCode |= ERR_PARAM_gdWakeupSymbolRxWindow;
130 if (__notInRange(clusterConfigPtr->gdWakeupSymbolTxIdle, 45, 180)) *errCode |= ERR_PARAM_gdWakeupSymbolTxIdle;
131 if (__notInRange(clusterConfigPtr->gdWakeupSymbolTxLow, 15, 60)) *errCode |= ERR_PARAM_gdWakeupSymbolTxLow;
132 if (__notInRange(clusterConfigPtr->gListenNoise, 2, 16)) *errCode |= ERR_PARAM_gListenNoise;
133 if (__notInRange(clusterConfigPtr->gMacroPerCycle, 10, 16000)) *errCode |= ERR_PARAM_gMacroPerCycle;
134 if (__notInRange(clusterConfigPtr->gMaxWithoutClockCorrectionFatal,
135 clusterConfigPtr->gMaxWithoutClockCorrectionPassive, 15)) *errCode |= ERR_PARAM_gMaxWithoutClockCorrectionFatal;
136 if (__notInRange(clusterConfigPtr->gMaxWithoutClockCorrectionPassive,
137 1, 15)) *errCode |= ERR_PARAM_gMaxWithoutClockCorrectionPassive;
138 if (clusterConfigPtr->gNumberOfMinislots > 7986) *errCode |= ERR_PARAM_gNumberOfMinislots;
139 if (__notInRange(clusterConfigPtr->gNumberOfStaticSlots,
140 2, cStaticSlotIDMax)) *errCode |= ERR_PARAM_gNumberOfStaticSlots;
141 if (__notInRange(clusterConfigPtr->gOffsetCorrectionStart,
142 9, 15999)) *errCode |= ERR_PARAM_gOffsetCorrectionStart;
143 if (clusterConfigPtr->gPayloadLengthStatic > cPayloadLengthMax) *errCode |= ERR_PARAM_gPayloadLengthStatic;
144 if (__notInRange(clusterConfigPtr->gSyncNodeMax, 2, cSyncNodeMax)) *errCode |= ERR_PARAM_gSyncNodeMax;
145 if (__notInRange(clusterConfigPtr->gdNIT, 2, 805)) *errCode |= ERR_PARAM_gdNIT;
146 if (clusterConfigPtr->gdSampleClockPeriod > 2) *errCode |= ERR_PARAM_gdSampleClockPeriod;
147 if (clusterConfigPtr->gNetworkManagementVectorLength > 12) *errCode |= ERR_PARAM_gNetworkManagementVectorLength;
149 return (*errCode == 0) ? E_OK : E_NOT_OK;
153 * @brief Copy node config parameters into FlexRay configuration registers.
155 * This function does not check values ranges. This is a responsibility of higher
156 * layers. Node configuration parameters are copied from data structure
157 * into right bit position in configuration registers.
159 * @param [in] nodeConfigPtr Address of structure with node configuration parameters
161 void Fr_config_node_parameters(const Fr_TMS570LS_NodeConfigType* nodeConfigPtr) {
162 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_HCSE_MSK, frayREG->SUCC1_UN.SUCC1_UL, nodeConfigPtr->pAllowHaltDueToClock);
163 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_PTA_MSK, frayREG->SUCC1_UN.SUCC1_UL, nodeConfigPtr->pAllowPassiveToActive);
164 if (nodeConfigPtr->pChannels == FR_CHANNEL_AB) {
165 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHA_MSK, frayREG->SUCC1_UN.SUCC1_UL, 1);
166 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHB_MSK, frayREG->SUCC1_UN.SUCC1_UL, 1);
169 else if (nodeConfigPtr->pChannels == FR_CHANNEL_A) {
170 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHA_MSK, frayREG->SUCC1_UN.SUCC1_UL, 1);
171 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHB_MSK, frayREG->SUCC1_UN.SUCC1_UL, 0);
174 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHA_MSK, frayREG->SUCC1_UN.SUCC1_UL, 0);
175 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_CCHB_MSK, frayREG->SUCC1_UN.SUCC1_UL, 1);
177 frayREG->GTUC6_UN.GTUC6_UL = __insval2mfld(GTUC6_ASR_MSK , frayREG->GTUC6_UN.GTUC6_UL , nodeConfigPtr->pdAcceptedStartupRange);
178 frayREG->GTUC5_UN.GTUC5_UL = __insval2mfld(GTUC5_CDD_MSK , frayREG->GTUC5_UN.GTUC5_UL , nodeConfigPtr->pClusterDriftDamping);
179 frayREG->GTUC5_UN.GTUC5_UL = __insval2mfld(GTUC5_DCA_MSK , frayREG->GTUC5_UN.GTUC5_UL , nodeConfigPtr->pDelayCompensationA);
180 frayREG->GTUC5_UN.GTUC5_UL = __insval2mfld(GTUC5_DCB_MSK , frayREG->GTUC5_UN.GTUC5_UL , nodeConfigPtr->pDelayCompensationB);
181 frayREG->SUCC2_UN.SUCC2_UL = __insval2mfld(SUCC2_LT_MSK , frayREG->SUCC2_UN.SUCC2_UL , nodeConfigPtr->pdListenTimeout);
182 frayREG->GTUC6_UN.GTUC6_UL = __insval2mfld(GTUC6_MOD_MSK , frayREG->GTUC6_UN.GTUC6_UL , nodeConfigPtr->pdMaxDrift);
183 frayREG->GTUC11_UN.GTUC11_UL = __insval2mfld(GTUC11_EOC_MSK, frayREG->GTUC11_UN.GTUC11_UL, nodeConfigPtr->pExternOffsetCorrection);
184 frayREG->GTUC11_UN.GTUC11_UL = __insval2mfld(GTUC11_ERC_MSK, frayREG->GTUC11_UN.GTUC11_UL, nodeConfigPtr->pExternRateCorrection);
185 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_TXST_MSK, frayREG->SUCC1_UN.SUCC1_UL , nodeConfigPtr->pKeySlotUsedForStartup);
186 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_TXSY_MSK, frayREG->SUCC1_UN.SUCC1_UL , nodeConfigPtr->pKeySlotUsedForSync);
187 frayREG->MHDC_UN.MHDC_UL = __insval2mfld(MHDC_SLT_MSK , frayREG->MHDC_UN.MHDC_UL , nodeConfigPtr->pLatestTx);
188 frayREG->GTUC3_UN.GTUC3_UL = __insval2mfld(GTUC3_MIOA_MSK, frayREG->GTUC3_UN.GTUC3_UL , nodeConfigPtr->pMacroInitialOffsetA);
189 frayREG->GTUC3_UN.GTUC3_UL = __insval2mfld(GTUC3_MIOB_MSK, frayREG->GTUC3_UN.GTUC3_UL , nodeConfigPtr->pMacroInitialOffsetB);
190 frayREG->GTUC3_UN.GTUC3_UL = __insval2mfld(GTUC3_UIOA_MSK, frayREG->GTUC3_UN.GTUC3_UL , nodeConfigPtr->pMicroInitialOffsetA);
191 frayREG->GTUC3_UN.GTUC3_UL = __insval2mfld(GTUC3_UIOB_MSK, frayREG->GTUC3_UN.GTUC3_UL , nodeConfigPtr->pMicroInitialOffsetB);
192 frayREG->GTUC1_UN.GTUC1_UL = __insval2mfld(GTUC1_UT_MSK , frayREG->GTUC1_UN.GTUC1_UL , nodeConfigPtr->pMicroPerCycle);
193 frayREG->GTUC10_UN.GTUC10_UL = __insval2mfld(GTUC10_MOC_MSK, frayREG->GTUC10_UN.GTUC10_UL, nodeConfigPtr->pRateCorrectionOut);
194 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_TSM_MSK , frayREG->SUCC1_UN.SUCC1_UL , nodeConfigPtr->pSingleSlotEnabled);
195 if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_A) {
196 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_WUCS_MSK, frayREG->SUCC1_UN.SUCC1_UL, 0);
198 else if (nodeConfigPtr->pWakeupChannel == FR_CHANNEL_B) {
199 frayREG->SUCC1_UN.SUCC1_UL = __insval2mfld(SUCC1_WUCS_MSK, frayREG->SUCC1_UN.SUCC1_UL, 1);
201 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_RWP_MSK, frayREG->PRTC1_UN.PRTC1_UL, nodeConfigPtr->pWakeupPattern);
202 frayREG->PRTC1_UN.PRTC1_UL = __insval2mfld(PRTC1_BRP_MSK, frayREG->PRTC1_UN.PRTC1_UL, nodeConfigPtr->pSamplesPerMicrotick);
207 * @brief Check node configuration parameters.
209 * This function checks values of the node configuration parameters,
210 * if they are in ranges noted in FlexRay specification.
212 * @param [in] nodeConfigPtr Address of structure with node configuration parameters
213 * @param [out] errCode Address where error flags will be stored.
214 * We have 24 parameters to check. Every one of them has assigned its bit in this flag.
215 * Error flags are defined as macros ERR_PARAM_nameOfParameter.
216 * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
218 Std_ReturnType Fr_check_node_parameters(const Fr_TMS570LS_NodeConfigType* nodeConfigPtr, uint32_t* errCode) {
219 *errCode = ERR_PARAM_NO_ERROR;
221 if (nodeConfigPtr->pAllowPassiveToActive > 31) *errCode |= ERR_PARAM_pAllowPassiveToActive;
222 if (nodeConfigPtr->pChannels != FR_CHANNEL_A &&
223 nodeConfigPtr->pChannels != FR_CHANNEL_B &&
224 nodeConfigPtr->pChannels != FR_CHANNEL_AB ) *errCode |= ERR_PARAM_pChannels;
225 if (nodeConfigPtr->pdAcceptedStartupRange > 1875) *errCode |= ERR_PARAM_pdAcceptedStartupRange;
226 if (nodeConfigPtr->pClusterDriftDamping > 20) *errCode |= ERR_PARAM_pClusterDriftDamping;
227 if (nodeConfigPtr->pDelayCompensationA > 200) *errCode |= ERR_PARAM_pDelayCompensationA;
228 if (nodeConfigPtr->pDelayCompensationB > 200) *errCode |= ERR_PARAM_pDelayCompensationB;
229 if (__notInRange(nodeConfigPtr->pdListenTimeout, 1284, 1283846)) *errCode |= ERR_PARAM_pdListenTimeout;
230 if (__notInRange(nodeConfigPtr->pdMaxDrift, 2, 1923)) *errCode |= ERR_PARAM_pdMaxDrift;
231 if (nodeConfigPtr->pExternOffsetCorrection > 7) *errCode |= ERR_PARAM_pExternOffsetCorrection;
232 if (nodeConfigPtr->pExternRateCorrection > 7) *errCode |= ERR_PARAM_pExternRateCorrection;
233 if (nodeConfigPtr->pKeySlotUsedForStartup == TRUE &&
234 nodeConfigPtr->pKeySlotUsedForSync == FALSE) *errCode |= ERR_PARAM_pKeySlotUsedForSync
235 | ERR_PARAM_pKeySlotUsedForStartup; // If pKeySlotUsedForStartup is set to true then pKeySlotUsedForSync must also be set to true.
236 if (nodeConfigPtr->pLatestTx > 7980) *errCode |= ERR_PARAM_pLatestTx;
237 if (__notInRange(nodeConfigPtr->pMacroInitialOffsetA, 2, 68)) *errCode |= ERR_PARAM_pMacroInitialOffsetA;
238 if (__notInRange(nodeConfigPtr->pMacroInitialOffsetB, 2, 68)) *errCode |= ERR_PARAM_pMacroInitialOffsetB;
239 if (nodeConfigPtr->pMicroInitialOffsetA > 239) *errCode |= ERR_PARAM_pMicroInitialOffsetA;
240 if (nodeConfigPtr->pMicroInitialOffsetB > 239) *errCode |= ERR_PARAM_pMicroInitialOffsetB;
241 if (__notInRange(nodeConfigPtr->pMicroPerCycle, 640, 640000)) *errCode |= ERR_PARAM_pMicroPerCycle;
242 if (__notInRange(nodeConfigPtr->pRateCorrectionOut, 2, 1923)) *errCode |= ERR_PARAM_pRateCorrectionOut;
243 if (nodeConfigPtr->pWakeupChannel != FR_CHANNEL_A &&
244 nodeConfigPtr->pWakeupChannel != FR_CHANNEL_B ) *errCode |= ERR_PARAM_pWakeupChannel;
245 if (__notInRange(nodeConfigPtr->pWakeupPattern, 2, 63)) *errCode |= ERR_PARAM_pWakeupPattern;
246 if (nodeConfigPtr->pSamplesPerMicrotick != 1 &&
247 nodeConfigPtr->pSamplesPerMicrotick != 2 &&
248 nodeConfigPtr->pSamplesPerMicrotick != 4 ) *errCode |= ERR_PARAM_pSamplesPerMicrotick;
250 return (*errCode == 0) ? E_OK : E_NOT_OK;
254 * @brief Check Configuration parameters for all buffers
256 * This function checks configuration parameters.
258 * - All of them have to be RX
259 * - All of them have the same payload <= 256B
260 * - Same channels active
261 * - Same cycle counter filter
264 * - not reconfigurable
265 * - frame ID can be 0, which means that all messages not received by others buffers are received in FIFO.
266 * For dynamic segment buffers and static segment buffers:
267 * - frame ID must not be 0
269 * The sum of all configured payloads must be <= 8KB.
271 * @param [in] statBufCfgPtr Address of structure with static buffers configuration parameters
272 * @param [in] dynBufCfgPtr Address of structure with dynamic buffers configuration parameters
273 * @param [in] fifoBufCfgPtr Address of structure with fifo buffers configuration parameters
274 * @param [in] statBufCnt Number of static buffers to be configured
275 * @param [in] dynBufCnt Number of dynamic buffers to be configured
276 * @param [in] fifoBufCnt Number of fifo buffers to be configured
277 * @param [out] errCode Address where error flags will be stored.
278 * Flags are defined as ERR_PARAM_BUF.....
279 * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
281 Std_ReturnType Fr_check_buffer_parameters(const Fr_TMS570LS_BufferConfigType* statBufCfgPtr, const Fr_TMS570LS_BufferConfigType* dynBufCfgPtr, const Fr_TMS570LS_BufferConfigType* fifoBufCfgPtr,
282 uint8_t statBufCnt, uint8_t dynBufCnt, uint8_t fifoBufCnt, uint32_t* errCode) {
283 uint32_t payloadTotal = 0;
284 *errCode = ERR_PARAM_NO_ERROR;
286 Fr_ChannelType fifoChannels;
287 uint8_t fifoCycleCounterFiltering;
290 /* Check FIFO buffer parameters */
291 fifoPayload = fifoBufCfgPtr[0].maxPayload;
292 fifoChannels = fifoBufCfgPtr[0].channel;
293 fifoCycleCounterFiltering = fifoBufCfgPtr[0].cycleCounterFiltering;
294 if (fifoBufCnt != 0 && fifoPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFFIFO_PAYLOAD_HIGH;
295 for (i = 0; i < fifoBufCnt; i++) {
296 if (fifoBufCfgPtr[i].isTx == TRUE) *errCode |= ERR_PARAM_BUFFIFO_NOT_RX;
297 if (fifoBufCfgPtr[i].maxPayload != fifoPayload) *errCode |= ERR_PARAM_BUFFIFO_PAYLOAD_DIFFERS;
298 if (fifoBufCfgPtr[i].channel != fifoChannels) *errCode |= ERR_PARAM_BUFFIFO_CHANNEL_DIFFERS;
299 if (fifoBufCfgPtr[i].cycleCounterFiltering != fifoCycleCounterFiltering) *errCode |= ERR_PARAM_BUFFIFO_CCFILTER_DIFFERS;
300 payloadTotal += fifoBufCfgPtr[i].maxPayload;
303 for (i = 0; i < dynBufCnt; i++) {
304 if (dynBufCfgPtr[i].slotId == 0) *errCode |= ERR_PARAM_BUFDYN_FRAMEID_INVALID;
305 if (dynBufCfgPtr[i].maxPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFDYN_PAYLOAD_HIGH;
306 if (dynBufCfgPtr[i].channel == FR_CHANNEL_AB) *errCode |= ERR_PARAM_BUFDYN_CHANNELS;
307 payloadTotal += dynBufCfgPtr[i].maxPayload;
310 for (i = 0; i < statBufCnt; i++) {
311 if (statBufCfgPtr[i].slotId == 0) *errCode |= ERR_PARAM_BUFSTAT_FRAMEID_INVALID;
312 if (statBufCfgPtr[i].maxPayload > cPayloadLengthMax) *errCode |= ERR_PARAM_BUFSTAT_PAYLOAD_HIGH;
313 payloadTotal += statBufCfgPtr[i].maxPayload;
316 if (payloadTotal > 8192/2) *errCode |= ERR_PARAM_BUF_TOTAL_PAYLOAD_HIGH;
318 return (*errCode == 0) ? E_OK : E_NOT_OK;
322 * @brief Compute and set message RAM config parameters into FlexRay configuration registers.
324 * This function does not check values ranges. This is a responsibility of other functions.
325 * Message RAM configuration parameters are computed from data in the structure and
326 * written into right bit position in configuration registers.
328 * @param [in] msgRAMConfigPtr Address of structure with message RAM configuration parameters
329 * @return Number of configured buffers
331 uint8_t Fr_config_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig* msgRAMConfigPtr) {
332 /* If dynSegmentBufferCount is not 0 then first dynamic buffer = statSegmentBufferCount.
333 * If dynSegmentBufferCount is 0 then first dynamic buffer is 0x80 (see TMS570LS31x documentation)
335 if (msgRAMConfigPtr->dynSegmentBufferCount == 0) {
336 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_FDB_MSK, frayREG->MRC_UN.MRC_UL, 0x80);
339 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_FDB_MSK, frayREG->MRC_UN.MRC_UL, msgRAMConfigPtr->statSegmentBufferCount);
341 /* If fifoBufferCount is not 0 then first fifo buffer = statSegmentBufferCount + dynSegmentBufferCount
342 * If fifoBufferCount is 0 then first fifo buffer is 0x80 (see TMS570LS31x documentation)
344 if (msgRAMConfigPtr->fifoBufferCount == 0) {
345 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_FFB_MSK, frayREG->MRC_UN.MRC_UL, 0x80);
348 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_FFB_MSK, frayREG->MRC_UN.MRC_UL, msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount);
350 /* Last configured buffer = statSegmentBufferCount + dynSegmentBufferCount + fifoBufferCount - 1 */
351 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_LCB_MSK, frayREG->MRC_UN.MRC_UL, msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount + msgRAMConfigPtr->fifoBufferCount - 1);
353 /* Secure buffers setting */
354 if (msgRAMConfigPtr->secureBuffers == FR_SB_RECONFIG_ENABLED) {
355 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SEC_MSK, frayREG->MRC_UN.MRC_UL, 0);
357 else if (msgRAMConfigPtr->secureBuffers == FR_SB_STAT_REC_DISABLED_STAT_TR_DISABLED) {
358 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SEC_MSK, frayREG->MRC_UN.MRC_UL, 1);
360 else if (msgRAMConfigPtr->secureBuffers == FR_SB_ALL_REC_DISABLED) {
361 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SEC_MSK, frayREG->MRC_UN.MRC_UL, 2);
364 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SEC_MSK, frayREG->MRC_UN.MRC_UL, 3);
367 /* Sync frame payload multiplex setting */
368 if (msgRAMConfigPtr->syncFramePayloadMultiplexEnabled == TRUE) {
369 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SPLM_MSK, frayREG->MRC_UN.MRC_UL, 1);
372 frayREG->MRC_UN.MRC_UL = __insval2mfld(MRC_SPLM_MSK, frayREG->MRC_UN.MRC_UL, 0);
375 return msgRAMConfigPtr->statSegmentBufferCount + msgRAMConfigPtr->dynSegmentBufferCount + msgRAMConfigPtr->fifoBufferCount;
378 #define __notInRange(val, min, max) (((val) < (min)) || ((val) > (max)))
381 * @brief Check message RAM configuration parameters.
383 * This function checks values of the message RAM configuration parameters.
384 * FlexRay implementation in TMS570 can have up to 128 buffers configured, so
385 * the sum of all values buffer count must not exceed this ceiling.
388 * @param [in] clusterConfigPtr Address of structure with cluster configuration parameters
389 * @param [out] errCode Address where error flags will be stored.
390 * Error flags are defined as macros ERR_PARAM_nameOfParameter.
391 * @return E_OK: Parameters are OK. E_NOT_OK: Some parameter is out of range.
393 Std_ReturnType Fr_check_msgRAM_parameters(const Fr_TMS570LS_MsgRAMConfig* msgRAMConfigPtr, uint32_t* errCode) {
394 *errCode = ERR_PARAM_NO_ERROR;
396 if (__notInRange(msgRAMConfigPtr->statSegmentBufferCount, 1, 127)) *errCode |= ERR_PARAM_statSegmentBufferCount;
397 if (msgRAMConfigPtr->dynSegmentBufferCount >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_dynSegmentBufferCount;
398 if (msgRAMConfigPtr->fifoBufferCount >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_fifoBufferCount;
399 if ((msgRAMConfigPtr->statSegmentBufferCount +
400 msgRAMConfigPtr->dynSegmentBufferCount +
401 msgRAMConfigPtr->fifoBufferCount) >= FR_MAX_BUFFERS_CNT) *errCode |= ERR_PARAM_maxBuffLimit;
403 return (*errCode == 0) ? E_OK : E_NOT_OK;
406 void Fr_Init(const Fr_ConfigType* Fr_ConfigPtr) {
410 if (Fr_ConfigPtr == NULL) {
414 /* Save pointers for parameters indexed by CIDX indexes
415 * This array representation is used by Fr_ReadCCConfig function.
416 * Parameter thet are not configurable in tms570 FlexRay implementation
419 Fr_ConfigParPtrs[FR_CIDX_GDCYCLE] = NULL;
420 Fr_ConfigParPtrs[FR_CIDX_PMICROPERCYCLE] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pMicroPerCycle;
421 Fr_ConfigParPtrs[FR_CIDX_PDLISTENTIMEOUT] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gMacroPerCycle;
422 Fr_ConfigParPtrs[FR_CIDX_GDMACROTICK] = NULL;
423 Fr_ConfigParPtrs[FR_CIDX_GNUMBEROFMINISLOTS] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gNumberOfMinislots;
424 Fr_ConfigParPtrs[FR_CIDX_GNUMBEROFSTATICSLOTS] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gNumberOfStaticSlots;
425 Fr_ConfigParPtrs[FR_CIDX_GDNIT] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdNIT;
426 Fr_ConfigParPtrs[FR_CIDX_GDSTATICSLOT] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdNIT;
427 Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPRXWINDOW] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdWakeupSymbolRxWindow;
428 Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTID] = NULL;
429 Fr_ConfigParPtrs[FR_CIDX_PLATESTTX] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pLatestTx;
430 Fr_ConfigParPtrs[FR_CIDX_POFFSETCORRECTIONOUT] = NULL;
431 Fr_ConfigParPtrs[FR_CIDX_POFFSETCORRECTIONSTART] = NULL;
432 Fr_ConfigParPtrs[FR_CIDX_PRATECORRECTIONOUT] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pRateCorrectionOut;
433 Fr_ConfigParPtrs[FR_CIDX_PSECONDKEYSLOTID] = NULL;
434 Fr_ConfigParPtrs[FR_CIDX_PDACCEPTEDSTARTUPRANGE] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pdAcceptedStartupRange;
435 Fr_ConfigParPtrs[FR_CIDX_GCOLDSTARTATTEMPTS] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gColdStartAttempts;
436 Fr_ConfigParPtrs[FR_CIDX_GCYCLECOUNTMAX] = NULL;
437 Fr_ConfigParPtrs[FR_CIDX_GLISTENNOISE] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gListenNoise;
438 Fr_ConfigParPtrs[FR_CIDX_GMAXWITHOUTCLOCKCORRECTFATAL] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gMaxWithoutClockCorrectionFatal;
439 Fr_ConfigParPtrs[FR_CIDX_GMAXWITHOUTCLOCKCORRECTPASSIVE] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gMaxWithoutClockCorrectionPassive;
440 Fr_ConfigParPtrs[FR_CIDX_GNETWORKMANAGEMENTVECTORLENGTH] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gNetworkManagementVectorLength;
441 Fr_ConfigParPtrs[FR_CIDX_GPAYLOADLENGTHSTATIC] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gPayloadLengthStatic;
442 Fr_ConfigParPtrs[FR_CIDX_GSYNCFRAMEIDCOUNTMAX] = NULL;
443 Fr_ConfigParPtrs[FR_CIDX_GDACTIONPOINTOFFSET] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdActionPointOffset;
444 Fr_ConfigParPtrs[FR_CIDX_GDBIT] = NULL;
445 Fr_ConfigParPtrs[FR_CIDX_GDCASRXLOWMAX] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdCASRxLowMax;
446 Fr_ConfigParPtrs[FR_CIDX_GDDYNAMICSLOTIDLEPHASE] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdDynamicSlotIdlePhase;
447 Fr_ConfigParPtrs[FR_CIDX_GDMINISLOTACTIONPOINTOFFSET] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdMinislotActionPointOffset;
448 Fr_ConfigParPtrs[FR_CIDX_GDMINISLOT] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdMinislot;
449 Fr_ConfigParPtrs[FR_CIDX_GDSAMPLECLOCKPERIOD] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdSampleClockPeriod;
450 Fr_ConfigParPtrs[FR_CIDX_GDSYMBOLWINDOW] = NULL;
451 Fr_ConfigParPtrs[FR_CIDX_GDSYMBOLWINDOWACTIONPOINTOFFSET] = NULL;
452 Fr_ConfigParPtrs[FR_CIDX_GDTSSTRANSMITTER] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdTSSTransmitter;
453 Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPRXIDLE] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdWakeupSymbolRxIdle;
454 Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPRXLOW] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdWakeupSymbolRxLow;
455 Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPTXACTIVE] = NULL;
456 Fr_ConfigParPtrs[FR_CIDX_GDWAKEUPTXIDLE] = (const uint32_t*)&Fr_ConfigPtr->clusterConfiguration.gdWakeupSymbolTxIdle;
457 Fr_ConfigParPtrs[FR_CIDX_PALLOWPASSIVETOACTIVE] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pAllowPassiveToActive;
458 Fr_ConfigParPtrs[FR_CIDX_PCHANNELS] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pChannels;
459 Fr_ConfigParPtrs[FR_CIDX_PCLUSTERDRIFTDAMPING] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pClusterDriftDamping;
460 Fr_ConfigParPtrs[FR_CIDX_PDECODINGCORRECTION] = NULL;
461 Fr_ConfigParPtrs[FR_CIDX_PDELAYCOMPENSATIONA] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pDelayCompensationA;
462 Fr_ConfigParPtrs[FR_CIDX_PDELAYCOMPENSATIONB] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pDelayCompensationB;
463 Fr_ConfigParPtrs[FR_CIDX_PMACROINITIALOFFSETA] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pMacroInitialOffsetA;
464 Fr_ConfigParPtrs[FR_CIDX_PMACROINITIALOFFSETB] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pMacroInitialOffsetB;
465 Fr_ConfigParPtrs[FR_CIDX_PMICROINITIALOFFSETA] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pMicroInitialOffsetA;
466 Fr_ConfigParPtrs[FR_CIDX_PMICROINITIALOFFSETB] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pMicroInitialOffsetB;
467 Fr_ConfigParPtrs[FR_CIDX_PPAYLOADLENGTHDYNMAX] = NULL;
468 Fr_ConfigParPtrs[FR_CIDX_PSAMPLESPERMICROTICK] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pSamplesPerMicrotick;
469 Fr_ConfigParPtrs[FR_CIDX_PWAKEUPCHANNEL] =(const uint32_t*) &Fr_ConfigPtr->nodeConfiguration.pWakeupChannel;
470 Fr_ConfigParPtrs[FR_CIDX_PWAKEUPPATTERN] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pWakeupPattern;
471 Fr_ConfigParPtrs[FR_CIDX_PDMICROTICK] = NULL;
472 Fr_ConfigParPtrs[FR_CIDX_GDIGNOREAFTERTX] = NULL;
473 Fr_ConfigParPtrs[FR_CIDX_PALLOWHALTDUETOCLOCK] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pAllowHaltDueToClock;
474 Fr_ConfigParPtrs[FR_CIDX_PEXTERNALSYNC] = NULL;
475 Fr_ConfigParPtrs[FR_CIDX_PFALLBACKINTERNAL] = NULL;
476 Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTONLYENABLED] = NULL;
477 Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSTARTUP] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pKeySlotUsedForStartup;
478 Fr_ConfigParPtrs[FR_CIDX_PKEYSLOTUSEDFORSYNC] = (const uint32_t*)&Fr_ConfigPtr->nodeConfiguration.pKeySlotUsedForSync;
479 Fr_ConfigParPtrs[FR_CIDX_PNMVECTOREARLYUPDATE] = NULL;
480 Fr_ConfigParPtrs[FR_CIDX_PTWOKEYSLOTMODE] = NULL;
482 /* Store whole configuration address
483 * This structured representation is used by other function in API.
485 Fr_Config = Fr_ConfigPtr;
487 /* Store pointers to structures with configuration parameters of buffers
488 * Reset configured flags for all buffers */
489 for (i = 0; i < Fr_ConfigPtr->msgRAMConfig.statSegmentBufferCount; ++i) { // Statis segment buffers
490 Fr_BuffersPtrs[i] = (const Fr_TMS570LS_BufferConfigType*)&Fr_ConfigPtr->staticBufferConfigs[i];
491 Fr_BuffersConfigured[i] = FALSE;
493 for (i = 0; i < Fr_ConfigPtr->msgRAMConfig.dynSegmentBufferCount; ++i) { // Dynamic segment buffers
494 Fr_BuffersPtrs[i + Fr_ConfigPtr->msgRAMConfig.statSegmentBufferCount] = (const Fr_TMS570LS_BufferConfigType*)&Fr_ConfigPtr->dynamicBufferConfigs[i];
495 Fr_BuffersConfigured[i + Fr_ConfigPtr->msgRAMConfig.statSegmentBufferCount] = FALSE;
497 for (i = 0; i < Fr_ConfigPtr->msgRAMConfig.fifoBufferCount; ++i) { // Fifo buffrers
498 Fr_BuffersPtrs[i + Fr_ConfigPtr->msgRAMConfig.statSegmentBufferCount + Fr_ConfigPtr->msgRAMConfig.dynSegmentBufferCount] = (const Fr_TMS570LS_BufferConfigType*)&Fr_ConfigPtr->fifoBufferConfigs[i];
499 Fr_BuffersConfigured[i + Fr_ConfigPtr->msgRAMConfig.statSegmentBufferCount + Fr_ConfigPtr->msgRAMConfig.dynSegmentBufferCount] = FALSE;
502 /* Set some default POC state values */
503 Fr_POCStatus.WakeupStatus = FR_WAKEUP_UNDEFINED;
504 Fr_POCStatus.State = FR_POCSTATE_DEFAULT_CONFIG;
505 Fr_POCStatus.StartupState = FR_STARTUP_UNDEFINED;
506 Fr_POCStatus.SlotMode = FR_SLOTMODE_ALL;
507 Fr_POCStatus.Freeze = FALSE;
508 Fr_POCStatus.ErrorMode = FR_ERRORMODE_ACTIVE;
509 Fr_POCStatus.ColdstartNoise = FALSE;
510 Fr_POCStatus.CHIReadyRequest = FALSE;
511 Fr_POCStatus.CHIHaltRequest = FALSE;
514 Fr_Initialized = TRUE;
518 Std_ReturnType Fr_ControllerInit(uint8_t Fr_CtrlIdx) {
519 uint32_t errCode = ERR_PARAM_NO_ERROR;
521 uint8_t totalBufferCount;
523 /* Switch CC into ‘POC:config’ (from any other POCState) */
524 if (Fr_POC_go_to_config() == E_NOT_OK) {
527 /* Check Cluster config parameters */
528 if (Fr_check_cluster_parameters(&Fr_Config->clusterConfiguration, &errCode) == E_NOT_OK) {
529 return E_NOT_OK | errCode | FR_INIT_ERR_CLUSTER_CONFIG;
531 /* Check node config parameters */
532 if (Fr_check_node_parameters(&Fr_Config->nodeConfiguration, &errCode) == E_NOT_OK) {
533 return E_NOT_OK | errCode | FR_INIT_ERR_NODE_CONFIG;
535 /* Check msgRAM config parameters */
536 if (Fr_check_msgRAM_parameters(&Fr_Config->msgRAMConfig, &errCode) == E_NOT_OK) {
537 return E_NOT_OK | errCode | FR_INIT_ERR_MSGRAM_CONFIG;
539 /* Check buffers parameters */
540 if (Fr_check_buffer_parameters(Fr_Config->staticBufferConfigs, Fr_Config->dynamicBufferConfigs, Fr_Config->fifoBufferConfigs,
541 Fr_Config->msgRAMConfig.statSegmentBufferCount, Fr_Config->msgRAMConfig.dynSegmentBufferCount, Fr_Config->msgRAMConfig.fifoBufferCount, &errCode) == E_NOT_OK) {
542 return E_NOT_OK | errCode | FR_INIT_ERR_BUFFPARAM_CONFIG;
545 /* Configure all FlexRay cluster, node and msgRAM parameters */
546 Fr_config_cluster_parameters(&Fr_Config->clusterConfiguration);
547 Fr_config_node_parameters(&Fr_Config->nodeConfiguration);
548 totalBufferCount = Fr_config_msgRAM_parameters(&Fr_Config->msgRAMConfig);
549 Fr_MsgRAMDataStartAddress = totalBufferCount*4U; // First data section after headers sections in message RAM.
550 Fr_MsgRAMDataOffset = Fr_MsgRAMDataStartAddress;
551 /* Configure all transmit/receive resources */
552 for (i = 0; i < totalBufferCount; i++) {
553 if (Fr_PrepareLPdu(Fr_CtrlIdx, Fr_BuffersPtrs[i]->slotId) == E_NOT_OK) {
554 return E_NOT_OK | FR_INIT_ERR_BUFF_CONFIG;
559 //The function Fr_ControllerInit shall ensure that no transmission requests are pending
561 //The function Fr_ControllerInit shall ensure that no reception indications are pending.
563 //The function Fr_ControllerInit shall ensure that no interrupts are pending.
565 //The function Fr_ControllerInit shall ensure that all timers are disabled.
567 //The function Fr_ControllerInit shall disable all LPdus which are dynamically reconfigurable
569 /*If the function Fr_ControllerInit detects errors while testing the
570 CC (CC test), then it shall repeat the test procedure a configurable number
571 (FrCtrlTestCount) of times. If all tests fail, then it calls Dem_ReportErrorStatus
572 (FrDemCtrlTestResultRef,
573 DEM_EVENT_STATUS_FAILED)
577 The CC test as described in SWS_Fr_00147 shall verify (read
578 back and compare to reference values held in the configuration) that the node and
579 cluster FlexRay parameters were written properly into the FlexRay CC.
585 Std_ReturnType Fr_StartCommunication(uint8_t Fr_CtrlIdx) {
589 Std_ReturnType Fr_AllowColdstart(uint8_t Fr_CtrlIdx) {
593 Std_ReturnType Fr_AllSlots(uint8_t Fr_CtrlIdx) {
597 Std_ReturnType Fr_HaltCommunication(uint8_t Fr_CtrlIdx) {
601 Std_ReturnType Fr_AbortCommunication(uint8_t Fr_CtrlIdx) {
605 Std_ReturnType Fr_SendWUP(uint8_t Fr_CtrlIdx) {
609 Std_ReturnType Fr_SetWakeupChannel(uint8_t Fr_CtrlIdx, Fr_ChannelType Fr_ChnlIdx) {
613 Std_ReturnType Fr_GetPOCStatus(uint8_t Fr_CtrlIdx, Fr_POCStatusType* Fr_POCStatusPtr) {
617 Std_ReturnType Fr_TransmitTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, const uint8_t* Fr_LSduPtr, uint8_t Fr_LSduLength) {
621 Std_ReturnType Fr_CancelTxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx) {
625 Std_ReturnType Fr_ReceiveRxLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint8_t* Fr_LSduPtr, Fr_RxLPduStatusType* Fr_LPduStatusPtr, uint8_t* Fr_LSduLengthPtr) {
629 Std_ReturnType Fr_CheckTxLPduStatus(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, Fr_TxLPduStatusType* Fr_TxLPduStatusPtr) {
633 Std_ReturnType Fr_PrepareLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx) {
638 if (Fr_CtrlIdx != 0) {
641 if (Fr_Initialized != TRUE) {
644 if (Fr_LPduIdx > cSlotIDMax) {
648 /* Find the index of the buffer in configuration data array */
649 for (i = 0; i < FR_MAX_BUFFERS_CNT; i++) {
650 if (Fr_BuffersPtrs[i]->slotId == Fr_LPduIdx) { // Next occurence of the frame ID found, index retreived into i.
651 if (Fr_BuffersConfigured[i] == FALSE) { // Buffer was not yet configured
652 mode = (Fr_BuffersPtrs[i]->singleTransmit == TRUE) ? FRAY_BUF_MBI_EN : FRAY_BUF_MBI_DIS;
653 mode |= (Fr_BuffersPtrs[i]->singleTransmit == TRUE) ? FRAY_BUF_TX_MODE_SINGLE : FRAY_BUF_TX_MODE_CONTINUOUS;
654 mode |= (Fr_BuffersPtrs[i]->payloadPreambleIndicatorTr == TRUE) ? FRAY_BUF_NM_EN : FRAY_BUF_NM_DIS;
655 mode |= (Fr_BuffersPtrs[i]->isTx == TRUE) ? FRAY_BUF_TX : FRAY_BUF_RX;
656 mode |= (Fr_BuffersPtrs[i]->channel == FR_CHANNEL_A || Fr_BuffersPtrs[i]->channel == FR_CHANNEL_AB) ? FRAY_BUF_CHA_EN : FRAY_BUF_CHA_DIS;
657 mode |= (Fr_BuffersPtrs[i]->channel == FR_CHANNEL_B || Fr_BuffersPtrs[i]->channel == FR_CHANNEL_AB) ? FRAY_BUF_CHB_EN : FRAY_BUF_CHB_DIS;
658 mode |= (Fr_BuffersPtrs[i]->rejectNullFrames == TRUE) ? FRAY_BUF_REJECT_NULL_FRAMES : FRAY_BUF_ACCEPT_NULL_FRAMES;
659 mode |= (Fr_BuffersPtrs[i]->rejectStaticSegment == TRUE) ? FRAY_BUF_REJECT_STATIC_SEGMENT : FRAY_BUF_ACCEPT_STATIC_SEGMENT;
660 Fr_MsgRAMDataPtrs[i] = Fr_MsgRAMDataOffset;
661 if (i >= __mfld2val(MRC_FFB_MSK, frayREG->MRC_UN.MRC_UL)) { // This is RX FIFO buffer
662 fray_configure_fifo_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
664 else { // Static/dynamic segment buffer
665 fray_config_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
668 * Calculate new address.
669 * Payload contains the number of two-bytes words, Fr_MsgRAMDataPtrs contains addresses of 4B words in message RAM, all msgRAM addresses have
671 * Offset has to be divided by two each time because payload is in 2B words and msgRAM addresses are in 4B words.
673 Fr_MsgRAMDataOffset += ((Fr_BuffersPtrs[i]->maxPayload)%2U == 0U ? (Fr_BuffersPtrs[i]->maxPayload) : ((Fr_BuffersPtrs[i]->maxPayload)+1U))/2;
674 Fr_BuffersConfigured[i] = TRUE;
681 Std_ReturnType Fr_ReconfigLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx, uint16_t Fr_FrameId, Fr_ChannelType Fr_ChnlIdx, uint8_t Fr_CycleRepetition, uint8_t Fr_CycleOffset, uint8_t Fr_PayloadLength, uint16_t Fr_HeaderCRC) {
685 Std_ReturnType Fr_DisableLPdu(uint8_t Fr_CtrlIdx, uint16_t Fr_LPduIdx) {
689 Std_ReturnType Fr_GetGlobalTime(uint8_t Fr_CtrlIdx, uint8_t* Fr_CyclePtr, uint16_t* Fr_MacroTickPtr) {
693 Std_ReturnType Fr_GetNmVector(uint8_t Fr_CtrlIdx, uint8_t* Fr_NmVectorPtr) {
697 Std_ReturnType Fr_GetNumOfStartupFrames(uint8_t Fr_CtrlIdx, uint8_t* Fr_NumOfStartupFramesPtr) {
701 Std_ReturnType Fr_GetChannelStatus(uint8_t Fr_CtrlIdx, uint16_t* Fr_ChannelAStatusPtr, uint16_t* Fr_ChannelBStatusPtr) {
705 Std_ReturnType Fr_GetClockCorrection(uint8_t Fr_CtrlIdx, int16_t* Fr_RateCorrectionPtr, int32_t* Fr_OffsetCorrectionPtr) {
709 Std_ReturnType Fr_GetSyncFrameList(uint8_t Fr_CtrlIdx, uint8_t Fr_ListSize, uint16_t* Fr_ChannelAEvenListPtr, uint16_t* Fr_ChannelBEvenListPtr, uint16_t* Fr_ChannelAOddListPtr, uint16_t* Fr_ChannelBOddListPtr) {
713 Std_ReturnType Fr_GetWakeupRxStatus(uint8_t Fr_CtrlIdx, uint8_t* Fr_WakeupRxStatusPtr) {
717 Std_ReturnType Fr_SetAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, uint8_t Fr_Cycle, uint16_t Fr_Offset) {
721 Std_ReturnType Fr_CancelAbsoluteTimer(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
725 Std_ReturnType Fr_EnableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
729 Std_ReturnType Fr_AckAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
733 Std_ReturnType Fr_DisableAbsoluteTimerIRQ(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx) {
737 Std_ReturnType Fr_GetAbsoluteTimerIRQStatus(uint8_t Fr_CtrlIdx, uint8_t Fr_AbsTimerIdx, boolean_t* Fr_IRQStatusPtr) {
741 void Fr_GetVersionInfo(Std_VersionInfoType* VersioninfoPtr) {
743 if (VersioninfoPtr == NULL) {
747 VersioninfoPtr->vendorID = Fr_versionInfo.vendorID;
748 VersioninfoPtr->moduleID = Fr_versionInfo.moduleID;
749 VersioninfoPtr->sw_major_version = Fr_versionInfo.sw_major_version;
750 VersioninfoPtr->sw_minor_version= Fr_versionInfo.sw_minor_version;
751 VersioninfoPtr->sw_patch_version= Fr_versionInfo.sw_patch_version;
754 Std_ReturnType Fr_ReadCCConfig( uint8_t Fr_CtrlIdx, uint8_t Fr_ConfigParamIdx, uint32_t* Fr_ConfigParamValuePtr) {
756 if (Fr_CtrlIdx != 0) {
759 if (Fr_ConfigParamIdx >= FR_CIDX_CNT) {
762 if (Fr_ConfigParamValuePtr >= NULL) {
765 if (Fr_Initialized != TRUE) {
770 Fr_ConfigParamValuePtr = (uint32_t*)Fr_ConfigParPtrs[Fr_ConfigParamIdx];