Changed 'pointer acces' to cards memory to ioread/iowrite. This also handles Endianne...

diff --git a/src/uio/mf624/kernel/mf624.c b/src/uio/mf624/kernel/mf624.c
index 939f290155212163a78fac26a64bb260b1d4e8d4..d1945943566d072461203da8361a6a930aa5082b 100755 (executable)
--- a/src/uio/mf624/kernel/mf624.c
+++ b/src/uio/mf624/kernel/mf624.c
@@ -7,6 +7,7 @@
 #include <linux/kernel.h>
 #include <linux/uio_driver.h>
 
+
 #define PCI_VENDOR_ID_HUMUSOFT         0x186c
 #define PCI_DEVICE_ID_MF624            0x0624
 #define PCI_SUBVENDOR_ID_HUMUSOFT      0x186c
@@ -19,25 +20,29 @@
 #define INTCSR_ADINT_STATUS            (1 << 2)
 #define INTCSR_CTR4INT_STATUS          (1 << 5)
 
-
 typedef enum {ADC, CTR4, ALL} mf624_interrupt_source_t;
 
+
 void mf624_disable_interrupt(mf624_interrupt_source_t source, struct uio_info *info)
 {
        u32 *INTCSR_reg = ((u32*) info->mem[0].internal_addr) + INTCSR;
 
        switch (source) {
                case ADC:
-                       *INTCSR_reg &= ~(INTCSR_ADINT_ENABLE);
+                       iowrite32(ioread32(INTCSR_reg) & ~(INTCSR_ADINT_ENABLE), 
+                               INTCSR_reg);
                        break;
                case CTR4:
-                       *INTCSR_reg &= ~(INTCSR_CTR4INT_ENABLE);
+                       iowrite32(ioread32(INTCSR_reg) & ~(INTCSR_CTR4INT_ENABLE), 
+                               INTCSR_reg);
                        break;
                case ALL:
-                       *INTCSR_reg &= ~(INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE);
+                       iowrite32(ioread32(INTCSR_reg) & ~(INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE),
+                               INTCSR_reg);
                        break;
                default:
-                       *INTCSR_reg &= ~(INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE);
+                       iowrite32(ioread32(INTCSR_reg) & ~(INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE), 
+                               INTCSR_reg);
                        break;
        }
 }
@@ -48,16 +53,20 @@ void mf624_enable_interrupt(mf624_interrupt_source_t source, struct uio_info *in
 
        switch (source) {
                case ADC:
-                       *INTCSR_reg |= (INTCSR_ADINT_ENABLE);
+                       iowrite32(ioread32(INTCSR_reg) | (INTCSR_ADINT_ENABLE), 
+                               INTCSR_reg);
                        break;
                case CTR4:
-                       *INTCSR_reg |= (INTCSR_CTR4INT_ENABLE);
+                       iowrite32(ioread32(INTCSR_reg) | (INTCSR_CTR4INT_ENABLE),
+                               INTCSR_reg);
                        break;
                case ALL:
-                       *INTCSR_reg |= (INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE);
+                       iowrite32(ioread32(INTCSR_reg) | (INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE),
+                               INTCSR_reg);
                        break;
                default:
-                       *INTCSR_reg |= (INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE);
+                       iowrite32(ioread32(INTCSR_reg) | (INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE),
+                               INTCSR_reg);
                        break;
        }
 }
@@ -66,14 +75,16 @@ static irqreturn_t mf624_irq_handler(int irq, struct uio_info *info)
 {
        u32 *INTCSR_reg = ((u32*) info->mem[0].internal_addr) + INTCSR;
 
-       if (((*INTCSR_reg & INTCSR_ADINT_ENABLE) > 0) && ((*INTCSR_reg & INTCSR_ADINT_STATUS) > 0))
+       if (((ioread32(INTCSR_reg) & INTCSR_ADINT_ENABLE) > 0) 
+               && ((ioread32(INTCSR_reg) & INTCSR_ADINT_STATUS) > 0))
        {
                //disable interrupt
                mf624_disable_interrupt(ADC, info);
                return IRQ_HANDLED;
        }
 
-       if (((*INTCSR_reg & INTCSR_CTR4INT_ENABLE) > 0) && ((*INTCSR_reg & INTCSR_CTR4INT_STATUS) > 0))
+       if (((ioread32(INTCSR_reg) & INTCSR_CTR4INT_ENABLE) > 0) 
+               && ((ioread32(INTCSR_reg) & INTCSR_CTR4INT_STATUS) > 0))
        {
                //disable interrupt
                mf624_disable_interrupt(CTR4, info);
@@ -85,7 +96,7 @@ static irqreturn_t mf624_irq_handler(int irq, struct uio_info *info)
 
 static int mf624_irqcontrol(struct uio_info *info, s32 irq_on)
 {
-       if (irq_on == 0) { /* Disable interrupts */
+       if (irq_on == 0) { // Disable interrupts
                mf624_disable_interrupt(ALL, info);
        } 
        else if (irq_on == 1) {
@@ -113,6 +124,7 @@ static int __devinit mf624_pci_probe(struct pci_dev *dev,
        info->name = "MF624";
        info->version = "0.0.1";
 
+       // BAR0
        info->mem[0].name = "PCI chipset, interrupts, status bits, special functions";
        info->mem[0].addr = pci_resource_start(dev, 0);
        if (!info->mem[0].addr)
@@ -123,7 +135,8 @@ static int __devinit mf624_pci_probe(struct pci_dev *dev,
        if (!info->mem[0].internal_addr)
                goto out_release;
 
-       
+
+       //BAR2  
        info->mem[1].name = "ADC, DAC, DIO";
        info->mem[1].addr = pci_resource_start(dev, 2);
        if (!info->mem[1].addr)
@@ -135,6 +148,7 @@ static int __devinit mf624_pci_probe(struct pci_dev *dev,
                goto out_release;
 
 
+       //BAR4
        info->mem[2].name = "Counter/timer chip";
        info->mem[2].addr = pci_resource_start(dev, 4);
        if (!info->mem[2].addr)