5 #include <stdint.h> // uintX_t
10 /*masked fields macros*/
12 #define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
15 #define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
18 /* Hardware specific */
20 #define GPIOC_reg 0x54
23 #define ADCTRL_reg 0x00
24 #define ADDATA0_reg 0x00
25 #define ADDATA1_reg 0x02
26 #define ADDATA2_reg 0x04
27 #define ADDATA3_reg 0x06
28 #define ADDATA4_reg 0x08
29 #define ADDATA5_reg 0x0a
30 #define ADDATA6_reg 0x0c
31 #define ADDATA7_reg 0x0e
32 #define ADSTART_reg 0x20
58 #define IRCSTATUS_reg 0x6C
59 #define IRCCTRL_reg 0x6C
65 #define IRCCTRL_IRC0MODE_mask 0x00000003
66 #define IRCCTRL_IRC0COUNT_mask 0x0000000C
67 #define IRCCTRL_IRC0RESET_mask 0x00000070
68 #define IRCCTRL_IRC0FILTER_mask 0x00000080
70 #define IRCCTRL_IRC1MODE_mask 0x00000300
71 #define IRCCTRL_IRC1COUNT_mask 0x00000C00
72 #define IRCCTRL_IRC1RESET_mask 0x00007000
73 #define IRCCTRL_IRC1FILTER_mask 0x00008000
75 #define IRCCTRL_IRC2MODE_mask 0x00030000
76 #define IRCCTRL_IRC2COUNT_mask 0x000C0000
77 #define IRCCTRL_IRC2RESET_mask 0x00700000
78 #define IRCCTRL_IRC2FILTER_mask 0x00800000
80 #define IRCCTRL_IRC3MODE_mask 0x03000000
81 #define IRCCTRL_IRC3COUNT_mask 0x0C000000
82 #define IRCCTRL_IRC3RESET_mask 0x70000000
83 #define IRCCTRL_IRC3FILTER_mask 0x80000000
85 #define IRCCTRL_CHANNEL_SHIFT 8
87 #define IRCCTRL_MODE_mask(ch) (0x03<<((ch)*IRCCTRL_CHANNEL_SHIFT))
88 #define IRCCTRL_COUNT_mask(ch) (0x0C<<((ch)*IRCCTRL_CHANNEL_SHIFT))
89 #define IRCCTRL_RESET_mask(ch) (0x70<<((ch)*IRCCTRL_CHANNEL_SHIFT))
90 #define IRCCTRL_FILTER_mask(ch) (0x80<<((ch)*IRCCTRL_CHANNEL_SHIFT))
92 #define IRCCTRL_MODE_IRC 0
93 #define IRCCTRL_MODE_BIDIR_RE 1
94 #define IRCCTRL_MODE_BIDIR_FE 2
95 #define IRCCTRL_MODE_BIDIR_BOTH 3
97 #define IRCCTRL_COUNT_ENABLED 0
98 #define IRCCTRL_COUNT_DISABLED 1
99 #define IRCCTRL_COUNT_IF_IDX_LO 2
100 #define IRCCTRL_COUNT_IF_IDX_HI 3
102 #define IRCCTRL_RESET_DISABLED 0
103 #define IRCCTRL_RESET_ALWAYS 1
104 #define IRCCTRL_RESET_IF_IDX_LO 2
105 #define IRCCTRL_RESET_IF_IDX_HI 3
106 #define IRCCTRL_RESET_IF_IDX_RE 4
107 #define IRCCTRL_RESET_IF_IDX_FE 5
108 #define IRCCTRL_RESET_IF_IDX_BOTH 6
110 #define IRCSTATUS_IRC0INDEX_mask 0x00000001
111 #define IRCSTATUS_IRC1INDEX_mask 0x00000100
112 #define IRCSTATUS_IRC2INDEX_mask 0x00000100
113 #define IRCSTATUS_IRC3INDEX_mask 0x00000100
115 #define IRCSTATUS_CHANNEL_SHIFT 8
117 #define IRCSTATUS_INDEX_mask(ch) (0x01<<((ch)*IRCSTATUS_CHANNEL_SHIFT))
119 #define GPIOC_DACEN_mask (1 << 26)
120 #define GPIOC_LDAC_mask (1 << 23)
121 #define GPIOC_EOLC_mask (1 << 17)
123 #define MFST2REG(mfst, bar_num, reg_offs) \
124 ((void *)(mfst->bar##bar_num.virt_addr + (reg_offs)))
127 typedef struct bar_mapping_t {
137 typedef enum {DA0, DA1, DA2, DA3, DA4, DA5, DA6, DA7} dac_channel_t;
138 typedef enum {AD0, AD1, AD2, AD3, AD4, AD5, AD6, AD7} adc_channel_t;
140 typedef struct mf624_state_t {
147 int ADC_enabled; // Which ADCs are enabled
152 //extern mf624_state_t mf624_state;
153 extern mf624_state_t* mfst;
155 static uint32_t dac_channel2reg[] = {
166 static uint32_t adc_channel2reg[] = {
177 static inline int16_t mf624_read16(void *ptr)
179 return *(volatile uint16_t*)ptr;
182 static inline int32_t mf624_read32(void *ptr)
184 return *(volatile uint32_t*) ptr;
187 static inline void mf624_write16(uint16_t val, void *ptr)
189 *(volatile uint16_t*) ptr = val;
192 static inline void mf624_write32(uint32_t val, void *ptr)
194 *(volatile uint32_t*) ptr = val;
197 extern void DIO_write(mf624_state_t* mfst, int16_t val);
199 extern uint16_t DIO_read(mf624_state_t* mfst);
201 extern void DAC_enable(mf624_state_t* mfst);
203 extern int DAC_write(mf624_state_t* mfst, dac_channel_t channel, int val);
205 extern int ADC_enable(mf624_state_t* mfst, adc_channel_t channel);
207 extern double ADC_read(mf624_state_t* mfst, adc_channel_t channel);
209 extern uint32_t IRC_mode_change(mf624_state_t* mfst, uint32_t change_mask, uint32_t change_val);
211 int mf624_init(SimStruct *S);
212 int mf624_check(SimStruct *S);