5 #include <stdint.h> // uintX_t
10 /* Hardware specific */
12 #define GPIOC_reg 0x54
15 #define ADCTRL_reg 0x00
16 #define ADDATA0_reg 0x00
17 #define ADDATA1_reg 0x02
18 #define ADDATA2_reg 0x04
19 #define ADDATA3_reg 0x06
20 #define ADDATA4_reg 0x08
21 #define ADDATA5_reg 0x0a
22 #define ADDATA6_reg 0x0c
23 #define ADDATA7_reg 0x0e
24 #define ADSTART_reg 0x20
50 #define IRCSTATUS_reg 0x6C
51 #define IRCCTRL_reg 0x6C
57 #define IRCCTRL_IRC0MODE_mask 0x00000003
58 #define IRCCTRL_IRC0COUNT_mask 0x0000000C
59 #define IRCCTRL_IRC0RESET_mask 0x00000070
60 #define IRCCTRL_IRC0FILTER_mask 0x00000080
62 #define IRCCTRL_IRC1MODE_mask 0x00000300
63 #define IRCCTRL_IRC1COUNT_mask 0x00000C00
64 #define IRCCTRL_IRC1RESET_mask 0x00007000
65 #define IRCCTRL_IRC1FILTER_mask 0x00008000
67 #define IRCCTRL_IRC2MODE_mask 0x00030000
68 #define IRCCTRL_IRC2COUNT_mask 0x000C0000
69 #define IRCCTRL_IRC2RESET_mask 0x00700000
70 #define IRCCTRL_IRC2FILTER_mask 0x00800000
72 #define IRCCTRL_IRC3MODE_mask 0x03000000
73 #define IRCCTRL_IRC3COUNT_mask 0x0C000000
74 #define IRCCTRL_IRC3RESET_mask 0x70000000
75 #define IRCCTRL_IRC3FILTER_mask 0x80000000
77 #define IRCCTRL_CHANNEL_SHIFT 8
79 #define IRCCTRL_MODE_mask(ch) (0x03<<((ch)*IRCCTRL_CHANNEL_SHIFT))
80 #define IRCCTRL_COUNT_mask(ch) (0x0C<<((ch)*IRCCTRL_CHANNEL_SHIFT))
81 #define IRCCTRL_RESET_mask(ch) (0x70<<((ch)*IRCCTRL_CHANNEL_SHIFT))
82 #define IRCCTRL_FILTER_mask(ch) (0x80<<((ch)*IRCCTRL_CHANNEL_SHIFT))
84 #define IRCCTRL_MODE_IRC 0
85 #define IRCCTRL_MODE_BIDIR_RE 1
86 #define IRCCTRL_MODE_BIDIR_FE 2
87 #define IRCCTRL_MODE_BIDIR_BOTH 3
89 #define IRCCTRL_COUNT_ENABLED 0
90 #define IRCCTRL_COUNT_DISABLED 1
91 #define IRCCTRL_COUNT_IF_IDX_LO 2
92 #define IRCCTRL_COUNT_IF_IDX_HI 3
94 #define IRCCTRL_RESET_DISABLED 0
95 #define IRCCTRL_RESET_ALWAYS 1
96 #define IRCCTRL_RESET_IF_IDX_LO 2
97 #define IRCCTRL_RESET_IF_IDX_HI 3
98 #define IRCCTRL_RESET_IF_IDX_RE 4
99 #define IRCCTRL_RESET_IF_IDX_FE 5
100 #define IRCCTRL_RESET_IF_IDX_BOTH 6
102 #define IRCSTATUS_IRC0INDEX_mask 0x00000001
103 #define IRCSTATUS_IRC1INDEX_mask 0x00000100
104 #define IRCSTATUS_IRC2INDEX_mask 0x00000100
105 #define IRCSTATUS_IRC3INDEX_mask 0x00000100
107 #define IRCSTATUS_CHANNEL_SHIFT 8
109 #define IRCSTATUS_INDEX_mask(ch) (0x01<<((ch)*IRCSTATUS_CHANNEL_SHIFT))
111 #define GPIOC_DACEN_mask (1 << 26)
112 #define GPIOC_LDAC_mask (1 << 23)
113 #define GPIOC_EOLC_mask (1 << 17)
115 #define MFST2REG(mfst, bar_num, reg_offs) \
116 ((void *)(mfst->bar##bar_num.virt_addr + (reg_offs)))
119 typedef struct bar_mapping_t {
129 typedef enum {DA0, DA1, DA2, DA3, DA4, DA5, DA6, DA7} dac_channel_t;
130 typedef enum {AD0, AD1, AD2, AD3, AD4, AD5, AD6, AD7} adc_channel_t;
132 typedef struct mf624_state_t {
139 int ADC_enabled; // Which ADCs are enabled
143 //extern mf624_state_t mf624_state;
144 extern mf624_state_t* mfst;
146 static uint32_t dac_channel2reg[] = {
157 static uint32_t adc_channel2reg[] = {
168 static inline int16_t mf624_read16(void *ptr)
170 return *(volatile uint16_t*)ptr;
173 static inline int32_t mf624_read32(void *ptr)
175 return *(volatile uint32_t*) ptr;
178 static inline void mf624_write16(uint16_t val, void *ptr)
180 *(volatile uint16_t*) ptr = val;
183 static inline void mf624_write32(uint32_t val, void *ptr)
185 *(volatile uint32_t*) ptr = val;
188 extern void DIO_write(mf624_state_t* mfst, int16_t val);
190 extern uint16_t DIO_read(mf624_state_t* mfst);
192 extern void DAC_enable(mf624_state_t* mfst);
194 extern int DAC_write(mf624_state_t* mfst, dac_channel_t channel, int val);
196 extern int ADC_enable(mf624_state_t* mfst, adc_channel_t channel);
198 extern double ADC_read(mf624_state_t* mfst, adc_channel_t channel);
200 int mf624_init(SimStruct *S);
201 int mf624_check(SimStruct *S);