2 * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
4 * Copyright Freescale Semiconductor, Inc. 2007
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #ifndef __MCF5445X_SSI_H__
13 #define __MCF5445X_SSI_H__
15 /*********************************************************************
17 * Synchronous Serial Interface (SSI)
19 *********************************************************************/
21 /* Register read/write macros */
22 #define MCF_SSI_TX0 MCF_REG32(0xFC0BC000)
23 #define MCF_SSI_TX1 MCF_REG32(0xFC0BC004)
24 #define MCF_SSI_RX0 MCF_REG32(0xFC0BC008)
25 #define MCF_SSI_RX1 MCF_REG32(0xFC0BC00C)
26 #define MCF_SSI_CR MCF_REG32(0xFC0BC010)
27 #define MCF_SSI_ISR MCF_REG32(0xFC0BC014)
28 #define MCF_SSI_IER MCF_REG32(0xFC0BC018)
29 #define MCF_SSI_TCR MCF_REG32(0xFC0BC01C)
30 #define MCF_SSI_RCR MCF_REG32(0xFC0BC020)
31 #define MCF_SSI_CCR MCF_REG32(0xFC0BC024)
32 #define MCF_SSI_FCSR MCF_REG32(0xFC0BC02C)
33 #define MCF_SSI_ACR MCF_REG32(0xFC0BC038)
34 #define MCF_SSI_ACADD MCF_REG32(0xFC0BC03C)
35 #define MCF_SSI_ACDAT MCF_REG32(0xFC0BC040)
36 #define MCF_SSI_ATAG MCF_REG32(0xFC0BC044)
37 #define MCF_SSI_TMASK MCF_REG32(0xFC0BC048)
38 #define MCF_SSI_RMASK MCF_REG32(0xFC0BC04C)
40 /* Parameterized register read/write macros for multiple registers */
41 #define MCF_SSI_TX(x) MCF_REG32(0xFC0BC000+((x)*0x004))
42 #define MCF_SSI_RX(x) MCF_REG32(0xFC0BC008+((x)*0x004))
44 /* Bit definitions and macros for TX group */
45 #define MCF_SSI_TX_SSI_TX(x) (x)
47 /* Bit definitions and macros for TX0 */
48 #define MCF_SSI_TX0_SSI_TX(x) (x)
50 /* Bit definitions and macros for TX1 */
51 #define MCF_SSI_TX1_SSI_TX(x) (x)
53 /* Bit definitions and macros for RX group */
54 #define MCF_SSI_RX_SSI_RX(x) (x)
56 /* Bit definitions and macros for RX0 */
57 #define MCF_SSI_RX0_SSI_RX(x) (x)
59 /* Bit definitions and macros for RX1 */
60 #define MCF_SSI_RX1_SSI_RX(x) (x)
62 /* Bit definitions and macros for CR */
63 #define MCF_SSI_CR_SSI_EN (0x00000001)
64 #define MCF_SSI_CR_TE (0x00000002)
65 #define MCF_SSI_CR_RE (0x00000004)
66 #define MCF_SSI_CR_NET (0x00000008)
67 #define MCF_SSI_CR_SYN (0x00000010)
68 #define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5)
69 #define MCF_SSI_CR_MCE (0x00000080)
70 #define MCF_SSI_CR_TCH (0x00000100)
71 #define MCF_SSI_CR_CIS (0x00000200)
72 #define MCF_SSI_CR_I2S_NORMAL (0x00000000)
73 #define MCF_SSI_CR_I2S_MASTER (0x00000020)
74 #define MCF_SSI_CR_I2S_SLAVE (0x00000040)
76 /* Bit definitions and macros for ISR */
77 #define MCF_SSI_ISR_TFE0 (0x00000001)
78 #define MCF_SSI_ISR_TFE1 (0x00000002)
79 #define MCF_SSI_ISR_RFF0 (0x00000004)
80 #define MCF_SSI_ISR_RFF1 (0x00000008)
81 #define MCF_SSI_ISR_RLS (0x00000010)
82 #define MCF_SSI_ISR_TLS (0x00000020)
83 #define MCF_SSI_ISR_RFS (0x00000040)
84 #define MCF_SSI_ISR_TFS (0x00000080)
85 #define MCF_SSI_ISR_TUE0 (0x00000100)
86 #define MCF_SSI_ISR_TUE1 (0x00000200)
87 #define MCF_SSI_ISR_ROE0 (0x00000400)
88 #define MCF_SSI_ISR_ROE1 (0x00000800)
89 #define MCF_SSI_ISR_TDE0 (0x00001000)
90 #define MCF_SSI_ISR_TDE1 (0x00002000)
91 #define MCF_SSI_ISR_RDR0 (0x00004000)
92 #define MCF_SSI_ISR_RDR1 (0x00008000)
93 #define MCF_SSI_ISR_RXT (0x00010000)
94 #define MCF_SSI_ISR_CMDDU (0x00020000)
95 #define MCF_SSI_ISR_CMDAU (0x00040000)
97 /* Bit definitions and macros for IER */
98 #define MCF_SSI_IER_TFE0 (0x00000001)
99 #define MCF_SSI_IER_TFE1 (0x00000002)
100 #define MCF_SSI_IER_RFF0 (0x00000004)
101 #define MCF_SSI_IER_RFF1 (0x00000008)
102 #define MCF_SSI_IER_RLS (0x00000010)
103 #define MCF_SSI_IER_TLS (0x00000020)
104 #define MCF_SSI_IER_RFS (0x00000040)
105 #define MCF_SSI_IER_TFS (0x00000080)
106 #define MCF_SSI_IER_TUE0 (0x00000100)
107 #define MCF_SSI_IER_TUE1 (0x00000200)
108 #define MCF_SSI_IER_ROE0 (0x00000400)
109 #define MCF_SSI_IER_ROE1 (0x00000800)
110 #define MCF_SSI_IER_TDE0 (0x00001000)
111 #define MCF_SSI_IER_TDE1 (0x00002000)
112 #define MCF_SSI_IER_RDR0 (0x00004000)
113 #define MCF_SSI_IER_RDR1 (0x00008000)
114 #define MCF_SSI_IER_RXT (0x00010000)
115 #define MCF_SSI_IER_CMDU (0x00020000)
116 #define MCF_SSI_IER_CMDAU (0x00040000)
117 #define MCF_SSI_IER_TIE (0x00080000)
118 #define MCF_SSI_IER_TDMAE (0x00100000)
119 #define MCF_SSI_IER_RIE (0x00200000)
120 #define MCF_SSI_IER_RDMAE (0x00400000)
122 /* Bit definitions and macros for TCR */
123 #define MCF_SSI_TCR_TEFS (0x00000001)
124 #define MCF_SSI_TCR_TFSL (0x00000002)
125 #define MCF_SSI_TCR_TFSI (0x00000004)
126 #define MCF_SSI_TCR_TSCKP (0x00000008)
127 #define MCF_SSI_TCR_TSHFD (0x00000010)
128 #define MCF_SSI_TCR_TXDIR (0x00000020)
129 #define MCF_SSI_TCR_TFDIR (0x00000040)
130 #define MCF_SSI_TCR_TFEN0 (0x00000080)
131 #define MCF_SSI_TCR_TFEN1 (0x00000100)
132 #define MCF_SSI_TCR_TXBIT0 (0x00000200)
134 /* Bit definitions and macros for RCR */
135 #define MCF_SSI_RCR_REFS (0x00000001)
136 #define MCF_SSI_RCR_RFSL (0x00000002)
137 #define MCF_SSI_RCR_RFSI (0x00000004)
138 #define MCF_SSI_RCR_RSCKP (0x00000008)
139 #define MCF_SSI_RCR_RSHFD (0x00000010)
140 #define MCF_SSI_RCR_RFEN0 (0x00000080)
141 #define MCF_SSI_RCR_RFEN1 (0x00000100)
142 #define MCF_SSI_RCR_RXBIT0 (0x00000200)
143 #define MCF_SSI_RCR_RXEXT (0x00000400)
145 /* Bit definitions and macros for CCR */
146 #define MCF_SSI_CCR_PM(x) (((x)&0x000000FF))
147 #define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
148 #define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
149 #define MCF_SSI_CCR_PSR (0x00020000)
150 #define MCF_SSI_CCR_DIV2 (0x00040000)
152 /* Bit definitions and macros for FCSR */
153 #define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F))
154 #define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
155 #define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
156 #define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
157 #define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
158 #define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
159 #define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
160 #define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
162 /* Bit definitions and macros for ACR */
163 #define MCF_SSI_ACR_AC97EN (0x00000001)
164 #define MCF_SSI_ACR_FV (0x00000002)
165 #define MCF_SSI_ACR_TIF (0x00000004)
166 #define MCF_SSI_ACR_RD (0x00000008)
167 #define MCF_SSI_ACR_WR (0x00000010)
168 #define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
170 /* Bit definitions and macros for ACADD */
171 #define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF))
173 /* Bit definitions and macros for ACDAT */
174 #define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF))
176 /* Bit definitions and macros for ATAG */
177 #define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF))
179 /* Bit definitions and macros for TMASK */
180 #define MCF_SSI_TMASK_SSI_TMASK(x) (x)
182 /* Bit definitions and macros for RMASK */
183 #define MCF_SSI_RMASK_SSI_RMASK(x) (x)
185 /********************************************************************/
187 #endif /* __MCF5445X_SSI_H__ */