1 /*********************************************************************
3 * Copyright (C) 2004 Motorola, Inc.
4 * MOTOROLA, INC. All Rights Reserved.
5 * You are hereby granted a copyright license to use
6 * the SOFTWARE so long as this entire notice is
7 * retained without alteration in any modified and/or redistributed
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10 * otherwise under any patents or trademarks of Motorola, Inc. This
11 * software is provided on an "AS IS" basis and without warranty.
13 * To the maximum extent permitted by applicable law, MOTOROLA
14 * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
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16 * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
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28 ********************************************************************/
32 * Purpose: Main header file for multi-channel DMA API.
41 #include <asm/types.h>
44 * Turn Execution Unit tasks ON (#define) or OFF (#undef)
49 * Number of DMA channels
54 * Total number of variants
57 #define NUMOFVARIANTS 6
59 #define NUMOFVARIANTS 4
63 * Define sizes of the various tables
65 #define TASK_TABLE_SIZE (NCHANNELS*32)
66 #define VAR_TAB_SIZE (128)
67 #define CONTEXT_SAVE_SIZE (128)
68 #define FUNCDESC_TAB_SIZE (256)
71 #define FUNCDESC_TAB_NUM 16
73 #define FUNCDESC_TAB_NUM 1
80 * Portability typedefs
87 typedef unsigned int u32;
93 typedef unsigned short u16;
99 typedef unsigned char u8;
103 * These structures represent the internal registers of the
107 u32 taskbar; /* task table base address register */
112 u16 ptdControl; /* ptd control */
113 u32 intPending; /* interrupt pending register */
114 u32 intMask; /* interrupt mask register */
115 u16 taskControl[16]; /* task control registers */
116 u8 priority[32]; /* priority registers */
117 u32 initiatorMux; /* initiator mux control */
118 u32 taskSize0; /* task size control register 0. */
119 u32 taskSize1; /* task size control register 1. */
120 u32 dma_rsvd1; /* reserved */
121 u32 dma_rsvd2; /* reserved */
122 u32 debugComp1; /* debug comparator 1 */
123 u32 debugComp2; /* debug comparator 2 */
124 u32 debugControl; /* debug control */
125 u32 debugStatus; /* debug status */
126 u32 ptdDebug; /* priority task decode debug */
127 u32 dma_rsvd3[31]; /* reserved */
129 typedef volatile struct dmaRegs_s dmaRegs;
134 * PTD contrl reg bits
136 #define PTD_CTL_TSK_PRI 0x8000
137 #define PTD_CTL_COMM_PREFETCH 0x0001
140 * Task Control reg bits and field masks
142 #define TASK_CTL_EN 0x8000
143 #define TASK_CTL_VALID 0x4000
144 #define TASK_CTL_ALWAYS 0x2000
145 #define TASK_CTL_INIT_MASK 0x1f00
146 #define TASK_CTL_ASTRT 0x0080
147 #define TASK_CTL_HIPRITSKEN 0x0040
148 #define TASK_CTL_HLDINITNUM 0x0020
149 #define TASK_CTL_ASTSKNUM_MASK 0x000f
152 * Priority reg bits and field masks
154 #define PRIORITY_HLD 0x80
155 #define PRIORITY_PRI_MASK 0x07
158 * Debug Control reg bits and field masks
160 #define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
161 #define DBG_CTL_AUTO_ARM 0x00008000
162 #define DBG_CTL_BREAK 0x00004000
163 #define DBG_CTL_COMP1_TYP_MASK 0x00003800
164 #define DBG_CTL_COMP2_TYP_MASK 0x00000070
165 #define DBG_CTL_EXT_BREAK 0x00000004
166 #define DBG_CTL_INT_BREAK 0x00000002
169 * PTD Debug reg selector addresses
170 * This reg must be written with a value to show the contents of
171 * one of the desired internal register.
173 #define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
174 #define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
175 have initiators asserted */
179 * General return values
183 #define MCD_TABLE_UNALIGNED -2
184 #define MCD_CHANNEL_INVALID -3
187 * MCD_initDma input flags
189 #define MCD_RELOC_TASKS 0x00000001
190 #define MCD_NO_RELOC_TASKS 0x00000000
191 #define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */
194 * MCD_dmaStatus Status Values for each channel
196 #define MCD_NO_DMA 1 /* No DMA has been requested since reset */
197 #define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */
198 #define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
199 #define MCD_PAUSED 4 /* DMA active but it is currently paused */
200 #define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */
201 #define MCD_DONE 6 /* the most recent DMA has completed. */
205 * MCD_startDma parameter defines
209 * Constants for the funcDesc parameter
212 #define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */
213 #define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */
214 #define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of
215 each 32-bit data value being DMAed.*/
216 #define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each
217 16-bit half of each 32-bit data value DMAed */
218 #define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */
219 #define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */
221 #define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */
222 #define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */
223 #define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */
224 #define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/
225 #define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */
227 #define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
228 #define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
231 * Constants for the flags parameter
233 #define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
234 #define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
235 #define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */
236 #define MCD_TT_FLAGS_MASK 0x000000ff
237 #define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
239 #define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
240 #define MCD_CHAIN_DMA /* TBD */
241 #define MCD_EU_DMA /* TBD */
242 #define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
243 #define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
246 /* these flags are valid for MCD_startDma and the chained buffer descriptors */
247 #define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */
248 #define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
249 #define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */
250 #define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring
251 last byte of data in buffer */
252 #define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
253 prior to performing the DMA. */
255 /* Defines for the FEC buffer descriptor control/status word*/
256 #define MCD_FEC_BUF_READY 0x8000
257 #define MCD_FEC_WRAP 0x2000
258 #define MCD_FEC_INTERRUPT 0x1000
259 #define MCD_FEC_END_FRAME 0x0800
263 * Defines for general intuitiveness
270 * Three different cases for destination and source.
278 /* Task Table Entry struct*/
280 u32 TDTstart; /* task descriptor table start */
281 u32 TDTend; /* task descriptor table end */
282 u32 varTab; /* variable table start */
283 u32 FDTandFlags; /* function descriptor table start and flags */
284 volatile u32 descAddrAndStatus;
285 volatile u32 modifiedVarTab;
286 u32 contextSaveSpace; /* context save space start */
291 /* Chained buffer descriptor */
292 typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
293 struct MCD_bufDesc_struct {
294 u32 flags; /* flags describing the DMA */
295 u32 csumResult; /* checksum from checksumming performed since last checksum reset */
296 s8 *srcAddr; /* the address to move data from */
297 s8 *destAddr; /* the address to move data to */
298 s8 *lastDestAddr; /* the last address written to */
299 u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */
300 MCD_bufDesc *next; /* next buffer descriptor in chain */
301 u32 info; /* private information about this descriptor; DMA does not affect it */
304 /* Progress Query struct */
305 typedef volatile struct MCD_XferProg_struct {
306 s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */
307 s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */
308 u32 dmaSize; /* the amount of data transferred for the current buffer */
309 MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
313 /* FEC buffer descriptor */
314 typedef volatile struct MCD_bufDescFec_struct {
321 /*************************************************************************/
323 * API function Prototypes - see MCD_dmaApi.c for further notes
327 * MCD_startDma starts a particular kind of DMA .
330 int channel, /* the channel on which to run the DMA */
331 s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */
332 s16 srcIncr, /* the amount to increment the source address per transfer */
333 s8 *destAddr, /* the address to move data to */
334 s16 destIncr, /* the amount to increment the destination address per transfer */
335 u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
336 u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
337 u32 initiator, /* what device initiates the DMA */
338 int priority, /* priority of the DMA */
339 u32 flags, /* flags describing the DMA */
340 u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
344 * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
345 * registers, relocating and creating the appropriate task structures, and
346 * setting up some global settings
348 int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
351 * MCD_dmaStatus() returns the status of the DMA on the requested channel.
353 int MCD_dmaStatus (int channel);
356 * MCD_XferProgrQuery() returns progress of DMA on requested channel
358 int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
361 * MCD_killDma() halts the DMA on the requested channel, without any
362 * intention of resuming the DMA.
364 int MCD_killDma (int channel);
367 * MCD_continDma() continues a DMA which as stopped due to encountering an
368 * unready buffer descriptor.
370 int MCD_continDma (int channel);
373 * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
374 * running on that channel).
376 int MCD_pauseDma (int channel);
379 * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
380 * running on that channel).
382 int MCD_resumeDma (int channel);
385 * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
387 int MCD_csumQuery (int channel, u32 *csum);
390 * MCD_getCodeSize provides the packed size required by the microcoded task
393 int MCD_getCodeSize(void);
396 * MCD_getVersion provides a pointer to a version string and returns a
399 int MCD_getVersion(char **longVersion);
401 /* macro for setting a location in the variable table */
402 #define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
403 /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
404 so I'm avoiding surrounding it with "do {} while(0)" */
406 #endif /* DEFINESONLY */
408 #endif /* _MCD_API_H */