2 * Kurt Mahan kmahan@freescale.com
4 * Copyright Freescale Semiconductor, Inc. 2007
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #ifndef __MCF5445X_PCI_H__
13 #define __MCF5445X_PCI_H__
15 /*********************************************************************
17 * PCI Bus Controller (PCI)
19 *********************************************************************/
21 /* Register read/write macros */
22 #define MCF_PCI_PCIIDR MCF_REG32(0xFC0A8000)
23 #define MCF_PCI_PCISCR MCF_REG32(0xFC0A8004)
24 #define MCF_PCI_PCICCRIR MCF_REG32(0xFC0A8008)
25 #define MCF_PCI_PCICR1 MCF_REG32(0xFC0A800C)
26 #define MCF_PCI_PCIBAR0 MCF_REG32(0xFC0A8010)
27 #define MCF_PCI_PCIBAR1 MCF_REG32(0xFC0A8014)
28 #define MCF_PCI_PCIBAR2 MCF_REG32(0xFC0A8018)
29 #define MCF_PCI_PCIBAR3 MCF_REG32(0xFC0A801C)
30 #define MCF_PCI_PCIBAR4 MCF_REG32(0xFC0A8020)
31 #define MCF_PCI_PCIBAR5 MCF_REG32(0xFC0A8024)
32 #define MCF_PCI_PCISID MCF_REG32(0xFC0A802C)
33 #define MCF_PCI_PCICR2 MCF_REG32(0xFC0A803C)
34 #define MCF_PCI_PCIGSCR MCF_REG32(0xFC0A8060)
35 #define MCF_PCI_PCITBATR0A MCF_REG32(0xFC0A8064)
36 #define MCF_PCI_PCITBATR1A MCF_REG32(0xFC0A8068)
37 #define MCF_PCI_PCITCR MCF_REG32(0xFC0A806C)
38 #define MCF_PCI_PCIIW0BTAR MCF_REG32(0xFC0A8070)
39 #define MCF_PCI_PCIIW1BTAR MCF_REG32(0xFC0A8074)
40 #define MCF_PCI_PCIIW2BTAR MCF_REG32(0xFC0A8078)
41 #define MCF_PCI_PCIIWCR MCF_REG32(0xFC0A8080)
42 #define MCF_PCI_PCIICR MCF_REG32(0xFC0A8084)
43 #define MCF_PCI_PCIISR MCF_REG32(0xFC0A8088)
44 #define MCF_PCI_PCITCR2 MCF_REG32(0xFC0A808C)
45 #define MCF_PCI_PCITBATR0 MCF_REG32(0xFC0A8090)
46 #define MCF_PCI_PCITBATR1 MCF_REG32(0xFC0A8094)
47 #define MCF_PCI_PCITBATR2 MCF_REG32(0xFC0A8098)
48 #define MCF_PCI_PCITBATR3 MCF_REG32(0xFC0A809C)
49 #define MCF_PCI_PCITBATR4 MCF_REG32(0xFC0A80A0)
50 #define MCF_PCI_PCITBATR5 MCF_REG32(0xFC0A80A4)
51 #define MCF_PCI_PCICAR MCF_REG32(0xFC0A80F8)
53 /* Parameterized register read/write macros for multiple registers */
54 #define MCF_PCI_PCIIWBTAR(x) MCF_REG32(0xFC0A8070+((x)*0x004))
56 /* Bit definitions and macros for PCIIDR */
57 #define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF))
58 #define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
60 /* Bit definitions and macros for PCISCR */
61 #define MCF_PCI_PCISCR_M (0x00000002)
62 #define MCF_PCI_PCISCR_B (0x00000004)
63 #define MCF_PCI_PCISCR_SP (0x00000008)
64 #define MCF_PCI_PCISCR_MW (0x00000010)
65 #define MCF_PCI_PCISCR_PER (0x00000040)
66 #define MCF_PCI_PCISCR_S (0x00000100)
67 #define MCF_PCI_PCISCR_F (0x00000200)
68 #define MCF_PCI_PCISCR_C (0x00100000)
69 #define MCF_PCI_PCISCR_66M (0x00200000)
70 #define MCF_PCI_PCISCR_R (0x00400000)
71 #define MCF_PCI_PCISCR_FC (0x00800000)
72 #define MCF_PCI_PCISCR_DP (0x01000000)
73 #define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25)
74 #define MCF_PCI_PCISCR_TS (0x08000000)
75 #define MCF_PCI_PCISCR_TR (0x10000000)
76 #define MCF_PCI_PCISCR_MA (0x20000000)
77 #define MCF_PCI_PCISCR_SE (0x40000000)
78 #define MCF_PCI_PCISCR_PE (0x80000000)
80 /* Bit definitions and macros for PCICCRIR */
81 #define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF))
82 #define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
84 /* Bit definitions and macros for PCICR1 */
85 #define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F))
86 #define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
87 #define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
88 #define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
90 /* Bit definitions and macros for PCIBAR0 */
91 #define MCF_PCI_PCIBAR0_IO (0x00000001)
92 #define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1)
93 #define MCF_PCI_PCIBAR0_PREF (0x00000008)
94 #define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18)
96 /* Bit definitions and macros for PCIBAR1 */
97 #define MCF_PCI_PCIBAR1_IO (0x00000001)
98 #define MCF_PCI_PCIBAR1_PREF (0x00000008)
99 #define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000FFF)<<20)
101 /* Bit definitions and macros for PCIBAR2 */
102 #define MCF_PCI_PCIBAR2_IO (0x00000001)
103 #define MCF_PCI_PCIBAR2_RANGE(x) (((x)&0x00000003)<<1)
104 #define MCF_PCI_PCIBAR2_PREF (0x00000008)
105 #define MCF_PCI_PCIBAR2_BAR2(x) (((x)&0x000003FF)<<22)
107 /* Bit definitions and macros for PCIBAR3 */
108 #define MCF_PCI_PCIBAR3_IO (0x00000001)
109 #define MCF_PCI_PCIBAR3_PREF (0x00000008)
110 #define MCF_PCI_PCIBAR3_BAR3(x) (((x)&0x000000FF)<<24)
112 /* Bit definitions and macros for PCIBAR4 */
113 #define MCF_PCI_PCIBAR4_IO (0x00000001)
114 #define MCF_PCI_PCIBAR4_RANGE(x) (((x)&0x00000003)<<1)
115 #define MCF_PCI_PCIBAR4_PREF (0x00000008)
116 #define MCF_PCI_PCIBAR4_BAR4(x) (((x)&0x0000001F)<<27)
118 /* Bit definitions and macros for PCIBAR5 */
119 #define MCF_PCI_PCIBAR5_IO (0x00000001)
120 #define MCF_PCI_PCIBAR5_PREF (0x00000008)
121 #define MCF_PCI_PCIBAR5_BAR5(x) (((x)&0x0000000F)<<28)
123 /* Bit definitions and macros for PCISID */
124 #define MCF_PCI_PCISID_VENDORID(x) (((x)&0x0000FFFF))
125 #define MCF_PCI_PCISID_ID(x) (((x)&0x0000FFFF)<<16)
127 /* Bit definitions and macros for PCICR2 */
128 #define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF))
129 #define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
130 #define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
131 #define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
133 /* Bit definitions and macros for PCIGSCR */
134 #define MCF_PCI_PCIGSCR_PR (0x00000001)
135 #define MCF_PCI_PCIGSCR_SEE (0x00001000)
136 #define MCF_PCI_PCIGSCR_PEE (0x00002000)
137 #define MCF_PCI_PCIGSCR_SE (0x10000000)
138 #define MCF_PCI_PCIGSCR_PE (0x20000000)
140 /* Bit definitions and macros for PCITBATR0A */
141 #define MCF_PCI_PCITBATR0A_EN (0x00000001)
142 #define MCF_PCI_PCITBATR0A_BAT0(x) (((x)&0x00003FFF)<<18)
144 /* Bit definitions and macros for PCITBATR1A */
145 #define MCF_PCI_PCITBATR1A_EN (0x00000001)
146 #define MCF_PCI_PCITBATR1A_BAT1(x) (((x)&0x00000FFF)<<20)
148 /* Bit definitions and macros for PCITCR */
149 #define MCF_PCI_PCITCR_WCT(x) (((x)&0x000000FF))
150 #define MCF_PCI_PCITCR_WCD (0x00000100)
151 #define MCF_PCI_PCITCR_P (0x00010000)
152 #define MCF_PCI_PCITCR_PID (0x00020000)
153 #define MCF_PCI_PCITCR_LD (0x01000000)
155 /* Bit definitions and macros for PCIIWBTAR group */
156 #define MCF_PCI_PCIIWBTAR_WBA(x) ((((x)&0xFF000000)))
157 #define MCF_PCI_PCIIWBTAR_WAM(x) ((((x)&0xFF000000)
158 #define MCF_PCI_PCIIWBTAR_WTA(x) ((((x)&0xFF000000)
160 /* Bit definitions and macros for PCIIW0BTAR */
161 #define MCF_PCI_PCIIW0BTAR_WBA(x) ((((x)&0xFF000000)))
162 #define MCF_PCI_PCIIW0BTAR_WAM(x) ((((x)&0xFF000000)
163 #define MCF_PCI_PCIIW0BTAR_WTA(x) ((((x)&0xFF000000)
165 /* Bit definitions and macros for PCIIWCR */
166 #define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
167 #define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
168 #define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
169 #define MCF_PCI_PCIIWCR_WINCTRL0_ENABLE (0x01000000)
170 #define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
171 #define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
172 #define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
173 #define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000)
174 #define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
175 #define MCF_PCI_PCIIWCR_WINCTRL1_ENABLE (0x00010000)
176 #define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
177 #define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
178 #define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000)
179 #define MCF_PCI_PCIIWCR_WINCTRL2_ENABLE (0x00000100)
180 #define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
181 #define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
182 #define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
183 #define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900)
185 /* Bit definitions and macros for PCIICR */
186 #define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF))
187 #define MCF_PCI_PCIICR_TAE (0x01000000)
188 #define MCF_PCI_PCIICR_IAE (0x02000000)
189 #define MCF_PCI_PCIICR_REE (0x04000000)
191 /* Bit definitions and macros for PCIISR */
192 #define MCF_PCI_PCIISR_TA (0x01000000)
193 #define MCF_PCI_PCIISR_IA (0x02000000)
194 #define MCF_PCI_PCIISR_RE (0x04000000)
196 /* Bit definitions and macros for PCITCR2 */
197 #define MCF_PCI_PCITCR2_CR (0x00000001)
198 #define MCF_PCI_PCITCR2_B0E (0x00000100)
199 #define MCF_PCI_PCITCR2_B1E (0x00000200)
200 #define MCF_PCI_PCITCR2_B2E (0x00000400)
201 #define MCF_PCI_PCITCR2_B3E (0x00000800)
202 #define MCF_PCI_PCITCR2_B4E (0x00001000)
203 #define MCF_PCI_PCITCR2_B5E (0x00002000)
205 /* Bit definitions and macros for PCITBATR0 */
206 #define MCF_PCI_PCITBATR0_EN (0x00000001)
207 #define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
209 /* Bit definitions and macros for PCITBATR1 */
210 #define MCF_PCI_PCITBATR1_EN (0x00000001)
211 #define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000FFF)<<20)
213 /* Bit definitions and macros for PCITBATR2 */
214 #define MCF_PCI_PCITBATR2_EN (0x00000001)
215 #define MCF_PCI_PCITBATR2_BAT2(x) (((x)&0x000003FF)<<22)
217 /* Bit definitions and macros for PCITBATR3 */
218 #define MCF_PCI_PCITBATR3_EN (0x00000001)
219 #define MCF_PCI_PCITBATR3_BAT3(x) (((x)&0x000000FF)<<24)
221 /* Bit definitions and macros for PCITBATR4 */
222 #define MCF_PCI_PCITBATR4_EN (0x00000001)
223 #define MCF_PCI_PCITBATR4_BAT4(x) (((x)&0x0000001F)<<27)
225 /* Bit definitions and macros for PCITBATR5 */
226 #define MCF_PCI_PCITBATR5_EN (0x00000001)
227 #define MCF_PCI_PCITBATR5_BAT5(x) (((x)&0x0000000F)<<28)
229 /* Bit definitions and macros for PCICAR */
230 #define MCF_PCI_PCICAR_DWORD(x) ((x)&0x000000FC)
231 #define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
232 #define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
233 #define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
234 #define MCF_PCI_PCICAR_E (0x80000000)
236 /********************************************************************/
238 #endif /* __MCF5445X_PCI_H__ */