1 /****************************************************************************/
4 * mcfsim.h -- ColdFire System Integration Module support.
6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
10 /****************************************************************************/
13 /****************************************************************************/
15 #if defined(CONFIG_COLDFIRE)
16 #include <asm/coldfire.h>
20 * Include the appropriate ColdFire CPU specific System Integration Module
23 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
24 #include <asm/m5206sim.h>
25 #include <asm/mcfintc.h>
26 #elif defined(CONFIG_M520x)
27 #include <asm/m520xsim.h>
28 #elif defined(CONFIG_M523x)
29 #include <asm/m523xsim.h>
30 #include <asm/mcfintc.h>
31 #elif defined(CONFIG_M5249)
32 #include <asm/m5249sim.h>
33 #include <asm/mcfintc.h>
34 #elif defined(CONFIG_M527x)
35 #include <asm/m527xsim.h>
36 #elif defined(CONFIG_M5272)
37 #include <asm/m5272sim.h>
38 #elif defined(CONFIG_M528x)
39 #include <asm/m528xsim.h>
40 #elif defined(CONFIG_M5307)
41 #include <asm/m5307sim.h>
42 #include <asm/mcfintc.h>
43 #elif defined(CONFIG_M532x)
44 #include <asm/m532xsim.h>
45 #elif defined(CONFIG_M5407)
46 #include <asm/m5407sim.h>
47 #include <asm/mcfintc.h>
48 #elif defined(CONFIG_M5445X) //with MMU
49 #include <asm/mcf5445x_intc.h>
50 #include <asm/mcf5445x_gpio.h>
51 #include <asm/mcf5445x_ccm.h>
52 #include <asm/mcf5445x_eport.h>
53 #include <asm/mcf5445x_fbcs.h>
54 #include <asm/mcf5445x_xbs.h>
55 #include <asm/mcf5445x_dtim.h>
56 #include <asm/mcf5445x_rtc.h>
57 #include <asm/mcf5445x_scm.h>
58 #elif defined(CONFIG_M547X_8X) //with MMU
59 #include <asm/m548xsim.h>
60 #include <asm/m548xgpio.h>
61 #include <asm/m548xgpt.h>
65 * Define the base address of the SIM within the MBAR address space.
67 #define MCFSIM_BASE 0x0 /* Base address of SIM */
70 * Bit definitions for the ICR family of registers.
72 #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
73 #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
74 #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
75 #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
76 #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
77 #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
78 #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
79 #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
80 #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
82 #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
83 #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
84 #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
85 #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
88 * Bit definitions for the Interrupt Mask register (IMR).
90 #define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
91 #define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
92 #define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
93 #define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
94 #define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
95 #define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
96 #define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
98 #define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
99 #define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
100 #define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
101 #define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
102 #define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
103 #define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
106 * Mask for all of the SIM devices. Some parts have more or less
107 * SIM devices. This is a catchall for the sandard set.
109 #ifndef MCFSIM_IMR_MASKALL
110 #define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
115 * PIT interrupt settings, if not found in mXXXXsim.h file.
118 #define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */
121 #define MCFPIT_IMR MCFINTC_IMRH
123 #ifndef MCFPIT_IMR_IBIT
124 #define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32))
130 * Definition for the interrupt auto-vectoring support.
132 extern void mcf_autovector(unsigned int vec);
133 #endif /* __ASSEMBLY__ */
135 /****************************************************************************/
136 #endif /* mcfsim_h */