drivers/staging/sbe-2t3e3/intr.c

   1 /*
   2  * SBE 2T3E3 synchronous serial card driver for Linux
   3  *
   4  * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  * This code is based on a driver written by SBE Inc.
  11  */
  12
  13 #include <linux/hdlc.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/netdevice.h>
  16 #include "2t3e3.h"
  17
  18 irqreturn_t t3e3_intr(int irq, void *dev_instance)
  19 {
  20         struct channel *sc = dev_to_priv(dev_instance);
  21         u32 val;
  22         irqreturn_t ret = IRQ_NONE;
  23
  24         sc->interrupt_active = 1;
  25
  26         val = cpld_read(sc, SBE_2T3E3_CPLD_REG_PICSR);
  27
  28         if (val & SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_CHANGE) {
  29                 dev_dbg(&sc->pdev->dev,
  30                         "Rx LOS Chng Int r=%02x (LOS|OOF=%02x)\n",
  31                         val, (sc->s.LOS << 4) | sc->s.OOF);
  32                 cpld_LOS_update(sc);
  33                 ret = IRQ_HANDLED;
  34         }
  35
  36         if (val & SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_ETHERNET_ASSERTED) {
  37                 dc_intr(sc);
  38                 ret = IRQ_HANDLED;
  39         }
  40
  41         if (val & SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_FRAMER_ASSERTED) {
  42                 exar7250_intr(sc);
  43                 ret = IRQ_HANDLED;
  44         }
  45
  46         /*
  47           we don't care about other interrupt sources (DMO, LOS, LCV) because
  48           they are handled by Framer too
  49         */
  50
  51         sc->interrupt_active = 0;
  52         return ret;
  53 }
  54
  55 void dc_intr(struct channel *sc)
  56 {
  57         u32 val;
  58
  59         /* disable ethernet interrupts */
  60         /* grrr this clears interrupt summary bits !!! */
  61         dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
  62
  63         while ((val = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS)) &
  64                (SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED |
  65                 SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE |
  66                 SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT |
  67                 SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW |
  68                 SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE |
  69                 SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED |
  70                 SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT)) {
  71                 dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, val);
  72
  73                 dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Ethernet controller interrupt! (CSR5 = %08X)\n",
  74                         val);
  75
  76                 if (val & (SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT |
  77                            SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE |
  78                            SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED)) {
  79                         if (val & SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT)
  80                                 dev_dbg(&sc->pdev->dev,
  81                                         "Receive interrupt (LOS=%d, OOF=%d)\n",
  82                                         sc->s.LOS, sc->s.OOF);
  83                         if (val & SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE)
  84                                 dev_dbg(&sc->pdev->dev,
  85                                         "Receive buffer unavailable\n");
  86                         if (val & SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED)
  87                                 dev_dbg(&sc->pdev->dev,
  88                                         "Receive process stopped\n");
  89                         dc_intr_rx(sc);
  90                 }
  91
  92                 if (val & SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW) {
  93                         dev_dbg(&sc->pdev->dev, "Transmit underflow\n");
  94                         dc_intr_tx_underflow(sc);
  95                 }
  96
  97                 if (val & (SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE |
  98                            SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT |
  99                            SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED)) {
 100                         if (val & SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT)
 101                                 dev_dbg(&sc->pdev->dev, "Transmit interrupt\n");
 102                         if (val & SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE)
 103                                 dev_dbg(&sc->pdev->dev,
 104                                         "Transmit buffer unavailable\n");
 105                         if (val & SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED)
 106                                 dev_dbg(&sc->pdev->dev,
 107                                         "Transmit process stopped\n");
 108                         dc_intr_tx(sc);
 109                 }
 110         }
 111
 112         /* enable ethernet interrupts */
 113         dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE,
 114                  sc->ether.interrupt_enable_mask);
 115 }
 116
 117 void dc_intr_rx(struct channel *sc)
 118 {
 119         u32 current_read;
 120         u32 error_mask, error;
 121         t3e3_rx_desc_t *current_desc;
 122         struct sk_buff *m, *m2;
 123         unsigned rcv_len;
 124
 125         sc->rcv_count++; /* for the activity LED */
 126
 127         current_read = sc->ether.rx_ring_current_read;
 128         dev_dbg(&sc->pdev->dev, "intr_rx current_read = %d\n", current_read);
 129
 130         /* when ethernet loopback is set, ignore framer signals */
 131         if ((sc->p.loopback != SBE_2T3E3_LOOPBACK_ETHERNET) && sc->s.OOF) {
 132                 while (!(sc->ether.rx_ring[current_read].rdes0 &
 133                          SBE_2T3E3_RX_DESC_21143_OWN)) {
 134                         current_desc = &sc->ether.rx_ring[current_read];
 135                         current_desc->rdes1 &= SBE_2T3E3_RX_DESC_END_OF_RING |
 136                                 SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED;
 137                         current_desc->rdes1 |= SBE_2T3E3_MTU;
 138                         current_desc->rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
 139                         current_read = (current_read + 1) % SBE_2T3E3_RX_DESC_RING_SIZE;
 140                 }
 141                 sc->ether.rx_ring_current_read = current_read;
 142                 return;
 143         }
 144
 145         while (!(sc->ether.rx_ring[current_read].rdes0 &
 146                  SBE_2T3E3_RX_DESC_21143_OWN)) {
 147                 current_desc = &sc->ether.rx_ring[current_read];
 148
 149                 dev_dbg(&sc->pdev->dev, "rdes0: %08X        rdes1: %08X\n",
 150                         current_desc->rdes0, current_desc->rdes1);
 151
 152                 m = sc->ether.rx_data[current_read];
 153                 rcv_len = (current_desc->rdes0 & SBE_2T3E3_RX_DESC_FRAME_LENGTH) >>
 154                         SBE_2T3E3_RX_DESC_FRAME_LENGTH_SHIFT;
 155
 156                 dev_dbg(&sc->pdev->dev, "mbuf was received (mbuf len = %d)\n",
 157                         rcv_len);
 158
 159                 switch (sc->p.crc) {
 160                 case SBE_2T3E3_CRC_16:
 161                         rcv_len -= SBE_2T3E3_CRC16_LENGTH;
 162                         break;
 163                 case SBE_2T3E3_CRC_32:
 164                         rcv_len -= SBE_2T3E3_CRC32_LENGTH;
 165                         break;
 166                 default:
 167                         break;
 168                 }
 169
 170                 if (current_desc->rdes0 & SBE_2T3E3_RX_DESC_LAST_DESC) {
 171
 172                         /* TODO: is collision possible? */
 173                         error_mask = SBE_2T3E3_RX_DESC_DESC_ERROR |
 174                                 SBE_2T3E3_RX_DESC_COLLISION_SEEN |
 175                                 SBE_2T3E3_RX_DESC_DRIBBLING_BIT;
 176
 177                         switch (sc->p.frame_mode) {
 178                         case SBE_2T3E3_FRAME_MODE_HDLC:
 179                                 error_mask |= SBE_2T3E3_RX_DESC_MII_ERROR;
 180                                 if (sc->p.crc == SBE_2T3E3_CRC_32)
 181                                         error_mask |= SBE_2T3E3_RX_DESC_CRC_ERROR;
 182                                 break;
 183                         case SBE_2T3E3_FRAME_MODE_TRANSPARENT:
 184                         case SBE_2T3E3_FRAME_MODE_RAW:
 185                                 break;
 186                         default:
 187                                 error_mask = 0;
 188                         }
 189
 190                         if (sc->s.LOS) {
 191                                 error_mask &= ~(SBE_2T3E3_RX_DESC_DRIBBLING_BIT ||
 192                                                 SBE_2T3E3_RX_DESC_MII_ERROR);
 193                         }
 194
 195                         error = current_desc->rdes0 & error_mask;
 196                         if (error) {
 197                                 sc->s.in_errors++;
 198                                 dev_dbg(&sc->pdev->dev,
 199                                         "error interrupt: NO_ERROR_MESSAGE = %d\n",
 200                                         sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES ? 1 : 0);
 201
 202                                 current_desc->rdes1 &= SBE_2T3E3_RX_DESC_END_OF_RING |
 203                                         SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED;
 204                                 current_desc->rdes1 |= SBE_2T3E3_MTU;
 205                                 current_desc->rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
 206
 207                                 if (error & SBE_2T3E3_RX_DESC_DESC_ERROR) {
 208                                         if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
 209                                                 dev_err(&sc->pdev->dev,
 210                                                         "SBE 2T3E3: descriptor error\n");
 211                                         sc->s.in_error_desc++;
 212                                 }
 213
 214                                 if (error & SBE_2T3E3_RX_DESC_COLLISION_SEEN) {
 215                                         if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
 216                                                 dev_err(&sc->pdev->dev,
 217                                                         "SBE 2T3E3: collision seen\n");
 218                                         sc->s.in_error_coll++;
 219                                 } else {
 220                                         if (error & SBE_2T3E3_RX_DESC_DRIBBLING_BIT) {
 221                                                 if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
 222                                                         dev_err(&sc->pdev->dev,
 223                                                                 "SBE 2T3E3: dribbling bits error\n");
 224                                                 sc->s.in_error_drib++;
 225                                         }
 226
 227                                         if (error & SBE_2T3E3_RX_DESC_CRC_ERROR) {
 228                                                 if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
 229                                                         dev_err(&sc->pdev->dev,
 230                                                                 "SBE 2T3E3: crc error\n");
 231                                                 sc->s.in_error_crc++;
 232                                         }
 233                                 }
 234
 235                                 if (error & SBE_2T3E3_RX_DESC_MII_ERROR) {
 236                                         if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
 237                                                 dev_err(&sc->pdev->dev, "SBE 2T3E3: mii error\n");
 238                                         sc->s.in_error_mii++;
 239                                 }
 240
 241                                 current_read = (current_read + 1) % SBE_2T3E3_RX_DESC_RING_SIZE;
 242                                 sc->r.flags |= SBE_2T3E3_FLAG_NO_ERROR_MESSAGES;
 243                                 continue;
 244                         }
 245                 }
 246
 247                 current_desc->rdes1 &= SBE_2T3E3_RX_DESC_END_OF_RING |
 248                         SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED;
 249                 current_desc->rdes1 |= SBE_2T3E3_MTU;
 250
 251                 if (rcv_len > 1600) {
 252                         sc->s.in_errors++;
 253                         sc->s.in_dropped++;
 254                         if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
 255                                 dev_err(&sc->pdev->dev, "SBE 2T3E3: oversized rx: rdes0 = %08X\n",
 256                                         current_desc->rdes0);
 257                 } else {
 258                         m2 = dev_alloc_skb(MCLBYTES);
 259                         if (m2 != NULL) {
 260                                 current_desc->rdes2 = virt_to_phys(m2->data);
 261                                 sc->ether.rx_data[current_read] = m2;
 262                                 sc->s.in_packets++;
 263                                 sc->s.in_bytes += rcv_len;
 264                                 m->dev = sc->dev;
 265                                 skb_put(m, rcv_len);
 266                                 skb_reset_mac_header(m);
 267                                 m->protocol = hdlc_type_trans(m, m->dev);
 268                                 netif_rx(m);
 269
 270                                 /* good packet was received so we will show error messages again... */
 271                                 if (sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES) {
 272                                         dev_dbg(&sc->pdev->dev,
 273                                                 "setting ERROR_MESSAGES->0\n");
 274                                         sc->r.flags &= ~SBE_2T3E3_FLAG_NO_ERROR_MESSAGES;
 275                                 }
 276
 277                         } else {
 278                                 sc->s.in_errors++;
 279                                 sc->s.in_dropped++;
 280                         }
 281                 }
 282                 current_desc->rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
 283                 current_read = (current_read + 1) % SBE_2T3E3_RX_DESC_RING_SIZE;
 284         }
 285
 286         sc->ether.rx_ring_current_read = current_read;
 287
 288         dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND, 0xFFFFFFFF);
 289 }
 290
 291 void dc_intr_tx(struct channel *sc)
 292 {
 293         u32 current_read, current_write;
 294         u32 last_segment, error;
 295         t3e3_tx_desc_t *current_desc;
 296
 297         spin_lock(&sc->ether.tx_lock);
 298
 299         current_read = sc->ether.tx_ring_current_read;
 300         current_write = sc->ether.tx_ring_current_write;
 301
 302         while (current_read != current_write) {
 303                 current_desc = &sc->ether.tx_ring[current_read];
 304
 305                 if (current_desc->tdes0 & SBE_2T3E3_RX_DESC_21143_OWN)
 306                         break;
 307
 308                 dev_dbg(&sc->pdev->dev,
 309                         "txeof: tdes0 = %08X        tdes1 = %08X\n",
 310                         current_desc->tdes0, current_desc->tdes1);
 311
 312                 error = current_desc->tdes0 & (SBE_2T3E3_TX_DESC_ERROR_SUMMARY |
 313                                                SBE_2T3E3_TX_DESC_TRANSMIT_JABBER_TIMEOUT |
 314                                                SBE_2T3E3_TX_DESC_LOSS_OF_CARRIER |
 315                                                SBE_2T3E3_TX_DESC_NO_CARRIER |
 316                                                SBE_2T3E3_TX_DESC_LINK_FAIL_REPORT |
 317                                                SBE_2T3E3_TX_DESC_UNDERFLOW_ERROR |
 318                                                SBE_2T3E3_TX_DESC_DEFFERED);
 319
 320                 last_segment = current_desc->tdes1 & SBE_2T3E3_TX_DESC_LAST_SEGMENT;
 321
 322                 current_desc->tdes0 = 0;
 323                 current_desc->tdes1 &= SBE_2T3E3_TX_DESC_END_OF_RING |
 324                         SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED;
 325                 current_desc->tdes2 = 0;
 326                 sc->ether.tx_free_cnt++;
 327
 328                 if (last_segment != SBE_2T3E3_TX_DESC_LAST_SEGMENT) {
 329                         current_read = (current_read + 1) % SBE_2T3E3_TX_DESC_RING_SIZE;
 330                         continue;
 331                 }
 332
 333
 334                 if (sc->ether.tx_data[current_read]) {
 335                         sc->s.out_packets++;
 336                         sc->s.out_bytes += sc->ether.tx_data[current_read]->len;
 337                         dev_kfree_skb_any(sc->ether.tx_data[current_read]);
 338                         sc->ether.tx_data[current_read] = NULL;
 339                 }
 340
 341                 if (error > 0) {
 342                         sc->s.out_errors++;
 343
 344                         if (error & SBE_2T3E3_TX_DESC_TRANSMIT_JABBER_TIMEOUT) {
 345                                 dev_err(&sc->pdev->dev, "SBE 2T3E3: transmit jabber timeout\n");
 346                                 sc->s.out_error_jab++;
 347                         }
 348
 349                         if (sc->p.loopback != SBE_2T3E3_LOOPBACK_ETHERNET) {
 350                                 if (error & SBE_2T3E3_TX_DESC_LOSS_OF_CARRIER) {
 351                                         dev_err(&sc->pdev->dev, "SBE 2T3E3: loss of carrier\n");
 352                                         sc->s.out_error_lost_carr++;
 353                                 }
 354
 355                                 if (error & SBE_2T3E3_TX_DESC_NO_CARRIER) {
 356                                         dev_err(&sc->pdev->dev, "SBE 2T3E3: no carrier\n");
 357                                         sc->s.out_error_no_carr++;
 358                                 }
 359                         }
 360
 361                         if (error & SBE_2T3E3_TX_DESC_LINK_FAIL_REPORT) {
 362                                 dev_err(&sc->pdev->dev, "SBE 2T3E3: link fail report\n");
 363                                 sc->s.out_error_link_fail++;
 364                         }
 365
 366                         if (error & SBE_2T3E3_TX_DESC_UNDERFLOW_ERROR) {
 367                                 dev_err(&sc->pdev->dev, "SBE 2T3E3:"
 368                                         " transmission underflow error\n");
 369                                 sc->s.out_error_underflow++;
 370                                 spin_unlock(&sc->ether.tx_lock);
 371
 372                                 dc_restart(sc);
 373                                 return;
 374                         }
 375
 376                         if (error & SBE_2T3E3_TX_DESC_DEFFERED) {
 377                                 dev_err(&sc->pdev->dev, "SBE 2T3E3: transmission deferred\n");
 378                                 sc->s.out_error_dereferred++;
 379                         }
 380                 }
 381
 382                 current_read = (current_read + 1) % SBE_2T3E3_TX_DESC_RING_SIZE;
 383         }
 384
 385         sc->ether.tx_ring_current_read = current_read;
 386
 387         /* Relieve flow control when the TX queue is drained at least half way */
 388         if (sc->ether.tx_full &&
 389             (sc->ether.tx_free_cnt >= (SBE_2T3E3_TX_DESC_RING_SIZE / 2))) {
 390                 sc->ether.tx_full = 0;
 391                 netif_wake_queue(sc->dev);
 392         }
 393         spin_unlock(&sc->ether.tx_lock);
 394 }
 395
 396
 397 void dc_intr_tx_underflow(struct channel *sc)
 398 {
 399         u32 val;
 400
 401         dc_transmitter_onoff(sc, SBE_2T3E3_OFF);
 402
 403         val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE);
 404         dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
 405                       SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS);
 406
 407         switch (val & SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS) {
 408         case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_1:
 409                 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
 410                             SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_2);
 411                 break;
 412         case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_2:
 413                 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
 414                             SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_3);
 415                 break;
 416         case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_3:
 417                 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
 418                             SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_4);
 419                 break;
 420         case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_4:
 421         default:
 422                 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
 423                             SBE_2T3E3_21143_VAL_STORE_AND_FORWARD);
 424                 break;
 425         }
 426
 427         dc_transmitter_onoff(sc, SBE_2T3E3_ON);
 428 }
 429
 430
 431
 432
 433 void exar7250_intr(struct channel *sc)
 434 {
 435         u32 status, old_OOF;
 436
 437 #if 0
 438         /* disable interrupts */
 439         exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE, 0);
 440 #endif
 441
 442         old_OOF = sc->s.OOF;
 443
 444         status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS);
 445         dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt! (REG[0x05] = %02X)\n", status);
 446
 447         switch (sc->p.frame_type) {
 448         case SBE_2T3E3_FRAME_TYPE_E3_G751:
 449         case SBE_2T3E3_FRAME_TYPE_E3_G832:
 450                 exar7250_E3_intr(sc, status);
 451                 break;
 452
 453         case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
 454         case SBE_2T3E3_FRAME_TYPE_T3_M13:
 455                 exar7250_T3_intr(sc, status);
 456                 break;
 457
 458         default:
 459                 break;
 460         }
 461
 462         if (sc->s.OOF != old_OOF) {
 463                 if (sc->s.OOF) {
 464                         if (sc->p.loopback == SBE_2T3E3_LOOPBACK_NONE) {
 465                                 dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Disabling eth interrupts\n");
 466                                 /* turn off ethernet interrupts */
 467                                 dc_stop_intr(sc);
 468                         }
 469                 } else if (sc->r.flags & SBE_2T3E3_FLAG_NETWORK_UP) {
 470                         dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Enabling eth interrupts\n");
 471                         /* start interrupts */
 472                         sc->s.OOF = 1;
 473                         dc_intr_rx(sc);
 474                         sc->s.OOF = 0;
 475                         if (sc->p.receiver_on) {
 476                                 dc_receiver_onoff(sc, SBE_2T3E3_OFF);
 477                                 dc_receiver_onoff(sc, SBE_2T3E3_ON);
 478                         }
 479                         dc_start_intr(sc);
 480                 }
 481         }
 482 #if 0
 483         /* reenable interrupts */
 484         exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE,
 485                        SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_ENABLE |
 486                        SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_ENABLE
 487                 );
 488 #endif
 489 }
 490
 491
 492 void exar7250_T3_intr(struct channel *sc, u32 block_status)
 493 {
 494         u32 status, result;
 495
 496         if (block_status & SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_STATUS) {
 497                 status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS);
 498
 499                 if (status) {
 500                         dev_dbg(&sc->pdev->dev,
 501                                 "Framer interrupt T3 RX (REG[0x13] = %02X)\n",
 502                                 status);
 503
 504                         result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
 505
 506 #if 0
 507                         if (status & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_STATUS) {
 508                                 dev_dbg(&sc->pdev->dev,
 509                                         "Framer interrupt T3: LOS\n");
 510                                 sc->s.LOS = result & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS ? 1 : 0;
 511
 512                         }
 513 #else
 514                         cpld_LOS_update(sc);
 515 #endif
 516                         if (status & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_STATUS) {
 517                                 sc->s.OOF = result & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
 518                                 dev_dbg(&sc->pdev->dev,
 519                                         "Framer interrupt T3: OOF (%d)\n",
 520                                         sc->s.OOF);
 521                         }
 522
 523                         exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE,
 524                                        SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
 525                                        SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE);
 526 #if 0
 527                         SBE_2T3E3_FRAMER_VAL_T3_RX_CP_BIT_ERROR_INTERRUPT_ENABLE |
 528                                 SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
 529                                 SBE_2T3E3_FRAMER_VAL_T3_RX_AIS_INTERRUPT_ENABLE |
 530                                 SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE_INTERRUPT_ENABLE |
 531                                 SBE_2T3E3_FRAMER_VAL_T3_RX_FERF_INTERRUPT_ENABLE |
 532                                 SBE_2T3E3_FRAMER_VAL_T3_RX_AIC_INTERRUPT_ENABLE |
 533                                 SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE |
 534                                 SBE_2T3E3_FRAMER_VAL_T3_RX_P_BIT_INTERRUPT_ENABLE
 535 #endif
 536                                 }
 537
 538                 status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS);
 539                 if (status) {
 540                         dev_dbg(&sc->pdev->dev,
 541                                 "Framer interrupt T3 RX (REG[0x17] = %02X)\n",
 542                                 status);
 543 #if 0
 544                         exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS,
 545                                        SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_ENABLE |
 546                                        SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_ENABLE
 547                                 );
 548 #endif
 549                 }
 550
 551                 status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL);
 552                 if (status)
 553                         dev_dbg(&sc->pdev->dev,
 554                                 "Framer interrupt T3 RX (REG[0x18] = %02X)\n",
 555                                 status);
 556         }
 557
 558
 559         if (block_status & SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_STATUS) {
 560                 status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS);
 561                 dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt T3 TX (REG[0x31] = %02X)\n",
 562                         status);
 563
 564                 status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS);
 565                 dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt T3 TX (REG[0x34] = %02X)\n",
 566                         status);
 567         }
 568 }
 569
 570
 571 void exar7250_E3_intr(struct channel *sc, u32 block_status)
 572 {
 573         u32 status, result;
 574
 575         if (block_status & SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_STATUS) {
 576                 status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1);
 577
 578                 if (status) {
 579                         dev_dbg(&sc->pdev->dev,
 580                                 "Framer interrupt E3 RX (REG[0x14] = %02X)\n",
 581                                 status);
 582
 583                         result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
 584
 585 #if 0
 586                         if (status & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_STATUS) {
 587                                 dev_dbg(&sc->pdev->dev,
 588                                         "Framer interrupt E3: LOS\n");
 589                                 sc->s.LOS = result & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS ? 1 : 0;
 590                         }
 591 #else
 592                         cpld_LOS_update(sc);
 593 #endif
 594                         if (status & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_STATUS) {
 595                                 sc->s.OOF = result & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
 596                                 dev_dbg(&sc->pdev->dev,
 597                                         "Framer interrupt E3: OOF (%d)\n",
 598                                         sc->s.OOF);
 599                         }
 600
 601                         exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1,
 602                                        SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
 603                                        SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE
 604                                 );
 605 #if 0
 606                         SBE_2T3E3_FRAMER_VAL_E3_RX_COFA_INTERRUPT_ENABLE |
 607                                 SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
 608                                 SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_INTERRUPT_ENABLE |
 609                                 SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE |
 610                                 SBE_2T3E3_FRAMER_VAL_E3_RX_AIS_INTERRUPT_ENABLE
 611 #endif
 612                                 }
 613
 614                 status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2);
 615                 if (status) {
 616                         dev_dbg(&sc->pdev->dev,
 617                                 "Framer interrupt E3 RX (REG[0x15] = %02X)\n",
 618                                 status);
 619
 620 #if 0
 621                         exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2,
 622                                        SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_ENABLE |
 623                                        SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_ENABLE |
 624                                        SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_ENABLE);
 625 #endif
 626                 }
 627
 628         }
 629
 630         if (block_status & SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_STATUS) {
 631                 status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS);
 632                 dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt E3 TX (REG[0x34] = %02X)\n",
 633                         status);
 634         }
 635 }