2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "sysemu/kvm.h"
37 #if !defined(CONFIG_USER_ONLY)
39 /* no MMU emulation */
40 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
41 target_ulong address, int rw, int access_type)
44 *prot = PAGE_READ | PAGE_WRITE;
48 /* fixed mapping MMU emulation */
49 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
50 target_ulong address, int rw, int access_type)
52 if (address <= (int32_t)0x7FFFFFFFUL) {
53 if (!(env->CP0_Status & (1 << CP0St_ERL)))
54 *physical = address + 0x40000000UL;
57 } else if (address <= (int32_t)0xBFFFFFFFUL)
58 *physical = address & 0x1FFFFFFF;
62 *prot = PAGE_READ | PAGE_WRITE;
66 /* MIPS32/MIPS64 R4000-style MMU emulation */
67 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
68 target_ulong address, int rw, int access_type)
70 uint8_t ASID = env->CP0_EntryHi & 0xFF;
73 for (i = 0; i < env->tlb->tlb_in_use; i++) {
74 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
75 /* 1k pages are not supported. */
76 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
77 target_ulong tag = address & ~mask;
78 target_ulong VPN = tlb->VPN & ~mask;
79 #if defined(TARGET_MIPS64)
83 /* Check ASID, virtual page number & size */
84 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
86 int n = !!(address & mask & ~(mask >> 1));
87 /* Check access rights */
88 if (!(n ? tlb->V1 : tlb->V0))
89 return TLBRET_INVALID;
90 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
91 *physical = tlb->PFN[n] | (address & (mask >> 1));
93 if (n ? tlb->D1 : tlb->D0)
100 return TLBRET_NOMATCH;
103 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
104 int *prot, target_ulong real_address,
105 int rw, int access_type)
107 /* User mode can only access useg/xuseg */
108 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
109 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
110 int kernel_mode = !user_mode && !supervisor_mode;
111 #if defined(TARGET_MIPS64)
112 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
113 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
114 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
116 int ret = TLBRET_MATCH;
117 /* effective address (modified for KVM T&E kernel segments) */
118 target_ulong address = real_address;
121 qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
124 #define USEG_LIMIT 0x7FFFFFFFUL
125 #define KSEG0_BASE 0x80000000UL
126 #define KSEG1_BASE 0xA0000000UL
127 #define KSEG2_BASE 0xC0000000UL
128 #define KSEG3_BASE 0xE0000000UL
130 #define KVM_KSEG0_BASE 0x40000000UL
131 #define KVM_KSEG2_BASE 0x60000000UL
134 /* KVM T&E adds guest kernel segments in useg */
135 if (real_address >= KVM_KSEG0_BASE) {
136 if (real_address < KVM_KSEG2_BASE) {
138 address += KSEG0_BASE - KVM_KSEG0_BASE;
139 } else if (real_address <= USEG_LIMIT) {
141 address += KSEG2_BASE - KVM_KSEG2_BASE;
146 if (address <= USEG_LIMIT) {
148 if (env->CP0_Status & (1 << CP0St_ERL)) {
149 *physical = address & 0xFFFFFFFF;
150 *prot = PAGE_READ | PAGE_WRITE;
152 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
154 #if defined(TARGET_MIPS64)
155 } else if (address < 0x4000000000000000ULL) {
157 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
158 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
160 ret = TLBRET_BADADDR;
162 } else if (address < 0x8000000000000000ULL) {
164 if ((supervisor_mode || kernel_mode) &&
165 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
166 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
168 ret = TLBRET_BADADDR;
170 } else if (address < 0xC000000000000000ULL) {
172 if (kernel_mode && KX &&
173 (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
174 *physical = address & env->PAMask;
175 *prot = PAGE_READ | PAGE_WRITE;
177 ret = TLBRET_BADADDR;
179 } else if (address < 0xFFFFFFFF80000000ULL) {
181 if (kernel_mode && KX &&
182 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
183 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
185 ret = TLBRET_BADADDR;
188 } else if (address < (int32_t)KSEG1_BASE) {
191 *physical = address - (int32_t)KSEG0_BASE;
192 *prot = PAGE_READ | PAGE_WRITE;
194 ret = TLBRET_BADADDR;
196 } else if (address < (int32_t)KSEG2_BASE) {
199 *physical = address - (int32_t)KSEG1_BASE;
200 *prot = PAGE_READ | PAGE_WRITE;
202 ret = TLBRET_BADADDR;
204 } else if (address < (int32_t)KSEG3_BASE) {
206 if (supervisor_mode || kernel_mode) {
207 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
209 ret = TLBRET_BADADDR;
213 /* XXX: debug segment is not emulated */
215 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
217 ret = TLBRET_BADADDR;
221 qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n",
222 address, rw, access_type, *physical, *prot, ret);
229 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
230 int rw, int tlb_error)
232 CPUState *cs = CPU(mips_env_get_cpu(env));
233 int exception = 0, error_code = 0;
238 /* Reference to kernel address from user mode or supervisor mode */
239 /* Reference to supervisor address from user mode */
241 exception = EXCP_AdES;
243 exception = EXCP_AdEL;
246 /* No TLB match for a mapped address */
248 exception = EXCP_TLBS;
250 exception = EXCP_TLBL;
254 /* TLB match with no valid bit */
256 exception = EXCP_TLBS;
258 exception = EXCP_TLBL;
261 /* TLB match but 'D' bit is cleared */
262 exception = EXCP_LTLBL;
266 /* Raise exception */
267 env->CP0_BadVAddr = address;
268 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
269 ((address >> 9) & 0x007ffff0);
271 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
272 #if defined(TARGET_MIPS64)
273 env->CP0_EntryHi &= env->SEGMask;
274 env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
275 ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
276 ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
278 cs->exception_index = exception;
279 env->error_code = error_code;
282 #if !defined(CONFIG_USER_ONLY)
283 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
285 MIPSCPU *cpu = MIPS_CPU(cs);
289 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
297 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
300 MIPSCPU *cpu = MIPS_CPU(cs);
301 CPUMIPSState *env = &cpu->env;
302 #if !defined(CONFIG_USER_ONLY)
310 log_cpu_state(cs, 0);
312 qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
313 __func__, env->active_tc.PC, address, rw, mmu_idx);
318 #if !defined(CONFIG_USER_ONLY)
319 /* XXX: put correct access by using cpu_restore_state()
321 access_type = ACCESS_INT;
322 ret = get_physical_address(env, &physical, &prot,
323 address, rw, access_type);
324 qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
326 __func__, address, ret, physical, prot);
327 if (ret == TLBRET_MATCH) {
328 tlb_set_page(cs, address & TARGET_PAGE_MASK,
329 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
330 mmu_idx, TARGET_PAGE_SIZE);
335 raise_mmu_exception(env, address, rw, ret);
342 #if !defined(CONFIG_USER_ONLY)
343 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
353 access_type = ACCESS_INT;
354 ret = get_physical_address(env, &physical, &prot,
355 address, rw, access_type);
356 if (ret != TLBRET_MATCH) {
357 raise_mmu_exception(env, address, rw, ret);
365 static const char * const excp_names[EXCP_LAST + 1] = {
366 [EXCP_RESET] = "reset",
367 [EXCP_SRESET] = "soft reset",
368 [EXCP_DSS] = "debug single step",
369 [EXCP_DINT] = "debug interrupt",
370 [EXCP_NMI] = "non-maskable interrupt",
371 [EXCP_MCHECK] = "machine check",
372 [EXCP_EXT_INTERRUPT] = "interrupt",
373 [EXCP_DFWATCH] = "deferred watchpoint",
374 [EXCP_DIB] = "debug instruction breakpoint",
375 [EXCP_IWATCH] = "instruction fetch watchpoint",
376 [EXCP_AdEL] = "address error load",
377 [EXCP_AdES] = "address error store",
378 [EXCP_TLBF] = "TLB refill",
379 [EXCP_IBE] = "instruction bus error",
380 [EXCP_DBp] = "debug breakpoint",
381 [EXCP_SYSCALL] = "syscall",
382 [EXCP_BREAK] = "break",
383 [EXCP_CpU] = "coprocessor unusable",
384 [EXCP_RI] = "reserved instruction",
385 [EXCP_OVERFLOW] = "arithmetic overflow",
386 [EXCP_TRAP] = "trap",
387 [EXCP_FPE] = "floating point",
388 [EXCP_DDBS] = "debug data break store",
389 [EXCP_DWATCH] = "data watchpoint",
390 [EXCP_LTLBL] = "TLB modify",
391 [EXCP_TLBL] = "TLB load",
392 [EXCP_TLBS] = "TLB store",
393 [EXCP_DBE] = "data bus error",
394 [EXCP_DDBL] = "debug data break load",
395 [EXCP_THREAD] = "thread",
396 [EXCP_MDMX] = "MDMX",
397 [EXCP_C2E] = "precise coprocessor 2",
398 [EXCP_CACHE] = "cache error",
401 target_ulong exception_resume_pc (CPUMIPSState *env)
404 target_ulong isa_mode;
406 isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
407 bad_pc = env->active_tc.PC | isa_mode;
408 if (env->hflags & MIPS_HFLAG_BMASK) {
409 /* If the exception was raised from a delay slot, come back to
411 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
417 #if !defined(CONFIG_USER_ONLY)
418 static void set_hflags_for_handler (CPUMIPSState *env)
420 /* Exception handlers are entered in 32-bit mode. */
421 env->hflags &= ~(MIPS_HFLAG_M16);
422 /* ...except that microMIPS lets you choose. */
423 if (env->insn_flags & ASE_MICROMIPS) {
424 env->hflags |= (!!(env->CP0_Config3
425 & (1 << CP0C3_ISA_ON_EXC))
426 << MIPS_HFLAG_M16_SHIFT);
431 void mips_cpu_do_interrupt(CPUState *cs)
433 #if !defined(CONFIG_USER_ONLY)
434 MIPSCPU *cpu = MIPS_CPU(cs);
435 CPUMIPSState *env = &cpu->env;
440 if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
441 if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
444 name = excp_names[cs->exception_index];
447 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
448 __func__, env->active_tc.PC, env->CP0_EPC, name);
450 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
451 (env->hflags & MIPS_HFLAG_DM)) {
452 cs->exception_index = EXCP_DINT;
455 switch (cs->exception_index) {
457 env->CP0_Debug |= 1 << CP0DB_DSS;
458 /* Debug single step cannot be raised inside a delay slot and
459 resume will always occur on the next instruction
460 (but we assume the pc has always been updated during
461 code translation). */
462 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
463 goto enter_debug_mode;
465 env->CP0_Debug |= 1 << CP0DB_DINT;
468 env->CP0_Debug |= 1 << CP0DB_DIB;
471 env->CP0_Debug |= 1 << CP0DB_DBp;
474 env->CP0_Debug |= 1 << CP0DB_DDBS;
477 env->CP0_Debug |= 1 << CP0DB_DDBL;
479 env->CP0_DEPC = exception_resume_pc(env);
480 env->hflags &= ~MIPS_HFLAG_BMASK;
482 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
483 env->hflags &= ~(MIPS_HFLAG_KSU);
484 /* EJTAG probe trap enable is not implemented... */
485 if (!(env->CP0_Status & (1 << CP0St_EXL)))
486 env->CP0_Cause &= ~(1U << CP0Ca_BD);
487 env->active_tc.PC = (int32_t)0xBFC00480;
488 set_hflags_for_handler(env);
494 env->CP0_Status |= (1 << CP0St_SR);
495 memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
498 env->CP0_Status |= (1 << CP0St_NMI);
500 env->CP0_ErrorEPC = exception_resume_pc(env);
501 env->hflags &= ~MIPS_HFLAG_BMASK;
502 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
503 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
504 env->hflags &= ~(MIPS_HFLAG_KSU);
505 if (!(env->CP0_Status & (1 << CP0St_EXL)))
506 env->CP0_Cause &= ~(1U << CP0Ca_BD);
507 env->active_tc.PC = (int32_t)0xBFC00000;
508 set_hflags_for_handler(env);
510 case EXCP_EXT_INTERRUPT:
512 if (env->CP0_Cause & (1 << CP0Ca_IV))
515 if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
516 /* Vectored Interrupts. */
517 unsigned int spacing;
519 unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
521 pending &= env->CP0_Status >> 8;
522 /* Compute the Vector Spacing. */
523 spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
526 if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
527 /* For VInt mode, the MIPS computes the vector internally. */
528 for (vector = 7; vector > 0; vector--) {
529 if (pending & (1 << vector)) {
535 /* For VEIC mode, the external interrupt controller feeds the
536 vector through the CP0Cause IP lines. */
539 offset = 0x200 + vector * spacing;
547 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
548 #if defined(TARGET_MIPS64)
549 int R = env->CP0_BadVAddr >> 62;
550 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
551 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
552 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
554 if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
555 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
564 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
565 #if defined(TARGET_MIPS64)
566 int R = env->CP0_BadVAddr >> 62;
567 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
568 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
569 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
571 if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
572 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
602 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
603 (env->error_code << CP0Ca_CE);
622 /* XXX: TODO: manage defered watch exceptions */
635 if (env->CP0_Status & (1 << CP0St_BEV)) {
641 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
642 env->CP0_EPC = exception_resume_pc(env);
643 if (env->hflags & MIPS_HFLAG_BMASK) {
644 env->CP0_Cause |= (1U << CP0Ca_BD);
646 env->CP0_Cause &= ~(1U << CP0Ca_BD);
648 env->CP0_Status |= (1 << CP0St_EXL);
649 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
650 env->hflags &= ~(MIPS_HFLAG_KSU);
652 env->hflags &= ~MIPS_HFLAG_BMASK;
653 if (env->CP0_Status & (1 << CP0St_BEV)) {
654 env->active_tc.PC = (int32_t)0xBFC00200;
656 env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
658 env->active_tc.PC += offset;
659 set_hflags_for_handler(env);
660 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
663 qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
664 printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
667 if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
668 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
669 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
670 __func__, env->active_tc.PC, env->CP0_EPC, cause,
671 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
675 cs->exception_index = EXCP_NONE;
678 #if !defined(CONFIG_USER_ONLY)
679 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
681 MIPSCPU *cpu = mips_env_get_cpu(env);
686 uint8_t ASID = env->CP0_EntryHi & 0xFF;
689 tlb = &env->tlb->mmu.r4k.tlb[idx];
690 /* The qemu TLB is flushed when the ASID changes, so no need to
691 flush these entries again. */
692 if (tlb->G == 0 && tlb->ASID != ASID) {
696 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
697 /* For tlbwr, we can shadow the discarded entry into
698 a new (fake) TLB entry, as long as the guest can not
699 tell that it's there. */
700 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
701 env->tlb->tlb_in_use++;
705 /* 1k pages are not supported. */
706 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
709 addr = tlb->VPN & ~mask;
710 #if defined(TARGET_MIPS64)
711 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
712 addr |= 0x3FFFFF0000000000ULL;
715 end = addr | (mask >> 1);
717 tlb_flush_page(cs, addr);
718 addr += TARGET_PAGE_SIZE;
723 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
724 #if defined(TARGET_MIPS64)
725 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
726 addr |= 0x3FFFFF0000000000ULL;
730 while (addr - 1 < end) {
731 tlb_flush_page(cs, addr);
732 addr += TARGET_PAGE_SIZE;