2 * CRIS helper routines.
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "host-utils.h"
30 //#define CRIS_HELPER_DEBUG
33 #ifdef CRIS_HELPER_DEBUG
35 #define D_LOG(...) qemu_log(__VA__ARGS__)
38 #define D_LOG(...) do { } while (0)
41 #if defined(CONFIG_USER_ONLY)
43 void do_interrupt (CPUState *env)
45 env->exception_index = -1;
46 env->pregs[PR_ERP] = env->pc;
49 int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
52 env->exception_index = 0xaa;
53 env->pregs[PR_EDA] = address;
54 cpu_dump_state(env, stderr, fprintf, 0);
58 #else /* !CONFIG_USER_ONLY */
61 static void cris_shift_ccs(CPUState *env)
64 /* Apply the ccs shift. */
65 ccs = env->pregs[PR_CCS];
66 ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
67 env->pregs[PR_CCS] = ccs;
70 int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
73 struct cris_mmu_result res;
78 D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
79 miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
83 if (env->exception_index == EXCP_BUSFAULT)
85 "CRIS: Illegal recursive bus fault."
89 env->pregs[PR_EDA] = address;
90 env->exception_index = EXCP_BUSFAULT;
91 env->fault_vector = res.bf_vec;
97 * Mask off the cache selection bit. The ETRAX busses do not
100 phy = res.phy & ~0x80000000;
102 tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
103 prot, mmu_idx, TARGET_PAGE_SIZE);
107 D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
108 __func__, r, env->interrupt_request, address, res.phy,
109 res.bf_vec, env->pc);
113 static void do_interruptv10(CPUState *env)
117 D_LOG( "exception index=%d interrupt_req=%d\n",
118 env->exception_index,
119 env->interrupt_request);
121 assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
122 switch (env->exception_index)
125 /* These exceptions are genereated by the core itself.
126 ERP should point to the insn following the brk. */
127 ex_vec = env->trap_vector;
128 env->pregs[PR_ERP] = env->pc;
132 /* NMI is hardwired to vector zero. */
134 env->pregs[PR_CCS] &= ~M_FLAG;
135 env->pregs[PR_NRP] = env->pc;
139 cpu_abort(env, "Unhandled busfault");
143 /* The interrupt controller gives us the vector. */
144 ex_vec = env->interrupt_vector;
145 /* Normal interrupts are taken between
146 TB's. env->pc is valid here. */
147 env->pregs[PR_ERP] = env->pc;
151 if (env->pregs[PR_CCS] & U_FLAG) {
152 /* Swap stack pointers. */
153 env->pregs[PR_USP] = env->regs[R_SP];
154 env->regs[R_SP] = env->ksp;
157 /* Now that we are in kernel mode, load the handlers address. */
158 env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
160 env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
162 qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
163 __func__, env->pc, ex_vec,
169 void do_interrupt(CPUState *env)
173 if (env->pregs[PR_VR] < 32)
174 return do_interruptv10(env);
176 D_LOG( "exception index=%d interrupt_req=%d\n",
177 env->exception_index,
178 env->interrupt_request);
180 switch (env->exception_index)
183 /* These exceptions are genereated by the core itself.
184 ERP should point to the insn following the brk. */
185 ex_vec = env->trap_vector;
186 env->pregs[PR_ERP] = env->pc;
190 /* NMI is hardwired to vector zero. */
192 env->pregs[PR_CCS] &= ~M_FLAG;
193 env->pregs[PR_NRP] = env->pc;
197 ex_vec = env->fault_vector;
198 env->pregs[PR_ERP] = env->pc;
202 /* The interrupt controller gives us the vector. */
203 ex_vec = env->interrupt_vector;
204 /* Normal interrupts are taken between
205 TB's. env->pc is valid here. */
206 env->pregs[PR_ERP] = env->pc;
210 /* Fill in the IDX field. */
211 env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
214 D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
215 " ERP=%x pid=%x ccs=%x cc=%d %x\n",
216 ex_vec, env->pc, env->dslot,
218 env->pregs[PR_ERP], env->pregs[PR_PID],
220 env->cc_op, env->cc_mask);
221 /* We loose the btarget, btaken state here so rexec the
223 env->pregs[PR_ERP] -= env->dslot;
224 /* Exception starts with dslot cleared. */
228 if (env->pregs[PR_CCS] & U_FLAG) {
229 /* Swap stack pointers. */
230 env->pregs[PR_USP] = env->regs[R_SP];
231 env->regs[R_SP] = env->ksp;
234 /* Apply the CRIS CCS shift. Clears U if set. */
237 /* Now that we are in kernel mode, load the handlers address.
238 This load may not fault, real hw leaves that behaviour as
240 env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
242 /* Clear the excption_index to avoid spurios hw_aborts for recursive
244 env->exception_index = -1;
246 D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
247 __func__, env->pc, ex_vec,
253 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
256 struct cris_mmu_result res;
259 miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
260 /* If D TLB misses, try I TLB. */
262 miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
267 D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));