target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32
  33 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  34 {
  35     ARMCPU *cpu = ARM_CPU(cs);
  36
  37     cpu->env.regs[15] = value;
  38 }
  39
  40 static bool arm_cpu_has_work(CPUState *cs)
  41 {
  42     return cs->interrupt_request &
  43         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
  44 }
  45
  46 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  47 {
  48     /* Reset a single ARMCPRegInfo register */
  49     ARMCPRegInfo *ri = value;
  50     ARMCPU *cpu = opaque;
  51
  52     if (ri->type & ARM_CP_SPECIAL) {
  53         return;
  54     }
  55
  56     if (ri->resetfn) {
  57         ri->resetfn(&cpu->env, ri);
  58         return;
  59     }
  60
  61     /* A zero offset is never possible as it would be regs[0]
  62      * so we use it to indicate that reset is being handled elsewhere.
  63      * This is basically only used for fields in non-core coprocessors
  64      * (like the pxa2xx ones).
  65      */
  66     if (!ri->fieldoffset) {
  67         return;
  68     }
  69
  70     if (cpreg_field_is_64bit(ri)) {
  71         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  72     } else {
  73         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  74     }
  75 }
  76
  77 /* CPUClass::reset() */
  78 static void arm_cpu_reset(CPUState *s)
  79 {
  80     ARMCPU *cpu = ARM_CPU(s);
  81     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  82     CPUARMState *env = &cpu->env;
  83
  84     acc->parent_reset(s);
  85
  86     memset(env, 0, offsetof(CPUARMState, features));
  87     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  88     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  89     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  90     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  91
  92     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  93         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  94     }
  95
  96     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  97         /* 64 bit CPUs always start in 64 bit mode */
  98         env->aarch64 = 1;
  99 #if defined(CONFIG_USER_ONLY)
 100         env->pstate = PSTATE_MODE_EL0t;
 101         /* Userspace expects access to CTL_EL0 and the cache ops */
 102         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
 103         /* and to the FP/Neon instructions */
 104         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 105 #else
 106         env->pstate = PSTATE_MODE_EL1h;
 107 #endif
 108     } else {
 109 #if defined(CONFIG_USER_ONLY)
 110         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 111         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 112 #endif
 113     }
 114
 115 #if defined(CONFIG_USER_ONLY)
 116     env->uncached_cpsr = ARM_CPU_MODE_USR;
 117     /* For user mode we must enable access to coprocessors */
 118     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 119     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 120         env->cp15.c15_cpar = 3;
 121     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 122         env->cp15.c15_cpar = 1;
 123     }
 124 #else
 125     /* SVC mode with interrupts disabled.  */
 126     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 127     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 128     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 129        clear at reset.  Initial SP and PC are loaded from ROM.  */
 130     if (IS_M(env)) {
 131         uint32_t pc;
 132         uint8_t *rom;
 133         env->daif &= ~PSTATE_I;
 134         rom = rom_ptr(0);
 135         if (rom) {
 136             /* We should really use ldl_phys here, in case the guest
 137                modified flash and reset itself.  However images
 138                loaded via -kernel have not been copied yet, so load the
 139                values directly from there.  */
 140             env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
 141             pc = ldl_p(rom + 4);
 142             env->thumb = pc & 1;
 143             env->regs[15] = pc & ~1;
 144         }
 145     }
 146
 147     if (env->cp15.c1_sys & SCTLR_V) {
 148             env->regs[15] = 0xFFFF0000;
 149     }
 150
 151     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 152 #endif
 153     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 154     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 155     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 156     set_float_detect_tininess(float_tininess_before_rounding,
 157                               &env->vfp.fp_status);
 158     set_float_detect_tininess(float_tininess_before_rounding,
 159                               &env->vfp.standard_fp_status);
 160     tlb_flush(s, 1);
 161     /* Reset is a state change for some CPUARMState fields which we
 162      * bake assumptions about into translated code, so we need to
 163      * tb_flush().
 164      */
 165     tb_flush(env);
 166 }
 167
 168 #ifndef CONFIG_USER_ONLY
 169 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 170 {
 171     ARMCPU *cpu = opaque;
 172     CPUState *cs = CPU(cpu);
 173
 174     switch (irq) {
 175     case ARM_CPU_IRQ:
 176         if (level) {
 177             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 178         } else {
 179             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 180         }
 181         break;
 182     case ARM_CPU_FIQ:
 183         if (level) {
 184             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 185         } else {
 186             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 187         }
 188         break;
 189     default:
 190         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 191     }
 192 }
 193
 194 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 195 {
 196 #ifdef CONFIG_KVM
 197     ARMCPU *cpu = opaque;
 198     CPUState *cs = CPU(cpu);
 199     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 200
 201     switch (irq) {
 202     case ARM_CPU_IRQ:
 203         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 204         break;
 205     case ARM_CPU_FIQ:
 206         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 207         break;
 208     default:
 209         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 210     }
 211     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 212     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 213 #endif
 214 }
 215 #endif
 216
 217 static inline void set_feature(CPUARMState *env, int feature)
 218 {
 219     env->features |= 1ULL << feature;
 220 }
 221
 222 static void arm_cpu_initfn(Object *obj)
 223 {
 224     CPUState *cs = CPU(obj);
 225     ARMCPU *cpu = ARM_CPU(obj);
 226     static bool inited;
 227
 228     cs->env_ptr = &cpu->env;
 229     cpu_exec_init(&cpu->env);
 230     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 231                                          g_free, g_free);
 232
 233 #ifndef CONFIG_USER_ONLY
 234     /* Our inbound IRQ and FIQ lines */
 235     if (kvm_enabled()) {
 236         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 237     } else {
 238         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 239     }
 240
 241     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 242                                                 arm_gt_ptimer_cb, cpu);
 243     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 244                                                 arm_gt_vtimer_cb, cpu);
 245     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 246                        ARRAY_SIZE(cpu->gt_timer_outputs));
 247 #endif
 248
 249     /* DTB consumers generally don't in fact care what the 'compatible'
 250      * string is, so always provide some string and trust that a hypothetical
 251      * picky DTB consumer will also provide a helpful error message.
 252      */
 253     cpu->dtb_compatible = "qemu,unknown";
 254     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 255
 256     if (tcg_enabled() && !inited) {
 257         inited = true;
 258         arm_translate_init();
 259     }
 260 }
 261
 262 static Property arm_cpu_reset_cbar_property =
 263             DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0);
 264
 265 static Property arm_cpu_reset_hivecs_property =
 266             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 267
 268 static void arm_cpu_post_init(Object *obj)
 269 {
 270     ARMCPU *cpu = ARM_CPU(obj);
 271
 272     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {
 273         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 274                                  &error_abort);
 275     }
 276
 277     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 278         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 279                                  &error_abort);
 280     }
 281 }
 282
 283 static void arm_cpu_finalizefn(Object *obj)
 284 {
 285     ARMCPU *cpu = ARM_CPU(obj);
 286     g_hash_table_destroy(cpu->cp_regs);
 287 }
 288
 289 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 290 {
 291     CPUState *cs = CPU(dev);
 292     ARMCPU *cpu = ARM_CPU(dev);
 293     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 294     CPUARMState *env = &cpu->env;
 295
 296     /* Some features automatically imply others: */
 297     if (arm_feature(env, ARM_FEATURE_V8)) {
 298         set_feature(env, ARM_FEATURE_V7);
 299         set_feature(env, ARM_FEATURE_ARM_DIV);
 300         set_feature(env, ARM_FEATURE_LPAE);
 301         set_feature(env, ARM_FEATURE_V8_AES);
 302     }
 303     if (arm_feature(env, ARM_FEATURE_V7)) {
 304         set_feature(env, ARM_FEATURE_VAPA);
 305         set_feature(env, ARM_FEATURE_THUMB2);
 306         set_feature(env, ARM_FEATURE_MPIDR);
 307         if (!arm_feature(env, ARM_FEATURE_M)) {
 308             set_feature(env, ARM_FEATURE_V6K);
 309         } else {
 310             set_feature(env, ARM_FEATURE_V6);
 311         }
 312     }
 313     if (arm_feature(env, ARM_FEATURE_V6K)) {
 314         set_feature(env, ARM_FEATURE_V6);
 315         set_feature(env, ARM_FEATURE_MVFR);
 316     }
 317     if (arm_feature(env, ARM_FEATURE_V6)) {
 318         set_feature(env, ARM_FEATURE_V5);
 319         if (!arm_feature(env, ARM_FEATURE_M)) {
 320             set_feature(env, ARM_FEATURE_AUXCR);
 321         }
 322     }
 323     if (arm_feature(env, ARM_FEATURE_V5)) {
 324         set_feature(env, ARM_FEATURE_V4T);
 325     }
 326     if (arm_feature(env, ARM_FEATURE_M)) {
 327         set_feature(env, ARM_FEATURE_THUMB_DIV);
 328     }
 329     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 330         set_feature(env, ARM_FEATURE_THUMB_DIV);
 331     }
 332     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 333         set_feature(env, ARM_FEATURE_VFP3);
 334     }
 335     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 336         set_feature(env, ARM_FEATURE_VFP);
 337     }
 338     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 339         set_feature(env, ARM_FEATURE_V7MP);
 340         set_feature(env, ARM_FEATURE_PXN);
 341     }
 342
 343     if (cpu->reset_hivecs) {
 344             cpu->reset_sctlr |= (1 << 13);
 345     }
 346
 347     register_cp_regs_for_features(cpu);
 348     arm_cpu_register_gdb_regs_for_features(cpu);
 349
 350     init_cpreg_list(cpu);
 351
 352     cpu_reset(cs);
 353     qemu_init_vcpu(cs);
 354
 355     acc->parent_realize(dev, errp);
 356 }
 357
 358 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 359 {
 360     ObjectClass *oc;
 361     char *typename;
 362
 363     if (!cpu_model) {
 364         return NULL;
 365     }
 366
 367     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 368     oc = object_class_by_name(typename);
 369     g_free(typename);
 370     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 371         object_class_is_abstract(oc)) {
 372         return NULL;
 373     }
 374     return oc;
 375 }
 376
 377 /* CPU models. These are not needed for the AArch64 linux-user build. */
 378 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 379
 380 static void arm926_initfn(Object *obj)
 381 {
 382     ARMCPU *cpu = ARM_CPU(obj);
 383
 384     cpu->dtb_compatible = "arm,arm926";
 385     set_feature(&cpu->env, ARM_FEATURE_V5);
 386     set_feature(&cpu->env, ARM_FEATURE_VFP);
 387     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 388     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 389     cpu->midr = 0x41069265;
 390     cpu->reset_fpsid = 0x41011090;
 391     cpu->ctr = 0x1dd20d2;
 392     cpu->reset_sctlr = 0x00090078;
 393 }
 394
 395 static void arm946_initfn(Object *obj)
 396 {
 397     ARMCPU *cpu = ARM_CPU(obj);
 398
 399     cpu->dtb_compatible = "arm,arm946";
 400     set_feature(&cpu->env, ARM_FEATURE_V5);
 401     set_feature(&cpu->env, ARM_FEATURE_MPU);
 402     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 403     cpu->midr = 0x41059461;
 404     cpu->ctr = 0x0f004006;
 405     cpu->reset_sctlr = 0x00000078;
 406 }
 407
 408 static void arm1026_initfn(Object *obj)
 409 {
 410     ARMCPU *cpu = ARM_CPU(obj);
 411
 412     cpu->dtb_compatible = "arm,arm1026";
 413     set_feature(&cpu->env, ARM_FEATURE_V5);
 414     set_feature(&cpu->env, ARM_FEATURE_VFP);
 415     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 416     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 417     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 418     cpu->midr = 0x4106a262;
 419     cpu->reset_fpsid = 0x410110a0;
 420     cpu->ctr = 0x1dd20d2;
 421     cpu->reset_sctlr = 0x00090078;
 422     cpu->reset_auxcr = 1;
 423     {
 424         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 425         ARMCPRegInfo ifar = {
 426             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 427             .access = PL1_RW,
 428             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 429             .resetvalue = 0
 430         };
 431         define_one_arm_cp_reg(cpu, &ifar);
 432     }
 433 }
 434
 435 static void arm1136_r2_initfn(Object *obj)
 436 {
 437     ARMCPU *cpu = ARM_CPU(obj);
 438     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 439      * older core than plain "arm1136". In particular this does not
 440      * have the v6K features.
 441      * These ID register values are correct for 1136 but may be wrong
 442      * for 1136_r2 (in particular r0p2 does not actually implement most
 443      * of the ID registers).
 444      */
 445
 446     cpu->dtb_compatible = "arm,arm1136";
 447     set_feature(&cpu->env, ARM_FEATURE_V6);
 448     set_feature(&cpu->env, ARM_FEATURE_VFP);
 449     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 450     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 451     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 452     cpu->midr = 0x4107b362;
 453     cpu->reset_fpsid = 0x410120b4;
 454     cpu->mvfr0 = 0x11111111;
 455     cpu->mvfr1 = 0x00000000;
 456     cpu->ctr = 0x1dd20d2;
 457     cpu->reset_sctlr = 0x00050078;
 458     cpu->id_pfr0 = 0x111;
 459     cpu->id_pfr1 = 0x1;
 460     cpu->id_dfr0 = 0x2;
 461     cpu->id_afr0 = 0x3;
 462     cpu->id_mmfr0 = 0x01130003;
 463     cpu->id_mmfr1 = 0x10030302;
 464     cpu->id_mmfr2 = 0x01222110;
 465     cpu->id_isar0 = 0x00140011;
 466     cpu->id_isar1 = 0x12002111;
 467     cpu->id_isar2 = 0x11231111;
 468     cpu->id_isar3 = 0x01102131;
 469     cpu->id_isar4 = 0x141;
 470     cpu->reset_auxcr = 7;
 471 }
 472
 473 static void arm1136_initfn(Object *obj)
 474 {
 475     ARMCPU *cpu = ARM_CPU(obj);
 476
 477     cpu->dtb_compatible = "arm,arm1136";
 478     set_feature(&cpu->env, ARM_FEATURE_V6K);
 479     set_feature(&cpu->env, ARM_FEATURE_V6);
 480     set_feature(&cpu->env, ARM_FEATURE_VFP);
 481     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 482     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 483     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 484     cpu->midr = 0x4117b363;
 485     cpu->reset_fpsid = 0x410120b4;
 486     cpu->mvfr0 = 0x11111111;
 487     cpu->mvfr1 = 0x00000000;
 488     cpu->ctr = 0x1dd20d2;
 489     cpu->reset_sctlr = 0x00050078;
 490     cpu->id_pfr0 = 0x111;
 491     cpu->id_pfr1 = 0x1;
 492     cpu->id_dfr0 = 0x2;
 493     cpu->id_afr0 = 0x3;
 494     cpu->id_mmfr0 = 0x01130003;
 495     cpu->id_mmfr1 = 0x10030302;
 496     cpu->id_mmfr2 = 0x01222110;
 497     cpu->id_isar0 = 0x00140011;
 498     cpu->id_isar1 = 0x12002111;
 499     cpu->id_isar2 = 0x11231111;
 500     cpu->id_isar3 = 0x01102131;
 501     cpu->id_isar4 = 0x141;
 502     cpu->reset_auxcr = 7;
 503 }
 504
 505 static void arm1176_initfn(Object *obj)
 506 {
 507     ARMCPU *cpu = ARM_CPU(obj);
 508
 509     cpu->dtb_compatible = "arm,arm1176";
 510     set_feature(&cpu->env, ARM_FEATURE_V6K);
 511     set_feature(&cpu->env, ARM_FEATURE_VFP);
 512     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 513     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 514     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 515     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 516     cpu->midr = 0x410fb767;
 517     cpu->reset_fpsid = 0x410120b5;
 518     cpu->mvfr0 = 0x11111111;
 519     cpu->mvfr1 = 0x00000000;
 520     cpu->ctr = 0x1dd20d2;
 521     cpu->reset_sctlr = 0x00050078;
 522     cpu->id_pfr0 = 0x111;
 523     cpu->id_pfr1 = 0x11;
 524     cpu->id_dfr0 = 0x33;
 525     cpu->id_afr0 = 0;
 526     cpu->id_mmfr0 = 0x01130003;
 527     cpu->id_mmfr1 = 0x10030302;
 528     cpu->id_mmfr2 = 0x01222100;
 529     cpu->id_isar0 = 0x0140011;
 530     cpu->id_isar1 = 0x12002111;
 531     cpu->id_isar2 = 0x11231121;
 532     cpu->id_isar3 = 0x01102131;
 533     cpu->id_isar4 = 0x01141;
 534     cpu->reset_auxcr = 7;
 535 }
 536
 537 static void arm11mpcore_initfn(Object *obj)
 538 {
 539     ARMCPU *cpu = ARM_CPU(obj);
 540
 541     cpu->dtb_compatible = "arm,arm11mpcore";
 542     set_feature(&cpu->env, ARM_FEATURE_V6K);
 543     set_feature(&cpu->env, ARM_FEATURE_VFP);
 544     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 545     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 546     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 547     cpu->midr = 0x410fb022;
 548     cpu->reset_fpsid = 0x410120b4;
 549     cpu->mvfr0 = 0x11111111;
 550     cpu->mvfr1 = 0x00000000;
 551     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 552     cpu->id_pfr0 = 0x111;
 553     cpu->id_pfr1 = 0x1;
 554     cpu->id_dfr0 = 0;
 555     cpu->id_afr0 = 0x2;
 556     cpu->id_mmfr0 = 0x01100103;
 557     cpu->id_mmfr1 = 0x10020302;
 558     cpu->id_mmfr2 = 0x01222000;
 559     cpu->id_isar0 = 0x00100011;
 560     cpu->id_isar1 = 0x12002111;
 561     cpu->id_isar2 = 0x11221011;
 562     cpu->id_isar3 = 0x01102131;
 563     cpu->id_isar4 = 0x141;
 564     cpu->reset_auxcr = 1;
 565 }
 566
 567 static void cortex_m3_initfn(Object *obj)
 568 {
 569     ARMCPU *cpu = ARM_CPU(obj);
 570     set_feature(&cpu->env, ARM_FEATURE_V7);
 571     set_feature(&cpu->env, ARM_FEATURE_M);
 572     cpu->midr = 0x410fc231;
 573 }
 574
 575 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 576 {
 577 #ifndef CONFIG_USER_ONLY
 578     CPUClass *cc = CPU_CLASS(oc);
 579
 580     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 581 #endif
 582 }
 583
 584 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 585     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 586       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 587     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 588       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 589     REGINFO_SENTINEL
 590 };
 591
 592 static void cortex_a8_initfn(Object *obj)
 593 {
 594     ARMCPU *cpu = ARM_CPU(obj);
 595
 596     cpu->dtb_compatible = "arm,cortex-a8";
 597     set_feature(&cpu->env, ARM_FEATURE_V7);
 598     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 599     set_feature(&cpu->env, ARM_FEATURE_NEON);
 600     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 601     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 602     cpu->midr = 0x410fc080;
 603     cpu->reset_fpsid = 0x410330c0;
 604     cpu->mvfr0 = 0x11110222;
 605     cpu->mvfr1 = 0x00011100;
 606     cpu->ctr = 0x82048004;
 607     cpu->reset_sctlr = 0x00c50078;
 608     cpu->id_pfr0 = 0x1031;
 609     cpu->id_pfr1 = 0x11;
 610     cpu->id_dfr0 = 0x400;
 611     cpu->id_afr0 = 0;
 612     cpu->id_mmfr0 = 0x31100003;
 613     cpu->id_mmfr1 = 0x20000000;
 614     cpu->id_mmfr2 = 0x01202000;
 615     cpu->id_mmfr3 = 0x11;
 616     cpu->id_isar0 = 0x00101111;
 617     cpu->id_isar1 = 0x12112111;
 618     cpu->id_isar2 = 0x21232031;
 619     cpu->id_isar3 = 0x11112131;
 620     cpu->id_isar4 = 0x00111142;
 621     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 622     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 623     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 624     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 625     cpu->reset_auxcr = 2;
 626     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 627 }
 628
 629 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 630     /* power_control should be set to maximum latency. Again,
 631      * default to 0 and set by private hook
 632      */
 633     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 634       .access = PL1_RW, .resetvalue = 0,
 635       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 636     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 637       .access = PL1_RW, .resetvalue = 0,
 638       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 639     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 640       .access = PL1_RW, .resetvalue = 0,
 641       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 642     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 643       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 644     /* TLB lockdown control */
 645     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 646       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 647     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 648       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 649     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 650       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 651     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 652       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 653     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 654       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 655     REGINFO_SENTINEL
 656 };
 657
 658 static void cortex_a9_initfn(Object *obj)
 659 {
 660     ARMCPU *cpu = ARM_CPU(obj);
 661
 662     cpu->dtb_compatible = "arm,cortex-a9";
 663     set_feature(&cpu->env, ARM_FEATURE_V7);
 664     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 665     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 666     set_feature(&cpu->env, ARM_FEATURE_NEON);
 667     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 668     /* Note that A9 supports the MP extensions even for
 669      * A9UP and single-core A9MP (which are both different
 670      * and valid configurations; we don't model A9UP).
 671      */
 672     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 673     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 674     cpu->midr = 0x410fc090;
 675     cpu->reset_fpsid = 0x41033090;
 676     cpu->mvfr0 = 0x11110222;
 677     cpu->mvfr1 = 0x01111111;
 678     cpu->ctr = 0x80038003;
 679     cpu->reset_sctlr = 0x00c50078;
 680     cpu->id_pfr0 = 0x1031;
 681     cpu->id_pfr1 = 0x11;
 682     cpu->id_dfr0 = 0x000;
 683     cpu->id_afr0 = 0;
 684     cpu->id_mmfr0 = 0x00100103;
 685     cpu->id_mmfr1 = 0x20000000;
 686     cpu->id_mmfr2 = 0x01230000;
 687     cpu->id_mmfr3 = 0x00002111;
 688     cpu->id_isar0 = 0x00101111;
 689     cpu->id_isar1 = 0x13112111;
 690     cpu->id_isar2 = 0x21232041;
 691     cpu->id_isar3 = 0x11112131;
 692     cpu->id_isar4 = 0x00111142;
 693     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 694     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 695     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 696     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 697 }
 698
 699 #ifndef CONFIG_USER_ONLY
 700 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 701 {
 702     /* Linux wants the number of processors from here.
 703      * Might as well set the interrupt-controller bit too.
 704      */
 705     return ((smp_cpus - 1) << 24) | (1 << 23);
 706 }
 707 #endif
 708
 709 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 710 #ifndef CONFIG_USER_ONLY
 711     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 712       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 713       .writefn = arm_cp_write_ignore, },
 714 #endif
 715     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 716       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 717     REGINFO_SENTINEL
 718 };
 719
 720 static void cortex_a15_initfn(Object *obj)
 721 {
 722     ARMCPU *cpu = ARM_CPU(obj);
 723
 724     cpu->dtb_compatible = "arm,cortex-a15";
 725     set_feature(&cpu->env, ARM_FEATURE_V7);
 726     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 727     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 728     set_feature(&cpu->env, ARM_FEATURE_NEON);
 729     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 730     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 731     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 732     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 733     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 734     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 735     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 736     cpu->midr = 0x412fc0f1;
 737     cpu->reset_fpsid = 0x410430f0;
 738     cpu->mvfr0 = 0x10110222;
 739     cpu->mvfr1 = 0x11111111;
 740     cpu->ctr = 0x8444c004;
 741     cpu->reset_sctlr = 0x00c50078;
 742     cpu->id_pfr0 = 0x00001131;
 743     cpu->id_pfr1 = 0x00011011;
 744     cpu->id_dfr0 = 0x02010555;
 745     cpu->id_afr0 = 0x00000000;
 746     cpu->id_mmfr0 = 0x10201105;
 747     cpu->id_mmfr1 = 0x20000000;
 748     cpu->id_mmfr2 = 0x01240000;
 749     cpu->id_mmfr3 = 0x02102211;
 750     cpu->id_isar0 = 0x02101110;
 751     cpu->id_isar1 = 0x13112111;
 752     cpu->id_isar2 = 0x21232041;
 753     cpu->id_isar3 = 0x11112131;
 754     cpu->id_isar4 = 0x10011142;
 755     cpu->clidr = 0x0a200023;
 756     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 757     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 758     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 759     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 760 }
 761
 762 static void ti925t_initfn(Object *obj)
 763 {
 764     ARMCPU *cpu = ARM_CPU(obj);
 765     set_feature(&cpu->env, ARM_FEATURE_V4T);
 766     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 767     cpu->midr = ARM_CPUID_TI925T;
 768     cpu->ctr = 0x5109149;
 769     cpu->reset_sctlr = 0x00000070;
 770 }
 771
 772 static void sa1100_initfn(Object *obj)
 773 {
 774     ARMCPU *cpu = ARM_CPU(obj);
 775
 776     cpu->dtb_compatible = "intel,sa1100";
 777     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 778     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 779     cpu->midr = 0x4401A11B;
 780     cpu->reset_sctlr = 0x00000070;
 781 }
 782
 783 static void sa1110_initfn(Object *obj)
 784 {
 785     ARMCPU *cpu = ARM_CPU(obj);
 786     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 787     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 788     cpu->midr = 0x6901B119;
 789     cpu->reset_sctlr = 0x00000070;
 790 }
 791
 792 static void pxa250_initfn(Object *obj)
 793 {
 794     ARMCPU *cpu = ARM_CPU(obj);
 795
 796     cpu->dtb_compatible = "marvell,xscale";
 797     set_feature(&cpu->env, ARM_FEATURE_V5);
 798     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 799     cpu->midr = 0x69052100;
 800     cpu->ctr = 0xd172172;
 801     cpu->reset_sctlr = 0x00000078;
 802 }
 803
 804 static void pxa255_initfn(Object *obj)
 805 {
 806     ARMCPU *cpu = ARM_CPU(obj);
 807
 808     cpu->dtb_compatible = "marvell,xscale";
 809     set_feature(&cpu->env, ARM_FEATURE_V5);
 810     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 811     cpu->midr = 0x69052d00;
 812     cpu->ctr = 0xd172172;
 813     cpu->reset_sctlr = 0x00000078;
 814 }
 815
 816 static void pxa260_initfn(Object *obj)
 817 {
 818     ARMCPU *cpu = ARM_CPU(obj);
 819
 820     cpu->dtb_compatible = "marvell,xscale";
 821     set_feature(&cpu->env, ARM_FEATURE_V5);
 822     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 823     cpu->midr = 0x69052903;
 824     cpu->ctr = 0xd172172;
 825     cpu->reset_sctlr = 0x00000078;
 826 }
 827
 828 static void pxa261_initfn(Object *obj)
 829 {
 830     ARMCPU *cpu = ARM_CPU(obj);
 831
 832     cpu->dtb_compatible = "marvell,xscale";
 833     set_feature(&cpu->env, ARM_FEATURE_V5);
 834     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 835     cpu->midr = 0x69052d05;
 836     cpu->ctr = 0xd172172;
 837     cpu->reset_sctlr = 0x00000078;
 838 }
 839
 840 static void pxa262_initfn(Object *obj)
 841 {
 842     ARMCPU *cpu = ARM_CPU(obj);
 843
 844     cpu->dtb_compatible = "marvell,xscale";
 845     set_feature(&cpu->env, ARM_FEATURE_V5);
 846     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 847     cpu->midr = 0x69052d06;
 848     cpu->ctr = 0xd172172;
 849     cpu->reset_sctlr = 0x00000078;
 850 }
 851
 852 static void pxa270a0_initfn(Object *obj)
 853 {
 854     ARMCPU *cpu = ARM_CPU(obj);
 855
 856     cpu->dtb_compatible = "marvell,xscale";
 857     set_feature(&cpu->env, ARM_FEATURE_V5);
 858     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 859     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 860     cpu->midr = 0x69054110;
 861     cpu->ctr = 0xd172172;
 862     cpu->reset_sctlr = 0x00000078;
 863 }
 864
 865 static void pxa270a1_initfn(Object *obj)
 866 {
 867     ARMCPU *cpu = ARM_CPU(obj);
 868
 869     cpu->dtb_compatible = "marvell,xscale";
 870     set_feature(&cpu->env, ARM_FEATURE_V5);
 871     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 872     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 873     cpu->midr = 0x69054111;
 874     cpu->ctr = 0xd172172;
 875     cpu->reset_sctlr = 0x00000078;
 876 }
 877
 878 static void pxa270b0_initfn(Object *obj)
 879 {
 880     ARMCPU *cpu = ARM_CPU(obj);
 881
 882     cpu->dtb_compatible = "marvell,xscale";
 883     set_feature(&cpu->env, ARM_FEATURE_V5);
 884     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 885     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 886     cpu->midr = 0x69054112;
 887     cpu->ctr = 0xd172172;
 888     cpu->reset_sctlr = 0x00000078;
 889 }
 890
 891 static void pxa270b1_initfn(Object *obj)
 892 {
 893     ARMCPU *cpu = ARM_CPU(obj);
 894
 895     cpu->dtb_compatible = "marvell,xscale";
 896     set_feature(&cpu->env, ARM_FEATURE_V5);
 897     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 898     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 899     cpu->midr = 0x69054113;
 900     cpu->ctr = 0xd172172;
 901     cpu->reset_sctlr = 0x00000078;
 902 }
 903
 904 static void pxa270c0_initfn(Object *obj)
 905 {
 906     ARMCPU *cpu = ARM_CPU(obj);
 907
 908     cpu->dtb_compatible = "marvell,xscale";
 909     set_feature(&cpu->env, ARM_FEATURE_V5);
 910     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 911     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 912     cpu->midr = 0x69054114;
 913     cpu->ctr = 0xd172172;
 914     cpu->reset_sctlr = 0x00000078;
 915 }
 916
 917 static void pxa270c5_initfn(Object *obj)
 918 {
 919     ARMCPU *cpu = ARM_CPU(obj);
 920
 921     cpu->dtb_compatible = "marvell,xscale";
 922     set_feature(&cpu->env, ARM_FEATURE_V5);
 923     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 924     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 925     cpu->midr = 0x69054117;
 926     cpu->ctr = 0xd172172;
 927     cpu->reset_sctlr = 0x00000078;
 928 }
 929
 930 #ifdef CONFIG_USER_ONLY
 931 static void arm_any_initfn(Object *obj)
 932 {
 933     ARMCPU *cpu = ARM_CPU(obj);
 934     set_feature(&cpu->env, ARM_FEATURE_V8);
 935     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 936     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 937     set_feature(&cpu->env, ARM_FEATURE_NEON);
 938     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 939     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 940     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 941     set_feature(&cpu->env, ARM_FEATURE_CRC);
 942 #ifdef TARGET_AARCH64
 943     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 944 #endif
 945     cpu->midr = 0xffffffff;
 946 }
 947 #endif
 948
 949 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
 950
 951 typedef struct ARMCPUInfo {
 952     const char *name;
 953     void (*initfn)(Object *obj);
 954     void (*class_init)(ObjectClass *oc, void *data);
 955 } ARMCPUInfo;
 956
 957 static const ARMCPUInfo arm_cpus[] = {
 958 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 959     { .name = "arm926",      .initfn = arm926_initfn },
 960     { .name = "arm946",      .initfn = arm946_initfn },
 961     { .name = "arm1026",     .initfn = arm1026_initfn },
 962     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 963      * older core than plain "arm1136". In particular this does not
 964      * have the v6K features.
 965      */
 966     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 967     { .name = "arm1136",     .initfn = arm1136_initfn },
 968     { .name = "arm1176",     .initfn = arm1176_initfn },
 969     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 970     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 971                              .class_init = arm_v7m_class_init },
 972     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 973     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 974     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 975     { .name = "ti925t",      .initfn = ti925t_initfn },
 976     { .name = "sa1100",      .initfn = sa1100_initfn },
 977     { .name = "sa1110",      .initfn = sa1110_initfn },
 978     { .name = "pxa250",      .initfn = pxa250_initfn },
 979     { .name = "pxa255",      .initfn = pxa255_initfn },
 980     { .name = "pxa260",      .initfn = pxa260_initfn },
 981     { .name = "pxa261",      .initfn = pxa261_initfn },
 982     { .name = "pxa262",      .initfn = pxa262_initfn },
 983     /* "pxa270" is an alias for "pxa270-a0" */
 984     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 985     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 986     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 987     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 988     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 989     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 990     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 991 #ifdef CONFIG_USER_ONLY
 992     { .name = "any",         .initfn = arm_any_initfn },
 993 #endif
 994 #endif
 995     { .name = NULL }
 996 };
 997
 998 static Property arm_cpu_properties[] = {
 999     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1000     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1001     DEFINE_PROP_END_OF_LIST()
1002 };
1003
1004 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1005 {
1006     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1007     CPUClass *cc = CPU_CLASS(acc);
1008     DeviceClass *dc = DEVICE_CLASS(oc);
1009
1010     acc->parent_realize = dc->realize;
1011     dc->realize = arm_cpu_realizefn;
1012     dc->props = arm_cpu_properties;
1013
1014     acc->parent_reset = cc->reset;
1015     cc->reset = arm_cpu_reset;
1016
1017     cc->class_by_name = arm_cpu_class_by_name;
1018     cc->has_work = arm_cpu_has_work;
1019     cc->do_interrupt = arm_cpu_do_interrupt;
1020     cc->dump_state = arm_cpu_dump_state;
1021     cc->set_pc = arm_cpu_set_pc;
1022     cc->gdb_read_register = arm_cpu_gdb_read_register;
1023     cc->gdb_write_register = arm_cpu_gdb_write_register;
1024 #ifdef CONFIG_USER_ONLY
1025     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1026 #else
1027     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1028     cc->vmsd = &vmstate_arm_cpu;
1029 #endif
1030     cc->gdb_num_core_regs = 26;
1031     cc->gdb_core_xml_file = "arm-core.xml";
1032 }
1033
1034 static void cpu_register(const ARMCPUInfo *info)
1035 {
1036     TypeInfo type_info = {
1037         .parent = TYPE_ARM_CPU,
1038         .instance_size = sizeof(ARMCPU),
1039         .instance_init = info->initfn,
1040         .class_size = sizeof(ARMCPUClass),
1041         .class_init = info->class_init,
1042     };
1043
1044     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1045     type_register(&type_info);
1046     g_free((void *)type_info.name);
1047 }
1048
1049 static const TypeInfo arm_cpu_type_info = {
1050     .name = TYPE_ARM_CPU,
1051     .parent = TYPE_CPU,
1052     .instance_size = sizeof(ARMCPU),
1053     .instance_init = arm_cpu_initfn,
1054     .instance_post_init = arm_cpu_post_init,
1055     .instance_finalize = arm_cpu_finalizefn,
1056     .abstract = true,
1057     .class_size = sizeof(ARMCPUClass),
1058     .class_init = arm_cpu_class_init,
1059 };
1060
1061 static void arm_cpu_register_types(void)
1062 {
1063     const ARMCPUInfo *info = arm_cpus;
1064
1065     type_register_static(&arm_cpu_type_info);
1066
1067     while (info->name) {
1068         cpu_register(info);
1069         info++;
1070     }
1071 }
1072
1073 type_init(arm_cpu_register_types)