hw/unin_pci.c

   1 /*
   2  * QEMU Uninorth PCI host (for all Mac99 and newer machines)
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc_mac.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28
  29 /* debug UniNorth */
  30 //#define DEBUG_UNIN
  31
  32 #ifdef DEBUG_UNIN
  33 #define UNIN_DPRINTF(fmt, ...)                                  \
  34     do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define UNIN_DPRINTF(fmt, ...)
  37 #endif
  38
  39 static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
  40
  41 typedef struct UNINState {
  42     PCIHostState host_state;
  43     MemoryRegion pci_mmio;
  44     MemoryRegion pci_hole;
  45 } UNINState;
  46
  47 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
  48 {
  49     int retval;
  50     int devfn = pci_dev->devfn & 0x00FFFFFF;
  51
  52     retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
  53
  54     return retval;
  55 }
  56
  57 static void pci_unin_set_irq(void *opaque, int irq_num, int level)
  58 {
  59     qemu_irq *pic = opaque;
  60
  61     UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
  62                  unin_irq_line[irq_num], level);
  63     qemu_set_irq(pic[unin_irq_line[irq_num]], level);
  64 }
  65
  66 static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
  67 {
  68     uint32_t retval;
  69
  70     if (reg & (1u << 31)) {
  71         /* XXX OpenBIOS compatibility hack */
  72         retval = reg | (addr & 3);
  73     } else if (reg & 1) {
  74         /* CFA1 style */
  75         retval = (reg & ~7u) | (addr & 7);
  76     } else {
  77         uint32_t slot, func;
  78
  79         /* Grab CFA0 style values */
  80         slot = ffs(reg & 0xfffff800) - 1;
  81         func = (reg >> 8) & 7;
  82
  83         /* ... and then convert them to x86 format */
  84         /* config pointer */
  85         retval = (reg & (0xff - 7)) | (addr & 7);
  86         /* slot */
  87         retval |= slot << 11;
  88         /* fn */
  89         retval |= func << 8;
  90     }
  91
  92
  93     UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
  94                  reg, addr, retval);
  95
  96     return retval;
  97 }
  98
  99 static void unin_data_write(void *opaque, target_phys_addr_t addr,
 100                             uint64_t val, unsigned len)
 101 {
 102     UNINState *s = opaque;
 103     UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
 104                  addr, len, val);
 105     pci_data_write(s->host_state.bus,
 106                    unin_get_config_reg(s->host_state.config_reg, addr),
 107                    val, len);
 108 }
 109
 110 static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
 111                                unsigned len)
 112 {
 113     UNINState *s = opaque;
 114     uint32_t val;
 115
 116     val = pci_data_read(s->host_state.bus,
 117                         unin_get_config_reg(s->host_state.config_reg, addr),
 118                         len);
 119     UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
 120                  addr, len, val);
 121     return val;
 122 }
 123
 124 static const MemoryRegionOps unin_data_ops = {
 125     .read = unin_data_read,
 126     .write = unin_data_write,
 127     .endianness = DEVICE_LITTLE_ENDIAN,
 128 };
 129
 130 static int pci_unin_main_init_device(SysBusDevice *dev)
 131 {
 132     PCIHostState *h;
 133     UNINState *s;
 134
 135     /* Use values found on a real PowerMac */
 136     /* Uninorth main bus */
 137     h = FROM_SYSBUS(PCIHostState, dev);
 138     s = DO_UPCAST(UNINState, host_state, h);
 139
 140     memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
 141                           &s->host_state, "pci-conf-idx", 0x1000);
 142     memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
 143                           "pci-conf-data", 0x1000);
 144     sysbus_init_mmio(dev, &s->host_state.conf_mem);
 145     sysbus_init_mmio(dev, &s->host_state.data_mem);
 146
 147     return 0;
 148 }
 149
 150
 151 static int pci_u3_agp_init_device(SysBusDevice *dev)
 152 {
 153     PCIHostState *h;
 154     UNINState *s;
 155
 156     /* Uninorth U3 AGP bus */
 157     h = FROM_SYSBUS(PCIHostState, dev);
 158     s = DO_UPCAST(UNINState, host_state, h);
 159
 160     memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
 161                           &s->host_state, "pci-conf-idx", 0x1000);
 162     memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
 163                           "pci-conf-data", 0x1000);
 164     sysbus_init_mmio(dev, &s->host_state.conf_mem);
 165     sysbus_init_mmio(dev, &s->host_state.data_mem);
 166
 167     return 0;
 168 }
 169
 170 static int pci_unin_agp_init_device(SysBusDevice *dev)
 171 {
 172     PCIHostState *h;
 173     UNINState *s;
 174
 175     /* Uninorth AGP bus */
 176     h = FROM_SYSBUS(PCIHostState, dev);
 177     s = DO_UPCAST(UNINState, host_state, h);
 178
 179     memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
 180                           &s->host_state, "pci-conf-idx", 0x1000);
 181     memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
 182                           &s->host_state, "pci-conf-data", 0x1000);
 183     sysbus_init_mmio(dev, &s->host_state.conf_mem);
 184     sysbus_init_mmio(dev, &s->host_state.data_mem);
 185     return 0;
 186 }
 187
 188 static int pci_unin_internal_init_device(SysBusDevice *dev)
 189 {
 190     PCIHostState *h;
 191     UNINState *s;
 192
 193     /* Uninorth internal bus */
 194     h = FROM_SYSBUS(PCIHostState, dev);
 195     s = DO_UPCAST(UNINState, host_state, h);
 196
 197     memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
 198                           &s->host_state, "pci-conf-idx", 0x1000);
 199     memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
 200                           &s->host_state, "pci-conf-data", 0x1000);
 201     sysbus_init_mmio(dev, &s->host_state.conf_mem);
 202     sysbus_init_mmio(dev, &s->host_state.data_mem);
 203     return 0;
 204 }
 205
 206 PCIBus *pci_pmac_init(qemu_irq *pic,
 207                       MemoryRegion *address_space_mem,
 208                       MemoryRegion *address_space_io)
 209 {
 210     DeviceState *dev;
 211     SysBusDevice *s;
 212     PCIHostState *h;
 213     UNINState *d;
 214
 215     /* Use values found on a real PowerMac */
 216     /* Uninorth main bus */
 217     dev = qdev_create(NULL, "uni-north-pci-pcihost");
 218     qdev_init_nofail(dev);
 219     s = sysbus_from_qdev(dev);
 220     h = FROM_SYSBUS(PCIHostState, s);
 221     d = DO_UPCAST(UNINState, host_state, h);
 222     memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
 223     memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
 224                              0x80000000ULL, 0x70000000ULL);
 225     memory_region_add_subregion(address_space_mem, 0x80000000ULL,
 226                                 &d->pci_hole);
 227
 228     d->host_state.bus = pci_register_bus(dev, "pci",
 229                                          pci_unin_set_irq, pci_unin_map_irq,
 230                                          pic,
 231                                          &d->pci_mmio,
 232                                          address_space_io,
 233                                          PCI_DEVFN(11, 0), 4);
 234
 235 #if 0
 236     pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
 237 #endif
 238
 239     sysbus_mmio_map(s, 0, 0xf2800000);
 240     sysbus_mmio_map(s, 1, 0xf2c00000);
 241
 242     /* DEC 21154 bridge */
 243 #if 0
 244     /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
 245     pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
 246 #endif
 247
 248     /* Uninorth AGP bus */
 249     pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
 250     dev = qdev_create(NULL, "uni-north-agp-pcihost");
 251     qdev_init_nofail(dev);
 252     s = sysbus_from_qdev(dev);
 253     sysbus_mmio_map(s, 0, 0xf0800000);
 254     sysbus_mmio_map(s, 1, 0xf0c00000);
 255
 256     /* Uninorth internal bus */
 257 #if 0
 258     /* XXX: not needed for now */
 259     pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0),
 260                       "uni-north-internal-pci");
 261     dev = qdev_create(NULL, "uni-north-internal-pci-pcihost");
 262     qdev_init_nofail(dev);
 263     s = sysbus_from_qdev(dev);
 264     sysbus_mmio_map(s, 0, 0xf4800000);
 265     sysbus_mmio_map(s, 1, 0xf4c00000);
 266 #endif
 267
 268     return d->host_state.bus;
 269 }
 270
 271 PCIBus *pci_pmac_u3_init(qemu_irq *pic,
 272                          MemoryRegion *address_space_mem,
 273                          MemoryRegion *address_space_io)
 274 {
 275     DeviceState *dev;
 276     SysBusDevice *s;
 277     PCIHostState *h;
 278     UNINState *d;
 279
 280     /* Uninorth AGP bus */
 281
 282     dev = qdev_create(NULL, "u3-agp-pcihost");
 283     qdev_init_nofail(dev);
 284     s = sysbus_from_qdev(dev);
 285     h = FROM_SYSBUS(PCIHostState, s);
 286     d = DO_UPCAST(UNINState, host_state, h);
 287
 288     memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
 289     memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
 290                              0x80000000ULL, 0x70000000ULL);
 291     memory_region_add_subregion(address_space_mem, 0x80000000ULL,
 292                                 &d->pci_hole);
 293
 294     d->host_state.bus = pci_register_bus(dev, "pci",
 295                                          pci_unin_set_irq, pci_unin_map_irq,
 296                                          pic,
 297                                          &d->pci_mmio,
 298                                          address_space_io,
 299                                          PCI_DEVFN(11, 0), 4);
 300
 301     sysbus_mmio_map(s, 0, 0xf0800000);
 302     sysbus_mmio_map(s, 1, 0xf0c00000);
 303
 304     pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");
 305
 306     return d->host_state.bus;
 307 }
 308
 309 static int unin_main_pci_host_init(PCIDevice *d)
 310 {
 311     d->config[0x0C] = 0x08; // cache_line_size
 312     d->config[0x0D] = 0x10; // latency_timer
 313     d->config[0x34] = 0x00; // capabilities_pointer
 314     return 0;
 315 }
 316
 317 static int unin_agp_pci_host_init(PCIDevice *d)
 318 {
 319     d->config[0x0C] = 0x08; // cache_line_size
 320     d->config[0x0D] = 0x10; // latency_timer
 321     //    d->config[0x34] = 0x80; // capabilities_pointer
 322     return 0;
 323 }
 324
 325 static int u3_agp_pci_host_init(PCIDevice *d)
 326 {
 327     /* cache line size */
 328     d->config[0x0C] = 0x08;
 329     /* latency timer */
 330     d->config[0x0D] = 0x10;
 331     return 0;
 332 }
 333
 334 static int unin_internal_pci_host_init(PCIDevice *d)
 335 {
 336     d->config[0x0C] = 0x08; // cache_line_size
 337     d->config[0x0D] = 0x10; // latency_timer
 338     d->config[0x34] = 0x00; // capabilities_pointer
 339     return 0;
 340 }
 341
 342 static PCIDeviceInfo unin_main_pci_host_info = {
 343     .qdev.name = "uni-north-pci",
 344     .qdev.size = sizeof(PCIDevice),
 345     .init      = unin_main_pci_host_init,
 346     .vendor_id = PCI_VENDOR_ID_APPLE,
 347     .device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
 348     .revision  = 0x00,
 349     .class_id  = PCI_CLASS_BRIDGE_HOST,
 350 };
 351
 352 static PCIDeviceInfo u3_agp_pci_host_info = {
 353     .qdev.name = "u3-agp",
 354     .qdev.size = sizeof(PCIDevice),
 355     .init      = u3_agp_pci_host_init,
 356     .vendor_id = PCI_VENDOR_ID_APPLE,
 357     .device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
 358     .revision  = 0x00,
 359     .class_id  = PCI_CLASS_BRIDGE_HOST,
 360 };
 361
 362 static PCIDeviceInfo unin_agp_pci_host_info = {
 363     .qdev.name = "uni-north-agp",
 364     .qdev.size = sizeof(PCIDevice),
 365     .init      = unin_agp_pci_host_init,
 366     .vendor_id = PCI_VENDOR_ID_APPLE,
 367     .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
 368     .revision  = 0x00,
 369     .class_id  = PCI_CLASS_BRIDGE_HOST,
 370 };
 371
 372 static PCIDeviceInfo unin_internal_pci_host_info = {
 373     .qdev.name = "uni-north-internal-pci",
 374     .qdev.size = sizeof(PCIDevice),
 375     .init      = unin_internal_pci_host_init,
 376     .vendor_id = PCI_VENDOR_ID_APPLE,
 377     .device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
 378     .revision  = 0x00,
 379     .class_id  = PCI_CLASS_BRIDGE_HOST,
 380 };
 381
 382 static SysBusDeviceInfo sysbus_unin_pci_host_info = {
 383     .qdev.name = "uni-north-pci-pcihost",
 384     .qdev.size = sizeof(UNINState),
 385     .init      = pci_unin_main_init_device,
 386 };
 387
 388 static SysBusDeviceInfo sysbus_u3_agp_pci_host_info = {
 389     .qdev.name = "u3-agp-pcihost",
 390     .qdev.size = sizeof(UNINState),
 391     .init      = pci_u3_agp_init_device,
 392 };
 393
 394 static SysBusDeviceInfo sysbus_unin_agp_pci_host_info = {
 395     .qdev.name = "uni-north-agp-pcihost",
 396     .qdev.size = sizeof(UNINState),
 397     .init      = pci_unin_agp_init_device,
 398 };
 399
 400 static SysBusDeviceInfo sysbus_unin_internal_pci_host_info = {
 401     .qdev.name = "uni-north-internal-pci-pcihost",
 402     .qdev.size = sizeof(UNINState),
 403     .init      = pci_unin_internal_init_device,
 404 };
 405
 406 static void unin_register_devices(void)
 407 {
 408     sysbus_register_withprop(&sysbus_unin_pci_host_info);
 409     pci_qdev_register(&unin_main_pci_host_info);
 410
 411     sysbus_register_withprop(&sysbus_u3_agp_pci_host_info);
 412     pci_qdev_register(&u3_agp_pci_host_info);
 413
 414     sysbus_register_withprop(&sysbus_unin_agp_pci_host_info);
 415     pci_qdev_register(&unin_agp_pci_host_info);
 416
 417     sysbus_register_withprop(&sysbus_unin_internal_pci_host_info);
 418     pci_qdev_register(&unin_internal_pci_host_info);
 419 }
 420
 421 device_init(unin_register_devices)