2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
4 * Author: Mike Lavender, mike@steroidmicros.com
6 * Copyright (c) 2005, Intec Automation Inc.
8 * Some parts are based on lart.c by Abraham Van Der Merwe
10 * Cleaned up and generalized based on mtd_dataflash.c
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/math64.h>
24 #include <linux/slab.h>
25 #include <linux/sched.h>
26 #include <linux/mod_devicetable.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/partitions.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/flash.h>
35 #define OPCODE_WREN 0x06 /* Write enable */
36 #define OPCODE_RDSR 0x05 /* Read status register */
37 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
38 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
39 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
40 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
41 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
42 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
43 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
44 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
45 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
47 /* Used for SST flashes only. */
48 #define OPCODE_BP 0x02 /* Byte program */
49 #define OPCODE_WRDI 0x04 /* Write disable */
50 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
52 /* Status Register bits. */
53 #define SR_WIP 1 /* Write in progress */
54 #define SR_WEL 2 /* Write enable latch */
55 /* meaning of other SR_* bits may differ between vendors */
56 #define SR_BP0 4 /* Block protect 0 */
57 #define SR_BP1 8 /* Block protect 1 */
58 #define SR_BP2 0x10 /* Block protect 2 */
59 #define SR_SRWD 0x80 /* SR write protect */
61 /* Define max times to check status register before we give up. */
62 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
63 #define MAX_CMD_SIZE 4
65 #ifdef CONFIG_M25PXX_USE_FAST_READ
66 #define OPCODE_READ OPCODE_FAST_READ
67 #define FAST_READ_DUMMY_BYTE 1
69 #define OPCODE_READ OPCODE_NORM_READ
70 #define FAST_READ_DUMMY_BYTE 0
73 /****************************************************************************/
76 struct spi_device *spi;
79 unsigned partitioned:1;
86 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
88 return container_of(mtd, struct m25p, mtd);
91 /****************************************************************************/
94 * Internal helper functions
98 * Read the status register, returning its value in the location
99 * Return the status register value.
100 * Returns negative if error occurred.
102 static int read_sr(struct m25p *flash)
105 u8 code = OPCODE_RDSR;
108 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
111 dev_err(&flash->spi->dev, "error %d reading SR\n",
120 * Write status register 1 byte
121 * Returns negative if error occurred.
123 static int write_sr(struct m25p *flash, u8 val)
125 flash->command[0] = OPCODE_WRSR;
126 flash->command[1] = val;
128 return spi_write(flash->spi, flash->command, 2);
132 * Set write enable latch with Write Enable command.
133 * Returns negative if error occurred.
135 static inline int write_enable(struct m25p *flash)
137 u8 code = OPCODE_WREN;
139 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
143 * Send write disble instruction to the chip.
145 static inline int write_disable(struct m25p *flash)
147 u8 code = OPCODE_WRDI;
149 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
153 * Service routine to read status register until ready, or timeout occurs.
154 * Returns non-zero if error.
156 static int wait_till_ready(struct m25p *flash)
158 unsigned long deadline;
161 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
164 if ((sr = read_sr(flash)) < 0)
166 else if (!(sr & SR_WIP))
171 } while (!time_after_eq(jiffies, deadline));
177 * Erase the whole flash memory
179 * Returns 0 if successful, non-zero otherwise.
181 static int erase_chip(struct m25p *flash)
183 DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %lldKiB\n",
184 dev_name(&flash->spi->dev), __func__,
185 (long long)(flash->mtd.size >> 10));
187 /* Wait until finished previous write command. */
188 if (wait_till_ready(flash))
191 /* Send write enable, then erase commands. */
194 /* Set up command buffer. */
195 flash->command[0] = OPCODE_CHIP_ERASE;
197 spi_write(flash->spi, flash->command, 1);
202 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
204 /* opcode is in cmd[0] */
205 cmd[1] = addr >> (flash->addr_width * 8 - 8);
206 cmd[2] = addr >> (flash->addr_width * 8 - 16);
207 cmd[3] = addr >> (flash->addr_width * 8 - 24);
210 static int m25p_cmdsz(struct m25p *flash)
212 return 1 + flash->addr_width;
216 * Erase one sector of flash memory at offset ``offset'' which is any
217 * address within the sector which should be erased.
219 * Returns 0 if successful, non-zero otherwise.
221 static int erase_sector(struct m25p *flash, u32 offset)
223 DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n",
224 dev_name(&flash->spi->dev), __func__,
225 flash->mtd.erasesize / 1024, offset);
227 /* Wait until finished previous write command. */
228 if (wait_till_ready(flash))
231 /* Send write enable, then erase commands. */
234 /* Set up command buffer. */
235 flash->command[0] = flash->erase_opcode;
236 m25p_addr2cmd(flash, offset, flash->command);
238 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
243 /****************************************************************************/
250 * Erase an address range on the flash chip. The address range may extend
251 * one or more erase sectors. Return an error is there is a problem erasing.
253 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
255 struct m25p *flash = mtd_to_m25p(mtd);
259 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%llx, len %lld\n",
260 dev_name(&flash->spi->dev), __func__, "at",
261 (long long)instr->addr, (long long)instr->len);
264 if (instr->addr + instr->len > flash->mtd.size)
266 div_u64_rem(instr->len, mtd->erasesize, &rem);
273 mutex_lock(&flash->lock);
275 /* whole-chip erase? */
276 if (len == flash->mtd.size) {
277 if (erase_chip(flash)) {
278 instr->state = MTD_ERASE_FAILED;
279 mutex_unlock(&flash->lock);
283 /* REVISIT in some cases we could speed up erasing large regions
284 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
285 * to use "small sector erase", but that's not always optimal.
288 /* "sector"-at-a-time erase */
291 if (erase_sector(flash, addr)) {
292 instr->state = MTD_ERASE_FAILED;
293 mutex_unlock(&flash->lock);
297 addr += mtd->erasesize;
298 len -= mtd->erasesize;
302 mutex_unlock(&flash->lock);
304 instr->state = MTD_ERASE_DONE;
305 mtd_erase_callback(instr);
311 * Read an address range from the flash chip. The address range
312 * may be any size provided it is within the physical boundaries.
314 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
315 size_t *retlen, u_char *buf)
317 struct m25p *flash = mtd_to_m25p(mtd);
318 struct spi_transfer t[2];
319 struct spi_message m;
321 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n",
322 dev_name(&flash->spi->dev), __func__, "from",
329 if (from + len > flash->mtd.size)
332 spi_message_init(&m);
333 memset(t, 0, (sizeof t));
336 * OPCODE_FAST_READ (if available) is faster.
337 * Should add 1 byte DUMMY_BYTE.
339 t[0].tx_buf = flash->command;
340 t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
341 spi_message_add_tail(&t[0], &m);
345 spi_message_add_tail(&t[1], &m);
347 /* Byte count starts at zero. */
351 mutex_lock(&flash->lock);
353 /* Wait till previous write/erase is done. */
354 if (wait_till_ready(flash)) {
355 /* REVISIT status return?? */
356 mutex_unlock(&flash->lock);
360 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
361 * clocks; and at this writing, every chip this driver handles
362 * supports that opcode.
365 /* Set up the write data buffer. */
366 flash->command[0] = OPCODE_READ;
367 m25p_addr2cmd(flash, from, flash->command);
369 spi_sync(flash->spi, &m);
371 *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
373 mutex_unlock(&flash->lock);
379 * Write an address range to the flash chip. Data must be written in
380 * FLASH_PAGESIZE chunks. The address range may be any size provided
381 * it is within the physical boundaries.
383 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
384 size_t *retlen, const u_char *buf)
386 struct m25p *flash = mtd_to_m25p(mtd);
387 u32 page_offset, page_size;
388 struct spi_transfer t[2];
389 struct spi_message m;
391 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n",
392 dev_name(&flash->spi->dev), __func__, "to",
402 if (to + len > flash->mtd.size)
405 spi_message_init(&m);
406 memset(t, 0, (sizeof t));
408 t[0].tx_buf = flash->command;
409 t[0].len = m25p_cmdsz(flash);
410 spi_message_add_tail(&t[0], &m);
413 spi_message_add_tail(&t[1], &m);
415 mutex_lock(&flash->lock);
417 /* Wait until finished previous write command. */
418 if (wait_till_ready(flash)) {
419 mutex_unlock(&flash->lock);
425 /* Set up the opcode in the write buffer. */
426 flash->command[0] = OPCODE_PP;
427 m25p_addr2cmd(flash, to, flash->command);
429 page_offset = to & (flash->page_size - 1);
431 /* do all the bytes fit onto one page? */
432 if (page_offset + len <= flash->page_size) {
435 spi_sync(flash->spi, &m);
437 *retlen = m.actual_length - m25p_cmdsz(flash);
441 /* the size of data remaining on the first page */
442 page_size = flash->page_size - page_offset;
444 t[1].len = page_size;
445 spi_sync(flash->spi, &m);
447 *retlen = m.actual_length - m25p_cmdsz(flash);
449 /* write everything in flash->page_size chunks */
450 for (i = page_size; i < len; i += page_size) {
452 if (page_size > flash->page_size)
453 page_size = flash->page_size;
455 /* write the next page to flash */
456 m25p_addr2cmd(flash, to + i, flash->command);
458 t[1].tx_buf = buf + i;
459 t[1].len = page_size;
461 wait_till_ready(flash);
465 spi_sync(flash->spi, &m);
468 *retlen += m.actual_length - m25p_cmdsz(flash);
472 mutex_unlock(&flash->lock);
477 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
478 size_t *retlen, const u_char *buf)
480 struct m25p *flash = mtd_to_m25p(mtd);
481 struct spi_transfer t[2];
482 struct spi_message m;
493 if (to + len > flash->mtd.size)
496 spi_message_init(&m);
497 memset(t, 0, (sizeof t));
499 t[0].tx_buf = flash->command;
500 t[0].len = m25p_cmdsz(flash);
501 spi_message_add_tail(&t[0], &m);
504 spi_message_add_tail(&t[1], &m);
506 mutex_lock(&flash->lock);
508 /* Wait until finished previous write command. */
509 ret = wait_till_ready(flash);
516 /* Start write from odd address. */
518 flash->command[0] = OPCODE_BP;
519 m25p_addr2cmd(flash, to, flash->command);
521 /* write one byte. */
523 spi_sync(flash->spi, &m);
524 ret = wait_till_ready(flash);
527 *retlen += m.actual_length - m25p_cmdsz(flash);
531 flash->command[0] = OPCODE_AAI_WP;
532 m25p_addr2cmd(flash, to, flash->command);
534 /* Write out most of the data here. */
535 cmd_sz = m25p_cmdsz(flash);
536 for (; actual < len - 1; actual += 2) {
538 /* write two bytes. */
540 t[1].tx_buf = buf + actual;
542 spi_sync(flash->spi, &m);
543 ret = wait_till_ready(flash);
546 *retlen += m.actual_length - cmd_sz;
550 write_disable(flash);
551 ret = wait_till_ready(flash);
555 /* Write out trailing byte if it exists. */
558 flash->command[0] = OPCODE_BP;
559 m25p_addr2cmd(flash, to, flash->command);
560 t[0].len = m25p_cmdsz(flash);
562 t[1].tx_buf = buf + actual;
564 spi_sync(flash->spi, &m);
565 ret = wait_till_ready(flash);
568 *retlen += m.actual_length - m25p_cmdsz(flash);
569 write_disable(flash);
573 mutex_unlock(&flash->lock);
577 /****************************************************************************/
580 * SPI device driver setup and teardown
584 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
585 * a high byte of zero plus three data bytes: the manufacturer id,
586 * then a two byte device id.
591 /* The size listed here is what works with OPCODE_SE, which isn't
592 * necessarily called a "sector" by the vendor.
594 unsigned sector_size;
601 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
602 #define M25P_NO_ERASE 0x02 /* No erase command needed */
605 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
606 ((kernel_ulong_t)&(struct flash_info) { \
607 .jedec_id = (_jedec_id), \
608 .ext_id = (_ext_id), \
609 .sector_size = (_sector_size), \
610 .n_sectors = (_n_sectors), \
616 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \
617 ((kernel_ulong_t)&(struct flash_info) { \
618 .sector_size = (_sector_size), \
619 .n_sectors = (_n_sectors), \
620 .page_size = (_page_size), \
621 .addr_width = (_addr_width), \
622 .flags = M25P_NO_ERASE, \
625 /* NOTE: double check command sets and memory organization when you add
626 * more flash chips. This current list focusses on newer chips, which
627 * have been converging on command sets which including JEDEC ID.
629 static const struct spi_device_id m25p_ids[] = {
630 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
631 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
632 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
634 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
635 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
637 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
638 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
639 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
640 { "at26df321", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
643 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
644 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
645 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
646 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
647 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
648 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
650 /* Spansion -- single (large) sector size only, at least
651 * for the chips listed here (without boot sectors).
653 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
654 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
655 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
656 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
657 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
658 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
659 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
660 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
661 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
663 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
664 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) },
665 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) },
666 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) },
667 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) },
668 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) },
669 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) },
670 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) },
671 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) },
673 /* ST Microelectronics -- newer production may have feature updates */
674 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
675 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
676 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
677 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
678 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
679 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
680 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
681 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
682 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
684 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
685 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
686 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
687 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
688 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
689 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
690 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
691 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
692 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
694 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
695 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
696 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
698 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
699 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
701 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
702 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
703 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
704 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
705 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
706 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
707 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
708 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
710 /* Catalyst / On Semiconductor -- non-JEDEC */
711 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
712 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) },
713 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) },
714 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) },
715 { "cat25128", CAT25_INFO(2048, 8, 64, 2) },
718 MODULE_DEVICE_TABLE(spi, m25p_ids);
720 static const struct spi_device_id *__devinit jedec_probe(struct spi_device *spi)
723 u8 code = OPCODE_RDID;
727 struct flash_info *info;
729 /* JEDEC also defines an optional "extended device information"
730 * string for after vendor-specific data, after the three bytes
731 * we use here. Supporting some chips might require using it.
733 tmp = spi_write_then_read(spi, &code, 1, id, 5);
735 DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n",
736 dev_name(&spi->dev), tmp);
746 * Some chips (like Numonyx M25P80) have JEDEC and non-JEDEC variants,
747 * which depend on technology process. Officially RDID command doesn't
748 * exist for non-JEDEC chips, but for compatibility they return ID 0.
753 ext_jedec = id[3] << 8 | id[4];
755 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
756 info = (void *)m25p_ids[tmp].driver_data;
757 if (info->jedec_id == jedec) {
758 if (info->ext_id != 0 && info->ext_id != ext_jedec)
760 return &m25p_ids[tmp];
768 * board specific setup should have ensured the SPI clock used here
769 * matches what the READ command supports, at least until this driver
770 * understands FAST_READ (for clocks over 25 MHz).
772 static int __devinit m25p_probe(struct spi_device *spi)
774 const struct spi_device_id *id = spi_get_device_id(spi);
775 struct flash_platform_data *data;
777 struct flash_info *info;
780 /* Platform data helps sort out which chip type we have, as
781 * well as how this board partitions it. If we don't have
782 * a chip ID, try the JEDEC id commands; they'll work for most
783 * newer chips, even if we don't recognize the particular chip.
785 data = spi->dev.platform_data;
786 if (data && data->type) {
787 const struct spi_device_id *plat_id;
789 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
790 plat_id = &m25p_ids[i];
791 if (strcmp(data->type, plat_id->name))
799 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
802 info = (void *)id->driver_data;
804 if (info->jedec_id) {
805 const struct spi_device_id *jid;
807 jid = jedec_probe(spi);
810 } else if (jid != id) {
812 * JEDEC knows better, so overwrite platform ID. We
813 * can't trust partitions any longer, but we'll let
814 * mtd apply them anyway, since some partitions may be
815 * marked read-only, and we don't want to lose that
816 * information, even if it's not 100% accurate.
818 dev_warn(&spi->dev, "found %s, expected %s\n",
819 jid->name, id->name);
821 info = (void *)jid->driver_data;
825 flash = kzalloc(sizeof *flash, GFP_KERNEL);
828 flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL);
829 if (!flash->command) {
835 mutex_init(&flash->lock);
836 dev_set_drvdata(&spi->dev, flash);
839 * Atmel and SST serial flash tend to power
840 * up with the software protection bits set
843 if (info->jedec_id >> 16 == 0x1f ||
844 info->jedec_id >> 16 == 0xbf) {
849 if (data && data->name)
850 flash->mtd.name = data->name;
852 flash->mtd.name = dev_name(&spi->dev);
854 flash->mtd.type = MTD_NORFLASH;
855 flash->mtd.writesize = 1;
856 flash->mtd.flags = MTD_CAP_NORFLASH;
857 flash->mtd.size = info->sector_size * info->n_sectors;
858 flash->mtd.erase = m25p80_erase;
859 flash->mtd.read = m25p80_read;
861 /* sst flash chips use AAI word program */
862 if (info->jedec_id >> 16 == 0xbf)
863 flash->mtd.write = sst_write;
865 flash->mtd.write = m25p80_write;
867 /* prefer "small sector" erase if possible */
868 if (info->flags & SECT_4K) {
869 flash->erase_opcode = OPCODE_BE_4K;
870 flash->mtd.erasesize = 4096;
872 flash->erase_opcode = OPCODE_SE;
873 flash->mtd.erasesize = info->sector_size;
876 if (info->flags & M25P_NO_ERASE)
877 flash->mtd.flags |= MTD_NO_ERASE;
879 flash->mtd.dev.parent = &spi->dev;
880 flash->page_size = info->page_size;
881 flash->addr_width = info->addr_width;
883 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
884 (long long)flash->mtd.size >> 10);
886 DEBUG(MTD_DEBUG_LEVEL2,
887 "mtd .name = %s, .size = 0x%llx (%lldMiB) "
888 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
890 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
891 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
892 flash->mtd.numeraseregions);
894 if (flash->mtd.numeraseregions)
895 for (i = 0; i < flash->mtd.numeraseregions; i++)
896 DEBUG(MTD_DEBUG_LEVEL2,
897 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
898 ".erasesize = 0x%.8x (%uKiB), "
899 ".numblocks = %d }\n",
900 i, (long long)flash->mtd.eraseregions[i].offset,
901 flash->mtd.eraseregions[i].erasesize,
902 flash->mtd.eraseregions[i].erasesize / 1024,
903 flash->mtd.eraseregions[i].numblocks);
906 /* partitions should match sector boundaries; and it may be good to
907 * use readonly partitions for writeprotected sectors (BP2..BP0).
909 if (mtd_has_partitions()) {
910 struct mtd_partition *parts = NULL;
913 if (mtd_has_cmdlinepart()) {
914 static const char *part_probes[]
915 = { "cmdlinepart", NULL, };
917 nr_parts = parse_mtd_partitions(&flash->mtd,
918 part_probes, &parts, 0);
921 if (nr_parts <= 0 && data && data->parts) {
923 nr_parts = data->nr_parts;
927 for (i = 0; i < nr_parts; i++) {
928 DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = "
929 "{.name = %s, .offset = 0x%llx, "
930 ".size = 0x%llx (%lldKiB) }\n",
932 (long long)parts[i].offset,
933 (long long)parts[i].size,
934 (long long)(parts[i].size >> 10));
936 flash->partitioned = 1;
937 return add_mtd_partitions(&flash->mtd, parts, nr_parts);
939 } else if (data && data->nr_parts)
940 dev_warn(&spi->dev, "ignoring %d default partitions on %s\n",
941 data->nr_parts, data->name);
943 return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0;
947 static int __devexit m25p_remove(struct spi_device *spi)
949 struct m25p *flash = dev_get_drvdata(&spi->dev);
952 /* Clean up MTD stuff. */
953 if (mtd_has_partitions() && flash->partitioned)
954 status = del_mtd_partitions(&flash->mtd);
956 status = del_mtd_device(&flash->mtd);
958 kfree(flash->command);
965 static struct spi_driver m25p80_driver = {
968 .bus = &spi_bus_type,
969 .owner = THIS_MODULE,
971 .id_table = m25p_ids,
973 .remove = __devexit_p(m25p_remove),
975 /* REVISIT: many of these chips have deep power-down modes, which
976 * should clearly be entered on suspend() to minimize power use.
977 * And also when they're otherwise idle...
982 static int __init m25p80_init(void)
984 return spi_register_driver(&m25p80_driver);
988 static void __exit m25p80_exit(void)
990 spi_unregister_driver(&m25p80_driver);
994 module_init(m25p80_init);
995 module_exit(m25p80_exit);
997 MODULE_LICENSE("GPL");
998 MODULE_AUTHOR("Mike Lavender");
999 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");