2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
34 #include <linux/device.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37 #include <linux/serial.h>
38 #include <linux/sysrq.h>
39 #include <linux/console.h>
40 #include <linux/delay.h>
43 #include <linux/of_platform.h>
44 #include <linux/clk.h>
45 #include <linux/slab.h>
47 #include <asm/mpc52xx.h>
48 #include <asm/mpc52xx_psc.h>
50 #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
54 #include <linux/serial_core.h>
57 /* We've been assigned a range on the "Low-density serial ports" major */
58 #define SERIAL_PSC_MAJOR 204
59 #define SERIAL_PSC_MINOR 148
62 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
65 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
66 /* Rem: - We use the read_status_mask as a shadow of
67 * psc->mpc52xx_psc_imr
68 * - It's important that is array is all zero on start as we
69 * use it to know if it's initialized or not ! If it's not sure
70 * it's cleared, then a memset(...,0,...) should be added to
74 /* lookup table for matching device nodes to index numbers */
75 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
77 static void mpc52xx_uart_of_enumerate(void);
80 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
83 /* Forward declaration of the interruption handling routine */
84 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
85 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
88 /* Simple macro to test if a port is console or not. This one is taken
89 * for serial_core.c and maybe should be moved to serial_core.h ? */
90 #ifdef CONFIG_SERIAL_CORE_CONSOLE
91 #define uart_console(port) \
92 ((port)->cons && (port)->cons->index == (port)->line)
94 #define uart_console(port) (0)
97 /* ======================================================================== */
98 /* PSC fifo operations for isolating differences between 52xx and 512x */
99 /* ======================================================================== */
102 void (*fifo_init)(struct uart_port *port);
103 int (*raw_rx_rdy)(struct uart_port *port);
104 int (*raw_tx_rdy)(struct uart_port *port);
105 int (*rx_rdy)(struct uart_port *port);
106 int (*tx_rdy)(struct uart_port *port);
107 int (*tx_empty)(struct uart_port *port);
108 void (*stop_rx)(struct uart_port *port);
109 void (*start_tx)(struct uart_port *port);
110 void (*stop_tx)(struct uart_port *port);
111 void (*rx_clr_irq)(struct uart_port *port);
112 void (*tx_clr_irq)(struct uart_port *port);
113 void (*write_char)(struct uart_port *port, unsigned char c);
114 unsigned char (*read_char)(struct uart_port *port);
115 void (*cw_disable_ints)(struct uart_port *port);
116 void (*cw_restore_ints)(struct uart_port *port);
117 unsigned int (*set_baudrate)(struct uart_port *port,
118 struct ktermios *new,
119 struct ktermios *old);
120 int (*clock)(struct uart_port *port, int enable);
121 int (*fifoc_init)(void);
122 void (*fifoc_uninit)(void);
123 void (*get_irq)(struct uart_port *, struct device_node *);
124 irqreturn_t (*handle_irq)(struct uart_port *port);
127 struct mpc52xx_private_data {
128 int mode; // Determine wether to use port in RS-232 (=0) or RS-485 (=1) mode
131 /* setting the prescaler and divisor reg is common for all chips */
132 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
133 u16 prescaler, unsigned int divisor)
135 /* select prescaler */
136 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
137 out_8(&psc->ctur, divisor >> 8);
138 out_8(&psc->ctlr, divisor & 0xff);
141 #ifdef CONFIG_PPC_MPC52xx
142 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
143 static void mpc52xx_psc_fifo_init(struct uart_port *port)
145 struct mpc52xx_psc __iomem *psc = PSC(port);
146 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
148 out_8(&fifo->rfcntl, 0x00);
149 out_be16(&fifo->rfalarm, 0x1ff);
150 out_8(&fifo->tfcntl, 0x07);
151 out_be16(&fifo->tfalarm, 0x80);
153 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
154 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
157 static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
159 return in_be16(&PSC(port)->mpc52xx_psc_status)
160 & MPC52xx_PSC_SR_RXRDY;
163 static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
165 return in_be16(&PSC(port)->mpc52xx_psc_status)
166 & MPC52xx_PSC_SR_TXRDY;
170 static int mpc52xx_psc_rx_rdy(struct uart_port *port)
172 return in_be16(&PSC(port)->mpc52xx_psc_isr)
173 & port->read_status_mask
174 & MPC52xx_PSC_IMR_RXRDY;
177 static int mpc52xx_psc_tx_rdy(struct uart_port *port)
179 return in_be16(&PSC(port)->mpc52xx_psc_isr)
180 & port->read_status_mask
181 & MPC52xx_PSC_IMR_TXRDY;
184 static int mpc52xx_psc_tx_empty(struct uart_port *port)
186 return in_be16(&PSC(port)->mpc52xx_psc_status)
187 & MPC52xx_PSC_SR_TXEMP;
190 static void mpc52xx_psc_start_tx(struct uart_port *port)
192 struct mpc52xx_private_data *private_data = (struct mpc52xx_private_data *) port->private_data;
194 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
195 if (private_data->mode == 1)
196 port->read_status_mask |= MPC52xx_PSC_IMR_TXEMP;
197 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
200 static void mpc52xx_psc_stop_tx(struct uart_port *port)
202 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
203 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
206 static void mpc52xx_psc_stop_rx(struct uart_port *port)
208 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
209 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
212 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
216 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
220 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
222 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
225 static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
227 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
230 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
232 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
235 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
237 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
240 static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
241 struct ktermios *new,
242 struct ktermios *old)
245 unsigned int divisor;
247 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
248 baud = uart_get_baud_rate(port, new, old,
249 port->uartclk / (32 * 0xffff) + 1,
251 divisor = (port->uartclk + 16 * baud) / (32 * baud);
253 /* enable the /32 prescaler and set the divisor */
254 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
258 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
259 struct ktermios *new,
260 struct ktermios *old)
263 unsigned int divisor;
266 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
268 baud = uart_get_baud_rate(port, new, old,
269 port->uartclk / (32 * 0xffff) + 1,
271 divisor = (port->uartclk + 2 * baud) / (4 * baud);
273 /* select the proper prescaler and set the divisor */
274 if (divisor > 0xffff) {
275 divisor = (divisor + 4) / 8;
276 prescaler = 0xdd00; /* /32 */
278 prescaler = 0xff00; /* /4 */
279 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
283 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
285 port->irqflags = IRQF_DISABLED;
286 port->irq = irq_of_parse_and_map(np, 0);
289 /* 52xx specific interrupt handler. The caller holds the port lock */
290 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
292 return mpc5xxx_uart_process_int(port);
295 static struct psc_ops mpc52xx_psc_ops = {
296 .fifo_init = mpc52xx_psc_fifo_init,
297 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
298 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
299 .rx_rdy = mpc52xx_psc_rx_rdy,
300 .tx_rdy = mpc52xx_psc_tx_rdy,
301 .tx_empty = mpc52xx_psc_tx_empty,
302 .stop_rx = mpc52xx_psc_stop_rx,
303 .start_tx = mpc52xx_psc_start_tx,
304 .stop_tx = mpc52xx_psc_stop_tx,
305 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
306 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
307 .write_char = mpc52xx_psc_write_char,
308 .read_char = mpc52xx_psc_read_char,
309 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
310 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
311 .set_baudrate = mpc5200_psc_set_baudrate,
312 .get_irq = mpc52xx_psc_get_irq,
313 .handle_irq = mpc52xx_psc_handle_irq,
316 static struct psc_ops mpc5200b_psc_ops = {
317 .fifo_init = mpc52xx_psc_fifo_init,
318 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
319 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
320 .rx_rdy = mpc52xx_psc_rx_rdy,
321 .tx_rdy = mpc52xx_psc_tx_rdy,
322 .tx_empty = mpc52xx_psc_tx_empty,
323 .stop_rx = mpc52xx_psc_stop_rx,
324 .start_tx = mpc52xx_psc_start_tx,
325 .stop_tx = mpc52xx_psc_stop_tx,
326 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
327 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
328 .write_char = mpc52xx_psc_write_char,
329 .read_char = mpc52xx_psc_read_char,
330 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
331 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
332 .set_baudrate = mpc5200b_psc_set_baudrate,
333 .get_irq = mpc52xx_psc_get_irq,
334 .handle_irq = mpc52xx_psc_handle_irq,
337 #endif /* CONFIG_MPC52xx */
339 #ifdef CONFIG_PPC_MPC512x
340 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
342 /* PSC FIFO Controller for mpc512x */
351 static struct psc_fifoc __iomem *psc_fifoc;
352 static unsigned int psc_fifoc_irq;
354 static void mpc512x_psc_fifo_init(struct uart_port *port)
357 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
359 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
360 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
361 out_be32(&FIFO_512x(port)->txalarm, 1);
362 out_be32(&FIFO_512x(port)->tximr, 0);
364 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
365 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
366 out_be32(&FIFO_512x(port)->rxalarm, 1);
367 out_be32(&FIFO_512x(port)->rximr, 0);
369 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
370 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
373 static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
375 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
378 static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
380 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
383 static int mpc512x_psc_rx_rdy(struct uart_port *port)
385 return in_be32(&FIFO_512x(port)->rxsr)
386 & in_be32(&FIFO_512x(port)->rximr)
387 & MPC512x_PSC_FIFO_ALARM;
390 static int mpc512x_psc_tx_rdy(struct uart_port *port)
392 return in_be32(&FIFO_512x(port)->txsr)
393 & in_be32(&FIFO_512x(port)->tximr)
394 & MPC512x_PSC_FIFO_ALARM;
397 static int mpc512x_psc_tx_empty(struct uart_port *port)
399 return in_be32(&FIFO_512x(port)->txsr)
400 & MPC512x_PSC_FIFO_EMPTY;
403 static void mpc512x_psc_stop_rx(struct uart_port *port)
405 unsigned long rx_fifo_imr;
407 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
408 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
409 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
412 static void mpc512x_psc_start_tx(struct uart_port *port)
414 unsigned long tx_fifo_imr;
416 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
417 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
418 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
421 static void mpc512x_psc_stop_tx(struct uart_port *port)
423 unsigned long tx_fifo_imr;
425 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
426 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
427 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
430 static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
432 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
435 static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
437 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
440 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
442 out_8(&FIFO_512x(port)->txdata_8, c);
445 static unsigned char mpc512x_psc_read_char(struct uart_port *port)
447 return in_8(&FIFO_512x(port)->rxdata_8);
450 static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
452 port->read_status_mask =
453 in_be32(&FIFO_512x(port)->tximr) << 16 |
454 in_be32(&FIFO_512x(port)->rximr);
455 out_be32(&FIFO_512x(port)->tximr, 0);
456 out_be32(&FIFO_512x(port)->rximr, 0);
459 static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
461 out_be32(&FIFO_512x(port)->tximr,
462 (port->read_status_mask >> 16) & 0x7f);
463 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
466 static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
467 struct ktermios *new,
468 struct ktermios *old)
471 unsigned int divisor;
474 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
475 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
476 * Furthermore, it states that "After reset, the prescaler by 10
477 * for the UART mode is selected", but the reset register value is
478 * 0x0000 which means a /32 prescaler. This is wrong.
480 * In reality using /32 prescaler doesn't work, as it is not supported!
481 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
482 * Chapter 4.1 PSC in UART Mode.
483 * Calculate with a /16 prescaler here.
486 /* uartclk contains the ips freq */
487 baud = uart_get_baud_rate(port, new, old,
488 port->uartclk / (16 * 0xffff) + 1,
490 divisor = (port->uartclk + 8 * baud) / (16 * baud);
492 /* enable the /16 prescaler and set the divisor */
493 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
497 /* Init PSC FIFO Controller */
498 static int __init mpc512x_psc_fifoc_init(void)
500 struct device_node *np;
502 np = of_find_compatible_node(NULL, NULL,
503 "fsl,mpc5121-psc-fifo");
505 pr_err("%s: Can't find FIFOC node\n", __func__);
509 psc_fifoc = of_iomap(np, 0);
511 pr_err("%s: Can't map FIFOC\n", __func__);
516 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
518 if (psc_fifoc_irq == NO_IRQ) {
519 pr_err("%s: Can't get FIFOC irq\n", __func__);
527 static void __exit mpc512x_psc_fifoc_uninit(void)
532 /* 512x specific interrupt handler. The caller holds the port lock */
533 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
535 unsigned long fifoc_int;
538 /* Read pending PSC FIFOC interrupts */
539 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
541 /* Check if it is an interrupt for this port */
542 psc_num = (port->mapbase & 0xf00) >> 8;
543 if (test_bit(psc_num, &fifoc_int) ||
544 test_bit(psc_num + 16, &fifoc_int))
545 return mpc5xxx_uart_process_int(port);
550 static int mpc512x_psc_clock(struct uart_port *port, int enable)
556 if (uart_console(port))
559 psc_num = (port->mapbase & 0xf00) >> 8;
560 snprintf(clk_name, sizeof(clk_name), "psc%d_clk", psc_num);
561 psc_clk = clk_get(port->dev, clk_name);
562 if (IS_ERR(psc_clk)) {
563 dev_err(port->dev, "Failed to get PSC clock entry!\n");
567 dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
572 clk_disable(psc_clk);
577 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
579 port->irqflags = IRQF_SHARED;
580 port->irq = psc_fifoc_irq;
583 static struct psc_ops mpc512x_psc_ops = {
584 .fifo_init = mpc512x_psc_fifo_init,
585 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
586 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
587 .rx_rdy = mpc512x_psc_rx_rdy,
588 .tx_rdy = mpc512x_psc_tx_rdy,
589 .tx_empty = mpc512x_psc_tx_empty,
590 .stop_rx = mpc512x_psc_stop_rx,
591 .start_tx = mpc512x_psc_start_tx,
592 .stop_tx = mpc512x_psc_stop_tx,
593 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
594 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
595 .write_char = mpc512x_psc_write_char,
596 .read_char = mpc512x_psc_read_char,
597 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
598 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
599 .set_baudrate = mpc512x_psc_set_baudrate,
600 .clock = mpc512x_psc_clock,
601 .fifoc_init = mpc512x_psc_fifoc_init,
602 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
603 .get_irq = mpc512x_psc_get_irq,
604 .handle_irq = mpc512x_psc_handle_irq,
608 static struct psc_ops *psc_ops;
610 /* ======================================================================== */
611 /* UART operations */
612 /* ======================================================================== */
615 mpc52xx_uart_tx_empty(struct uart_port *port)
617 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
621 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
623 if (mctrl & TIOCM_RTS)
624 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
626 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
630 mpc52xx_uart_get_mctrl(struct uart_port *port)
632 unsigned int ret = TIOCM_DSR;
633 u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
635 if (!(status & MPC52xx_PSC_CTS))
637 if (!(status & MPC52xx_PSC_DCD))
644 mpc52xx_uart_stop_tx(struct uart_port *port)
646 /* port->lock taken by caller */
647 psc_ops->stop_tx(port);
651 mpc52xx_uart_start_tx(struct uart_port *port)
653 /* port->lock taken by caller */
654 psc_ops->start_tx(port);
655 // if(!uart_console(port))
656 // printk("mpc52xx: start_tx\n");
660 mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
663 spin_lock_irqsave(&port->lock, flags);
667 /* Make sure tx interrupts are on */
668 /* Truly necessary ??? They should be anyway */
669 psc_ops->start_tx(port);
672 spin_unlock_irqrestore(&port->lock, flags);
676 mpc52xx_uart_stop_rx(struct uart_port *port)
678 /* port->lock taken by caller */
679 psc_ops->stop_rx(port);
680 // if(!uart_console(port))
681 // printk("mpc52xx: stop_tx\n");
685 mpc52xx_uart_enable_ms(struct uart_port *port)
687 struct mpc52xx_psc __iomem *psc = PSC(port);
689 /* clear D_*-bits by reading them */
690 in_8(&psc->mpc52xx_psc_ipcr);
691 /* enable CTS and DCD as IPC interrupts */
692 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
694 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
695 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
699 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
702 spin_lock_irqsave(&port->lock, flags);
705 out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK);
707 out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK);
709 spin_unlock_irqrestore(&port->lock, flags);
713 mpc52xx_uart_startup(struct uart_port *port)
715 struct mpc52xx_psc __iomem *psc = PSC(port);
718 if (psc_ops->clock) {
719 ret = psc_ops->clock(port, 1);
725 ret = request_irq(port->irq, mpc52xx_uart_int,
726 port->irqflags, "mpc52xx_psc_uart", port);
730 /* Reset/activate the port, clear and enable interrupts */
731 out_8(&psc->command, MPC52xx_PSC_RST_RX);
732 out_8(&psc->command, MPC52xx_PSC_RST_TX);
734 out_be32(&psc->sicr, 0); /* UART mode DCD ignored */
736 psc_ops->fifo_init(port);
738 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
739 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
745 mpc52xx_uart_shutdown(struct uart_port *port)
747 struct mpc52xx_psc __iomem *psc = PSC(port);
749 /* Shut down the port. Leave TX active if on a console port */
750 out_8(&psc->command, MPC52xx_PSC_RST_RX);
751 if (!uart_console(port))
752 out_8(&psc->command, MPC52xx_PSC_RST_TX);
754 port->read_status_mask = 0;
755 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
758 psc_ops->clock(port, 0);
760 /* Release interrupt */
761 free_irq(port->irq, port);
765 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
766 struct ktermios *old)
768 struct mpc52xx_psc __iomem *psc = PSC(port);
770 unsigned char mr1, mr2;
774 /* Prepare what we're gonna write */
777 switch (new->c_cflag & CSIZE) {
778 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
780 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
782 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
785 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
788 if (new->c_cflag & PARENB) {
789 if (new->c_cflag & CMSPAR) {
790 mr1 |= MPC52xx_PSC_MODE_PARFORCE;
791 mr1 |= (new->c_cflag & PARODD) ?
792 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
794 mr1 |= (new->c_cflag & PARODD) ?
795 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
798 mr1 |= MPC52xx_PSC_MODE_PARNONE;
802 if (new->c_cflag & CSTOPB)
803 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
805 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
806 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
807 MPC52xx_PSC_MODE_ONE_STOP;
809 if (new->c_cflag & CRTSCTS) {
810 mr1 |= MPC52xx_PSC_MODE_RXRTS;
811 mr2 |= MPC52xx_PSC_MODE_TXCTS;
815 spin_lock_irqsave(&port->lock, flags);
817 /* Do our best to flush TX & RX, so we don't lose anything */
818 /* But we don't wait indefinitely ! */
819 j = 5000000; /* Maximum wait */
820 /* FIXME Can't receive chars since set_termios might be called at early
821 * boot for the console, all stuff is not yet ready to receive at that
822 * time and that just makes the kernel oops */
823 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
824 while (!mpc52xx_uart_tx_empty(port) && --j)
828 printk(KERN_ERR "mpc52xx_uart.c: "
829 "Unable to flush RX & TX fifos in-time in set_termios."
830 "Some chars may have been lost.\n");
832 /* Reset the TX & RX */
833 out_8(&psc->command, MPC52xx_PSC_RST_RX);
834 out_8(&psc->command, MPC52xx_PSC_RST_TX);
836 /* Send new mode settings */
837 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
838 out_8(&psc->mode, mr1);
839 out_8(&psc->mode, mr2);
840 baud = psc_ops->set_baudrate(port, new, old);
842 /* Update the per-port timeout */
843 uart_update_timeout(port, new->c_cflag, baud);
845 if (UART_ENABLE_MS(port, new->c_cflag))
846 mpc52xx_uart_enable_ms(port);
848 /* Reenable TX & RX */
849 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
850 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
852 /* RS-485 direction control - Switch to receiving TODO: if in 485 mode*/
853 out_8(&PSC(port)->op1, 0x1);
855 /* We're all set, release the lock */
856 spin_unlock_irqrestore(&port->lock, flags);
860 mpc52xx_uart_type(struct uart_port *port)
862 return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL;
866 mpc52xx_uart_release_port(struct uart_port *port)
868 /* remapped by us ? */
869 if (port->flags & UPF_IOREMAP) {
870 iounmap(port->membase);
871 port->membase = NULL;
874 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
878 mpc52xx_uart_request_port(struct uart_port *port)
882 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
883 port->membase = ioremap(port->mapbase,
884 sizeof(struct mpc52xx_psc));
889 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
890 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
892 if (err && (port->flags & UPF_IOREMAP)) {
893 iounmap(port->membase);
894 port->membase = NULL;
901 mpc52xx_uart_config_port(struct uart_port *port, int flags)
903 if ((flags & UART_CONFIG_TYPE)
904 && (mpc52xx_uart_request_port(port) == 0))
905 port->type = PORT_MPC52xx;
909 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
911 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
914 if ((ser->irq != port->irq) ||
915 (ser->io_type != UPIO_MEM) ||
916 (ser->baud_base != port->uartclk) ||
917 (ser->iomem_base != (void *)port->mapbase) ||
925 static struct uart_ops mpc52xx_uart_ops = {
926 .tx_empty = mpc52xx_uart_tx_empty,
927 .set_mctrl = mpc52xx_uart_set_mctrl,
928 .get_mctrl = mpc52xx_uart_get_mctrl,
929 .stop_tx = mpc52xx_uart_stop_tx,
930 .start_tx = mpc52xx_uart_start_tx,
931 .send_xchar = mpc52xx_uart_send_xchar,
932 .stop_rx = mpc52xx_uart_stop_rx,
933 .enable_ms = mpc52xx_uart_enable_ms,
934 .break_ctl = mpc52xx_uart_break_ctl,
935 .startup = mpc52xx_uart_startup,
936 .shutdown = mpc52xx_uart_shutdown,
937 .set_termios = mpc52xx_uart_set_termios,
938 /* .pm = mpc52xx_uart_pm, Not supported yet */
939 /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
940 .type = mpc52xx_uart_type,
941 .release_port = mpc52xx_uart_release_port,
942 .request_port = mpc52xx_uart_request_port,
943 .config_port = mpc52xx_uart_config_port,
944 .verify_port = mpc52xx_uart_verify_port
948 /* ======================================================================== */
949 /* Interrupt handling */
950 /* ======================================================================== */
953 mpc52xx_uart_int_rx_chars(struct uart_port *port)
955 struct tty_struct *tty = port->state->port.tty;
956 unsigned char ch, flag;
957 unsigned short status;
959 /* While we can read, do so ! */
960 while (psc_ops->raw_rx_rdy(port)) {
962 ch = psc_ops->read_char(port);
964 /* Handle sysreq char */
966 if (uart_handle_sysrq_char(port, ch)) {
977 status = in_be16(&PSC(port)->mpc52xx_psc_status);
979 if (status & (MPC52xx_PSC_SR_PE |
981 MPC52xx_PSC_SR_RB)) {
983 if (status & MPC52xx_PSC_SR_RB) {
985 uart_handle_break(port);
987 } else if (status & MPC52xx_PSC_SR_PE) {
989 port->icount.parity++;
991 else if (status & MPC52xx_PSC_SR_FE) {
993 port->icount.frame++;
996 /* Clear error condition */
997 out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT);
1000 tty_insert_flip_char(tty, ch, flag);
1001 if (status & MPC52xx_PSC_SR_OE) {
1003 * Overrun is special, since it's
1004 * reported immediately, and doesn't
1005 * affect the current character
1007 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1008 port->icount.overrun++;
1012 spin_unlock(&port->lock);
1013 tty_flip_buffer_push(tty);
1014 spin_lock(&port->lock);
1016 return psc_ops->raw_rx_rdy(port);
1020 mpc52xx_uart_int_tx_chars(struct uart_port *port)
1022 struct circ_buf *xmit = &port->state->xmit;
1024 /* Process out of band chars */
1026 psc_ops->write_char(port, port->x_char);
1032 /* Nothing to do ? */
1033 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1034 mpc52xx_uart_stop_tx(port);
1039 while (psc_ops->raw_tx_rdy(port)) {
1040 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1041 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1043 if (uart_circ_empty(xmit))
1048 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1049 uart_write_wakeup(port);
1051 /* Maybe we're done after all */
1052 if (uart_circ_empty(xmit)) {
1053 mpc52xx_uart_stop_tx(port);
1061 mpc5xxx_uart_process_int(struct uart_port *port)
1063 struct mpc52xx_private_data *private_data = (struct mpc52xx_private_data *) port->private_data;
1064 unsigned long pass = ISR_PASS_LIMIT;
1065 unsigned int keepgoing;
1066 struct circ_buf *xmit = &port->state->xmit;
1069 /* While we have stuff to do, we continue */
1071 /* If we don't find anything to do, we stop */
1074 psc_ops->rx_clr_irq(port);
1075 if (psc_ops->rx_rdy(port))
1076 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1078 /* RS-485 direction control */
1079 if (private_data->mode == 1) {
1080 if (!uart_circ_empty(xmit)) {
1081 out_8(&PSC(port)->op0, 0x1);
1085 psc_ops->tx_clr_irq(port);
1086 if (psc_ops->tx_rdy(port))
1087 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1089 /* RS-485 direction control */
1090 if (private_data->mode == 1) {
1091 //if ( ( status & MPC52xx_PSC_IMR_TXEMP) && ( (status & MPC52xx_PSC_IMR_TXRDY) == 0 ) && (uart_circ_empty(xmit)) ) {
1092 if ( (psc_ops->tx_empty(port)) && (psc_ops->raw_tx_rdy(port) != 0) && (uart_circ_empty(xmit)) ) {
1093 out_8(&PSC(port)->op1, 0x1);
1095 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXEMP;
1096 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
1102 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
1103 if (status & MPC52xx_PSC_D_DCD)
1104 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1106 if (status & MPC52xx_PSC_D_CTS)
1107 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1109 /* Limit number of iteration */
1113 } while (keepgoing);
1119 mpc52xx_uart_int(int irq, void *dev_id)
1121 struct uart_port *port = dev_id;
1124 spin_lock(&port->lock);
1126 ret = psc_ops->handle_irq(port);
1128 spin_unlock(&port->lock);
1133 /* ======================================================================== */
1134 /* Console ( if applicable ) */
1135 /* ======================================================================== */
1137 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1140 mpc52xx_console_get_options(struct uart_port *port,
1141 int *baud, int *parity, int *bits, int *flow)
1143 struct mpc52xx_psc __iomem *psc = PSC(port);
1146 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1148 /* Read the mode registers */
1149 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
1150 mr1 = in_8(&psc->mode);
1152 /* CT{U,L}R are write-only ! */
1153 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1156 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1157 case MPC52xx_PSC_MODE_5_BITS:
1160 case MPC52xx_PSC_MODE_6_BITS:
1163 case MPC52xx_PSC_MODE_7_BITS:
1166 case MPC52xx_PSC_MODE_8_BITS:
1171 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1174 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1178 mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1180 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1183 /* Disable interrupts */
1184 psc_ops->cw_disable_ints(port);
1186 /* Wait the TX buffer to be empty */
1187 j = 5000000; /* Maximum wait */
1188 while (!mpc52xx_uart_tx_empty(port) && --j)
1191 /* Write all the chars */
1192 for (i = 0; i < count; i++, s++) {
1193 /* Line return handling */
1195 psc_ops->write_char(port, '\r');
1198 psc_ops->write_char(port, *s);
1200 /* Wait the TX buffer to be empty */
1201 j = 20000; /* Maximum wait */
1202 while (!mpc52xx_uart_tx_empty(port) && --j)
1206 /* Restore interrupt state */
1207 psc_ops->cw_restore_ints(port);
1212 mpc52xx_console_setup(struct console *co, char *options)
1214 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1215 struct device_node *np = mpc52xx_uart_nodes[co->index];
1216 unsigned int uartclk;
1217 struct resource res;
1220 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1225 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1226 co, co->index, options);
1228 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1229 pr_debug("PSC%x out of range\n", co->index);
1234 pr_debug("PSC%x not found in device tree\n", co->index);
1238 pr_debug("Console on ttyPSC%x is %s\n",
1239 co->index, mpc52xx_uart_nodes[co->index]->full_name);
1241 /* Fetch register locations */
1242 ret = of_address_to_resource(np, 0, &res);
1244 pr_debug("Could not get resources for PSC%x\n", co->index);
1248 uartclk = mpc5xxx_get_bus_frequency(np);
1250 pr_debug("Could not find uart clock frequency!\n");
1254 /* Basic port init. Needed since we use some uart_??? func before
1255 * real init for early access */
1256 spin_lock_init(&port->lock);
1257 port->uartclk = uartclk;
1258 port->ops = &mpc52xx_uart_ops;
1259 port->mapbase = res.start;
1260 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1261 port->irq = irq_of_parse_and_map(np, 0);
1263 if (port->membase == NULL)
1266 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1267 (void *)port->mapbase, port->membase,
1268 port->irq, port->uartclk);
1270 /* Setup the port parameters accoding to options */
1272 uart_parse_options(options, &baud, &parity, &bits, &flow);
1274 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1276 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1277 baud, bits, parity, flow);
1279 return uart_set_options(port, co, baud, parity, bits, flow);
1283 static struct uart_driver mpc52xx_uart_driver;
1285 static struct console mpc52xx_console = {
1287 .write = mpc52xx_console_write,
1288 .device = uart_console_device,
1289 .setup = mpc52xx_console_setup,
1290 .flags = CON_PRINTBUFFER,
1291 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1292 .data = &mpc52xx_uart_driver,
1297 mpc52xx_console_init(void)
1299 mpc52xx_uart_of_enumerate();
1300 register_console(&mpc52xx_console);
1304 console_initcall(mpc52xx_console_init);
1306 #define MPC52xx_PSC_CONSOLE &mpc52xx_console
1308 #define MPC52xx_PSC_CONSOLE NULL
1312 /* ======================================================================== */
1314 /* ======================================================================== */
1316 static struct uart_driver mpc52xx_uart_driver = {
1317 .driver_name = "mpc52xx_psc_uart",
1318 .dev_name = "ttyPSC",
1319 .major = SERIAL_PSC_MAJOR,
1320 .minor = SERIAL_PSC_MINOR,
1321 .nr = MPC52xx_PSC_MAXNUM,
1322 .cons = MPC52xx_PSC_CONSOLE,
1325 /* ======================================================================== */
1326 /* OF Platform Driver */
1327 /* ======================================================================== */
1329 static struct of_device_id mpc52xx_uart_of_match[] = {
1330 #ifdef CONFIG_PPC_MPC52xx
1331 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1332 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1333 /* binding used by old lite5200 device trees: */
1334 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1335 /* binding used by efika: */
1336 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1338 #ifdef CONFIG_PPC_MPC512x
1339 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1344 static int __devinit
1345 mpc52xx_uart_of_probe(struct platform_device *op, const struct of_device_id *match)
1348 unsigned int uartclk;
1349 struct uart_port *port = NULL;
1350 struct resource res;
1352 struct mpc52xx_private_data *private_data = NULL;
1353 const char *port_mode = NULL;
1356 dev_dbg(&op->dev, "mpc52xx_uart_probe(op=%p, match=%p)\n", op, match);
1358 /* Check validity & presence */
1359 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1360 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1362 if (idx >= MPC52xx_PSC_MAXNUM)
1364 pr_debug("Found %s assigned to ttyPSC%x\n",
1365 mpc52xx_uart_nodes[idx]->full_name, idx);
1367 /* set the uart clock to the input clock of the psc, the different
1368 * prescalers are taken into account in the set_baudrate() methods
1369 * of the respective chip */
1370 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1372 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1376 /* Init the port structure */
1377 port = &mpc52xx_uart_ports[idx];
1379 spin_lock_init(&port->lock);
1380 port->uartclk = uartclk;
1381 port->fifosize = 512;
1382 port->iotype = UPIO_MEM;
1383 port->flags = UPF_BOOT_AUTOCONF |
1384 (uart_console(port) ? 0 : UPF_IOREMAP);
1386 port->ops = &mpc52xx_uart_ops;
1387 port->dev = &op->dev;
1389 /* Search for IRQ and mapbase */
1390 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1394 port->mapbase = res.start;
1395 if (!port->mapbase) {
1396 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1400 psc_ops->get_irq(port, op->dev.of_node);
1401 if (port->irq == NO_IRQ) {
1402 dev_dbg(&op->dev, "Could not get irq\n");
1406 private_data = (struct mpc52xx_private_data *) kzalloc(sizeof(struct mpc52xx_private_data), GFP_KERNEL);
1408 port_mode = of_get_property(op->dev.of_node, "uart_mode", &port_mode_len);
1410 if (strcmp(port_mode, "RS-485") == 0) {
1411 private_data->mode = 1;
1414 private_data->mode = 0;
1416 port->private_data = (void *) private_data;
1418 printk(KERN_ERR "Could not allocate private data for PSC\n");
1422 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1423 (void *)port->mapbase, port->irq, port->uartclk);
1425 /* Add the port to the uart sub-system */
1426 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1430 dev_set_drvdata(&op->dev, (void *)port);
1435 mpc52xx_uart_of_remove(struct platform_device *op)
1437 struct uart_port *port = dev_get_drvdata(&op->dev);
1438 dev_set_drvdata(&op->dev, NULL);
1441 if (port->private_data) {
1442 kfree(port->private_data);
1444 uart_remove_one_port(&mpc52xx_uart_driver, port);
1451 mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1453 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1456 uart_suspend_port(&mpc52xx_uart_driver, port);
1462 mpc52xx_uart_of_resume(struct platform_device *op)
1464 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1467 uart_resume_port(&mpc52xx_uart_driver, port);
1474 mpc52xx_uart_of_assign(struct device_node *np)
1478 /* Find the first free PSC number */
1479 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1480 if (mpc52xx_uart_nodes[i] == NULL) {
1482 mpc52xx_uart_nodes[i] = np;
1489 mpc52xx_uart_of_enumerate(void)
1491 static int enum_done;
1492 struct device_node *np;
1493 const struct of_device_id *match;
1499 /* Assign index to each PSC in device tree */
1500 for_each_matching_node(np, mpc52xx_uart_of_match) {
1501 match = of_match_node(mpc52xx_uart_of_match, np);
1502 psc_ops = match->data;
1503 mpc52xx_uart_of_assign(np);
1508 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1509 if (mpc52xx_uart_nodes[i])
1510 pr_debug("%s assigned to ttyPSC%x\n",
1511 mpc52xx_uart_nodes[i]->full_name, i);
1515 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1517 static struct of_platform_driver mpc52xx_uart_of_driver = {
1518 .probe = mpc52xx_uart_of_probe,
1519 .remove = mpc52xx_uart_of_remove,
1521 .suspend = mpc52xx_uart_of_suspend,
1522 .resume = mpc52xx_uart_of_resume,
1525 .name = "mpc52xx-psc-uart",
1526 .owner = THIS_MODULE,
1527 .of_match_table = mpc52xx_uart_of_match,
1532 /* ======================================================================== */
1534 /* ======================================================================== */
1537 mpc52xx_uart_init(void)
1541 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1543 ret = uart_register_driver(&mpc52xx_uart_driver);
1545 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1550 mpc52xx_uart_of_enumerate();
1553 * Map the PSC FIFO Controller and init if on MPC512x.
1555 if (psc_ops && psc_ops->fifoc_init) {
1556 ret = psc_ops->fifoc_init();
1561 ret = of_register_platform_driver(&mpc52xx_uart_of_driver);
1563 printk(KERN_ERR "%s: of_register_platform_driver failed (%i)\n",
1565 uart_unregister_driver(&mpc52xx_uart_driver);
1573 mpc52xx_uart_exit(void)
1575 if (psc_ops->fifoc_uninit)
1576 psc_ops->fifoc_uninit();
1578 of_unregister_platform_driver(&mpc52xx_uart_of_driver);
1579 uart_unregister_driver(&mpc52xx_uart_driver);
1583 module_init(mpc52xx_uart_init);
1584 module_exit(mpc52xx_uart_exit);
1586 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1587 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1588 MODULE_LICENSE("GPL");