drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "hw-ops.h"
  22 #include "rc.h"
  23 #include "ar5008_initvals.h"
  24 #include "ar9001_initvals.h"
  25 #include "ar9002_initvals.h"
  26 #include "ar9003_initvals.h"
  27
  28 #define ATH9K_CLOCK_RATE_CCK            22
  29 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  30 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  31
  32 static void ar9002_hw_attach_ops(struct ath_hw *ah);
  33 static void ar9003_hw_attach_ops(struct ath_hw *ah);
  34
  35 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  36
  37 MODULE_AUTHOR("Atheros Communications");
  38 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  39 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  40 MODULE_LICENSE("Dual BSD/GPL");
  41
  42 static int __init ath9k_init(void)
  43 {
  44         return 0;
  45 }
  46 module_init(ath9k_init);
  47
  48 static void __exit ath9k_exit(void)
  49 {
  50         return;
  51 }
  52 module_exit(ath9k_exit);
  53
  54 /* Private hardware callbacks */
  55
  56 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  57 {
  58         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  59 }
  60
  61 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  62 {
  63         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  64 }
  65
  66 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  67 {
  68         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  69
  70         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  71 }
  72
  73 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  74                                         struct ath9k_channel *chan)
  75 {
  76         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  77 }
  78
  79 /********************/
  80 /* Helper Functions */
  81 /********************/
  82
  83 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  84 {
  85         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  86
  87         if (!ah->curchan) /* should really check for CCK instead */
  88                 return usecs *ATH9K_CLOCK_RATE_CCK;
  89         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  90                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  91         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  92 }
  93
  94 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  95 {
  96         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  97
  98         if (conf_is_ht40(conf))
  99                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 100         else
 101                 return ath9k_hw_mac_clks(ah, usecs);
 102 }
 103
 104 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 105 {
 106         int i;
 107
 108         BUG_ON(timeout < AH_TIME_QUANTUM);
 109
 110         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 111                 if ((REG_READ(ah, reg) & mask) == val)
 112                         return true;
 113
 114                 udelay(AH_TIME_QUANTUM);
 115         }
 116
 117         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 118                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 119                   timeout, reg, REG_READ(ah, reg), mask, val);
 120
 121         return false;
 122 }
 123 EXPORT_SYMBOL(ath9k_hw_wait);
 124
 125 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 126 {
 127         u32 retval;
 128         int i;
 129
 130         for (i = 0, retval = 0; i < n; i++) {
 131                 retval = (retval << 1) | (val & 1);
 132                 val >>= 1;
 133         }
 134         return retval;
 135 }
 136
 137 bool ath9k_get_channel_edges(struct ath_hw *ah,
 138                              u16 flags, u16 *low,
 139                              u16 *high)
 140 {
 141         struct ath9k_hw_capabilities *pCap = &ah->caps;
 142
 143         if (flags & CHANNEL_5GHZ) {
 144                 *low = pCap->low_5ghz_chan;
 145                 *high = pCap->high_5ghz_chan;
 146                 return true;
 147         }
 148         if ((flags & CHANNEL_2GHZ)) {
 149                 *low = pCap->low_2ghz_chan;
 150                 *high = pCap->high_2ghz_chan;
 151                 return true;
 152         }
 153         return false;
 154 }
 155
 156 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 157                            u8 phy, int kbps,
 158                            u32 frameLen, u16 rateix,
 159                            bool shortPreamble)
 160 {
 161         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 162
 163         if (kbps == 0)
 164                 return 0;
 165
 166         switch (phy) {
 167         case WLAN_RC_PHY_CCK:
 168                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 169                 if (shortPreamble)
 170                         phyTime >>= 1;
 171                 numBits = frameLen << 3;
 172                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 173                 break;
 174         case WLAN_RC_PHY_OFDM:
 175                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 176                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 177                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 178                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 179                         txTime = OFDM_SIFS_TIME_QUARTER
 180                                 + OFDM_PREAMBLE_TIME_QUARTER
 181                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 182                 } else if (ah->curchan &&
 183                            IS_CHAN_HALF_RATE(ah->curchan)) {
 184                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 185                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 186                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 187                         txTime = OFDM_SIFS_TIME_HALF +
 188                                 OFDM_PREAMBLE_TIME_HALF
 189                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 190                 } else {
 191                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 192                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 193                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 194                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 195                                 + (numSymbols * OFDM_SYMBOL_TIME);
 196                 }
 197                 break;
 198         default:
 199                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 200                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 201                 txTime = 0;
 202                 break;
 203         }
 204
 205         return txTime;
 206 }
 207 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 208
 209 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 210                                   struct ath9k_channel *chan,
 211                                   struct chan_centers *centers)
 212 {
 213         int8_t extoff;
 214
 215         if (!IS_CHAN_HT40(chan)) {
 216                 centers->ctl_center = centers->ext_center =
 217                         centers->synth_center = chan->channel;
 218                 return;
 219         }
 220
 221         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 222             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 223                 centers->synth_center =
 224                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 225                 extoff = 1;
 226         } else {
 227                 centers->synth_center =
 228                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 229                 extoff = -1;
 230         }
 231
 232         centers->ctl_center =
 233                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 234         /* 25 MHz spacing is supported by hw but not on upper layers */
 235         centers->ext_center =
 236                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 237 }
 238
 239 /******************/
 240 /* Chip Revisions */
 241 /******************/
 242
 243 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 244 {
 245         u32 val;
 246
 247         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 248
 249         if (val == 0xFF) {
 250                 val = REG_READ(ah, AR_SREV);
 251                 ah->hw_version.macVersion =
 252                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 253                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 254                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 255         } else {
 256                 if (!AR_SREV_9100(ah))
 257                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 258
 259                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 260
 261                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 262                         ah->is_pciexpress = true;
 263         }
 264 }
 265
 266 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 267 {
 268         u32 val;
 269         int i;
 270
 271         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 272
 273         for (i = 0; i < 8; i++)
 274                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 275         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 276         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 277
 278         return ath9k_hw_reverse_bits(val, 8);
 279 }
 280
 281 /************************************/
 282 /* HW Attach, Detach, Init Routines */
 283 /************************************/
 284
 285 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 286 {
 287         if (AR_SREV_9100(ah))
 288                 return;
 289
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 294         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 295         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 296         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 297         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 298         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 299
 300         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 301 }
 302
 303 /* This should work for all families including legacy */
 304 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 305 {
 306         struct ath_common *common = ath9k_hw_common(ah);
 307         u32 regAddr[2] = { AR_STA_ID0 };
 308         u32 regHold[2];
 309         u32 patternData[4] = { 0x55555555,
 310                                0xaaaaaaaa,
 311                                0x66666666,
 312                                0x99999999 };
 313         int i, j, loop_max;
 314
 315         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 316                 loop_max = 2;
 317                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 318         } else
 319                 loop_max = 1;
 320
 321         for (i = 0; i < loop_max; i++) {
 322                 u32 addr = regAddr[i];
 323                 u32 wrData, rdData;
 324
 325                 regHold[i] = REG_READ(ah, addr);
 326                 for (j = 0; j < 0x100; j++) {
 327                         wrData = (j << 16) | j;
 328                         REG_WRITE(ah, addr, wrData);
 329                         rdData = REG_READ(ah, addr);
 330                         if (rdData != wrData) {
 331                                 ath_print(common, ATH_DBG_FATAL,
 332                                           "address test failed "
 333                                           "addr: 0x%08x - wr:0x%08x != "
 334                                           "rd:0x%08x\n",
 335                                           addr, wrData, rdData);
 336                                 return false;
 337                         }
 338                 }
 339                 for (j = 0; j < 4; j++) {
 340                         wrData = patternData[j];
 341                         REG_WRITE(ah, addr, wrData);
 342                         rdData = REG_READ(ah, addr);
 343                         if (wrData != rdData) {
 344                                 ath_print(common, ATH_DBG_FATAL,
 345                                           "address test failed "
 346                                           "addr: 0x%08x - wr:0x%08x != "
 347                                           "rd:0x%08x\n",
 348                                           addr, wrData, rdData);
 349                                 return false;
 350                         }
 351                 }
 352                 REG_WRITE(ah, regAddr[i], regHold[i]);
 353         }
 354         udelay(100);
 355
 356         return true;
 357 }
 358
 359 static void ath9k_hw_init_config(struct ath_hw *ah)
 360 {
 361         int i;
 362
 363         ah->config.dma_beacon_response_time = 2;
 364         ah->config.sw_beacon_response_time = 10;
 365         ah->config.additional_swba_backoff = 0;
 366         ah->config.ack_6mb = 0x0;
 367         ah->config.cwm_ignore_extcca = 0;
 368         ah->config.pcie_powersave_enable = 0;
 369         ah->config.pcie_clock_req = 0;
 370         ah->config.pcie_waen = 0;
 371         ah->config.analog_shiftreg = 1;
 372         ah->config.ofdm_trig_low = 200;
 373         ah->config.ofdm_trig_high = 500;
 374         ah->config.cck_trig_high = 200;
 375         ah->config.cck_trig_low = 100;
 376
 377         /*
 378          * For now ANI is disabled for AR9003, it is still
 379          * being tested.
 380          */
 381         if (!AR_SREV_9300_20_OR_LATER(ah))
 382                 ah->config.enable_ani = 1;
 383
 384         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 385                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 386                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 387         }
 388
 389         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 390                 ah->config.ht_enable = 1;
 391         else
 392                 ah->config.ht_enable = 0;
 393
 394         ah->config.rx_intr_mitigation = true;
 395
 396         /*
 397          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 398          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 399          * This means we use it for all AR5416 devices, and the few
 400          * minor PCI AR9280 devices out there.
 401          *
 402          * Serialization is required because these devices do not handle
 403          * well the case of two concurrent reads/writes due to the latency
 404          * involved. During one read/write another read/write can be issued
 405          * on another CPU while the previous read/write may still be working
 406          * on our hardware, if we hit this case the hardware poops in a loop.
 407          * We prevent this by serializing reads and writes.
 408          *
 409          * This issue is not present on PCI-Express devices or pre-AR5416
 410          * devices (legacy, 802.11abg).
 411          */
 412         if (num_possible_cpus() > 1)
 413                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 414 }
 415
 416 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 417 {
 418         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 419
 420         regulatory->country_code = CTRY_DEFAULT;
 421         regulatory->power_limit = MAX_RATE_POWER;
 422         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 423
 424         ah->hw_version.magic = AR5416_MAGIC;
 425         ah->hw_version.subvendorid = 0;
 426
 427         ah->ah_flags = 0;
 428         if (!AR_SREV_9100(ah))
 429                 ah->ah_flags = AH_USE_EEPROM;
 430
 431         ah->atim_window = 0;
 432         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 433         ah->beacon_interval = 100;
 434         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 435         ah->slottime = (u32) -1;
 436         ah->globaltxtimeout = (u32) -1;
 437         ah->power_mode = ATH9K_PM_UNDEFINED;
 438 }
 439
 440 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 441 {
 442         u32 val;
 443
 444         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 445
 446         val = ath9k_hw_get_radiorev(ah);
 447         switch (val & AR_RADIO_SREV_MAJOR) {
 448         case 0:
 449                 val = AR_RAD5133_SREV_MAJOR;
 450                 break;
 451         case AR_RAD5133_SREV_MAJOR:
 452         case AR_RAD5122_SREV_MAJOR:
 453         case AR_RAD2133_SREV_MAJOR:
 454         case AR_RAD2122_SREV_MAJOR:
 455                 break;
 456         default:
 457                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 458                           "Radio Chip Rev 0x%02X not supported\n",
 459                           val & AR_RADIO_SREV_MAJOR);
 460                 return -EOPNOTSUPP;
 461         }
 462
 463         ah->hw_version.analog5GhzRev = val;
 464
 465         return 0;
 466 }
 467
 468 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 469 {
 470         struct ath_common *common = ath9k_hw_common(ah);
 471         u32 sum;
 472         int i;
 473         u16 eeval;
 474
 475         sum = 0;
 476         for (i = 0; i < 3; i++) {
 477                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 478                 sum += eeval;
 479                 common->macaddr[2 * i] = eeval >> 8;
 480                 common->macaddr[2 * i + 1] = eeval & 0xff;
 481         }
 482         if (sum == 0 || sum == 0xffff * 3)
 483                 return -EADDRNOTAVAIL;
 484
 485         return 0;
 486 }
 487
 488 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 489 {
 490         u32 rxgain_type;
 491
 492         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 493                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 494
 495                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 496                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 497                         ar9280Modes_backoff_13db_rxgain_9280_2,
 498                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 499                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 500                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 501                         ar9280Modes_backoff_23db_rxgain_9280_2,
 502                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 503                 else
 504                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 505                         ar9280Modes_original_rxgain_9280_2,
 506                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 507         } else {
 508                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 509                         ar9280Modes_original_rxgain_9280_2,
 510                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 511         }
 512 }
 513
 514 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 515 {
 516         u32 txgain_type;
 517
 518         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 519                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 520
 521                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 522                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 523                         ar9280Modes_high_power_tx_gain_9280_2,
 524                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 525                 else
 526                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 527                         ar9280Modes_original_tx_gain_9280_2,
 528                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 529         } else {
 530                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 531                 ar9280Modes_original_tx_gain_9280_2,
 532                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 533         }
 534 }
 535
 536 static int ath9k_hw_post_init(struct ath_hw *ah)
 537 {
 538         int ecode;
 539
 540         if (!AR_SREV_9271(ah)) {
 541                 if (!ath9k_hw_chip_test(ah))
 542                         return -ENODEV;
 543         }
 544
 545         ecode = ath9k_hw_rf_claim(ah);
 546         if (ecode != 0)
 547                 return ecode;
 548
 549         ecode = ath9k_hw_eeprom_init(ah);
 550         if (ecode != 0)
 551                 return ecode;
 552
 553         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 554                   "Eeprom VER: %d, REV: %d\n",
 555                   ah->eep_ops->get_eeprom_ver(ah),
 556                   ah->eep_ops->get_eeprom_rev(ah));
 557
 558         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 559         if (ecode) {
 560                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 561                           "Failed allocating banks for "
 562                           "external radio\n");
 563                 return ecode;
 564         }
 565
 566         if (!AR_SREV_9100(ah)) {
 567                 ath9k_hw_ani_setup(ah);
 568                 ath9k_hw_ani_init(ah);
 569         }
 570
 571         return 0;
 572 }
 573
 574 static bool ar9002_hw_macversion_supported(u32 macversion)
 575 {
 576         switch (macversion) {
 577         case AR_SREV_VERSION_5416_PCI:
 578         case AR_SREV_VERSION_5416_PCIE:
 579         case AR_SREV_VERSION_9160:
 580         case AR_SREV_VERSION_9100:
 581         case AR_SREV_VERSION_9280:
 582         case AR_SREV_VERSION_9285:
 583         case AR_SREV_VERSION_9287:
 584         case AR_SREV_VERSION_9271:
 585                 return true;
 586         default:
 587                 break;
 588         }
 589         return false;
 590 }
 591
 592 static bool ar9003_hw_macversion_supported(u32 macversion)
 593 {
 594         switch (macversion) {
 595         case AR_SREV_VERSION_9300:
 596                 return true;
 597         default:
 598                 break;
 599         }
 600         return false;
 601 }
 602
 603 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
 604 {
 605         if (AR_SREV_9100(ah)) {
 606                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 607                 ah->supp_cals = IQ_MISMATCH_CAL;
 608                 return;
 609         }
 610
 611         if (AR_SREV_9160_10_OR_LATER(ah)) {
 612                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 613                         ah->iq_caldata.calData = &iq_cal_single_sample;
 614                         ah->adcgain_caldata.calData =
 615                                 &adc_gain_cal_single_sample;
 616                         ah->adcdc_caldata.calData =
 617                                 &adc_dc_cal_single_sample;
 618                         ah->adcdc_calinitdata.calData =
 619                                 &adc_init_dc_cal;
 620                 } else {
 621                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 622                         ah->adcgain_caldata.calData =
 623                                 &adc_gain_cal_multi_sample;
 624                         ah->adcdc_caldata.calData =
 625                                 &adc_dc_cal_multi_sample;
 626                         ah->adcdc_calinitdata.calData =
 627                                 &adc_init_dc_cal;
 628                 }
 629                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 630         }
 631 }
 632
 633 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
 634 {
 635         if (AR_SREV_9271(ah)) {
 636                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
 637                                ARRAY_SIZE(ar9271Modes_9271), 6);
 638                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
 639                                ARRAY_SIZE(ar9271Common_9271), 2);
 640                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
 641                                ar9271Common_normal_cck_fir_coeff_9271,
 642                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
 643                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
 644                                ar9271Common_japan_2484_cck_fir_coeff_9271,
 645                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
 646                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
 647                                ar9271Modes_9271_1_0_only,
 648                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
 649                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
 650                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
 651                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
 652                                ar9271Modes_high_power_tx_gain_9271,
 653                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
 654                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
 655                                ar9271Modes_normal_power_tx_gain_9271,
 656                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
 657                 return;
 658         }
 659
 660         if (AR_SREV_9287_11_OR_LATER(ah)) {
 661                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 662                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 663                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 664                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 665                 if (ah->config.pcie_clock_req)
 666                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 667                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 668                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 669                 else
 670                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 671                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 672                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 673                                         2);
 674         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 675                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 676                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 677                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 678                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 679
 680                 if (ah->config.pcie_clock_req)
 681                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 682                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 683                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 684                 else
 685                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 686                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 687                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 688                                   2);
 689         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 690
 691
 692                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 693                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 694                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 695                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 696
 697                 if (ah->config.pcie_clock_req) {
 698                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 699                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 700                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 701                 } else {
 702                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 703                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 704                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 705                                   2);
 706                 }
 707         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 708                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 709                                ARRAY_SIZE(ar9285Modes_9285), 6);
 710                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 711                                ARRAY_SIZE(ar9285Common_9285), 2);
 712
 713                 if (ah->config.pcie_clock_req) {
 714                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 715                         ar9285PciePhy_clkreq_off_L1_9285,
 716                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 717                 } else {
 718                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 719                         ar9285PciePhy_clkreq_always_on_L1_9285,
 720                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 721                 }
 722         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 723                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 724                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 725                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 726                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 727
 728                 if (ah->config.pcie_clock_req) {
 729                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 730                                ar9280PciePhy_clkreq_off_L1_9280,
 731                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 732                 } else {
 733                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 734                                ar9280PciePhy_clkreq_always_on_L1_9280,
 735                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 736                 }
 737                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 738                                ar9280Modes_fast_clock_9280_2,
 739                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 740         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 741                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 742                                ARRAY_SIZE(ar9280Modes_9280), 6);
 743                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 744                                ARRAY_SIZE(ar9280Common_9280), 2);
 745         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 746                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 747                                ARRAY_SIZE(ar5416Modes_9160), 6);
 748                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 749                                ARRAY_SIZE(ar5416Common_9160), 2);
 750                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 751                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 752                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 753                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 754                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 755                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 756                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 757                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 758                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 759                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 760                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 761                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 762                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 763                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 764                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 765                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 766                 if (AR_SREV_9160_11(ah)) {
 767                         INIT_INI_ARRAY(&ah->iniAddac,
 768                                        ar5416Addac_91601_1,
 769                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 770                 } else {
 771                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 772                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 773                 }
 774         } else if (AR_SREV_9100_OR_LATER(ah)) {
 775                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 776                                ARRAY_SIZE(ar5416Modes_9100), 6);
 777                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 778                                ARRAY_SIZE(ar5416Common_9100), 2);
 779                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 780                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 781                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 782                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 783                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 784                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 785                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 786                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 787                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 788                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 789                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 790                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 791                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 792                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 793                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 794                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 795                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 796                                ARRAY_SIZE(ar5416Addac_9100), 2);
 797         } else {
 798                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 799                                ARRAY_SIZE(ar5416Modes), 6);
 800                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 801                                ARRAY_SIZE(ar5416Common), 2);
 802                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 803                                ARRAY_SIZE(ar5416Bank0), 2);
 804                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 805                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 806                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 807                                ARRAY_SIZE(ar5416Bank1), 2);
 808                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 809                                ARRAY_SIZE(ar5416Bank2), 2);
 810                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 811                                ARRAY_SIZE(ar5416Bank3), 3);
 812                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 813                                ARRAY_SIZE(ar5416Bank6), 3);
 814                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 815                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 816                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 817                                ARRAY_SIZE(ar5416Bank7), 2);
 818                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 819                                ARRAY_SIZE(ar5416Addac), 2);
 820         }
 821 }
 822
 823 /* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
 824 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 825 {
 826         /* mac */
 827         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 828         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 829                        ar9300_2p0_mac_core,
 830                        ARRAY_SIZE(ar9300_2p0_mac_core), 2);
 831         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 832                        ar9300_2p0_mac_postamble,
 833                        ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
 834
 835         /* bb */
 836         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 837         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 838                        ar9300_2p0_baseband_core,
 839                        ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
 840         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 841                        ar9300_2p0_baseband_postamble,
 842                        ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
 843
 844         /* radio */
 845         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 846         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 847                        ar9300_2p0_radio_core,
 848                        ARRAY_SIZE(ar9300_2p0_radio_core), 2);
 849         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 850                        ar9300_2p0_radio_postamble,
 851                        ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
 852
 853         /* soc */
 854         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 855                        ar9300_2p0_soc_preamble,
 856                        ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
 857         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 858         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 859                        ar9300_2p0_soc_postamble,
 860                        ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
 861
 862         /* rx/tx gain */
 863         INIT_INI_ARRAY(&ah->iniModesRxGain,
 864                        ar9300Common_rx_gain_table_2p0,
 865                        ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
 866         INIT_INI_ARRAY(&ah->iniModesTxGain,
 867                        ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
 868                        ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
 869                        5);
 870
 871         /* Load PCIE SERDES settings from INI */
 872
 873         /* Awake Setting */
 874
 875         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 876                        ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
 877                        ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
 878                        2);
 879
 880         /* Sleep Setting */
 881
 882         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 883                        ar9300PciePhy_clkreq_enable_L1_2p0,
 884                        ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
 885                        2);
 886
 887         /* Fast clock modal settings */
 888         INIT_INI_ARRAY(&ah->iniModesAdditional,
 889                        ar9300Modes_fast_clock_2p0,
 890                        ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
 891                        3);
 892 }
 893
 894 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 895 {
 896         if (AR_SREV_9287_11_OR_LATER(ah))
 897                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 898                 ar9287Modes_rx_gain_9287_1_1,
 899                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 900         else if (AR_SREV_9287_10(ah))
 901                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 902                 ar9287Modes_rx_gain_9287_1_0,
 903                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 904         else if (AR_SREV_9280_20(ah))
 905                 ath9k_hw_init_rxgain_ini(ah);
 906
 907         if (AR_SREV_9287_11_OR_LATER(ah)) {
 908                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 909                 ar9287Modes_tx_gain_9287_1_1,
 910                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 911         } else if (AR_SREV_9287_10(ah)) {
 912                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 913                 ar9287Modes_tx_gain_9287_1_0,
 914                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 915         } else if (AR_SREV_9280_20(ah)) {
 916                 ath9k_hw_init_txgain_ini(ah);
 917         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 918                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 919
 920                 /* txgain table */
 921                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 922                         if (AR_SREV_9285E_20(ah)) {
 923                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 924                                 ar9285Modes_XE2_0_high_power,
 925                                 ARRAY_SIZE(
 926                                   ar9285Modes_XE2_0_high_power), 6);
 927                         } else {
 928                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 929                                 ar9285Modes_high_power_tx_gain_9285_1_2,
 930                                 ARRAY_SIZE(
 931                                   ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 932                         }
 933                 } else {
 934                         if (AR_SREV_9285E_20(ah)) {
 935                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 936                                 ar9285Modes_XE2_0_normal_power,
 937                                 ARRAY_SIZE(
 938                                   ar9285Modes_XE2_0_normal_power), 6);
 939                         } else {
 940                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 941                                 ar9285Modes_original_tx_gain_9285_1_2,
 942                                 ARRAY_SIZE(
 943                                   ar9285Modes_original_tx_gain_9285_1_2), 6);
 944                         }
 945                 }
 946         }
 947 }
 948
 949 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
 950 {
 951         struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
 952         struct ath_common *common = ath9k_hw_common(ah);
 953
 954         ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
 955                                  !AR_SREV_9285(ah) && !AR_SREV_9271(ah) &&
 956                                  ((pBase->version & 0xff) > 0x0a) &&
 957                                  (pBase->pwdclkind == 0);
 958
 959         if (ah->need_an_top2_fixup)
 960                 ath_print(common, ATH_DBG_EEPROM,
 961                           "needs fixup for AR_AN_TOP2 register\n");
 962 }
 963
 964 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 965 {
 966         if (AR_SREV_9300_20_OR_LATER(ah))
 967                 ar9003_hw_attach_ops(ah);
 968         else
 969                 ar9002_hw_attach_ops(ah);
 970 }
 971
 972 /* Called for all hardware families */
 973 static int __ath9k_hw_init(struct ath_hw *ah)
 974 {
 975         struct ath_common *common = ath9k_hw_common(ah);
 976         int r = 0;
 977
 978         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 979                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 980
 981         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 982                 ath_print(common, ATH_DBG_FATAL,
 983                           "Couldn't reset chip\n");
 984                 return -EIO;
 985         }
 986
 987         ath9k_hw_init_defaults(ah);
 988         ath9k_hw_init_config(ah);
 989
 990         ath9k_hw_attach_ops(ah);
 991
 992         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 993                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 994                 return -EIO;
 995         }
 996
 997         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 998                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 999                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
1000                         ah->config.serialize_regmode =
1001                                 SER_REG_MODE_ON;
1002                 } else {
1003                         ah->config.serialize_regmode =
1004                                 SER_REG_MODE_OFF;
1005                 }
1006         }
1007
1008         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
1009                 ah->config.serialize_regmode);
1010
1011         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1012                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
1013         else
1014                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
1015
1016         if (!ath9k_hw_macversion_supported(ah)) {
1017                 ath_print(common, ATH_DBG_FATAL,
1018                           "Mac Chip Rev 0x%02x.%x is not supported by "
1019                           "this driver\n", ah->hw_version.macVersion,
1020                           ah->hw_version.macRev);
1021                 return -EOPNOTSUPP;
1022         }
1023
1024         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
1025                 ah->is_pciexpress = false;
1026
1027         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
1028         ath9k_hw_init_cal_settings(ah);
1029
1030         ah->ani_function = ATH9K_ANI_ALL;
1031         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1032                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
1033
1034         ath9k_hw_init_mode_regs(ah);
1035
1036         if (ah->is_pciexpress)
1037                 ath9k_hw_configpcipowersave(ah, 0, 0);
1038         else
1039                 ath9k_hw_disablepcie(ah);
1040
1041         /* Support for Japan ch.14 (2484) spread */
1042         if (AR_SREV_9287_11_OR_LATER(ah)) {
1043                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
1044                        ar9287Common_normal_cck_fir_coeff_92871_1,
1045                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
1046                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
1047                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
1048                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
1049         }
1050
1051         r = ath9k_hw_post_init(ah);
1052         if (r)
1053                 return r;
1054
1055         ath9k_hw_init_mode_gain_regs(ah);
1056         r = ath9k_hw_fill_cap_info(ah);
1057         if (r)
1058                 return r;
1059
1060         ath9k_hw_init_eeprom_fix(ah);
1061
1062         r = ath9k_hw_init_macaddr(ah);
1063         if (r) {
1064                 ath_print(common, ATH_DBG_FATAL,
1065                           "Failed to initialize MAC address\n");
1066                 return r;
1067         }
1068
1069         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1070                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
1071         else
1072                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
1073
1074         if (AR_SREV_9300_20_OR_LATER(ah))
1075                 ar9003_hw_set_nf_limits(ah);
1076
1077         ath9k_init_nfcal_hist_buffer(ah);
1078
1079         common->state = ATH_HW_INITIALIZED;
1080
1081         return 0;
1082 }
1083
1084 int ath9k_hw_init(struct ath_hw *ah)
1085 {
1086         int ret;
1087         struct ath_common *common = ath9k_hw_common(ah);
1088
1089         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
1090         switch (ah->hw_version.devid) {
1091         case AR5416_DEVID_PCI:
1092         case AR5416_DEVID_PCIE:
1093         case AR5416_AR9100_DEVID:
1094         case AR9160_DEVID_PCI:
1095         case AR9280_DEVID_PCI:
1096         case AR9280_DEVID_PCIE:
1097         case AR9285_DEVID_PCIE:
1098         case AR9287_DEVID_PCI:
1099         case AR9287_DEVID_PCIE:
1100         case AR2427_DEVID_PCIE:
1101         case AR9300_DEVID_PCIE:
1102                 break;
1103         default:
1104                 if (common->bus_ops->ath_bus_type == ATH_USB)
1105                         break;
1106                 ath_print(common, ATH_DBG_FATAL,
1107                           "Hardware device ID 0x%04x not supported\n",
1108                           ah->hw_version.devid);
1109                 return -EOPNOTSUPP;
1110         }
1111
1112         ret = __ath9k_hw_init(ah);
1113         if (ret) {
1114                 ath_print(common, ATH_DBG_FATAL,
1115                           "Unable to initialize hardware; "
1116                           "initialization status: %d\n", ret);
1117                 return ret;
1118         }
1119
1120         return 0;
1121 }
1122 EXPORT_SYMBOL(ath9k_hw_init);
1123
1124 static void ath9k_hw_init_qos(struct ath_hw *ah)
1125 {
1126         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1127         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1128
1129         REG_WRITE(ah, AR_QOS_NO_ACK,
1130                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1131                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1132                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1133
1134         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1135         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1136         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1137         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1138         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1139 }
1140
1141 static void ath9k_hw_init_pll(struct ath_hw *ah,
1142                               struct ath9k_channel *chan)
1143 {
1144         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
1145
1146         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1147
1148         /* Switch the core clock for ar9271 to 117Mhz */
1149         if (AR_SREV_9271(ah)) {
1150                 udelay(500);
1151                 REG_WRITE(ah, 0x50040, 0x304);
1152         }
1153
1154         udelay(RTC_PLL_SETTLE_DELAY);
1155
1156         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1157 }
1158
1159 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1160                                           enum nl80211_iftype opmode)
1161 {
1162         u32 imr_reg = AR_IMR_TXERR |
1163                 AR_IMR_TXURN |
1164                 AR_IMR_RXERR |
1165                 AR_IMR_RXORN |
1166                 AR_IMR_BCNMISC;
1167
1168         if (ah->config.rx_intr_mitigation)
1169                 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1170         else
1171                 imr_reg |= AR_IMR_RXOK;
1172
1173         imr_reg |= AR_IMR_TXOK;
1174
1175         if (opmode == NL80211_IFTYPE_AP)
1176                 imr_reg |= AR_IMR_MIB;
1177
1178         REG_WRITE(ah, AR_IMR, imr_reg);
1179         ah->imrs2_reg |= AR_IMR_S2_GTT;
1180         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1181
1182         if (!AR_SREV_9100(ah)) {
1183                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1184                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1185                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1186         }
1187 }
1188
1189 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1190 {
1191         u32 val = ath9k_hw_mac_to_clks(ah, us);
1192         val = min(val, (u32) 0xFFFF);
1193         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1194 }
1195
1196 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1197 {
1198         u32 val = ath9k_hw_mac_to_clks(ah, us);
1199         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1200         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1201 }
1202
1203 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1204 {
1205         u32 val = ath9k_hw_mac_to_clks(ah, us);
1206         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1207         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1208 }
1209
1210 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1211 {
1212         if (tu > 0xFFFF) {
1213                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1214                           "bad global tx timeout %u\n", tu);
1215                 ah->globaltxtimeout = (u32) -1;
1216                 return false;
1217         } else {
1218                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1219                 ah->globaltxtimeout = tu;
1220                 return true;
1221         }
1222 }
1223
1224 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1225 {
1226         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1227         int acktimeout;
1228         int slottime;
1229         int sifstime;
1230
1231         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1232                   ah->misc_mode);
1233
1234         if (ah->misc_mode != 0)
1235                 REG_WRITE(ah, AR_PCU_MISC,
1236                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1237
1238         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1239                 sifstime = 16;
1240         else
1241                 sifstime = 10;
1242
1243         /* As defined by IEEE 802.11-2007 17.3.8.6 */
1244         slottime = ah->slottime + 3 * ah->coverage_class;
1245         acktimeout = slottime + sifstime;
1246
1247         /*
1248          * Workaround for early ACK timeouts, add an offset to match the
1249          * initval's 64us ack timeout value.
1250          * This was initially only meant to work around an issue with delayed
1251          * BA frames in some implementations, but it has been found to fix ACK
1252          * timeout issues in other cases as well.
1253          */
1254         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1255                 acktimeout += 64 - sifstime - ah->slottime;
1256
1257         ath9k_hw_setslottime(ah, slottime);
1258         ath9k_hw_set_ack_timeout(ah, acktimeout);
1259         ath9k_hw_set_cts_timeout(ah, acktimeout);
1260         if (ah->globaltxtimeout != (u32) -1)
1261                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1262 }
1263 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1264
1265 void ath9k_hw_deinit(struct ath_hw *ah)
1266 {
1267         struct ath_common *common = ath9k_hw_common(ah);
1268
1269         if (common->state < ATH_HW_INITIALIZED)
1270                 goto free_hw;
1271
1272         if (!AR_SREV_9100(ah))
1273                 ath9k_hw_ani_disable(ah);
1274
1275         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1276
1277 free_hw:
1278         ath9k_hw_rf_free_ext_banks(ah);
1279 }
1280 EXPORT_SYMBOL(ath9k_hw_deinit);
1281
1282 /*******/
1283 /* INI */
1284 /*******/
1285
1286 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1287 {
1288         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1289
1290         if (IS_CHAN_B(chan))
1291                 ctl |= CTL_11B;
1292         else if (IS_CHAN_G(chan))
1293                 ctl |= CTL_11G;
1294         else
1295                 ctl |= CTL_11A;
1296
1297         return ctl;
1298 }
1299
1300 /****************************************/
1301 /* Reset and Channel Switching Routines */
1302 /****************************************/
1303
1304 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1305 {
1306         u32 regval;
1307
1308         /*
1309          * set AHB_MODE not to do cacheline prefetches
1310         */
1311         regval = REG_READ(ah, AR_AHB_MODE);
1312         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1313
1314         /*
1315          * let mac dma reads be in 128 byte chunks
1316          */
1317         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1318         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1319
1320         /*
1321          * Restore TX Trigger Level to its pre-reset value.
1322          * The initial value depends on whether aggregation is enabled, and is
1323          * adjusted whenever underruns are detected.
1324          */
1325         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1326
1327         /*
1328          * let mac dma writes be in 128 byte chunks
1329          */
1330         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1331         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1332
1333         /*
1334          * Setup receive FIFO threshold to hold off TX activities
1335          */
1336         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1337
1338         /*
1339          * reduce the number of usable entries in PCU TXBUF to avoid
1340          * wrap around issues.
1341          */
1342         if (AR_SREV_9285(ah)) {
1343                 /* For AR9285 the number of Fifos are reduced to half.
1344                  * So set the usable tx buf size also to half to
1345                  * avoid data/delimiter underruns
1346                  */
1347                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1348                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1349         } else if (!AR_SREV_9271(ah)) {
1350                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1351                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1352         }
1353 }
1354
1355 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1356 {
1357         u32 val;
1358
1359         val = REG_READ(ah, AR_STA_ID1);
1360         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1361         switch (opmode) {
1362         case NL80211_IFTYPE_AP:
1363                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1364                           | AR_STA_ID1_KSRCH_MODE);
1365                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1366                 break;
1367         case NL80211_IFTYPE_ADHOC:
1368         case NL80211_IFTYPE_MESH_POINT:
1369                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1370                           | AR_STA_ID1_KSRCH_MODE);
1371                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1372                 break;
1373         case NL80211_IFTYPE_STATION:
1374         case NL80211_IFTYPE_MONITOR:
1375                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1376                 break;
1377         }
1378 }
1379
1380 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1381                                    u32 *coef_mantissa, u32 *coef_exponent)
1382 {
1383         u32 coef_exp, coef_man;
1384
1385         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1386                 if ((coef_scaled >> coef_exp) & 0x1)
1387                         break;
1388
1389         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1390
1391         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1392
1393         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1394         *coef_exponent = coef_exp - 16;
1395 }
1396
1397 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1398 {
1399         u32 rst_flags;
1400         u32 tmpReg;
1401
1402         if (AR_SREV_9100(ah)) {
1403                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1404                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1405                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1406                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1407                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1408         }
1409
1410         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1411                   AR_RTC_FORCE_WAKE_ON_INT);
1412
1413         if (AR_SREV_9100(ah)) {
1414                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1415                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1416         } else {
1417                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1418                 if (tmpReg &
1419                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1420                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1421                         u32 val;
1422                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1423
1424                         val = AR_RC_HOSTIF;
1425                         if (!AR_SREV_9300_20_OR_LATER(ah))
1426                                 val |= AR_RC_AHB;
1427                         REG_WRITE(ah, AR_RC, val);
1428
1429                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1430                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1431
1432                 rst_flags = AR_RTC_RC_MAC_WARM;
1433                 if (type == ATH9K_RESET_COLD)
1434                         rst_flags |= AR_RTC_RC_MAC_COLD;
1435         }
1436
1437         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1438         udelay(50);
1439
1440         REG_WRITE(ah, AR_RTC_RC, 0);
1441         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1442                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1443                           "RTC stuck in MAC reset\n");
1444                 return false;
1445         }
1446
1447         if (!AR_SREV_9100(ah))
1448                 REG_WRITE(ah, AR_RC, 0);
1449
1450         if (AR_SREV_9100(ah))
1451                 udelay(50);
1452
1453         return true;
1454 }
1455
1456 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1457 {
1458         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1459                   AR_RTC_FORCE_WAKE_ON_INT);
1460
1461         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1462                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1463
1464         REG_WRITE(ah, AR_RTC_RESET, 0);
1465
1466         if (!AR_SREV_9300_20_OR_LATER(ah))
1467                 udelay(2);
1468
1469         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1470                 REG_WRITE(ah, AR_RC, 0);
1471
1472         REG_WRITE(ah, AR_RTC_RESET, 1);
1473
1474         if (!ath9k_hw_wait(ah,
1475                            AR_RTC_STATUS,
1476                            AR_RTC_STATUS_M,
1477                            AR_RTC_STATUS_ON,
1478                            AH_WAIT_TIMEOUT)) {
1479                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1480                           "RTC not waking up\n");
1481                 return false;
1482         }
1483
1484         ath9k_hw_read_revisions(ah);
1485
1486         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1487 }
1488
1489 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1490 {
1491         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1492                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1493
1494         switch (type) {
1495         case ATH9K_RESET_POWER_ON:
1496                 return ath9k_hw_set_reset_power_on(ah);
1497         case ATH9K_RESET_WARM:
1498         case ATH9K_RESET_COLD:
1499                 return ath9k_hw_set_reset(ah, type);
1500         default:
1501                 return false;
1502         }
1503 }
1504
1505 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1506                                 struct ath9k_channel *chan)
1507 {
1508         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1509                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1510                         return false;
1511         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1512                 return false;
1513
1514         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1515                 return false;
1516
1517         ah->chip_fullsleep = false;
1518         ath9k_hw_init_pll(ah, chan);
1519         ath9k_hw_set_rfmode(ah, chan);
1520
1521         return true;
1522 }
1523
1524 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1525                                     struct ath9k_channel *chan)
1526 {
1527         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1528         struct ath_common *common = ath9k_hw_common(ah);
1529         struct ieee80211_channel *channel = chan->chan;
1530         u32 qnum;
1531         int r;
1532
1533         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1534                 if (ath9k_hw_numtxpending(ah, qnum)) {
1535                         ath_print(common, ATH_DBG_QUEUE,
1536                                   "Transmit frames pending on "
1537                                   "queue %d\n", qnum);
1538                         return false;
1539                 }
1540         }
1541
1542         if (!ath9k_hw_rfbus_req(ah)) {
1543                 ath_print(common, ATH_DBG_FATAL,
1544                           "Could not kill baseband RX\n");
1545                 return false;
1546         }
1547
1548         ath9k_hw_set_channel_regs(ah, chan);
1549
1550         r = ath9k_hw_rf_set_freq(ah, chan);
1551         if (r) {
1552                 ath_print(common, ATH_DBG_FATAL,
1553                           "Failed to set channel\n");
1554                 return false;
1555         }
1556
1557         ah->eep_ops->set_txpower(ah, chan,
1558                              ath9k_regd_get_ctl(regulatory, chan),
1559                              channel->max_antenna_gain * 2,
1560                              channel->max_power * 2,
1561                              min((u32) MAX_RATE_POWER,
1562                              (u32) regulatory->power_limit));
1563
1564         ath9k_hw_rfbus_done(ah);
1565
1566         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1567                 ath9k_hw_set_delta_slope(ah, chan);
1568
1569         ath9k_hw_spur_mitigate_freq(ah, chan);
1570
1571         if (!chan->oneTimeCalsDone)
1572                 chan->oneTimeCalsDone = true;
1573
1574         return true;
1575 }
1576
1577 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1578                     bool bChannelChange)
1579 {
1580         struct ath_common *common = ath9k_hw_common(ah);
1581         u32 saveLedState;
1582         struct ath9k_channel *curchan = ah->curchan;
1583         u32 saveDefAntenna;
1584         u32 macStaId1;
1585         u64 tsf = 0;
1586         int i, r;
1587
1588         ah->txchainmask = common->tx_chainmask;
1589         ah->rxchainmask = common->rx_chainmask;
1590
1591         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1592                 return -EIO;
1593
1594         if (curchan && !ah->chip_fullsleep)
1595                 ath9k_hw_getnf(ah, curchan);
1596
1597         if (bChannelChange &&
1598             (ah->chip_fullsleep != true) &&
1599             (ah->curchan != NULL) &&
1600             (chan->channel != ah->curchan->channel) &&
1601             ((chan->channelFlags & CHANNEL_ALL) ==
1602              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1603              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1604              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1605
1606                 if (ath9k_hw_channel_change(ah, chan)) {
1607                         ath9k_hw_loadnf(ah, ah->curchan);
1608                         ath9k_hw_start_nfcal(ah);
1609                         return 0;
1610                 }
1611         }
1612
1613         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1614         if (saveDefAntenna == 0)
1615                 saveDefAntenna = 1;
1616
1617         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1618
1619         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1620         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1621                 tsf = ath9k_hw_gettsf64(ah);
1622
1623         saveLedState = REG_READ(ah, AR_CFG_LED) &
1624                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1625                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1626
1627         ath9k_hw_mark_phy_inactive(ah);
1628
1629         /* Only required on the first reset */
1630         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1631                 REG_WRITE(ah,
1632                           AR9271_RESET_POWER_DOWN_CONTROL,
1633                           AR9271_RADIO_RF_RST);
1634                 udelay(50);
1635         }
1636
1637         if (!ath9k_hw_chip_reset(ah, chan)) {
1638                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1639                 return -EINVAL;
1640         }
1641
1642         /* Only required on the first reset */
1643         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1644                 ah->htc_reset_init = false;
1645                 REG_WRITE(ah,
1646                           AR9271_RESET_POWER_DOWN_CONTROL,
1647                           AR9271_GATE_MAC_CTL);
1648                 udelay(50);
1649         }
1650
1651         /* Restore TSF */
1652         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1653                 ath9k_hw_settsf64(ah, tsf);
1654
1655         if (AR_SREV_9280_10_OR_LATER(ah))
1656                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1657
1658         r = ath9k_hw_process_ini(ah, chan);
1659         if (r)
1660                 return r;
1661
1662         /* Setup MFP options for CCMP */
1663         if (AR_SREV_9280_20_OR_LATER(ah)) {
1664                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1665                  * frames when constructing CCMP AAD. */
1666                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1667                               0xc7ff);
1668                 ah->sw_mgmt_crypto = false;
1669         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1670                 /* Disable hardware crypto for management frames */
1671                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1672                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1673                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1674                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1675                 ah->sw_mgmt_crypto = true;
1676         } else
1677                 ah->sw_mgmt_crypto = true;
1678
1679         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1680                 ath9k_hw_set_delta_slope(ah, chan);
1681
1682         ath9k_hw_spur_mitigate_freq(ah, chan);
1683         ah->eep_ops->set_board_values(ah, chan);
1684
1685         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1686         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1687                   | macStaId1
1688                   | AR_STA_ID1_RTS_USE_DEF
1689                   | (ah->config.
1690                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1691                   | ah->sta_id1_defaults);
1692         ath9k_hw_set_operating_mode(ah, ah->opmode);
1693
1694         ath_hw_setbssidmask(common);
1695
1696         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1697
1698         ath9k_hw_write_associd(ah);
1699
1700         REG_WRITE(ah, AR_ISR, ~0);
1701
1702         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1703
1704         r = ath9k_hw_rf_set_freq(ah, chan);
1705         if (r)
1706                 return r;
1707
1708         for (i = 0; i < AR_NUM_DCU; i++)
1709                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1710
1711         ah->intr_txqs = 0;
1712         for (i = 0; i < ah->caps.total_queues; i++)
1713                 ath9k_hw_resettxqueue(ah, i);
1714
1715         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1716         ath9k_hw_init_qos(ah);
1717
1718         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1719                 ath9k_enable_rfkill(ah);
1720
1721         ath9k_hw_init_global_settings(ah);
1722
1723         if (AR_SREV_9287_12_OR_LATER(ah)) {
1724                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1725                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1726                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1727                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1728                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1729                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1730
1731                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1732                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1733
1734                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1735                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1736                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1737                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1738         }
1739         if (AR_SREV_9287_12_OR_LATER(ah)) {
1740                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1741                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1742         }
1743
1744         REG_WRITE(ah, AR_STA_ID1,
1745                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1746
1747         ath9k_hw_set_dma(ah);
1748
1749         REG_WRITE(ah, AR_OBS, 8);
1750
1751         if (ah->config.rx_intr_mitigation) {
1752                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1753                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1754         }
1755
1756         ath9k_hw_init_bb(ah, chan);
1757
1758         if (!ath9k_hw_init_cal(ah, chan))
1759                 return -EIO;
1760
1761         ath9k_hw_restore_chainmask(ah);
1762         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1763
1764         /*
1765          * For big endian systems turn on swapping for descriptors
1766          */
1767         if (AR_SREV_9100(ah)) {
1768                 u32 mask;
1769                 mask = REG_READ(ah, AR_CFG);
1770                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1771                         ath_print(common, ATH_DBG_RESET,
1772                                 "CFG Byte Swap Set 0x%x\n", mask);
1773                 } else {
1774                         mask =
1775                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1776                         REG_WRITE(ah, AR_CFG, mask);
1777                         ath_print(common, ATH_DBG_RESET,
1778                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1779                 }
1780         } else {
1781                 /* Configure AR9271 target WLAN */
1782                 if (AR_SREV_9271(ah))
1783                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1784 #ifdef __BIG_ENDIAN
1785                 else
1786                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1787 #endif
1788         }
1789
1790         if (ah->btcoex_hw.enabled)
1791                 ath9k_hw_btcoex_enable(ah);
1792
1793         return 0;
1794 }
1795 EXPORT_SYMBOL(ath9k_hw_reset);
1796
1797 /************************/
1798 /* Key Cache Management */
1799 /************************/
1800
1801 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1802 {
1803         u32 keyType;
1804
1805         if (entry >= ah->caps.keycache_size) {
1806                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1807                           "keychache entry %u out of range\n", entry);
1808                 return false;
1809         }
1810
1811         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1812
1813         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1814         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1815         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1816         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1817         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1818         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1819         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1820         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1821
1822         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1823                 u16 micentry = entry + 64;
1824
1825                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1826                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1827                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1828                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1829
1830         }
1831
1832         return true;
1833 }
1834 EXPORT_SYMBOL(ath9k_hw_keyreset);
1835
1836 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1837 {
1838         u32 macHi, macLo;
1839
1840         if (entry >= ah->caps.keycache_size) {
1841                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1842                           "keychache entry %u out of range\n", entry);
1843                 return false;
1844         }
1845
1846         if (mac != NULL) {
1847                 macHi = (mac[5] << 8) | mac[4];
1848                 macLo = (mac[3] << 24) |
1849                         (mac[2] << 16) |
1850                         (mac[1] << 8) |
1851                         mac[0];
1852                 macLo >>= 1;
1853                 macLo |= (macHi & 1) << 31;
1854                 macHi >>= 1;
1855         } else {
1856                 macLo = macHi = 0;
1857         }
1858         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1859         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1860
1861         return true;
1862 }
1863 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1864
1865 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1866                                  const struct ath9k_keyval *k,
1867                                  const u8 *mac)
1868 {
1869         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1870         struct ath_common *common = ath9k_hw_common(ah);
1871         u32 key0, key1, key2, key3, key4;
1872         u32 keyType;
1873
1874         if (entry >= pCap->keycache_size) {
1875                 ath_print(common, ATH_DBG_FATAL,
1876                           "keycache entry %u out of range\n", entry);
1877                 return false;
1878         }
1879
1880         switch (k->kv_type) {
1881         case ATH9K_CIPHER_AES_OCB:
1882                 keyType = AR_KEYTABLE_TYPE_AES;
1883                 break;
1884         case ATH9K_CIPHER_AES_CCM:
1885                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1886                         ath_print(common, ATH_DBG_ANY,
1887                                   "AES-CCM not supported by mac rev 0x%x\n",
1888                                   ah->hw_version.macRev);
1889                         return false;
1890                 }
1891                 keyType = AR_KEYTABLE_TYPE_CCM;
1892                 break;
1893         case ATH9K_CIPHER_TKIP:
1894                 keyType = AR_KEYTABLE_TYPE_TKIP;
1895                 if (ATH9K_IS_MIC_ENABLED(ah)
1896                     && entry + 64 >= pCap->keycache_size) {
1897                         ath_print(common, ATH_DBG_ANY,
1898                                   "entry %u inappropriate for TKIP\n", entry);
1899                         return false;
1900                 }
1901                 break;
1902         case ATH9K_CIPHER_WEP:
1903                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1904                         ath_print(common, ATH_DBG_ANY,
1905                                   "WEP key length %u too small\n", k->kv_len);
1906                         return false;
1907                 }
1908                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1909                         keyType = AR_KEYTABLE_TYPE_40;
1910                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1911                         keyType = AR_KEYTABLE_TYPE_104;
1912                 else
1913                         keyType = AR_KEYTABLE_TYPE_128;
1914                 break;
1915         case ATH9K_CIPHER_CLR:
1916                 keyType = AR_KEYTABLE_TYPE_CLR;
1917                 break;
1918         default:
1919                 ath_print(common, ATH_DBG_FATAL,
1920                           "cipher %u not supported\n", k->kv_type);
1921                 return false;
1922         }
1923
1924         key0 = get_unaligned_le32(k->kv_val + 0);
1925         key1 = get_unaligned_le16(k->kv_val + 4);
1926         key2 = get_unaligned_le32(k->kv_val + 6);
1927         key3 = get_unaligned_le16(k->kv_val + 10);
1928         key4 = get_unaligned_le32(k->kv_val + 12);
1929         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1930                 key4 &= 0xff;
1931
1932         /*
1933          * Note: Key cache registers access special memory area that requires
1934          * two 32-bit writes to actually update the values in the internal
1935          * memory. Consequently, the exact order and pairs used here must be
1936          * maintained.
1937          */
1938
1939         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1940                 u16 micentry = entry + 64;
1941
1942                 /*
1943                  * Write inverted key[47:0] first to avoid Michael MIC errors
1944                  * on frames that could be sent or received at the same time.
1945                  * The correct key will be written in the end once everything
1946                  * else is ready.
1947                  */
1948                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1949                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1950
1951                 /* Write key[95:48] */
1952                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1953                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1954
1955                 /* Write key[127:96] and key type */
1956                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1957                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1958
1959                 /* Write MAC address for the entry */
1960                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1961
1962                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1963                         /*
1964                          * TKIP uses two key cache entries:
1965                          * Michael MIC TX/RX keys in the same key cache entry
1966                          * (idx = main index + 64):
1967                          * key0 [31:0] = RX key [31:0]
1968                          * key1 [15:0] = TX key [31:16]
1969                          * key1 [31:16] = reserved
1970                          * key2 [31:0] = RX key [63:32]
1971                          * key3 [15:0] = TX key [15:0]
1972                          * key3 [31:16] = reserved
1973                          * key4 [31:0] = TX key [63:32]
1974                          */
1975                         u32 mic0, mic1, mic2, mic3, mic4;
1976
1977                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1978                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1979                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1980                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1981                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1982
1983                         /* Write RX[31:0] and TX[31:16] */
1984                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1985                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1986
1987                         /* Write RX[63:32] and TX[15:0] */
1988                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1989                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1990
1991                         /* Write TX[63:32] and keyType(reserved) */
1992                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1993                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1994                                   AR_KEYTABLE_TYPE_CLR);
1995
1996                 } else {
1997                         /*
1998                          * TKIP uses four key cache entries (two for group
1999                          * keys):
2000                          * Michael MIC TX/RX keys are in different key cache
2001                          * entries (idx = main index + 64 for TX and
2002                          * main index + 32 + 96 for RX):
2003                          * key0 [31:0] = TX/RX MIC key [31:0]
2004                          * key1 [31:0] = reserved
2005                          * key2 [31:0] = TX/RX MIC key [63:32]
2006                          * key3 [31:0] = reserved
2007                          * key4 [31:0] = reserved
2008                          *
2009                          * Upper layer code will call this function separately
2010                          * for TX and RX keys when these registers offsets are
2011                          * used.
2012                          */
2013                         u32 mic0, mic2;
2014
2015                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2016                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2017
2018                         /* Write MIC key[31:0] */
2019                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2020                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2021
2022                         /* Write MIC key[63:32] */
2023                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2024                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2025
2026                         /* Write TX[63:32] and keyType(reserved) */
2027                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2028                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2029                                   AR_KEYTABLE_TYPE_CLR);
2030                 }
2031
2032                 /* MAC address registers are reserved for the MIC entry */
2033                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2034                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2035
2036                 /*
2037                  * Write the correct (un-inverted) key[47:0] last to enable
2038                  * TKIP now that all other registers are set with correct
2039                  * values.
2040                  */
2041                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2042                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2043         } else {
2044                 /* Write key[47:0] */
2045                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2046                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2047
2048                 /* Write key[95:48] */
2049                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2050                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2051
2052                 /* Write key[127:96] and key type */
2053                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2054                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2055
2056                 /* Write MAC address for the entry */
2057                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2058         }
2059
2060         return true;
2061 }
2062 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2063
2064 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2065 {
2066         if (entry < ah->caps.keycache_size) {
2067                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2068                 if (val & AR_KEYTABLE_VALID)
2069                         return true;
2070         }
2071         return false;
2072 }
2073 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2074
2075 /******************************/
2076 /* Power Management (Chipset) */
2077 /******************************/
2078
2079 /*
2080  * Notify Power Mgt is disabled in self-generated frames.
2081  * If requested, force chip to sleep.
2082  */
2083 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2084 {
2085         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2086         if (setChip) {
2087                 /*
2088                  * Clear the RTC force wake bit to allow the
2089                  * mac to go to sleep.
2090                  */
2091                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2092                             AR_RTC_FORCE_WAKE_EN);
2093                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2094                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2095
2096                 /* Shutdown chip. Active low */
2097                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2098                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2099                                     AR_RTC_RESET_EN);
2100         }
2101 }
2102
2103 /*
2104  * Notify Power Management is enabled in self-generating
2105  * frames. If request, set power mode of chip to
2106  * auto/normal.  Duration in units of 128us (1/8 TU).
2107  */
2108 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2109 {
2110         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2111         if (setChip) {
2112                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2113
2114                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2115                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
2116                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2117                                   AR_RTC_FORCE_WAKE_ON_INT);
2118                 } else {
2119                         /*
2120                          * Clear the RTC force wake bit to allow the
2121                          * mac to go to sleep.
2122                          */
2123                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2124                                     AR_RTC_FORCE_WAKE_EN);
2125                 }
2126         }
2127 }
2128
2129 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2130 {
2131         u32 val;
2132         int i;
2133
2134         if (setChip) {
2135                 if ((REG_READ(ah, AR_RTC_STATUS) &
2136                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2137                         if (ath9k_hw_set_reset_reg(ah,
2138                                            ATH9K_RESET_POWER_ON) != true) {
2139                                 return false;
2140                         }
2141                         if (!AR_SREV_9300_20_OR_LATER(ah))
2142                                 ath9k_hw_init_pll(ah, NULL);
2143                 }
2144                 if (AR_SREV_9100(ah))
2145                         REG_SET_BIT(ah, AR_RTC_RESET,
2146                                     AR_RTC_RESET_EN);
2147
2148                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2149                             AR_RTC_FORCE_WAKE_EN);
2150                 udelay(50);
2151
2152                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2153                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2154                         if (val == AR_RTC_STATUS_ON)
2155                                 break;
2156                         udelay(50);
2157                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2158                                     AR_RTC_FORCE_WAKE_EN);
2159                 }
2160                 if (i == 0) {
2161                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2162                                   "Failed to wakeup in %uus\n",
2163                                   POWER_UP_TIME / 20);
2164                         return false;
2165                 }
2166         }
2167
2168         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2169
2170         return true;
2171 }
2172
2173 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2174 {
2175         struct ath_common *common = ath9k_hw_common(ah);
2176         int status = true, setChip = true;
2177         static const char *modes[] = {
2178                 "AWAKE",
2179                 "FULL-SLEEP",
2180                 "NETWORK SLEEP",
2181                 "UNDEFINED"
2182         };
2183
2184         if (ah->power_mode == mode)
2185                 return status;
2186
2187         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2188                   modes[ah->power_mode], modes[mode]);
2189
2190         switch (mode) {
2191         case ATH9K_PM_AWAKE:
2192                 status = ath9k_hw_set_power_awake(ah, setChip);
2193                 break;
2194         case ATH9K_PM_FULL_SLEEP:
2195                 ath9k_set_power_sleep(ah, setChip);
2196                 ah->chip_fullsleep = true;
2197                 break;
2198         case ATH9K_PM_NETWORK_SLEEP:
2199                 ath9k_set_power_network_sleep(ah, setChip);
2200                 break;
2201         default:
2202                 ath_print(common, ATH_DBG_FATAL,
2203                           "Unknown power mode %u\n", mode);
2204                 return false;
2205         }
2206         ah->power_mode = mode;
2207
2208         return status;
2209 }
2210 EXPORT_SYMBOL(ath9k_hw_setpower);
2211
2212 /*
2213  * Helper for ASPM support.
2214  *
2215  * Disable PLL when in L0s as well as receiver clock when in L1.
2216  * This power saving option must be enabled through the SerDes.
2217  *
2218  * Programming the SerDes must go through the same 288 bit serial shift
2219  * register as the other analog registers.  Hence the 9 writes.
2220  */
2221 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
2222                                          int restore,
2223                                          int power_off)
2224 {
2225         u8 i;
2226         u32 val;
2227
2228         if (ah->is_pciexpress != true)
2229                 return;
2230
2231         /* Do not touch SerDes registers */
2232         if (ah->config.pcie_powersave_enable == 2)
2233                 return;
2234
2235         /* Nothing to do on restore for 11N */
2236         if (!restore) {
2237                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2238                         /*
2239                          * AR9280 2.0 or later chips use SerDes values from the
2240                          * initvals.h initialized depending on chipset during
2241                          * __ath9k_hw_init()
2242                          */
2243                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2244                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2245                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2246                         }
2247                 } else if (AR_SREV_9280(ah) &&
2248                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2249                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2250                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2251
2252                         /* RX shut off when elecidle is asserted */
2253                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2254                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2255                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2256
2257                         /* Shut off CLKREQ active in L1 */
2258                         if (ah->config.pcie_clock_req)
2259                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2260                         else
2261                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2262
2263                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2264                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2265                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2266
2267                         /* Load the new settings */
2268                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2269
2270                 } else {
2271                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2272                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2273
2274                         /* RX shut off when elecidle is asserted */
2275                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2276                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2277                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2278
2279                         /*
2280                          * Ignore ah->ah_config.pcie_clock_req setting for
2281                          * pre-AR9280 11n
2282                          */
2283                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2284
2285                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2286                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2287                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2288
2289                         /* Load the new settings */
2290                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2291                 }
2292
2293                 udelay(1000);
2294
2295                 /* set bit 19 to allow forcing of pcie core into L1 state */
2296                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2297
2298                 /* Several PCIe massages to ensure proper behaviour */
2299                 if (ah->config.pcie_waen) {
2300                         val = ah->config.pcie_waen;
2301                         if (!power_off)
2302                                 val &= (~AR_WA_D3_L1_DISABLE);
2303                 } else {
2304                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2305                             AR_SREV_9287(ah)) {
2306                                 val = AR9285_WA_DEFAULT;
2307                                 if (!power_off)
2308                                         val &= (~AR_WA_D3_L1_DISABLE);
2309                         } else if (AR_SREV_9280(ah)) {
2310                                 /*
2311                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2312                                  * set otherwise card may disappear.
2313                                  */
2314                                 val = AR9280_WA_DEFAULT;
2315                                 if (!power_off)
2316                                         val &= (~AR_WA_D3_L1_DISABLE);
2317                         } else
2318                                 val = AR_WA_DEFAULT;
2319                 }
2320
2321                 REG_WRITE(ah, AR_WA, val);
2322         }
2323
2324         if (power_off) {
2325                 /*
2326                  * Set PCIe workaround bits
2327                  * bit 14 in WA register (disable L1) should only
2328                  * be set when device enters D3 and be cleared
2329                  * when device comes back to D0.
2330                  */
2331                 if (ah->config.pcie_waen) {
2332                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2333                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2334                 } else {
2335                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2336                               AR_SREV_9287(ah)) &&
2337                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2338                             (AR_SREV_9280(ah) &&
2339                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2340                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2341                         }
2342                 }
2343         }
2344 }
2345
2346 /**********************/
2347 /* Interrupt Handling */
2348 /**********************/
2349
2350 bool ath9k_hw_intrpend(struct ath_hw *ah)
2351 {
2352         u32 host_isr;
2353
2354         if (AR_SREV_9100(ah))
2355                 return true;
2356
2357         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2358         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2359                 return true;
2360
2361         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2362         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2363             && (host_isr != AR_INTR_SPURIOUS))
2364                 return true;
2365
2366         return false;
2367 }
2368 EXPORT_SYMBOL(ath9k_hw_intrpend);
2369
2370 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2371 {
2372         u32 isr = 0;
2373         u32 mask2 = 0;
2374         struct ath9k_hw_capabilities *pCap = &ah->caps;
2375         u32 sync_cause = 0;
2376         bool fatal_int = false;
2377         struct ath_common *common = ath9k_hw_common(ah);
2378
2379         if (!AR_SREV_9100(ah)) {
2380                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2381                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2382                             == AR_RTC_STATUS_ON) {
2383                                 isr = REG_READ(ah, AR_ISR);
2384                         }
2385                 }
2386
2387                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2388                         AR_INTR_SYNC_DEFAULT;
2389
2390                 *masked = 0;
2391
2392                 if (!isr && !sync_cause)
2393                         return false;
2394         } else {
2395                 *masked = 0;
2396                 isr = REG_READ(ah, AR_ISR);
2397         }
2398
2399         if (isr) {
2400                 if (isr & AR_ISR_BCNMISC) {
2401                         u32 isr2;
2402                         isr2 = REG_READ(ah, AR_ISR_S2);
2403                         if (isr2 & AR_ISR_S2_TIM)
2404                                 mask2 |= ATH9K_INT_TIM;
2405                         if (isr2 & AR_ISR_S2_DTIM)
2406                                 mask2 |= ATH9K_INT_DTIM;
2407                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2408                                 mask2 |= ATH9K_INT_DTIMSYNC;
2409                         if (isr2 & (AR_ISR_S2_CABEND))
2410                                 mask2 |= ATH9K_INT_CABEND;
2411                         if (isr2 & AR_ISR_S2_GTT)
2412                                 mask2 |= ATH9K_INT_GTT;
2413                         if (isr2 & AR_ISR_S2_CST)
2414                                 mask2 |= ATH9K_INT_CST;
2415                         if (isr2 & AR_ISR_S2_TSFOOR)
2416                                 mask2 |= ATH9K_INT_TSFOOR;
2417                 }
2418
2419                 isr = REG_READ(ah, AR_ISR_RAC);
2420                 if (isr == 0xffffffff) {
2421                         *masked = 0;
2422                         return false;
2423                 }
2424
2425                 *masked = isr & ATH9K_INT_COMMON;
2426
2427                 if (ah->config.rx_intr_mitigation) {
2428                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2429                                 *masked |= ATH9K_INT_RX;
2430                 }
2431
2432                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2433                         *masked |= ATH9K_INT_RX;
2434                 if (isr &
2435                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2436                      AR_ISR_TXEOL)) {
2437                         u32 s0_s, s1_s;
2438
2439                         *masked |= ATH9K_INT_TX;
2440
2441                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2442                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2443                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2444
2445                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2446                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2447                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2448                 }
2449
2450                 if (isr & AR_ISR_RXORN) {
2451                         ath_print(common, ATH_DBG_INTERRUPT,
2452                                   "receive FIFO overrun interrupt\n");
2453                 }
2454
2455                 if (!AR_SREV_9100(ah)) {
2456                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2457                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2458                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2459                                         *masked |= ATH9K_INT_TIM_TIMER;
2460                         }
2461                 }
2462
2463                 *masked |= mask2;
2464         }
2465
2466         if (AR_SREV_9100(ah))
2467                 return true;
2468
2469         if (isr & AR_ISR_GENTMR) {
2470                 u32 s5_s;
2471
2472                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2473                 if (isr & AR_ISR_GENTMR) {
2474                         ah->intr_gen_timer_trigger =
2475                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2476
2477                         ah->intr_gen_timer_thresh =
2478                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2479
2480                         if (ah->intr_gen_timer_trigger)
2481                                 *masked |= ATH9K_INT_GENTIMER;
2482
2483                 }
2484         }
2485
2486         if (sync_cause) {
2487                 fatal_int =
2488                         (sync_cause &
2489                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2490                         ? true : false;
2491
2492                 if (fatal_int) {
2493                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2494                                 ath_print(common, ATH_DBG_ANY,
2495                                           "received PCI FATAL interrupt\n");
2496                         }
2497                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2498                                 ath_print(common, ATH_DBG_ANY,
2499                                           "received PCI PERR interrupt\n");
2500                         }
2501                         *masked |= ATH9K_INT_FATAL;
2502                 }
2503                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2504                         ath_print(common, ATH_DBG_INTERRUPT,
2505                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2506                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2507                         REG_WRITE(ah, AR_RC, 0);
2508                         *masked |= ATH9K_INT_FATAL;
2509                 }
2510                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2511                         ath_print(common, ATH_DBG_INTERRUPT,
2512                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2513                 }
2514
2515                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2516                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2517         }
2518
2519         return true;
2520 }
2521 EXPORT_SYMBOL(ath9k_hw_getisr);
2522
2523 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2524 {
2525         enum ath9k_int omask = ah->imask;
2526         u32 mask, mask2;
2527         struct ath9k_hw_capabilities *pCap = &ah->caps;
2528         struct ath_common *common = ath9k_hw_common(ah);
2529
2530         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2531
2532         if (omask & ATH9K_INT_GLOBAL) {
2533                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2534                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2535                 (void) REG_READ(ah, AR_IER);
2536                 if (!AR_SREV_9100(ah)) {
2537                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2538                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2539
2540                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2541                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2542                 }
2543         }
2544
2545         mask = ints & ATH9K_INT_COMMON;
2546         mask2 = 0;
2547
2548         if (ints & ATH9K_INT_TX) {
2549                 if (ah->txok_interrupt_mask)
2550                         mask |= AR_IMR_TXOK;
2551                 if (ah->txdesc_interrupt_mask)
2552                         mask |= AR_IMR_TXDESC;
2553                 if (ah->txerr_interrupt_mask)
2554                         mask |= AR_IMR_TXERR;
2555                 if (ah->txeol_interrupt_mask)
2556                         mask |= AR_IMR_TXEOL;
2557         }
2558         if (ints & ATH9K_INT_RX) {
2559                 mask |= AR_IMR_RXERR;
2560                 if (ah->config.rx_intr_mitigation)
2561                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2562                 else
2563                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2564                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2565                         mask |= AR_IMR_GENTMR;
2566         }
2567
2568         if (ints & (ATH9K_INT_BMISC)) {
2569                 mask |= AR_IMR_BCNMISC;
2570                 if (ints & ATH9K_INT_TIM)
2571                         mask2 |= AR_IMR_S2_TIM;
2572                 if (ints & ATH9K_INT_DTIM)
2573                         mask2 |= AR_IMR_S2_DTIM;
2574                 if (ints & ATH9K_INT_DTIMSYNC)
2575                         mask2 |= AR_IMR_S2_DTIMSYNC;
2576                 if (ints & ATH9K_INT_CABEND)
2577                         mask2 |= AR_IMR_S2_CABEND;
2578                 if (ints & ATH9K_INT_TSFOOR)
2579                         mask2 |= AR_IMR_S2_TSFOOR;
2580         }
2581
2582         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2583                 mask |= AR_IMR_BCNMISC;
2584                 if (ints & ATH9K_INT_GTT)
2585                         mask2 |= AR_IMR_S2_GTT;
2586                 if (ints & ATH9K_INT_CST)
2587                         mask2 |= AR_IMR_S2_CST;
2588         }
2589
2590         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2591         REG_WRITE(ah, AR_IMR, mask);
2592         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2593                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2594                            AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2595         ah->imrs2_reg |= mask2;
2596         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2597
2598         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2599                 if (ints & ATH9K_INT_TIM_TIMER)
2600                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2601                 else
2602                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2603         }
2604
2605         if (ints & ATH9K_INT_GLOBAL) {
2606                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2607                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2608                 if (!AR_SREV_9100(ah)) {
2609                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2610                                   AR_INTR_MAC_IRQ);
2611                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2612
2613
2614                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2615                                   AR_INTR_SYNC_DEFAULT);
2616                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2617                                   AR_INTR_SYNC_DEFAULT);
2618                 }
2619                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2620                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2621         }
2622
2623         return omask;
2624 }
2625 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2626
2627 /*******************/
2628 /* Beacon Handling */
2629 /*******************/
2630
2631 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2632 {
2633         int flags = 0;
2634
2635         ah->beacon_interval = beacon_period;
2636
2637         switch (ah->opmode) {
2638         case NL80211_IFTYPE_STATION:
2639         case NL80211_IFTYPE_MONITOR:
2640                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2641                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2642                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2643                 flags |= AR_TBTT_TIMER_EN;
2644                 break;
2645         case NL80211_IFTYPE_ADHOC:
2646         case NL80211_IFTYPE_MESH_POINT:
2647                 REG_SET_BIT(ah, AR_TXCFG,
2648                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2649                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2650                           TU_TO_USEC(next_beacon +
2651                                      (ah->atim_window ? ah->
2652                                       atim_window : 1)));
2653                 flags |= AR_NDP_TIMER_EN;
2654         case NL80211_IFTYPE_AP:
2655                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2656                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2657                           TU_TO_USEC(next_beacon -
2658                                      ah->config.
2659                                      dma_beacon_response_time));
2660                 REG_WRITE(ah, AR_NEXT_SWBA,
2661                           TU_TO_USEC(next_beacon -
2662                                      ah->config.
2663                                      sw_beacon_response_time));
2664                 flags |=
2665                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2666                 break;
2667         default:
2668                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2669                           "%s: unsupported opmode: %d\n",
2670                           __func__, ah->opmode);
2671                 return;
2672                 break;
2673         }
2674
2675         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2676         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2677         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2678         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2679
2680         beacon_period &= ~ATH9K_BEACON_ENA;
2681         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2682                 ath9k_hw_reset_tsf(ah);
2683         }
2684
2685         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2686 }
2687 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2688
2689 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2690                                     const struct ath9k_beacon_state *bs)
2691 {
2692         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2693         struct ath9k_hw_capabilities *pCap = &ah->caps;
2694         struct ath_common *common = ath9k_hw_common(ah);
2695
2696         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2697
2698         REG_WRITE(ah, AR_BEACON_PERIOD,
2699                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2700         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2701                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2702
2703         REG_RMW_FIELD(ah, AR_RSSI_THR,
2704                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2705
2706         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
2707
2708         if (bs->bs_sleepduration > beaconintval)
2709                 beaconintval = bs->bs_sleepduration;
2710
2711         dtimperiod = bs->bs_dtimperiod;
2712         if (bs->bs_sleepduration > dtimperiod)
2713                 dtimperiod = bs->bs_sleepduration;
2714
2715         if (beaconintval == dtimperiod)
2716                 nextTbtt = bs->bs_nextdtim;
2717         else
2718                 nextTbtt = bs->bs_nexttbtt;
2719
2720         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2721         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2722         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2723         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2724
2725         REG_WRITE(ah, AR_NEXT_DTIM,
2726                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2727         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2728
2729         REG_WRITE(ah, AR_SLEEP1,
2730                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2731                   | AR_SLEEP1_ASSUME_DTIM);
2732
2733         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2734                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2735         else
2736                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2737
2738         REG_WRITE(ah, AR_SLEEP2,
2739                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2740
2741         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2742         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2743
2744         REG_SET_BIT(ah, AR_TIMER_MODE,
2745                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2746                     AR_DTIM_TIMER_EN);
2747
2748         /* TSF Out of Range Threshold */
2749         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2750 }
2751 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2752
2753 /*******************/
2754 /* HW Capabilities */
2755 /*******************/
2756
2757 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2758 {
2759         struct ath9k_hw_capabilities *pCap = &ah->caps;
2760         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2761         struct ath_common *common = ath9k_hw_common(ah);
2762         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2763
2764         u16 capField = 0, eeval;
2765
2766         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2767         regulatory->current_rd = eeval;
2768
2769         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2770         if (AR_SREV_9285_10_OR_LATER(ah))
2771                 eeval |= AR9285_RDEXT_DEFAULT;
2772         regulatory->current_rd_ext = eeval;
2773
2774         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2775
2776         if (ah->opmode != NL80211_IFTYPE_AP &&
2777             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2778                 if (regulatory->current_rd == 0x64 ||
2779                     regulatory->current_rd == 0x65)
2780                         regulatory->current_rd += 5;
2781                 else if (regulatory->current_rd == 0x41)
2782                         regulatory->current_rd = 0x43;
2783                 ath_print(common, ATH_DBG_REGULATORY,
2784                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2785         }
2786
2787         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2788         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2789                 ath_print(common, ATH_DBG_FATAL,
2790                           "no band has been marked as supported in EEPROM.\n");
2791                 return -EINVAL;
2792         }
2793
2794         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2795
2796         if (eeval & AR5416_OPFLAGS_11A) {
2797                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2798                 if (ah->config.ht_enable) {
2799                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2800                                 set_bit(ATH9K_MODE_11NA_HT20,
2801                                         pCap->wireless_modes);
2802                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2803                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2804                                         pCap->wireless_modes);
2805                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2806                                         pCap->wireless_modes);
2807                         }
2808                 }
2809         }
2810
2811         if (eeval & AR5416_OPFLAGS_11G) {
2812                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2813                 if (ah->config.ht_enable) {
2814                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2815                                 set_bit(ATH9K_MODE_11NG_HT20,
2816                                         pCap->wireless_modes);
2817                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2818                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2819                                         pCap->wireless_modes);
2820                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2821                                         pCap->wireless_modes);
2822                         }
2823                 }
2824         }
2825
2826         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2827         /*
2828          * For AR9271 we will temporarilly uses the rx chainmax as read from
2829          * the EEPROM.
2830          */
2831         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2832             !(eeval & AR5416_OPFLAGS_11A) &&
2833             !(AR_SREV_9271(ah)))
2834                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2835                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2836         else
2837                 /* Use rx_chainmask from EEPROM. */
2838                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2839
2840         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2841                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2842
2843         pCap->low_2ghz_chan = 2312;
2844         pCap->high_2ghz_chan = 2732;
2845
2846         pCap->low_5ghz_chan = 4920;
2847         pCap->high_5ghz_chan = 6100;
2848
2849         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2850         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2851         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2852
2853         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2854         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2855         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2856
2857         if (ah->config.ht_enable)
2858                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2859         else
2860                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2861
2862         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2863         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2864         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2865         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2866
2867         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2868                 pCap->total_queues =
2869                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2870         else
2871                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2872
2873         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2874                 pCap->keycache_size =
2875                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2876         else
2877                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2878
2879         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2880
2881         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2882                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2883         else
2884                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2885
2886         if (AR_SREV_9271(ah))
2887                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2888         else if (AR_SREV_9285_10_OR_LATER(ah))
2889                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2890         else if (AR_SREV_9280_10_OR_LATER(ah))
2891                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2892         else
2893                 pCap->num_gpio_pins = AR_NUM_GPIO;
2894
2895         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2896                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2897                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2898         } else {
2899                 pCap->rts_aggr_limit = (8 * 1024);
2900         }
2901
2902         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2903
2904 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2905         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2906         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2907                 ah->rfkill_gpio =
2908                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2909                 ah->rfkill_polarity =
2910                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2911
2912                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2913         }
2914 #endif
2915         if (AR_SREV_9271(ah))
2916                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2917         else
2918                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2919
2920         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2921                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2922         else
2923                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2924
2925         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2926                 pCap->reg_cap =
2927                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2928                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2929                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2930                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2931         } else {
2932                 pCap->reg_cap =
2933                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2934                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2935         }
2936
2937         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2938         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2939             AR_SREV_5416(ah))
2940                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2941
2942         pCap->num_antcfg_5ghz =
2943                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2944         pCap->num_antcfg_2ghz =
2945                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2946
2947         if (AR_SREV_9280_10_OR_LATER(ah) &&
2948             ath9k_hw_btcoex_supported(ah)) {
2949                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2950                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2951
2952                 if (AR_SREV_9285(ah)) {
2953                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2954                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2955                 } else {
2956                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2957                 }
2958         } else {
2959                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2960         }
2961
2962         if (AR_SREV_9300_20_OR_LATER(ah)) {
2963                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
2964                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2965                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2966                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2967                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2968         } else {
2969                 pCap->tx_desc_len = sizeof(struct ath_desc);
2970         }
2971
2972         return 0;
2973 }
2974
2975 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2976                             u32 capability, u32 *result)
2977 {
2978         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2979         switch (type) {
2980         case ATH9K_CAP_CIPHER:
2981                 switch (capability) {
2982                 case ATH9K_CIPHER_AES_CCM:
2983                 case ATH9K_CIPHER_AES_OCB:
2984                 case ATH9K_CIPHER_TKIP:
2985                 case ATH9K_CIPHER_WEP:
2986                 case ATH9K_CIPHER_MIC:
2987                 case ATH9K_CIPHER_CLR:
2988                         return true;
2989                 default:
2990                         return false;
2991                 }
2992         case ATH9K_CAP_TKIP_MIC:
2993                 switch (capability) {
2994                 case 0:
2995                         return true;
2996                 case 1:
2997                         return (ah->sta_id1_defaults &
2998                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2999                         false;
3000                 }
3001         case ATH9K_CAP_TKIP_SPLIT:
3002                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3003                         false : true;
3004         case ATH9K_CAP_MCAST_KEYSRCH:
3005                 switch (capability) {
3006                 case 0:
3007                         return true;
3008                 case 1:
3009                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3010                                 return false;
3011                         } else {
3012                                 return (ah->sta_id1_defaults &
3013                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3014                                         false;
3015                         }
3016                 }
3017                 return false;
3018         case ATH9K_CAP_TXPOW:
3019                 switch (capability) {
3020                 case 0:
3021                         return 0;
3022                 case 1:
3023                         *result = regulatory->power_limit;
3024                         return 0;
3025                 case 2:
3026                         *result = regulatory->max_power_level;
3027                         return 0;
3028                 case 3:
3029                         *result = regulatory->tp_scale;
3030                         return 0;
3031                 }
3032                 return false;
3033         case ATH9K_CAP_DS:
3034                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3035                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3036                         ? false : true;
3037         default:
3038                 return false;
3039         }
3040 }
3041 EXPORT_SYMBOL(ath9k_hw_getcapability);
3042
3043 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3044                             u32 capability, u32 setting, int *status)
3045 {
3046         switch (type) {
3047         case ATH9K_CAP_TKIP_MIC:
3048                 if (setting)
3049                         ah->sta_id1_defaults |=
3050                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3051                 else
3052                         ah->sta_id1_defaults &=
3053                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3054                 return true;
3055         case ATH9K_CAP_MCAST_KEYSRCH:
3056                 if (setting)
3057                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3058                 else
3059                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3060                 return true;
3061         default:
3062                 return false;
3063         }
3064 }
3065 EXPORT_SYMBOL(ath9k_hw_setcapability);
3066
3067 /****************************/
3068 /* GPIO / RFKILL / Antennae */
3069 /****************************/
3070
3071 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3072                                          u32 gpio, u32 type)
3073 {
3074         int addr;
3075         u32 gpio_shift, tmp;
3076
3077         if (gpio > 11)
3078                 addr = AR_GPIO_OUTPUT_MUX3;
3079         else if (gpio > 5)
3080                 addr = AR_GPIO_OUTPUT_MUX2;
3081         else
3082                 addr = AR_GPIO_OUTPUT_MUX1;
3083
3084         gpio_shift = (gpio % 6) * 5;
3085
3086         if (AR_SREV_9280_20_OR_LATER(ah)
3087             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3088                 REG_RMW(ah, addr, (type << gpio_shift),
3089                         (0x1f << gpio_shift));
3090         } else {
3091                 tmp = REG_READ(ah, addr);
3092                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3093                 tmp &= ~(0x1f << gpio_shift);
3094                 tmp |= (type << gpio_shift);
3095                 REG_WRITE(ah, addr, tmp);
3096         }
3097 }
3098
3099 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3100 {
3101         u32 gpio_shift;
3102
3103         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3104
3105         gpio_shift = gpio << 1;
3106
3107         REG_RMW(ah,
3108                 AR_GPIO_OE_OUT,
3109                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3110                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3111 }
3112 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3113
3114 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3115 {
3116 #define MS_REG_READ(x, y) \
3117         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3118
3119         if (gpio >= ah->caps.num_gpio_pins)
3120                 return 0xffffffff;
3121
3122         if (AR_SREV_9300_20_OR_LATER(ah))
3123                 return MS_REG_READ(AR9300, gpio) != 0;
3124         else if (AR_SREV_9271(ah))
3125                 return MS_REG_READ(AR9271, gpio) != 0;
3126         else if (AR_SREV_9287_10_OR_LATER(ah))
3127                 return MS_REG_READ(AR9287, gpio) != 0;
3128         else if (AR_SREV_9285_10_OR_LATER(ah))
3129                 return MS_REG_READ(AR9285, gpio) != 0;
3130         else if (AR_SREV_9280_10_OR_LATER(ah))
3131                 return MS_REG_READ(AR928X, gpio) != 0;
3132         else
3133                 return MS_REG_READ(AR, gpio) != 0;
3134 }
3135 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3136
3137 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3138                          u32 ah_signal_type)
3139 {
3140         u32 gpio_shift;
3141
3142         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3143
3144         gpio_shift = 2 * gpio;
3145
3146         REG_RMW(ah,
3147                 AR_GPIO_OE_OUT,
3148                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3149                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3150 }
3151 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3152
3153 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3154 {
3155         if (AR_SREV_9271(ah))
3156                 val = ~val;
3157
3158         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3159                 AR_GPIO_BIT(gpio));
3160 }
3161 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3162
3163 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3164 {
3165         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3166 }
3167 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3168
3169 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3170 {
3171         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3172 }
3173 EXPORT_SYMBOL(ath9k_hw_setantenna);
3174
3175 /*********************/
3176 /* General Operation */
3177 /*********************/
3178
3179 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3180 {
3181         u32 bits = REG_READ(ah, AR_RX_FILTER);
3182         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3183
3184         if (phybits & AR_PHY_ERR_RADAR)
3185                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3186         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3187                 bits |= ATH9K_RX_FILTER_PHYERR;
3188
3189         return bits;
3190 }
3191 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3192
3193 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3194 {
3195         u32 phybits;
3196
3197         REG_WRITE(ah, AR_RX_FILTER, bits);
3198
3199         phybits = 0;
3200         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3201                 phybits |= AR_PHY_ERR_RADAR;
3202         if (bits & ATH9K_RX_FILTER_PHYERR)
3203                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3204         REG_WRITE(ah, AR_PHY_ERR, phybits);
3205
3206         if (phybits)
3207                 REG_WRITE(ah, AR_RXCFG,
3208                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3209         else
3210                 REG_WRITE(ah, AR_RXCFG,
3211                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3212 }
3213 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3214
3215 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3216 {
3217         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3218                 return false;
3219
3220         ath9k_hw_init_pll(ah, NULL);
3221         return true;
3222 }
3223 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3224
3225 bool ath9k_hw_disable(struct ath_hw *ah)
3226 {
3227         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3228                 return false;
3229
3230         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3231                 return false;
3232
3233         ath9k_hw_init_pll(ah, NULL);
3234         return true;
3235 }
3236 EXPORT_SYMBOL(ath9k_hw_disable);
3237
3238 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3239 {
3240         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3241         struct ath9k_channel *chan = ah->curchan;
3242         struct ieee80211_channel *channel = chan->chan;
3243
3244         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3245
3246         ah->eep_ops->set_txpower(ah, chan,
3247                                  ath9k_regd_get_ctl(regulatory, chan),
3248                                  channel->max_antenna_gain * 2,
3249                                  channel->max_power * 2,
3250                                  min((u32) MAX_RATE_POWER,
3251                                  (u32) regulatory->power_limit));
3252 }
3253 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3254
3255 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3256 {
3257         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3258 }
3259 EXPORT_SYMBOL(ath9k_hw_setmac);
3260
3261 void ath9k_hw_setopmode(struct ath_hw *ah)
3262 {
3263         ath9k_hw_set_operating_mode(ah, ah->opmode);
3264 }
3265 EXPORT_SYMBOL(ath9k_hw_setopmode);
3266
3267 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3268 {
3269         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3270         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3271 }
3272 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3273
3274 void ath9k_hw_write_associd(struct ath_hw *ah)
3275 {
3276         struct ath_common *common = ath9k_hw_common(ah);
3277
3278         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3279         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3280                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3281 }
3282 EXPORT_SYMBOL(ath9k_hw_write_associd);
3283
3284 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3285 {
3286         u64 tsf;
3287
3288         tsf = REG_READ(ah, AR_TSF_U32);
3289         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3290
3291         return tsf;
3292 }
3293 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3294
3295 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3296 {
3297         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3298         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3299 }
3300 EXPORT_SYMBOL(ath9k_hw_settsf64);
3301
3302 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3303 {
3304         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3305                            AH_TSF_WRITE_TIMEOUT))
3306                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3307                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3308
3309         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3310 }
3311 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3312
3313 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3314 {
3315         if (setting)
3316                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3317         else
3318                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3319 }
3320 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3321
3322 /*
3323  *  Extend 15-bit time stamp from rx descriptor to
3324  *  a full 64-bit TSF using the current h/w TSF.
3325 */
3326 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3327 {
3328         u64 tsf;
3329
3330         tsf = ath9k_hw_gettsf64(ah);
3331         if ((tsf & 0x7fff) < rstamp)
3332                 tsf -= 0x8000;
3333         return (tsf & ~0x7fff) | rstamp;
3334 }
3335 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3336
3337 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3338 {
3339         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3340         u32 macmode;
3341
3342         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3343                 macmode = AR_2040_JOINED_RX_CLEAR;
3344         else
3345                 macmode = 0;
3346
3347         REG_WRITE(ah, AR_2040_MODE, macmode);
3348 }
3349
3350 /* HW Generic timers configuration */
3351
3352 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3353 {
3354         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3355         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3356         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3357         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3358         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3359         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3360         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3361         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3362         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3363         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3364                                 AR_NDP2_TIMER_MODE, 0x0002},
3365         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3366                                 AR_NDP2_TIMER_MODE, 0x0004},
3367         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3368                                 AR_NDP2_TIMER_MODE, 0x0008},
3369         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3370                                 AR_NDP2_TIMER_MODE, 0x0010},
3371         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3372                                 AR_NDP2_TIMER_MODE, 0x0020},
3373         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3374                                 AR_NDP2_TIMER_MODE, 0x0040},
3375         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3376                                 AR_NDP2_TIMER_MODE, 0x0080}
3377 };
3378
3379 /* HW generic timer primitives */
3380
3381 /* compute and clear index of rightmost 1 */
3382 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3383 {
3384         u32 b;
3385
3386         b = *mask;
3387         b &= (0-b);
3388         *mask &= ~b;
3389         b *= debruijn32;
3390         b >>= 27;
3391
3392         return timer_table->gen_timer_index[b];
3393 }
3394
3395 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3396 {
3397         return REG_READ(ah, AR_TSF_L32);
3398 }
3399 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3400
3401 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3402                                           void (*trigger)(void *),
3403                                           void (*overflow)(void *),
3404                                           void *arg,
3405                                           u8 timer_index)
3406 {
3407         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3408         struct ath_gen_timer *timer;
3409
3410         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3411
3412         if (timer == NULL) {
3413                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3414                           "Failed to allocate memory"
3415                           "for hw timer[%d]\n", timer_index);
3416                 return NULL;
3417         }
3418
3419         /* allocate a hardware generic timer slot */
3420         timer_table->timers[timer_index] = timer;
3421         timer->index = timer_index;
3422         timer->trigger = trigger;
3423         timer->overflow = overflow;
3424         timer->arg = arg;
3425
3426         return timer;
3427 }
3428 EXPORT_SYMBOL(ath_gen_timer_alloc);
3429
3430 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3431                               struct ath_gen_timer *timer,
3432                               u32 timer_next,
3433                               u32 timer_period)
3434 {
3435         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3436         u32 tsf;
3437
3438         BUG_ON(!timer_period);
3439
3440         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3441
3442         tsf = ath9k_hw_gettsf32(ah);
3443
3444         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3445                   "curent tsf %x period %x"
3446                   "timer_next %x\n", tsf, timer_period, timer_next);
3447
3448         /*
3449          * Pull timer_next forward if the current TSF already passed it
3450          * because of software latency
3451          */
3452         if (timer_next < tsf)
3453                 timer_next = tsf + timer_period;
3454
3455         /*
3456          * Program generic timer registers
3457          */
3458         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3459                  timer_next);
3460         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3461                   timer_period);
3462         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3463                     gen_tmr_configuration[timer->index].mode_mask);
3464
3465         /* Enable both trigger and thresh interrupt masks */
3466         REG_SET_BIT(ah, AR_IMR_S5,
3467                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3468                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3469 }
3470 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3471
3472 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3473 {
3474         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3475
3476         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3477                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3478                 return;
3479         }
3480
3481         /* Clear generic timer enable bits. */
3482         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3483                         gen_tmr_configuration[timer->index].mode_mask);
3484
3485         /* Disable both trigger and thresh interrupt masks */
3486         REG_CLR_BIT(ah, AR_IMR_S5,
3487                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3488                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3489
3490         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3491 }
3492 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3493
3494 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3495 {
3496         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3497
3498         /* free the hardware generic timer slot */
3499         timer_table->timers[timer->index] = NULL;
3500         kfree(timer);
3501 }
3502 EXPORT_SYMBOL(ath_gen_timer_free);
3503
3504 /*
3505  * Generic Timer Interrupts handling
3506  */
3507 void ath_gen_timer_isr(struct ath_hw *ah)
3508 {
3509         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3510         struct ath_gen_timer *timer;
3511         struct ath_common *common = ath9k_hw_common(ah);
3512         u32 trigger_mask, thresh_mask, index;
3513
3514         /* get hardware generic timer interrupt status */
3515         trigger_mask = ah->intr_gen_timer_trigger;
3516         thresh_mask = ah->intr_gen_timer_thresh;
3517         trigger_mask &= timer_table->timer_mask.val;
3518         thresh_mask &= timer_table->timer_mask.val;
3519
3520         trigger_mask &= ~thresh_mask;
3521
3522         while (thresh_mask) {
3523                 index = rightmost_index(timer_table, &thresh_mask);
3524                 timer = timer_table->timers[index];
3525                 BUG_ON(!timer);
3526                 ath_print(common, ATH_DBG_HWTIMER,
3527                           "TSF overflow for Gen timer %d\n", index);
3528                 timer->overflow(timer->arg);
3529         }
3530
3531         while (trigger_mask) {
3532                 index = rightmost_index(timer_table, &trigger_mask);
3533                 timer = timer_table->timers[index];
3534                 BUG_ON(!timer);
3535                 ath_print(common, ATH_DBG_HWTIMER,
3536                           "Gen timer[%d] trigger\n", index);
3537                 timer->trigger(timer->arg);
3538         }
3539 }
3540 EXPORT_SYMBOL(ath_gen_timer_isr);
3541
3542 /********/
3543 /* HTC  */
3544 /********/
3545
3546 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3547 {
3548         ah->htc_reset_init = true;
3549 }
3550 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3551
3552 static struct {
3553         u32 version;
3554         const char * name;
3555 } ath_mac_bb_names[] = {
3556         /* Devices with external radios */
3557         { AR_SREV_VERSION_5416_PCI,     "5416" },
3558         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3559         { AR_SREV_VERSION_9100,         "9100" },
3560         { AR_SREV_VERSION_9160,         "9160" },
3561         /* Single-chip solutions */
3562         { AR_SREV_VERSION_9280,         "9280" },
3563         { AR_SREV_VERSION_9285,         "9285" },
3564         { AR_SREV_VERSION_9287,         "9287" },
3565         { AR_SREV_VERSION_9271,         "9271" },
3566 };
3567
3568 /* For devices with external radios */
3569 static struct {
3570         u16 version;
3571         const char * name;
3572 } ath_rf_names[] = {
3573         { 0,                            "5133" },
3574         { AR_RAD5133_SREV_MAJOR,        "5133" },
3575         { AR_RAD5122_SREV_MAJOR,        "5122" },
3576         { AR_RAD2133_SREV_MAJOR,        "2133" },
3577         { AR_RAD2122_SREV_MAJOR,        "2122" }
3578 };
3579
3580 /*
3581  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3582  */
3583 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3584 {
3585         int i;
3586
3587         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3588                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3589                         return ath_mac_bb_names[i].name;
3590                 }
3591         }
3592
3593         return "????";
3594 }
3595
3596 /*
3597  * Return the RF name. "????" is returned if the RF is unknown.
3598  * Used for devices with external radios.
3599  */
3600 static const char *ath9k_hw_rf_name(u16 rf_version)
3601 {
3602         int i;
3603
3604         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3605                 if (ath_rf_names[i].version == rf_version) {
3606                         return ath_rf_names[i].name;
3607                 }
3608         }
3609
3610         return "????";
3611 }
3612
3613 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3614 {
3615         int used;
3616
3617         /* chipsets >= AR9280 are single-chip */
3618         if (AR_SREV_9280_10_OR_LATER(ah)) {
3619                 used = snprintf(hw_name, len,
3620                                "Atheros AR%s Rev:%x",
3621                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3622                                ah->hw_version.macRev);
3623         }
3624         else {
3625                 used = snprintf(hw_name, len,
3626                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3627                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3628                                ah->hw_version.macRev,
3629                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3630                                                 AR_RADIO_SREV_MAJOR)),
3631                                ah->hw_version.phyRev);
3632         }
3633
3634         hw_name[used] = '\0';
3635 }
3636 EXPORT_SYMBOL(ath9k_hw_name);
3637
3638 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
3639 static void ar9002_hw_attach_ops(struct ath_hw *ah)
3640 {
3641         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3642         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
3643
3644         priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
3645         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
3646         priv_ops->macversion_supported = ar9002_hw_macversion_supported;
3647
3648         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
3649
3650         ar5008_hw_attach_phy_ops(ah);
3651         if (AR_SREV_9280_10_OR_LATER(ah))
3652                 ar9002_hw_attach_phy_ops(ah);
3653
3654         ar9002_hw_attach_mac_ops(ah);
3655 }
3656
3657 /* Sets up the AR9003 hardware familiy callbacks */
3658 static void ar9003_hw_attach_ops(struct ath_hw *ah)
3659 {
3660         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3661
3662         priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
3663         priv_ops->macversion_supported = ar9003_hw_macversion_supported;
3664
3665         ar9003_hw_attach_phy_ops(ah);
3666
3667         ar9003_hw_attach_mac_ops(ah);
3668 }