unsigned int video_start; /* start of video RAM */
unsigned int video_end; /* end of video RAM */
- unsigned int reserve_lp0 :1; /* never has lp0 */
- unsigned int reserve_lp1 :1; /* never has lp1 */
- unsigned int reserve_lp2 :1; /* never has lp2 */
- unsigned int soft_reboot :1; /* soft reboot */
+ unsigned char reserve_lp0 :1; /* never has lp0 */
+ unsigned char reserve_lp1 :1; /* never has lp1 */
+ unsigned char reserve_lp2 :1; /* never has lp2 */
+ char restart_mode; /* default restart mode */
void (*fixup)(struct tag *, char **,
struct meminfo *);
void (*reserve)(void);/* reserve mem blocks */
#ifdef CONFIG_MULTI_IRQ_HANDLER
void (*handle_irq)(struct pt_regs *);
#endif
+ void (*restart)(char, const char *);
};
/*
extern void cpu_init(void);
void arm_machine_restart(char mode, const char *cmd);
+void soft_restart(unsigned long);
extern void (*arm_pm_restart)(char str, const char *cmd);
#define UDBG_UNDEFINED (1 << 0)
extern const unsigned char relocate_new_kernel[];
extern const unsigned int relocate_new_kernel_size;
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
extern unsigned long kexec_start_address;
extern unsigned long kexec_indirection_page;
kexec_reinit();
local_irq_disable();
local_fiq_disable();
- setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
+ setup_mm_for_reboot();
flush_cache_all();
outer_flush_all();
outer_disable();
"ARM" , "Thumb" , "Jazelle", "ThumbEE"
};
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
static volatile int hlt_counter;
__setup("nohlt", nohlt_setup);
__setup("hlt", hlt_setup);
-void arm_machine_restart(char mode, const char *cmd)
+void soft_restart(unsigned long addr)
{
/* Disable interrupts first */
local_irq_disable();
* we may need it to insert some 1:1 mappings so that
* soft boot works.
*/
- setup_mm_for_reboot(mode);
+ setup_mm_for_reboot();
/* Clean and invalidate caches */
flush_cache_all();
/* Push out any further dirty data, and ensure cache is empty */
flush_cache_all();
- /*
- * Now call the architecture specific reboot code.
- */
- arch_reset(mode, cmd);
+ cpu_reset(addr);
+}
- /*
- * Whoops - the architecture was unable to reboot.
- * Tell the user!
- */
- mdelay(1000);
- printk("Reboot failed -- System halted\n");
- while (1);
+void arm_machine_restart(char mode, const char *cmd)
+{
+ /* Disable interrupts first */
+ local_irq_disable();
+ local_fiq_disable();
+
+ /* Call the architecture specific reboot code. */
+ arch_reset(mode, cmd);
}
/*
void machine_restart(char *cmd)
{
machine_shutdown();
+
arm_pm_restart(reboot_mode, cmd);
+
+ /* Give a grace period for failure to restart of 1s */
+ mdelay(1000);
+
+ /* Whoops - the platform was unable to reboot. Tell the user! */
+ printk("Reboot failed -- System halted\n");
+ while (1);
}
void __show_regs(struct pt_regs *regs)
arm_dma_zone_size = mdesc->dma_zone_size;
}
#endif
- if (mdesc->soft_reboot)
- reboot_setup("s");
+ if (mdesc->restart_mode)
+ reboot_setup(&mdesc->restart_mode);
init_mm.start_code = (unsigned long) _text;
init_mm.end_code = (unsigned long) _etext;
paging_init(mdesc);
request_standard_resources(mdesc);
+ if (mdesc->restart)
+ arm_pm_restart = mdesc->restart;
+
unflatten_device_tree();
#ifdef CONFIG_SMP
static inline void arch_reset(char mode, const char *cmd)
{
- cpu_reset(0);
+ soft_restart(0);
}
#endif
.atag_offset = 0x400,
.reserve_lp0 = 1,
.reserve_lp2 = 1,
- .soft_reboot = 1,
+ .restart_mode = 's',
.map_io = ebsa110_map_io,
.init_irq = ebsa110_init_irq,
.timer = &ebsa110_timer,
asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
}
-#define arch_reset(mode, cmd) cpu_reset(0x80000000)
+#define arch_reset(mode, cmd) soft_restart(0x80000000)
#endif
MACHINE_START(CATS, "Chalice-CATS")
/* Maintainer: Philip Blundell */
.atag_offset = 0x100,
- .soft_reboot = 1,
+ .restart_mode = 's',
.fixup = fixup_cats,
.map_io = footbridge_map_io,
.init_irq = footbridge_init_irq,
/*
* Jump into the ROM
*/
- cpu_reset(0x41000000);
+ soft_restart(0x41000000);
} else {
if (machine_is_netwinder()) {
/* open up the SuperIO chip
*IOP3XX_PCSR = 0x30;
/* Jump into ROM at address 0 */
- cpu_reset(0);
+ soft_restart(0);
}
*IOP3XX_PCSR = 0x30;
/* Jump into ROM at address 0 */
- cpu_reset(0);
+ soft_restart(0);
}
{
if ( 1 && mode == 's') {
/* Jump into ROM at address 0 */
- cpu_reset(0);
+ soft_restart(0);
} else {
/* Use on-chip reset capability */
unsigned int reg;
if (mode == 's')
- cpu_reset(0);
+ soft_restart(0);
/* disable timer0 */
reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
static inline void arch_reset(char mode, const char *cmd)
{
if (cpu_is_pxa168())
- cpu_reset(0xffff0000);
+ soft_restart(0xffff0000);
else
- cpu_reset(0);
+ soft_restart(0);
}
#endif /* __ASM_MACH_SYSTEM_H */
mdelay(50);
/* We'll take a jump through zero as a poor second */
- cpu_reset(0);
+ soft_restart(0);
}
static int __init mxs_arch_reset_init(void)
static inline void arch_reset(char mode, const char *cmd)
{
- cpu_reset(0);
+ soft_restart(0);
}
#endif
MACHINE_START(MIOA701, "MIO A701")
.atag_offset = 0x100,
+ .restart_mode = 's',
.map_io = &pxa27x_map_io,
.init_irq = &pxa27x_init_irq,
.handle_irq = &pxa27x_handle_irq,
switch (mode) {
case 's':
/* Jump into ROM at address 0 */
- cpu_reset(0);
+ soft_restart(0);
break;
case 'g':
do_gpio_reset();
#ifdef CONFIG_MACH_SPITZ
MACHINE_START(SPITZ, "SHARP Spitz")
+ .restart_mode = 'g',
.fixup = spitz_fixup,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
#ifdef CONFIG_MACH_BORZOI
MACHINE_START(BORZOI, "SHARP Borzoi")
+ .restart_mode = 'g',
.fixup = spitz_fixup,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
#ifdef CONFIG_MACH_AKITA
MACHINE_START(AKITA, "SHARP Akita")
+ .restart_mode = 'g',
.fixup = spitz_fixup,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
}
MACHINE_START(TOSA, "SHARP Tosa")
+ .restart_mode = 'g',
.fixup = fixup_tosa,
.map_io = pxa25x_map_io,
.nr_irqs = TOSA_NR_IRQS,
/*
* Jump into the ROM
*/
- cpu_reset(0);
+ soft_restart(0);
}
arch_reset(char mode, const char *cmd)
{
if (mode == 's') {
- cpu_reset(0);
+ soft_restart(0);
}
if (s3c24xx_reset_hook)
arch_wdt_reset();
/* we'll take a jump through zero as a poor second */
- cpu_reset(0);
+ soft_restart(0);
}
arch_wdt_reset();
/* if all else fails, or mode was for soft, jump to 0 */
- cpu_reset(0);
+ soft_restart(0);
}
#endif /* __ASM_ARCH_IRQ_H */
{
if (mode == 's') {
/* Jump into ROM at address 0 */
- cpu_reset(0);
+ soft_restart(0);
} else {
/* Use on-chip reset capability */
RSRR = RSRR_SWR;
static inline void arch_reset(char mode, const char *cmd)
{
- cpu_reset(0);
+ soft_restart(0);
}
#endif
{
if (mode == 's') {
/* Jump into ROM at address 0 */
- cpu_reset(0);
+ soft_restart(0);
} else {
__raw_writel(WTE | WTRE | WTCLK, WTCR);
}
* the user-mode pages. This will then ensure that we have predictable
* results when turning the mmu off
*/
-void setup_mm_for_reboot(char mode)
+void setup_mm_for_reboot(void)
{
/*
* We need to access to user-mode page tables here. For kernel threads
/*
* We don't need to do anything here for nommu machines.
*/
-void setup_mm_for_reboot(char mode)
+void setup_mm_for_reboot(void)
{
}
mdelay(50);
/* we'll take a jump through zero as a poor second */
- cpu_reset(0);
+ soft_restart(0);
}
void mxc_arch_reset_init(void __iomem *base)
{
if (mode == 's') {
/* software reset, Jump into ROM at address 0 */
- cpu_reset(0);
+ soft_restart(0);
} else {
/* hardware reset, Use on-chip reset capability */
sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
projects / linux-imx.git / commitdiff