2 * Marvell Wireless LAN device driver: SDIO specific definitions
4 * Copyright (C) 2011, Marvell International Ltd.
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
20 #ifndef _MWIFIEX_SDIO_H
21 #define _MWIFIEX_SDIO_H
24 #include <linux/mmc/sdio.h>
25 #include <linux/mmc/sdio_ids.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/host.h>
32 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
33 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
34 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
35 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
42 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
44 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
46 #define SDIO_MPA_ADDR_BASE 0x1000
48 #define CTRL_PORT_MASK 0x0001
50 #define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
51 #define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
52 #define HOST_TERM_CMD53 (0x1U << 2)
54 #define MEM_PORT 0x10000
55 #define CMD_RD_LEN_0 0xB4
56 #define CMD_RD_LEN_1 0xB5
57 #define CARD_CONFIG_2_1_REG 0xCD
58 #define CMD53_NEW_MODE (0x1U << 0)
59 #define CMD_CONFIG_0 0xB8
60 #define CMD_PORT_RD_LEN_EN (0x1U << 2)
61 #define CMD_CONFIG_1 0xB9
62 #define CMD_PORT_AUTO_EN (0x1U << 0)
63 #define CMD_PORT_SLCT 0x8000
64 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
65 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
67 #define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
69 /* Multi port RX aggregation buffer size */
70 #define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
72 /* Misc. Config Register : Auto Re-enable interrupts */
73 #define AUTO_RE_ENABLE_INT BIT(4)
75 /* Host Control Registers */
76 /* Host Control Registers : I/O port 0 */
77 #define IO_PORT_0_REG 0x78
78 /* Host Control Registers : I/O port 1 */
79 #define IO_PORT_1_REG 0x79
80 /* Host Control Registers : I/O port 2 */
81 #define IO_PORT_2_REG 0x7A
83 /* Host Control Registers : Configuration */
84 #define CONFIGURATION_REG 0x00
85 /* Host Control Registers : Host power up */
86 #define HOST_POWER_UP (0x1U << 1)
88 /* Host Control Registers : Host interrupt mask */
89 #define HOST_INT_MASK_REG 0x02
90 /* Host Control Registers : Upload host interrupt mask */
91 #define UP_LD_HOST_INT_MASK (0x1U)
92 /* Host Control Registers : Download host interrupt mask */
93 #define DN_LD_HOST_INT_MASK (0x2U)
95 /* Disable Host interrupt mask */
96 #define HOST_INT_DISABLE 0xff
98 /* Host Control Registers : Host interrupt status */
99 #define HOST_INTSTATUS_REG 0x03
100 /* Host Control Registers : Upload host interrupt status */
101 #define UP_LD_HOST_INT_STATUS (0x1U)
102 /* Host Control Registers : Download host interrupt status */
103 #define DN_LD_HOST_INT_STATUS (0x2U)
105 /* Host Control Registers : Host interrupt RSR */
106 #define HOST_INT_RSR_REG 0x01
108 /* Host Control Registers : Host interrupt status */
109 #define HOST_INT_STATUS_REG 0x28
111 /* Card Control Registers : Card I/O ready */
112 #define CARD_IO_READY (0x1U << 3)
113 /* Card Control Registers : Download card ready */
114 #define DN_LD_CARD_RDY (0x1U << 0)
116 /* Max retry number of CMD53 write */
117 #define MAX_WRITE_IOMEM_RETRY 2
119 /* SDIO Tx aggregation in progress ? */
120 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
122 /* SDIO Tx aggregation buffer room for next packet ? */
123 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
124 <= a->mpa_tx.buf_size)
126 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
127 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
128 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
130 a->mpa_tx.buf_len += pkt_len; \
131 if (!a->mpa_tx.pkt_cnt) \
132 a->mpa_tx.start_port = port; \
133 if (a->mpa_tx.start_port <= port) \
134 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
136 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
139 a->mpa_tx.pkt_cnt++; \
142 /* SDIO Tx aggregation limit ? */
143 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
144 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
146 /* Reset SDIO Tx aggregation buffer parameters */
147 #define MP_TX_AGGR_BUF_RESET(a) do { \
148 a->mpa_tx.pkt_cnt = 0; \
149 a->mpa_tx.buf_len = 0; \
150 a->mpa_tx.ports = 0; \
151 a->mpa_tx.start_port = 0; \
154 /* SDIO Rx aggregation limit ? */
155 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
156 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
158 /* SDIO Rx aggregation in progress ? */
159 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
161 /* SDIO Rx aggregation buffer room for next packet ? */
162 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
163 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
165 /* Reset SDIO Rx aggregation buffer parameters */
166 #define MP_RX_AGGR_BUF_RESET(a) do { \
167 a->mpa_rx.pkt_cnt = 0; \
168 a->mpa_rx.buf_len = 0; \
169 a->mpa_rx.ports = 0; \
170 a->mpa_rx.start_port = 0; \
173 /* data structure for SDIO MPA TX */
174 struct mwifiex_sdio_mpa_tx {
175 /* multiport tx aggregation buffer pointer */
186 struct mwifiex_sdio_mpa_rx {
193 struct sk_buff **skb_arr;
201 int mwifiex_bus_register(void);
202 void mwifiex_bus_unregister(void);
204 struct mwifiex_sdio_card_reg {
226 u8 card_misc_cfg_reg;
229 struct sdio_mmc_card {
230 struct sdio_func *func;
231 struct mwifiex_adapter *adapter;
233 const char *firmware;
234 const struct mwifiex_sdio_card_reg *reg;
237 bool supports_sdio_new_mode;
238 bool has_control_mask;
244 u32 mp_data_port_mask;
251 struct mwifiex_sdio_mpa_tx mpa_tx;
252 struct mwifiex_sdio_mpa_rx mpa_rx;
255 struct mwifiex_sdio_device {
256 const char *firmware;
257 const struct mwifiex_sdio_card_reg *reg;
260 bool supports_sdio_new_mode;
261 bool has_control_mask;
264 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
267 .base_0_reg = 0x0040,
268 .base_1_reg = 0x0041,
270 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
271 .status_reg_0 = 0x60,
272 .status_reg_1 = 0x61,
273 .sdio_int_mask = 0x3f,
274 .data_port_mask = 0x0000fffe,
282 .card_misc_cfg_reg = 0x6c,
285 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
291 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
292 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
293 .status_reg_0 = 0xc0,
294 .status_reg_1 = 0xc1,
295 .sdio_int_mask = 0xff,
296 .data_port_mask = 0xffffffff,
300 .rd_bitmap_1l = 0x06,
301 .rd_bitmap_1u = 0x07,
304 .wr_bitmap_1l = 0x0a,
305 .wr_bitmap_1u = 0x0b,
308 .card_misc_cfg_reg = 0xcc,
311 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
312 .firmware = SD8786_DEFAULT_FW_NAME,
313 .reg = &mwifiex_reg_sd87xx,
315 .mp_agg_pkt_limit = 8,
316 .supports_sdio_new_mode = false,
317 .has_control_mask = true,
320 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
321 .firmware = SD8787_DEFAULT_FW_NAME,
322 .reg = &mwifiex_reg_sd87xx,
324 .mp_agg_pkt_limit = 8,
325 .supports_sdio_new_mode = false,
326 .has_control_mask = true,
329 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
330 .firmware = SD8797_DEFAULT_FW_NAME,
331 .reg = &mwifiex_reg_sd87xx,
333 .mp_agg_pkt_limit = 8,
334 .supports_sdio_new_mode = false,
335 .has_control_mask = true,
338 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
339 .firmware = SD8897_DEFAULT_FW_NAME,
340 .reg = &mwifiex_reg_sd8897,
342 .mp_agg_pkt_limit = 16,
343 .supports_sdio_new_mode = true,
344 .has_control_mask = false,
348 * .cmdrsp_complete handler
350 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
353 dev_kfree_skb_any(skb);
358 * .event_complete handler
360 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
363 dev_kfree_skb_any(skb);
368 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
372 if (card->curr_rd_port < card->mpa_rx.start_port) {
373 if (card->supports_sdio_new_mode)
374 tmp = card->mp_end_port >> 1;
376 tmp = card->mp_agg_pkt_limit;
378 if (((card->max_ports - card->mpa_rx.start_port) +
379 card->curr_rd_port) >= tmp)
383 if (!card->supports_sdio_new_mode)
386 if ((card->curr_rd_port - card->mpa_rx.start_port) >=
387 (card->mp_end_port >> 1))
394 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
398 if (card->curr_wr_port < card->mpa_tx.start_port) {
399 if (card->supports_sdio_new_mode)
400 tmp = card->mp_end_port >> 1;
402 tmp = card->mp_agg_pkt_limit;
404 if (((card->max_ports - card->mpa_tx.start_port) +
405 card->curr_wr_port) >= tmp)
409 if (!card->supports_sdio_new_mode)
412 if ((card->curr_wr_port - card->mpa_tx.start_port) >=
413 (card->mp_end_port >> 1))
419 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
420 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
421 struct sk_buff *skb, u8 port)
423 card->mpa_rx.buf_len += skb->len;
425 if (!card->mpa_rx.pkt_cnt)
426 card->mpa_rx.start_port = port;
428 if (card->supports_sdio_new_mode) {
429 card->mpa_rx.ports |= (1 << port);
431 if (card->mpa_rx.start_port <= port)
432 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
434 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
436 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
437 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
438 card->mpa_rx.pkt_cnt++;
440 #endif /* _MWIFIEX_SDIO_H */