arch/arm/boot/dts/vf610.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include "skeleton.dtsi"
  11 #include "vf610-pinfunc.h"
  12 #include <dt-bindings/clock/vf610-clock.h>
  13
  14 / {
  15         aliases {
  16                 serial0 = &uart0;
  17                 serial1 = &uart1;
  18                 serial2 = &uart2;
  19                 serial3 = &uart3;
  20                 serial4 = &uart4;
  21                 serial5 = &uart5;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         compatible = "arm,cortex-a5";
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         next-level-cache = <&L2>;
  38                 };
  39         };
  40
  41         clocks {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 sxosc {
  46                         compatible = "fixed-clock";
  47                         clock-frequency = <32768>;
  48                 };
  49
  50                 fxosc {
  51                         compatible = "fixed-clock";
  52                         clock-frequency = <24000000>;
  53                 };
  54         };
  55
  56         soc {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 compatible = "simple-bus";
  60                 interrupt-parent = <&intc>;
  61                 ranges;
  62
  63                 aips0: aips-bus@40000000 {
  64                         compatible = "fsl,aips-bus", "simple-bus";
  65                         #address-cells = <1>;
  66                         #size-cells = <1>;
  67                         interrupt-parent = <&intc>;
  68                         reg = <0x40000000 0x70000>;
  69                         ranges;
  70
  71                         intc: interrupt-controller@40002000 {
  72                                 compatible = "arm,cortex-a9-gic";
  73                                 #interrupt-cells = <3>;
  74                                 #address-cells = <1>;
  75                                 #size-cells = <1>;
  76                                 interrupt-controller;
  77                                 reg = <0x40003000 0x1000>,
  78                                       <0x40002100 0x100>;
  79                         };
  80
  81                         L2: l2-cache@40006000 {
  82                                 compatible = "arm,pl310-cache";
  83                                 reg = <0x40006000 0x1000>;
  84                                 cache-unified;
  85                                 cache-level = <2>;
  86                                 arm,data-latency = <1 1 1>;
  87                                 arm,tag-latency = <2 2 2>;
  88                         };
  89
  90                         uart0: serial@40027000 {
  91                                 compatible = "fsl,vf610-lpuart";
  92                                 reg = <0x40027000 0x1000>;
  93                                 interrupts = <0 61 0x00>;
  94                                 clocks = <&clks VF610_CLK_UART0>;
  95                                 clock-names = "ipg";
  96                                 status = "disabled";
  97                         };
  98
  99                         uart1: serial@40028000 {
 100                                 compatible = "fsl,vf610-lpuart";
 101                                 reg = <0x40028000 0x1000>;
 102                                 interrupts = <0 62 0x04>;
 103                                 clocks = <&clks VF610_CLK_UART1>;
 104                                 clock-names = "ipg";
 105                                 status = "disabled";
 106                         };
 107
 108                         uart2: serial@40029000 {
 109                                 compatible = "fsl,vf610-lpuart";
 110                                 reg = <0x40029000 0x1000>;
 111                                 interrupts = <0 63 0x04>;
 112                                 clocks = <&clks VF610_CLK_UART2>;
 113                                 clock-names = "ipg";
 114                                 status = "disabled";
 115                         };
 116
 117                         uart3: serial@4002a000 {
 118                                 compatible = "fsl,vf610-lpuart";
 119                                 reg = <0x4002a000 0x1000>;
 120                                 interrupts = <0 64 0x04>;
 121                                 clocks = <&clks VF610_CLK_UART3>;
 122                                 clock-names = "ipg";
 123                                 status = "disabled";
 124                         };
 125
 126                         sai2: sai@40031000 {
 127                                 compatible = "fsl,vf610-sai";
 128                                 reg = <0x40031000 0x1000>;
 129                                 interrupts = <0 86 0x04>;
 130                                 clocks = <&clks VF610_CLK_SAI2>;
 131                                 clock-names = "sai";
 132                                 status = "disabled";
 133                         };
 134
 135                         pit: pit@40037000 {
 136                                 compatible = "fsl,vf610-pit";
 137                                 reg = <0x40037000 0x1000>;
 138                                 interrupts = <0 39 0x04>;
 139                                 clocks = <&clks VF610_CLK_PIT>;
 140                                 clock-names = "pit";
 141                         };
 142
 143                         wdog@4003e000 {
 144                                 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
 145                                 reg = <0x4003e000 0x1000>;
 146                                 clocks = <&clks VF610_CLK_WDT>;
 147                                 clock-names = "wdog";
 148                         };
 149
 150                         qspi0: quadspi@40044000 {
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153                                 compatible = "fsl,vf610-qspi";
 154                                 reg = <0x40044000 0x1000>;
 155                                 interrupts = <0 24 0x04>;
 156                                 clocks = <&clks VF610_CLK_QSPI0_EN>,
 157                                         <&clks VF610_CLK_QSPI0>;
 158                                 clock-names = "qspi_en", "qspi";
 159                                 status = "disabled";
 160                         };
 161
 162                         iomuxc: iomuxc@40048000 {
 163                                 compatible = "fsl,vf610-iomuxc";
 164                                 reg = <0x40048000 0x1000>;
 165                                 #gpio-range-cells = <3>;
 166
 167                                 /* functions and groups pins */
 168
 169                                 dcu0 {
 170                                         pinctrl_dcu0_1: dcu0grp_1 {
 171                                                 fsl,pins = <
 172                                                 VF610_PAD_PTB8__GPIO_30         0x42
 173                                                 VF610_PAD_PTE0__DCU0_HSYNC      0x42
 174                                                 VF610_PAD_PTE1__DCU0_VSYNC      0x42
 175                                                 VF610_PAD_PTE2__DCU0_PCLK       0x42
 176                                                 VF610_PAD_PTE4__DCU0_DE         0x42
 177                                                 VF610_PAD_PTE5__DCU0_R0         0x42
 178                                                 VF610_PAD_PTE6__DCU0_R1         0x42
 179                                                 VF610_PAD_PTE7__DCU0_R2         0x42
 180                                                 VF610_PAD_PTE8__DCU0_R3         0x42
 181                                                 VF610_PAD_PTE9__DCU0_R4         0x42
 182                                                 VF610_PAD_PTE10__DCU0_R5        0x42
 183                                                 VF610_PAD_PTE11__DCU0_R6        0x42
 184                                                 VF610_PAD_PTE12__DCU0_R7        0x42
 185                                                 VF610_PAD_PTE13__DCU0_G0        0x42
 186                                                 VF610_PAD_PTE14__DCU0_G1        0x42
 187                                                 VF610_PAD_PTE15__DCU0_G2        0x42
 188                                                 VF610_PAD_PTE16__DCU0_G3        0x42
 189                                                 VF610_PAD_PTE17__DCU0_G4        0x42
 190                                                 VF610_PAD_PTE18__DCU0_G5        0x42
 191                                                 VF610_PAD_PTE19__DCU0_G6        0x42
 192                                                 VF610_PAD_PTE20__DCU0_G7        0x42
 193                                                 VF610_PAD_PTE21__DCU0_B0        0x42
 194                                                 VF610_PAD_PTE22__DCU0_B1        0x42
 195                                                 VF610_PAD_PTE23__DCU0_B2        0x42
 196                                                 VF610_PAD_PTE24__DCU0_B3        0x42
 197                                                 VF610_PAD_PTE25__DCU0_B4        0x42
 198                                                 VF610_PAD_PTE26__DCU0_B5        0x42
 199                                                 VF610_PAD_PTE27__DCU0_B6        0x42
 200                                                 VF610_PAD_PTE28__DCU0_B7        0x42
 201                                                 >;
 202                                         };
 203                                 };
 204
 205                                 dspi0 {
 206                                         pinctrl_dspi0_1: dspi0grp_1 {
 207                                                 fsl,pins = <
 208                                                 VF610_PAD_PTB19__DSPI0_CS0      0x1182
 209                                                 VF610_PAD_PTB20__DSPI0_SIN      0x1181
 210                                                 VF610_PAD_PTB21__DSPI0_SOUT     0x1182
 211                                                 VF610_PAD_PTB22__DSPI0_SCK      0x1182
 212                                                 >;
 213                                         };
 214                                 };
 215
 216                                 esdhc1 {
 217                                         pinctrl_esdhc1_1: esdhc1grp_1 {
 218                                                 fsl,pins = <
 219                                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
 220                                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
 221                                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
 222                                                 VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
 223                                                 VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
 224                                                 VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
 225                                                 VF610_PAD_PTA7__GPIO_134        0x219d
 226                                                 >;
 227                                         };
 228                                 };
 229
 230                                 fec0 {
 231                                         pinctrl_fec0_1: fec0grp_1 {
 232                                                 fsl,pins = <
 233                                                 VF610_PAD_PTA6__RMII_CLKIN      0x30d1
 234                                                 VF610_PAD_PTC0__ENET_RMII0_MDC  0x30d3
 235                                                 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
 236                                                 VF610_PAD_PTC2__ENET_RMII0_CRS  0x30d1
 237                                                 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
 238                                                 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
 239                                                 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
 240                                                 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
 241                                                 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
 242                                                 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
 243                                                 >;
 244                                         };
 245                                 };
 246
 247                                 fec1 {
 248                                         pinctrl_fec1_1: fec1grp_1 {
 249                                                 fsl,pins = <
 250                                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 251                                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 252                                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 253                                                 VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
 254                                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 255                                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 256                                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 257                                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 258                                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 259                                                 >;
 260                                         };
 261                                 };
 262
 263                                 i2c0 {
 264                                         pinctrl_i2c0_1: i2c0grp_1 {
 265                                                 fsl,pins = <
 266                                                 VF610_PAD_PTB14__I2C0_SCL       0x30d3
 267                                                 VF610_PAD_PTB15__I2C0_SDA       0x30d3
 268                                                 >;
 269                                         };
 270                                 };
 271
 272                                 pwm0 {
 273                                         pinctrl_pwm0_1: pwm0grp_1 {
 274                                                 fsl,pins = <
 275                                                 VF610_PAD_PTB0__FTM0_CH0        0x1582
 276                                                 VF610_PAD_PTB1__FTM0_CH1        0x1582
 277                                                 VF610_PAD_PTB2__FTM0_CH2        0x1582
 278                                                 VF610_PAD_PTB3__FTM0_CH3        0x1582
 279                                                 VF610_PAD_PTB6__FTM0_CH6        0x1582
 280                                                 VF610_PAD_PTB7__FTM0_CH7        0x1582
 281                                                 >;
 282                                         };
 283                                 };
 284
 285                                 qspi0 {
 286                                         pinctrl_qspi0_1: qspi0grp_1 {
 287                                                 fsl,pins = <
 288                                                 VF610_PAD_PTD0__QSPI0_A_QSCK    0x307b
 289                                                 VF610_PAD_PTD1__QSPI0_A_CS0     0x307f
 290                                                 VF610_PAD_PTD2__QSPI0_A_DATA3   0x3073
 291                                                 VF610_PAD_PTD3__QSPI0_A_DATA2   0x3073
 292                                                 VF610_PAD_PTD4__QSPI0_A_DATA1   0x3073
 293                                                 VF610_PAD_PTD5__QSPI0_A_DATA0   0x307b
 294                                                 VF610_PAD_PTD7__QSPI0_B_QSCK    0x307b
 295                                                 VF610_PAD_PTD8__QSPI0_B_CS0     0x307f
 296                                                 VF610_PAD_PTD9__QSPI0_B_DATA3   0x3073
 297                                                 VF610_PAD_PTD10__QSPI0_B_DATA2  0x3073
 298                                                 VF610_PAD_PTD11__QSPI0_B_DATA1  0x3073
 299                                                 VF610_PAD_PTD12__QSPI0_B_DATA0  0x307b
 300                                                 >;
 301                                         };
 302                                 };
 303
 304                                 sai2 {
 305                                         pinctrl_sai2_1: sai2grp_1 {
 306                                                 fsl,pins = <
 307                                                 VF610_PAD_PTA16__SAI2_TX_BCLK   0x02ed
 308                                                 VF610_PAD_PTA18__SAI2_TX_DATA   0x02ee
 309                                                 VF610_PAD_PTA19__SAI2_TX_SYNC   0x02ed
 310                                                 VF610_PAD_PTA21__SAI2_RX_BCLK   0x02ed
 311                                                 VF610_PAD_PTA22__SAI2_RX_DATA   0x02ed
 312                                                 VF610_PAD_PTA23__SAI2_RX_SYNC   0x02ed
 313                                                 VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
 314                                                 >;
 315                                         };
 316                                 };
 317
 318                                 uart1 {
 319                                         pinctrl_uart1_1: uart1grp_1 {
 320                                                 fsl,pins = <
 321                                                 VF610_PAD_PTB4__UART1_TX        0x21a2
 322                                                 VF610_PAD_PTB5__UART1_RX        0x21a1
 323                                                 >;
 324                                         };
 325                                 };
 326
 327                                 usbvbus {
 328                                         pinctrl_usbvbus_1: usbvbusgrp_1 {
 329                                                 fsl,pins = <
 330                                                 VF610_PAD_PTA24__USB1_VBUS_EN   0x219c
 331                                                 VF610_PAD_PTA16__USB0_VBUS_EN   0x219c
 332                                                 >;
 333                                         };
 334                                 };
 335
 336                         };
 337
 338                         gpio1: gpio@40049000 {
 339                                 compatible = "fsl,vf610-gpio";
 340                                 reg = <0x40049000 0x1000 0x400ff000 0x40>;
 341                                 interrupts = <0 107 0x04>;
 342                                 gpio-controller;
 343                                 #gpio-cells = <2>;
 344                                 interrupt-controller;
 345                                 #interrupt-cells = <2>;
 346                                 gpio-ranges = <&iomuxc 0 0 32>;
 347                         };
 348
 349                         gpio2: gpio@4004a000 {
 350                                 compatible = "fsl,vf610-gpio";
 351                                 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
 352                                 interrupts = <0 108 0x04>;
 353                                 gpio-controller;
 354                                 #gpio-cells = <2>;
 355                                 interrupt-controller;
 356                                 #interrupt-cells = <2>;
 357                                 gpio-ranges = <&iomuxc 0 32 32>;
 358                         };
 359
 360                         gpio3: gpio@4004b000 {
 361                                 compatible = "fsl,vf610-gpio";
 362                                 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
 363                                 interrupts = <0 109 0x04>;
 364                                 gpio-controller;
 365                                 #gpio-cells = <2>;
 366                                 interrupt-controller;
 367                                 #interrupt-cells = <2>;
 368                                 gpio-ranges = <&iomuxc 0 64 32>;
 369                         };
 370
 371                         gpio4: gpio@4004c000 {
 372                                 compatible = "fsl,vf610-gpio";
 373                                 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
 374                                 interrupts = <0 110 0x04>;
 375                                 gpio-controller;
 376                                 #gpio-cells = <2>;
 377                                 interrupt-controller;
 378                                 #interrupt-cells = <2>;
 379                                 gpio-ranges = <&iomuxc 0 96 32>;
 380                         };
 381
 382                         gpio5: gpio@4004d000 {
 383                                 compatible = "fsl,vf610-gpio";
 384                                 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
 385                                 interrupts = <0 111 0x04>;
 386                                 gpio-controller;
 387                                 #gpio-cells = <2>;
 388                                 interrupt-controller;
 389                                 #interrupt-cells = <2>;
 390                                 gpio-ranges = <&iomuxc 0 128 7>;
 391                         };
 392
 393                         anatop@40050000 {
 394                                 compatible = "fsl,vf610-anatop";
 395                                 reg = <0x40050000 0x1000>;
 396                         };
 397
 398                         i2c0: i2c@40066000 {
 399                                 #address-cells = <1>;
 400                                 #size-cells = <0>;
 401                                 compatible = "fsl,vf610-i2c";
 402                                 reg = <0x40066000 0x1000>;
 403                                 interrupts =<0 71 0x04>;
 404                                 clocks = <&clks VF610_CLK_I2C0>;
 405                                 clock-names = "ipg";
 406                                 status = "disabled";
 407                         };
 408
 409                         clks: ccm@4006b000 {
 410                                 compatible = "fsl,vf610-ccm";
 411                                 reg = <0x4006b000 0x1000>;
 412                                 #clock-cells = <1>;
 413                         };
 414                 };
 415
 416                 aips1: aips-bus@40080000 {
 417                         compatible = "fsl,aips-bus", "simple-bus";
 418                         #address-cells = <1>;
 419                         #size-cells = <1>;
 420                         reg = <0x40080000 0x80000>;
 421                         ranges;
 422
 423                         uart4: serial@400a9000 {
 424                                 compatible = "fsl,vf610-lpuart";
 425                                 reg = <0x400a9000 0x1000>;
 426                                 interrupts = <0 65 0x04>;
 427                                 clocks = <&clks VF610_CLK_UART4>;
 428                                 clock-names = "ipg";
 429                                 status = "disabled";
 430                         };
 431
 432                         uart5: serial@400aa000 {
 433                                 compatible = "fsl,vf610-lpuart";
 434                                 reg = <0x400aa000 0x1000>;
 435                                 interrupts = <0 66 0x04>;
 436                                 clocks = <&clks VF610_CLK_UART5>;
 437                                 clock-names = "ipg";
 438                                 status = "disabled";
 439                         };
 440
 441                         fec0: ethernet@400d0000 {
 442                                 compatible = "fsl,mvf600-fec";
 443                                 reg = <0x400d0000 0x1000>;
 444                                 interrupts = <0 78 0x04>;
 445                                 clocks = <&clks VF610_CLK_ENET>,
 446                                         <&clks VF610_CLK_ENET>,
 447                                         <&clks VF610_CLK_ENET>;
 448                                 clock-names = "ipg", "ahb", "ptp";
 449                                 status = "disabled";
 450                         };
 451
 452                         fec1: ethernet@400d1000 {
 453                                 compatible = "fsl,mvf600-fec";
 454                                 reg = <0x400d1000 0x1000>;
 455                                 interrupts = <0 79 0x04>;
 456                                 clocks = <&clks VF610_CLK_ENET>,
 457                                         <&clks VF610_CLK_ENET>,
 458                                         <&clks VF610_CLK_ENET>;
 459                                 clock-names = "ipg", "ahb", "ptp";
 460                                 status = "disabled";
 461                         };
 462                 };
 463         };
 464 };