arch/arm/mach-mx5/mx53_vmx.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/sched.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/irq.h>
  27 #include <linux/init.h>
  28 #include <linux/input.h>
  29 #include <linux/nodemask.h>
  30 #include <linux/clk.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/fsl_devices.h>
  33 #include <linux/spi/spi.h>
  34 #include <linux/i2c.h>
  35 #include <linux/ata.h>
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/map.h>
  38 #include <linux/mtd/partitions.h>
  39 #include <linux/regulator/consumer.h>
  40 #include <linux/android_pmem.h>
  41 #include <linux/usb/android_composite.h>
  42 #include <linux/pmic_external.h>
  43 #include <linux/pmic_status.h>
  44 #include <linux/ipu.h>
  45 #include <linux/mxcfb.h>
  46 #include <linux/pwm_backlight.h>
  47 #include <linux/fec.h>
  48 #include <linux/powerkey.h>
  49 #include <linux/ahci_platform.h>
  50 #include <linux/gpio_keys.h>
  51 #include <linux/mfd/da9052/da9052.h>
  52 #include <mach/common.h>
  53 #include <mach/hardware.h>
  54 #include <asm/irq.h>
  55 #include <asm/setup.h>
  56 #include <asm/mach-types.h>
  57 #include <asm/mach/arch.h>
  58 #include <asm/mach/time.h>
  59 #include <asm/mach/keypad.h>
  60 #include <asm/mach/flash.h>
  61 #include <mach/spi.h>
  62 #include <mach/memory.h>
  63 #include <mach/gpio.h>
  64 #include <mach/mmc.h>
  65 #include <mach/mxc_dvfs.h>
  66 #include <mach/iomux-mx53.h>
  67 #include <mach/i2c.h>
  68 #include <linux/i2c/at24.h>
  69 #include <mach/mxc_iim.h>
  70 #include <mach/check_fuse.h>
  71 #include <linux/spi/ads7846.h>
  72 #include <linux/can/platform/mcp251x.h>
  73
  74 #include "crm_regs.h"
  75 #include "devices.h"
  76 #include "usb.h"
  77 #include "pmic.h"
  78
  79 // Fix spi and nand naming collision
  80 //#include <linux/spi/flash.h>
  81 struct spi_flash_platform_data {
  82         char            *name;
  83         struct mtd_partition *parts;
  84         unsigned int    nr_parts;
  85         char            *type;
  86 };
  87 /*!
  88  * @file mach-mx5/mx53_loco.c
  89  *
  90  * @brief This file contains MX53 loco board specific initialization routines.
  91  *
  92  * @ingroup MSL_MX53
  93  */
  94
  95 /* MX53 LOCO GPIO PIN configurations */
  96 //#define NVDD_FAULT                    (0*32 + 5)      /* GPIO1_5 */
  97
  98 //#define FEC_INT                               (1*32 + 4)      /* GPIO_2_4 */
  99 //#define HEADPHONE_DEC_B               (1*32 + 5)      /* GPIO_2_5 */
 100 //#define MIC_DEC_B                     (1*32 + 6)      /* GPIO_2_6 */
 101 //#define USER_UI1                      (1*32 + 14)     /* GPIO_2_14 */
 102 //#define USER_UI2                      (1*32 + 15)     /* GPIO_2_15 */
 103 //#define MX53_nONKEY                   (0*32 + 8)      /* GPIO_1_8 */
 104
 105 //#define SD3_CD                                (2*32 + 11)     /* GPIO_3_11 */
 106 //#define SD3_WP                                (2*32 + 12)     /* GPIO_3_12 */
 107 //#define DISP0_POWER_EN                (2*32 + 24)     /* GPIO_3_24 */
 108 //#define DISP0_DET_INT         (2*32 + 31)     /* GPIO_3_31 */
 109
 110 //#define DISP0_RESET                   (4*32 + 0)      /* GPIO_5_0 */
 111
 112 //#define CSI0_RTSB                     (5*32 + 9)      /* GPIO_6_9 */
 113 //#define CSI0_PWDN                     (5*32 + 10)     /* GPIO_6_10 */
 114 //#define ACCL_EN                               (5*32 + 14)     /* GPIO_6_14 */
 115 //#define ACCL_INT1_IN          (5*32 + 15)     /* GPIO_6_15 */
 116 //#define ACCL_INT2_IN          (5*32 + 16)     /* GPIO_6_16 */
 117
 118 //#define LCD_BLT_EN                    (6*32 + 2)      /* GPIO_7_2 */
 119 //#define FEC_RST                               (6*32 + 6)      /* GPIO_7_6 */
 120 //#define USER_LED_EN                   (6*32 + 7)      /* GPIO_7_7 */
 121 //#define USB_PWREN                     (6*32 + 8)      /* GPIO_7_8 */
 122 //#define NIRQ                          (6*32 + 11)     /* GPIO7_11 */
 123 //#define MX53_LOCO_MC34708_IRQ_REVA    (4*32 + 30)     /* GPIO5_30 */
 124 //#define MX53_LOCO_MC34708_IRQ_REVB    (4*32 + 23)     /* GPIO5_23 */
 125
 126 #define MX53_OFFSET                                     (0x20000000)
 127 #define TZIC_WAKEUP0_OFFSET         (0x0E00)
 128 #define TZIC_WAKEUP1_OFFSET         (0x0E04)
 129 #define TZIC_WAKEUP2_OFFSET         (0x0E08)
 130 #define TZIC_WAKEUP3_OFFSET         (0x0E0C)
 131 #define GPIO7_0_11_IRQ_BIT                      (0x1<<11)
 132
 133
 134 #define IMX_GPIO_NR(bank, nr)           (((bank) - 1) * 32 + (nr))
 135
 136 // SD/MMC
 137 #define VMX53_SD1_SEL           IMX_GPIO_NR(4, 0)
 138 #define VMX53_SD1_CD            IMX_GPIO_NR(3, 24)
 139 //#define VMX53_SD1_WP
 140 #define VMX53_SD2_CD            IMX_GPIO_NR(3, 25)
 141 #define VMX53_SD2_WP            IMX_GPIO_NR(2, 19)
 142
 143 // FEC
 144 #define VMX53_FEC_PEN           IMX_GPIO_NR(4, 1)
 145 #define VMX53_FEC_RST           IMX_GPIO_NR(4, 2)
 146
 147 // PMIC
 148 #define VMX53_nVDD_FAULT        IMX_GPIO_NR(4, 3)
 149 #define VMX53_nONKEY            IMX_GPIO_NR(4, 4)
 150 #define VMX53_nIRQ              IMX_GPIO_NR(7, 11)
 151
 152 // GPIO LED
 153 #define VMX53_DISP0_PEN         IMX_GPIO_NR(5, 4)
 154 #define VMX53_LED_RED           IMX_GPIO_NR(3, 29)
 155 #define VMX53_LED_ORANGE        IMX_GPIO_NR(2, 31)
 156
 157 // SPI
 158 #define VMX53_ECSPI1_CS0        IMX_GPIO_NR(2, 30)
 159 #define VMX53_ECSPI1_CS1        IMX_GPIO_NR(3, 19)
 160 #define VMX53_TSC2046_IRQ       IMX_GPIO_NR(2, 20)
 161 #define VMX53_TSC2046_CS        IMX_GPIO_NR(2, 16)
 162 #define VMX53_MCP2515_IRQ       IMX_GPIO_NR(2, 21)
 163 #define VMX53_MCP2515_CS        IMX_GPIO_NR(2, 17)
 164
 165 // I2C_INT
 166 #define VMX53_I2C_INT           IMX_GPIO_NR(6, 15)
 167
 168 // USB
 169 #define VMX53_USBH1_PEN         IMX_GPIO_NR(3, 31)
 170 #define VMX53_USBH1_OC          IMX_GPIO_NR(3, 30)
 171 #define VMX53_USBO_PEN          IMX_GPIO_NR(1, 7)
 172 #define VMX53_USBO_OC           IMX_GPIO_NR(1, 8)
 173
 174 // ACCL
 175 #define VMX53_ACCL_INT1         IMX_GPIO_NR(3, 20)
 176 #define VMX53_ACCL_INT2         IMX_GPIO_NR(5, 2)
 177
 178 extern void pm_i2c_init(u32 base_addr);
 179 //static u32 mx53_loco_mc34708_irq;
 180 static iomux_v3_cfg_t mx53_loco_pads[] = {
 181         /* UART1 */
 182         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
 183         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
 184         MX53_PAD_PATA_IORDY__UART1_RTS,
 185         MX53_PAD_PATA_RESET_B__UART1_CTS,
 186
 187         /* UART2 */
 188         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
 189         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
 190         MX53_PAD_PATA_DIOR__UART2_RTS,
 191         MX53_PAD_PATA_INTRQ__UART2_CTS,
 192
 193         /* UART3 */
 194         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
 195         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
 196         MX53_PAD_PATA_DA_2__UART3_RTS,
 197         MX53_PAD_PATA_DA_1__UART3_CTS,
 198
 199         /* FEC */
 200         MX53_PAD_FEC_MDC__FEC_MDC,
 201         MX53_PAD_FEC_MDIO__FEC_MDIO,
 202         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 203         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 204         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 205         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 206         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 207         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 208         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 209         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 210
 211         /* SSI1 = AUDMUX5 */
 212         MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
 213         MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
 214         MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
 215         MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
 216
 217         /* SSI2 */
 218         MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC,
 219         MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD,
 220         MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS,
 221         MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD,
 222
 223         /* ECSPI */
 224         MX53_PAD_EIM_D16__ECSPI1_SCLK,
 225         MX53_PAD_EIM_D17__ECSPI1_MISO,
 226         MX53_PAD_EIM_D18__ECSPI1_MOSI,
 227 //      MX53_PAD_GPIO_19__ECSPI1_RDY,
 228         MX53_PAD_GPIO_19__GPIO4_5,
 229 //      MX53_PAD_EIM_D19__ECSPI1_SS1,
 230 //      MX53_PAD_EIM_EB2__ECSPI1_SS0,
 231
 232         /* I2C1 */
 233 #define VMX53_PAD_EIM_D21__I2C1_SCL                     IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
 234 #define VMX53_PAD_EIM_D28__I2C1_SDA                     IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL)
 235
 236         VMX53_PAD_EIM_D21__I2C1_SCL,
 237         VMX53_PAD_EIM_D28__I2C1_SDA,
 238         /* I2C3 */
 239 #define VMX53_PAD_GPIO_3__I2C3_SCL                      IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
 240 #define VMX53_PAD_GPIO_6__I2C3_SDA                      IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
 241
 242         VMX53_PAD_GPIO_3__I2C3_SCL,
 243         VMX53_PAD_GPIO_6__I2C3_SDA,
 244
 245         /* KEYPAD */
 246 #define VMX53_PAD_KEY_COL2__KPP_COL_2            (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE))
 247 #define VMX53_PAD_KEY_COL3__KPP_COL_3            (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE))
 248 #define VMX53_PAD_KEY_COL4__KPP_COL_4            (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE))
 249 #define VMX53_PAD_GPIO_9__KPP_COL_6              (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE))
 250 #define VMX53_PAD_GPIO_4__KPP_COL_7              (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE))
 251
 252 #define VMX53_PAD_KEY_ROW2__KPP_ROW_2            (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP))
 253 #define VMX53_PAD_KEY_ROW3__KPP_ROW_3            (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP))
 254 #define VMX53_PAD_KEY_ROW4__KPP_ROW_4            (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP))
 255 #define VMX53_PAD_GPIO_2__KPP_ROW_6              (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP))
 256 #define VMX53_PAD_GPIO_5__KPP_ROW_7              (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP))
 257
 258         VMX53_PAD_GPIO_9__KPP_COL_6,
 259         VMX53_PAD_GPIO_4__KPP_COL_7,
 260         VMX53_PAD_KEY_COL2__KPP_COL_2,
 261         VMX53_PAD_KEY_COL3__KPP_COL_3,
 262         VMX53_PAD_KEY_COL4__KPP_COL_4,
 263         VMX53_PAD_GPIO_2__KPP_ROW_6,
 264         VMX53_PAD_GPIO_5__KPP_ROW_7,
 265         VMX53_PAD_KEY_ROW2__KPP_ROW_2,
 266         VMX53_PAD_KEY_ROW3__KPP_ROW_3,
 267         VMX53_PAD_KEY_ROW4__KPP_ROW_4,
 268
 269         /* SD1 */
 270         MX53_PAD_SD1_CMD__ESDHC1_CMD,
 271         MX53_PAD_SD1_CLK__ESDHC1_CLK,
 272         MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
 273         MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
 274         MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
 275         MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
 276
 277         /* SD2 */
 278         MX53_PAD_SD2_CMD__ESDHC2_CMD,
 279         MX53_PAD_SD2_CLK__ESDHC2_CLK,
 280         MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
 281         MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
 282         MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
 283         MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
 284
 285         /* CSI0 */
 286         MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
 287         MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
 288         MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
 289         MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
 290         MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
 291         MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
 292         MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
 293         MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
 294         MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
 295         MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
 296         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
 297         MX53_PAD_GPIO_0__CCM_CLKO,      // CSI0_MCLK
 298
 299         /* DISPLAY */
 300         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 301         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 302         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 303         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 304         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 305         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 306         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 307         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 308         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 309         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 310         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 311         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 312         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 313         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 314         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 315         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 316         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 317         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 318         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 319         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 320         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 321         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 322         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 323         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 324         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 325         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 326         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 327         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 328
 329         /* PWM */
 330 //      MX53_PAD_GPIO_1__GPIO1_1,
 331         MX53_PAD_GPIO_1__PWM2_PWMO,
 332
 333         /* OWIRE */
 334         MX53_PAD_GPIO_18__OWIRE_LINE,
 335
 336         /* GPIO */
 337         MX53_PAD_GPIO_13__GPIO4_3,      // DA9053 nVDD_FAULT
 338         MX53_PAD_GPIO_14__GPIO4_4,      // nONKEY
 339         MX53_PAD_GPIO_16__GPIO7_11,     // DA9053 nIRQ
 340
 341         MX53_PAD_EIM_A24__GPIO5_4,      // PSAVE
 342         MX53_PAD_EIM_D29__GPIO3_29,     // LED RED
 343         MX53_PAD_EIM_EB3__GPIO2_31,     // LED ORANGE
 344
 345         MX53_PAD_EIM_D20__GPIO3_20,     // ACCL_INT1
 346         MX53_PAD_EIM_A25__GPIO5_2,      // ACCL_INT2
 347
 348         MX53_PAD_GPIO_10__GPIO4_0,      // SD1_SEL
 349         MX53_PAD_EIM_D24__GPIO3_24,     // SD1_CD
 350         MX53_PAD_EIM_D25__GPIO3_25,     // SD2_CD
 351         MX53_PAD_EIM_A19__GPIO2_19,     // SD2_WP
 352
 353         MX53_PAD_GPIO_11__GPIO4_1,      // FEC_PEN
 354         MX53_PAD_GPIO_12__GPIO4_2,      // FEC_RST
 355
 356         MX53_PAD_EIM_D19__GPIO3_19,     // SS1
 357         MX53_PAD_EIM_EB2__GPIO2_30,     // SS0
 358         MX53_PAD_EIM_A18__GPIO2_20,     // TSC2046_IRQ
 359         MX53_PAD_EIM_A17__GPIO2_21,     // MCP2515_IRQ
 360         MX53_PAD_EIM_A22__GPIO2_16,     // TSC2046_CS
 361         MX53_PAD_EIM_A21__GPIO2_17,     // MCP2515_CS
 362
 363         MX53_PAD_NANDF_CS2__GPIO6_15,   // I2C_INT
 364
 365         MX53_PAD_EIM_D26__GPIO3_26,     // SSI1_INT
 366         MX53_PAD_EIM_D27__GPIO3_27,     // SSI2_INT
 367
 368         MX53_PAD_EIM_D31__GPIO3_31,     // USBH1_PEN
 369         MX53_PAD_EIM_D30__GPIO3_30,     // USBH1_OC
 370         MX53_PAD_GPIO_7__GPIO1_7,       // USB0_PEN
 371         MX53_PAD_GPIO_8__GPIO1_8,       // USB0_OC
 372
 373 };
 374
 375 static void loco_da9053_irq_wakeup_only_fixup(void)
 376 {
 377         void __iomem *tzic_base;
 378         tzic_base = ioremap(MX53_TZIC_BASE_ADDR, SZ_4K);
 379         if (NULL == tzic_base) {
 380                 pr_err("fail to map MX53_TZIC_BASE_ADDR\n");
 381                 return;
 382         }
 383         __raw_writel(0, tzic_base + TZIC_WAKEUP0_OFFSET);
 384         __raw_writel(0, tzic_base + TZIC_WAKEUP1_OFFSET);
 385         __raw_writel(0, tzic_base + TZIC_WAKEUP2_OFFSET);
 386         /* only enable irq wakeup for da9053 */
 387         __raw_writel(GPIO7_0_11_IRQ_BIT, tzic_base + TZIC_WAKEUP3_OFFSET);
 388         iounmap(tzic_base);
 389         pr_info("only da9053 irq is wakeup-enabled\n");
 390 }
 391
 392 static void loco_suspend_enter(void)
 393 {
 394 //      if (!board_is_mx53_loco_mc34708()) {
 395                 loco_da9053_irq_wakeup_only_fixup();
 396                 da9053_suspend_cmd_sw();
 397 //      }
 398 }
 399
 400 static void loco_suspend_exit(void)
 401 {
 402 //      if (!board_is_mx53_loco_mc34708()) {
 403                 if (da9053_get_chip_version())
 404                         da9053_restore_volt_settings();
 405 //      }
 406 }
 407
 408 static struct mxc_pm_platform_data loco_pm_data = {
 409         .suspend_enter = loco_suspend_enter,
 410         .suspend_exit = loco_suspend_exit,
 411 };
 412
 413 static struct fb_videomode video_modes[] = {
 414         {
 415          .name = "VGA",
 416          .refresh = 60,
 417          .xres =  640,
 418          .yres = 480,
 419          .pixclock = KHZ2PICOS(25175),
 420          .left_margin = 48,
 421          .right_margin = 16,
 422          .upper_margin = 33,
 423          .lower_margin = 10,
 424          .hsync_len = 96,
 425          .vsync_len = 2,
 426          .sync = 0,
 427          .vmode = FB_VMODE_NONINTERLACED,
 428          .flag = 0,
 429         },
 430         {
 431          .name = "SVGA",
 432          .refresh = 60,
 433          .xres =  800,
 434          .yres = 600,
 435          .pixclock = KHZ2PICOS(40000),
 436          .left_margin = 88,
 437          .right_margin = 40,
 438          .upper_margin = 23,
 439          .lower_margin = 2,
 440          .hsync_len = 128,
 441          .vsync_len = 5,
 442          .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 443          .vmode = FB_VMODE_NONINTERLACED,
 444          .flag = 0,
 445         },
 446         {
 447          .name = "XGA",
 448          .refresh = 60,
 449          .xres =  1024,
 450          .yres = 768,
 451          .pixclock = KHZ2PICOS(65000),
 452          .left_margin = 160,
 453          .right_margin = 24,
 454          .upper_margin = 29,
 455          .lower_margin = 3,
 456          .hsync_len = 136,
 457          .vsync_len = 6,
 458          .sync = 0,
 459          .vmode = FB_VMODE_NONINTERLACED,
 460          .flag = 0,
 461         },
 462         {
 463         /* VGA 1280x1024 108M pixel clk output */
 464         "SXGA", 60, 1280, 1024, 9259,
 465         48, 248,
 466         1, 38,
 467         112, 3,
 468         0,
 469         FB_VMODE_NONINTERLACED,
 470         0,},
 471         {
 472         /* 1600x1200 @ 60 Hz 162M pixel clk*/
 473         "UXGA", 60, 1600, 1200, 6172,
 474         304, 64,
 475         1, 46,
 476         192, 3,
 477         FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
 478         FB_VMODE_NONINTERLACED,
 479         0,},
 480         {
 481          .name = "WXGA",
 482          .refresh = 60,
 483          .xres =  1280,
 484          .yres = 800,
 485          .pixclock = KHZ2PICOS(83460),
 486          .left_margin = 200,
 487          .right_margin = 64,
 488          .upper_margin = 24,
 489          .lower_margin = 1,
 490          .hsync_len = 136,
 491          .vsync_len = 3,
 492          .sync = FB_SYNC_VERT_HIGH_ACT,
 493          .vmode = FB_VMODE_NONINTERLACED,
 494          .flag = 0,
 495         },
 496         {
 497          /* NTSC TV output */
 498          "TV-NTSC", 60, 720, 480, 74074,
 499          122, 15,
 500          18, 26,
 501          1, 1,
 502          FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 503          FB_VMODE_INTERLACED,
 504          0,},
 505         {
 506          /* PAL TV output */
 507          "TV-PAL", 50, 720, 576, 74074,
 508          132, 11,
 509          22, 26,
 510          1, 1,
 511          FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 512          FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
 513          0,},
 514         {
 515          /* 1080i50 TV output */
 516          "1080I50", 50, 1920, 1080, 13468,
 517          192, 527,
 518          20, 24,
 519          1, 1,
 520          FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 521          FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
 522          0,},
 523         {
 524          /* 1080i60 TV output */
 525          "1080I60", 60, 1920, 1080, 13468,
 526          192, 87,
 527          20, 24,
 528          1, 1,
 529          FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 530          FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
 531          0,},
 532         {
 533          /* 800x480 @ 57 Hz , pixel clk @ 27MHz */
 534          "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
 535          FB_SYNC_CLK_LAT_FALL,
 536          FB_VMODE_NONINTERLACED,
 537          0,},
 538         {
 539          /* 800x480 @ 60 Hz , pixel clk @ 32MHz */
 540          "SEIKO-WVGA", 60, 800, 480, 29850, 89, 164, 23, 10, 10, 10,
 541          FB_SYNC_CLK_LAT_FALL,
 542          FB_VMODE_NONINTERLACED,
 543          0,},
 544         {
 545          /* 720p30 TV output */
 546          "720P30", 30, 1280, 720, 13468,
 547          260, 1759,
 548          25, 4,
 549          1, 1,
 550          FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 551          FB_VMODE_NONINTERLACED,
 552          0,},
 553         {
 554         /* "1280x720-58" */
 555          "720P60", 60, 1280, 720, 13888,
 556          220, 110,
 557          20, 5,
 558          40, 5,
 559
 560          FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 561          FB_VMODE_NONINTERLACED,
 562          0,},
 563         {
 564          /* 1080p24 TV output */
 565          "1080P24", 24, 1920, 1080, 13468,
 566          192, 637,
 567          38, 6,
 568          1, 1,
 569          FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 570          FB_VMODE_NONINTERLACED,
 571          0,},
 572         {
 573          /* 1080p25 TV output */
 574          "1080P25", 25, 1920, 1080, 13468,
 575          192, 527,
 576          38, 6,
 577          1, 1,
 578          FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 579          FB_VMODE_NONINTERLACED,
 580          0,},
 581         {
 582          /* 1080p30 TV output */
 583          "1080P30", 30, 1920, 1080, 13468,
 584          192, 87,
 585          38, 6,
 586          1, 1,
 587          FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 588          FB_VMODE_NONINTERLACED,
 589          0,},
 590         {
 591          "1080P60", 60, 1920, 1080, 7692,
 592          100, 40,
 593          30, 3,
 594          10, 2,
 595          0,
 596          FB_VMODE_NONINTERLACED,
 597          0,},
 598         {
 599          // FG0700K5DSSWAGT1
 600          .name = "DATAIMAGE",
 601          .refresh = 59,
 602          .xres =  800,
 603          .yres = 480,
 604          .pixclock = KHZ2PICOS(33260),
 605          .left_margin = 160,
 606          .right_margin = 54,
 607          .upper_margin = 10,
 608          .lower_margin = 10,
 609          .hsync_len = 86,
 610          .vsync_len = 4,
 611          .sync = FB_SYNC_CLK_LAT_FALL,
 612          .vmode = FB_VMODE_NONINTERLACED,
 613          .flag = 0,
 614         },
 615         {
 616          // t-51750gd065j-lw
 617          .name = "OPTREX",
 618          .refresh = 59,
 619          .xres =  640,
 620          .yres = 480,
 621          .pixclock = KHZ2PICOS(24000),
 622          .left_margin = 84,
 623          .right_margin = 10,
 624          .upper_margin = 20,
 625          .lower_margin = 20,
 626          .hsync_len = 34,
 627          .vsync_len = 5,
 628          .sync = FB_SYNC_CLK_LAT_FALL,
 629          .vmode = FB_VMODE_NONINTERLACED,
 630          .flag = 0,
 631         },
 632         {
 633          // BRAVIA 1360x768@56
 634          .name = "BRAVIA",
 635          .refresh = 56,
 636          .xres =  1360,
 637          .yres = 768,
 638          .pixclock = KHZ2PICOS(80141),
 639          .left_margin = 240,
 640          .right_margin = 80,
 641          .upper_margin = 18,
 642          .lower_margin = 3,
 643          .hsync_len = 112,
 644          .vsync_len = 6,
 645          .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 646          .vmode = FB_VMODE_NONINTERLACED,
 647          .flag = 0,
 648         },
 649 };
 650
 651 static struct platform_pwm_backlight_data mxc_pwm_backlight_data = {
 652         .pwm_id = 1,
 653         .max_brightness = 255,
 654         .dft_brightness = 192,
 655         /* NOTE - ADENEO: this value is suitable for the SEIKO LCD.
 656            It needs to be adapted for different panels */
 657         .pwm_period_ns = 5000000,
 658 };
 659
 660 static struct flexcan_platform_data flexcan0_data = {
 661         .core_reg = NULL,
 662         .io_reg = NULL,
 663         .root_clk_id = "lp_apm", /*lp_apm is 24MHz */
 664 //      .xcvr_enable = flexcan_xcvr_enable,
 665         .br_clksrc = 0,
 666         .br_rjw = 2,
 667         .br_presdiv = 3,
 668         .br_propseg = 2,
 669         .br_pseg1 = 3,
 670         .br_pseg2 = 3,
 671         .bcc = 1,
 672         .srx_dis = 1,
 673         .smp = 1,
 674         .boff_rec = 1,
 675         .ext_msg = 1,
 676         .std_msg = 1,
 677 };
 678
 679 extern void mx5_ipu_reset(void);
 680 static struct mxc_ipu_config mxc_ipu_data = {
 681         .rev = 3,
 682         .reset = mx5_ipu_reset,
 683 };
 684
 685 extern void mx5_vpu_reset(void);
 686 static struct mxc_vpu_platform_data mxc_vpu_data = {
 687         .iram_enable = true,
 688         .iram_size = 0x14000,
 689         .reset = mx5_vpu_reset,
 690 };
 691
 692 static struct fec_platform_data fec_data = {
 693         .phy = PHY_INTERFACE_MODE_RMII,
 694 };
 695
 696 static struct mxc_dvfs_platform_data dvfs_core_data = {
 697         .clk1_id = "cpu_clk",
 698         .clk2_id = "gpc_dvfs_clk",
 699         .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
 700         .gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
 701         .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
 702         .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
 703         .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
 704         .prediv_mask = 0x1F800,
 705         .prediv_offset = 11,
 706         .prediv_val = 3,
 707         .div3ck_mask = 0xE0000000,
 708         .div3ck_offset = 29,
 709         .div3ck_val = 2,
 710         .emac_val = 0x08,
 711         .upthr_val = 25,
 712         .dnthr_val = 9,
 713         .pncthr_val = 33,
 714         .upcnt_val = 10,
 715         .dncnt_val = 10,
 716         .delay_time = 30,
 717 };
 718
 719 static struct mxc_bus_freq_platform_data bus_freq_data;
 720
 721 static struct tve_platform_data tve_data = {
 722         .boot_enable = MXC_TVE_VGA,
 723 };
 724
 725 static struct ldb_platform_data ldb_data = {
 726         .ext_ref = 1,
 727 };
 728
 729 static void mxc_iim_enable_fuse(void)
 730 {
 731         u32 reg;
 732
 733         if (!ccm_base)
 734                 return;
 735
 736         /* enable fuse blown */
 737         reg = readl(ccm_base + 0x64);
 738         reg |= 0x10;
 739         writel(reg, ccm_base + 0x64);
 740 }
 741
 742 static void mxc_iim_disable_fuse(void)
 743 {
 744         u32 reg;
 745
 746         if (!ccm_base)
 747                 return;
 748         /* enable fuse blown */
 749         reg = readl(ccm_base + 0x64);
 750         reg &= ~0x10;
 751         writel(reg, ccm_base + 0x64);
 752 }
 753
 754 static struct mxc_iim_data iim_data = {
 755         .bank_start = MXC_IIM_MX53_BANK_START_ADDR,
 756         .bank_end   = MXC_IIM_MX53_BANK_END_ADDR,
 757         .enable_fuse = mxc_iim_enable_fuse,
 758         .disable_fuse = mxc_iim_disable_fuse,
 759 };
 760
 761 static struct resource mxcfb_resources[] = {
 762         [0] = {
 763                .flags = IORESOURCE_MEM,
 764                },
 765 };
 766
 767 static struct mxc_fb_platform_data fb_data[] = {
 768         {
 769          .interface_pix_fmt = IPU_PIX_FMT_GBR24,
 770          .mode_str = "SXGA",
 771          .mode = video_modes,
 772          .num_modes = ARRAY_SIZE(video_modes),
 773          },
 774         {
 775          .interface_pix_fmt = IPU_PIX_FMT_RGB24,
 776          .mode_str = "SEIKO-WVGA",
 777          .mode = video_modes,
 778          .num_modes = ARRAY_SIZE(video_modes),
 779          },
 780 };
 781
 782 extern int primary_di;
 783 static int __init mxc_init_fb(void)
 784 {
 785 //      if (!machine_is_mx53_loco())
 786 //              return 0;
 787
 788         /*for loco board, set default display as VGA*/
 789         if (primary_di < 0)
 790                 primary_di = 0;
 791
 792         if (primary_di) {
 793                 printk(KERN_INFO "DI1 is primary\n");
 794                 /* DI1 -> DP-BG channel: */
 795                 mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources);
 796                 mxc_fb_devices[1].resource = mxcfb_resources;
 797                 mxc_register_device(&mxc_fb_devices[1], &fb_data[1]);
 798
 799                 /* DI0 -> DC channel: */
 800                 mxc_register_device(&mxc_fb_devices[0], &fb_data[0]);
 801         } else {
 802                 printk(KERN_INFO "DI0 is primary\n");
 803
 804                 /* DI0 -> DP-BG channel: */
 805                 mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources);
 806                 mxc_fb_devices[0].resource = mxcfb_resources;
 807                 mxc_register_device(&mxc_fb_devices[0], &fb_data[0]);
 808
 809                 /* DI1 -> DC channel: */
 810                 mxc_register_device(&mxc_fb_devices[1], &fb_data[1]);
 811         }
 812
 813         /*
 814          * DI0/1 DP-FG channel:
 815          */
 816         mxc_register_device(&mxc_fb_devices[2], NULL);
 817
 818         return 0;
 819 }
 820 device_initcall(mxc_init_fb);
 821 #if 0
 822 static void sii902x_hdmi_reset(void)
 823 {
 824         gpio_set_value(DISP0_RESET, 0);
 825         msleep(10);
 826         gpio_set_value(DISP0_RESET, 1);
 827         msleep(10);
 828 }
 829
 830 static int sii902x_get_pins(void)
 831 {
 832         /* Sii902x HDMI controller */
 833         gpio_request(DISP0_RESET, "disp0-reset");
 834         gpio_direction_output(DISP0_RESET, 0);
 835         gpio_request(DISP0_DET_INT, "disp0-detect");
 836         gpio_direction_input(DISP0_DET_INT);
 837         return 1;
 838 }
 839
 840 static void sii902x_put_pins(void)
 841 {
 842         gpio_free(DISP0_RESET);
 843         gpio_free(DISP0_DET_INT);
 844 }
 845
 846 static struct mxc_lcd_platform_data sii902x_hdmi_data = {
 847         .reset = sii902x_hdmi_reset,
 848         .fb_id = "DISP3 BG",
 849         .get_pins = sii902x_get_pins,
 850         .put_pins = sii902x_put_pins,
 851 };
 852 #endif
 853
 854 /* NAND Flash Partitions */
 855 #ifdef CONFIG_MTD_PARTITIONS
 856
 857 static struct mtd_partition nand_flash_partitions[] = {
 858        {
 859         .name = "nand.bootloader",
 860         .offset = 0,
 861         .size = 512 * 1024},
 862        {
 863         .name = "nand.bootenv",
 864         .offset = MTDPART_OFS_APPEND,
 865         .size = 512 * 1024},
 866        {
 867         .name = "nand.kernel",
 868         .offset = MTDPART_OFS_APPEND,
 869         .size = 4 * 1024 * 1024},
 870        {
 871         .name = "nand.rootfs",
 872         .offset = MTDPART_OFS_APPEND,
 873         .size = MTDPART_SIZ_FULL},
 874 };
 875
 876 #endif
 877
 878 #if defined(CONFIG_MTD_NAND_MXC_V3) || defined(CONFIG_MTD_NAND_MXC_V3_MODULE)
 879 static int nand_init(void)
 880 {
 881        /* Configure the pins */
 882        return 0;
 883 }
 884
 885 static void nand_exit(void)
 886 {
 887        /* Free the pins */
 888        ;
 889 }
 890
 891 static struct flash_platform_data mxc_nand_data = {
 892         .name = "vmx_nand",
 893 #ifdef CONFIG_MTD_PARTITIONS
 894        .parts = nand_flash_partitions,
 895        .nr_parts = ARRAY_SIZE(nand_flash_partitions),
 896 #endif // CONFIG_MTD_PARTITIONS
 897        .width = 1,
 898        .init = nand_init,
 899        .exit = nand_exit,
 900 };
 901 #endif // CONFIG_MTD_NAND_MXC_V3
 902
 903 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
 904 #ifdef CONFIG_MTD_PARTITIONS
 905 static struct mtd_partition mxc_spi_bbflash_partitions[] = {
 906        {
 907         .name = "spi.bbboot",
 908         .offset = 0,
 909         .size = 0x00040000,
 910         .mask_flags = MTD_CAP_ROM,
 911        },
 912        {
 913         .name = "spi.bbkernel",
 914         .offset = MTDPART_OFS_APPEND,
 915         .size = MTDPART_SIZ_FULL,
 916        },
 917 };
 918
 919 static struct mtd_partition mxc_spi_moflash_partitions[] = {
 920        {
 921         .name = "spi.moboot",
 922         .offset = 0,
 923         .size = 0x00040000,
 924         .mask_flags = MTD_CAP_ROM,
 925        },
 926        {
 927         .name = "spi.mokernel",
 928         .offset = MTDPART_OFS_APPEND,
 929         .size = MTDPART_SIZ_FULL,
 930        },
 931 };
 932 #endif
 933
 934 static struct spi_flash_platform_data mxc_spi_bbflash_data = {
 935 //static struct flash_platform_data mxc_spi_bbflash_data = {
 936         .name = "m25p80",
 937 #ifdef CONFIG_MTD_PARTITIONS
 938         .parts = mxc_spi_bbflash_partitions,
 939         .nr_parts = ARRAY_SIZE(mxc_spi_bbflash_partitions),
 940 #endif
 941         .type = "sst25vf032b",
 942 };
 943
 944 static struct spi_flash_platform_data mxc_spi_moflash_data = {
 945 //static struct flash_platform_data mxc_spi_moflash_data = {
 946         .name = "m25p80",
 947 #ifdef CONFIG_MTD_PARTITIONS
 948         .parts = mxc_spi_moflash_partitions,
 949         .nr_parts = ARRAY_SIZE(mxc_spi_moflash_partitions),
 950 #endif
 951         .type = "sst25vf032b",
 952 };
 953 #endif // CONFIG_MTD_M25P80
 954 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 955 static int ads7846_get_pendown_state(void)
 956 {
 957        return !gpio_get_value(VMX53_TSC2046_IRQ);
 958 }
 959
 960 static struct ads7846_platform_data ads7846_config __initdata = {
 961        .model                  = 7846,
 962        .vref_delay_usecs       = 100,
 963        .x_plate_ohms           = 300,
 964        .y_plate_ohms           = 600,
 965        /* debounce Filter */
 966        .debounce_max           = 10,           /* max number of additional readings per sample */
 967        .debounce_rep           = 1,            /* additional consecutive good readings required after the first two */
 968        .debounce_tol           = 5,            /* tolerance used for filtering */
 969
 970        .get_pendown_state       = ads7846_get_pendown_state,
 971        .keep_vref_on           = 0,
 972        .vref_mv                = 0,
 973 };
 974 #endif // CONFIG_TOUCHSCREEN_ADS7846
 975
 976 #if defined(CONFIG_CAN_MCP251X) || defined(CONFIG_CAN_MCP251X_MODULE)
 977 static struct mcp251x_platform_data mcp251x_config = {
 978        .oscillator_frequency = 16000000,
 979        .model = CAN_MCP251X_MCP2515,
 980        .board_specific_setup = NULL,
 981        .power_enable = NULL,
 982        .transceiver_enable = NULL,
 983 };
 984 #endif // CONFIG_CAN_MCP251X
 985
 986 static struct spi_board_info mxc_ecspi1_board_info[] __initdata = {
 987 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
 988        {
 989         .modalias = "m25p80",
 990         .bus_num = 0,
 991         .max_speed_hz = 80000000,      /* max spi clock (SCK) speed in HZ */
 992         .chip_select = 0,
 993         .platform_data = &mxc_spi_bbflash_data,
 994         .mode = SPI_MODE_0,
 995        },
 996        {
 997         .modalias = "m25p80",
 998         .bus_num = 0,
 999         .max_speed_hz = 66000000,      /* max spi clock (SCK) speed in HZ */
1000         .chip_select = 1,
1001         .platform_data = &mxc_spi_moflash_data,
1002         .mode = SPI_MODE_0,
1003        },
1004 #endif // CONFIG_MTD_M25P80
1005 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
1006        {
1007         .modalias = "ads7846",                                                 // MASU FIXME regulator
1008         .bus_num = 0,
1009         .max_speed_hz = (125000 * 26), /* AD speed x (cmd + sample + before, after)*/
1010         .irq = gpio_to_irq(VMX53_TSC2046_IRQ),
1011         .chip_select = 2,
1012         .platform_data = &ads7846_config,
1013         .mode = SPI_MODE_2,
1014        },
1015 #endif // CONFIG_TOUCHSCREEN_ADS7846
1016 #if defined(CONFIG_CAN_MCP251X) || defined(CONFIG_CAN_MCP251X_MODULE)
1017        {
1018         .modalias = "mcp251x",
1019         .bus_num = 0,
1020         .max_speed_hz = 10000000,
1021         .irq = gpio_to_irq(VMX53_MCP2515_IRQ),
1022         .chip_select = 3,
1023         .platform_data = &mcp251x_config,
1024         .mode = SPI_MODE_0,
1025        },
1026 #endif // CONFIG_CAN_MCP251X
1027 };
1028
1029 static int vmx53_spi_cs[] = {
1030         VMX53_ECSPI1_CS0,
1031         VMX53_ECSPI1_CS1,
1032         VMX53_TSC2046_CS,
1033         VMX53_MCP2515_CS,
1034 };
1035
1036 static struct spi_imx_master vmx53_spi_pdata = {
1037        .chipselect     = vmx53_spi_cs,
1038        .num_chipselect = ARRAY_SIZE(vmx53_spi_cs),
1039 };
1040
1041
1042 static struct imxi2c_platform_data mxci2c_data = {
1043        .bitrate = 100000,
1044 };
1045
1046 static struct at24_platform_data module_eeprom = {
1047         .byte_len = SZ_512K / 8,
1048         .page_size = 128,
1049         .flags = AT24_FLAG_ADDR16,
1050 };
1051
1052 static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
1053         {
1054         .type = "mma845x",
1055         .addr = 0x1c,
1056          },
1057         {
1058          .type = "24c512",
1059          .addr = 0x56,
1060          .platform_data = &module_eeprom,
1061          },
1062 };
1063
1064 static struct at24_platform_data bboard_eeprom = {
1065         .byte_len = SZ_512K / 8,
1066         .page_size = 128,
1067         .flags = AT24_FLAG_ADDR16,
1068 };
1069 #define FT5X06_IRQ      IMX_GPIO_NR(4, 5)
1070 static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
1071         {
1072          .type = "sgtl5000-i2c",
1073          .addr = 0x0a,
1074          },
1075         {
1076          .type = "ft5x06_ts",
1077          .addr = 0x38,
1078          .irq = gpio_to_irq(FT5X06_IRQ),
1079          },
1080         {
1081          .type = "24c512",
1082          .addr = 0x57,
1083          .platform_data = &bboard_eeprom,
1084          },
1085         {
1086          .type = "ds1339",
1087          .addr = 0x68,
1088          },
1089 //      {
1090 //       .type = "sii902x",
1091 //       .addr = 0x39,
1092 //       .irq = gpio_to_irq(DISP0_DET_INT),
1093 //       .platform_data = &sii902x_hdmi_data,
1094 //      },
1095 };
1096 #if 0
1097 static int p1003_ts_hw_status(void)
1098 {
1099         return gpio_get_value(DISP0_DET_INT);
1100 }
1101
1102 static struct p1003_ts_platform_data p1003_ts_data = {
1103         .hw_status = p1003_ts_hw_status,
1104 };
1105
1106 static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
1107         {
1108          .type = "p1003_fwv33",
1109          .addr = 0x41,
1110          .irq  = gpio_to_irq(DISP0_DET_INT),
1111          .platform_data = &p1003_ts_data,
1112         },
1113         {
1114          .type = "egalax_ts",
1115          .addr = 0x4,
1116          .irq  = gpio_to_irq(DISP0_DET_INT),
1117         },
1118 };
1119 #endif
1120 static int sdhc_write_protect(struct device *dev)
1121 {
1122         int ret = 0;
1123
1124         if (to_platform_device(dev)->id == 0)
1125                 ; // WP pin not available
1126         else
1127                 ret = gpio_get_value(VMX53_SD2_WP);
1128
1129         return ret;
1130 }
1131
1132 static unsigned int sdhc_get_card_det_status(struct device *dev)
1133 {
1134         int ret = 0;
1135
1136         if (to_platform_device(dev)->id == 0)
1137                 ret = gpio_get_value(VMX53_SD1_CD);
1138         else
1139                 ret = gpio_get_value(VMX53_SD2_CD);
1140
1141         return ret;
1142 }
1143
1144 static struct mxc_mmc_platform_data mmc1_data = {
1145         .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30
1146                 | MMC_VDD_31_32,
1147         .caps = MMC_CAP_4_BIT_DATA,
1148         .min_clk = 400000,
1149         .max_clk = 50000000,
1150         .card_inserted_state = 1,
1151         .status = sdhc_get_card_det_status,
1152         .wp_status = sdhc_write_protect,
1153         .clock_mmc = "esdhc_clk",
1154         .power_mmc = NULL,
1155 };
1156
1157 static struct mxc_mmc_platform_data mmc2_data = {
1158         .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30
1159                 | MMC_VDD_31_32,
1160         .caps = MMC_CAP_4_BIT_DATA,
1161         .min_clk = 400000,
1162         .max_clk = 50000000,
1163         .card_inserted_state = 0,
1164         .status = sdhc_get_card_det_status,
1165         .wp_status = sdhc_write_protect,
1166         .clock_mmc = "esdhc_clk",
1167         .power_mmc = NULL,
1168 };
1169
1170 static int mxc_sgtl5000_amp_enable(int enable)
1171 {
1172         return 0;
1173 }
1174
1175 static int mxc_sgtl5000_clock_enable(int enable)
1176 {
1177         return 0;
1178 }
1179
1180 static int headphone_det_status(void)
1181 {
1182         return 0;
1183 }
1184 //static int headphone_det_status(void)
1185 //{
1186 //      return (gpio_get_value(HEADPHONE_DEC_B) == 0);
1187 //}
1188
1189 //static int mxc_sgtl5000_init(void);
1190
1191 static struct mxc_audio_platform_data sgtl5000_data = {
1192         .ssi_num = 1,
1193         .src_port = 2,
1194         .ext_port = 5,
1195 //      .hp_irq = gpio_to_irq(HEADPHONE_DEC_B),
1196         .hp_status = headphone_det_status,
1197         .amp_enable = mxc_sgtl5000_amp_enable,
1198         .clock_enable = mxc_sgtl5000_clock_enable,
1199 //      .init = mxc_sgtl5000_init,
1200         .sysclk = 12288000,
1201         .ext_ram_rx = 1,
1202 };
1203 #if 0
1204 static int mxc_sgtl5000_init(void)
1205 {
1206         struct clk *ssi_ext1;
1207         int rate;
1208
1209         ssi_ext1 = clk_get(NULL, "ssi_ext1_clk");
1210         if (IS_ERR(ssi_ext1))
1211                         return -1;
1212
1213         rate = clk_round_rate(ssi_ext1, 24000000);
1214         if (rate < 8000000 || rate > 27000000) {
1215                         printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n",
1216                                    rate);
1217                         clk_put(ssi_ext1);
1218                         return -1;
1219         }
1220
1221         clk_set_rate(ssi_ext1, rate);
1222         clk_enable(ssi_ext1);
1223         sgtl5000_data.sysclk = rate;
1224
1225         return 0;
1226 }
1227 #endif
1228 static struct platform_device mxc_sgtl5000_device = {
1229         .name = "imx-3stack-sgtl5000",
1230 };
1231
1232 static struct android_pmem_platform_data android_pmem_data = {
1233         .name = "pmem_adsp",
1234         .size = SZ_32M,
1235 };
1236
1237 static struct android_pmem_platform_data android_pmem_gpu_data = {
1238         .name = "pmem_gpu",
1239         .size = SZ_64M,
1240         .cached = 1,
1241 };
1242
1243 static char *usb_functions_ums[] = {
1244         "usb_mass_storage",
1245 };
1246
1247 static char *usb_functions_ums_adb[] = {
1248         "usb_mass_storage",
1249         "adb",
1250 };
1251
1252 static char *usb_functions_rndis[] = {
1253         "rndis",
1254 };
1255
1256 static char *usb_functions_rndis_adb[] = {
1257         "rndis",
1258         "adb",
1259 };
1260
1261 static char *usb_functions_all[] = {
1262         "rndis",
1263         "usb_mass_storage",
1264         "adb"
1265 };
1266
1267 static struct android_usb_product usb_products[] = {
1268         {
1269                 .product_id     = 0x0c01,
1270                 .num_functions  = ARRAY_SIZE(usb_functions_ums),
1271                 .functions      = usb_functions_ums,
1272         },
1273         {
1274                 .product_id     = 0x0c02,
1275                 .num_functions  = ARRAY_SIZE(usb_functions_ums_adb),
1276                 .functions      = usb_functions_ums_adb,
1277         },
1278         {
1279                 .product_id     = 0x0c10,
1280                 .num_functions  = ARRAY_SIZE(usb_functions_rndis),
1281                 .functions      = usb_functions_rndis,
1282         },
1283
1284 };
1285
1286 static struct usb_mass_storage_platform_data mass_storage_data = {
1287         .nluns          = 3,
1288         .vendor         = "Freescale",
1289         .product        = "MX53 QS Android Phone",
1290         .release        = 0x0100,
1291 };
1292
1293 static struct usb_ether_platform_data rndis_data = {
1294         .vendorID       = 0x15a2,
1295         .vendorDescr    = "Freescale",
1296 };
1297
1298 static struct android_usb_platform_data android_usb_data = {
1299         .vendor_id      = 0x15a2,
1300         .product_id     = 0x0c01,
1301         .version        = 0x0100,
1302         .product_name   = "MX53 QS Android Phone",
1303         .manufacturer_name = "Freescale",
1304         .num_products = ARRAY_SIZE(usb_products),
1305         .products = usb_products,
1306         .num_functions = ARRAY_SIZE(usb_functions_all),
1307         .functions = usb_functions_all,
1308 };
1309
1310 static struct mxc_asrc_platform_data mxc_asrc_data = {
1311         .channel_bits = 4,
1312         .clk_map_ver = 2,
1313 };
1314
1315 static struct mxc_spdif_platform_data mxc_spdif_data = {
1316         .spdif_tx = 1,
1317         .spdif_rx = 0,
1318         .spdif_clk_44100 = -1,  /* Souce from CKIH1 for 44.1K */
1319         /* Source from CCM spdif_clk (24M) for 48k and 32k
1320          * It's not accurate
1321          */
1322         .spdif_clk_48000 = 1,
1323         .spdif_clkid = 0,
1324         .spdif_clk = NULL,      /* spdif bus clk */
1325 };
1326
1327 static struct mxc_audio_platform_data spdif_audio_data = {
1328         .ext_ram_tx = 1,
1329 };
1330
1331 static struct platform_device mxc_spdif_audio_device = {
1332         .name = "imx-spdif-audio-device",
1333 };
1334
1335 static void mx53_loco_usbh1_vbus(bool on)
1336 {
1337         gpio_set_value(VMX53_USBH1_PEN, (on)? 1 : 0);
1338 }
1339
1340 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1341 #define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)    \
1342 {                                                               \
1343         .gpio           = gpio_num,                             \
1344         .type           = EV_KEY,                               \
1345         .code           = ev_code,                              \
1346         .active_low     = act_low,                              \
1347         .desc           = "btn " descr,                         \
1348         .wakeup         = wake,                                 \
1349 }
1350
1351 static struct gpio_keys_button loco_buttons[] = {
1352         GPIO_BUTTON(VMX53_nONKEY, KEY_POWER, 1, "power", 0),
1353 //      GPIO_BUTTON(USER_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
1354 //      GPIO_BUTTON(USER_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
1355 };
1356
1357 static struct gpio_keys_platform_data loco_button_data = {
1358         .buttons        = loco_buttons,
1359         .nbuttons       = ARRAY_SIZE(loco_buttons),
1360 };
1361
1362 static struct platform_device loco_button_device = {
1363         .name           = "gpio-keys",
1364         .id             = -1,
1365         .num_resources  = 0,
1366         .dev            = {
1367                 .platform_data = &loco_button_data,
1368         }
1369 };
1370
1371 static void __init loco_add_device_buttons(void)
1372 {
1373         platform_device_register(&loco_button_device);
1374 }
1375 #else
1376 static void __init loco_add_device_buttons(void) {}
1377 #endif
1378
1379 static u16 keymapping[64] = {
1380        KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
1381        KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
1382        KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_ZOOM,     KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_MENU,
1383        KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
1384        KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
1385        KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
1386        KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_BACK,     KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_HOME,
1387        KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
1388 };
1389
1390 static struct keypad_data keypad_plat_data = {
1391        .rowmax = 8,
1392        .colmax = 8,
1393        .learning = 0,
1394        .delay = 2,
1395        .matrix = keymapping,
1396 };
1397
1398 static struct gpio_led vmx_leds[] = {
1399        {
1400         .name = "red",
1401         .default_trigger = "heartbeat",
1402         .gpio = VMX53_LED_RED,
1403        },
1404        {
1405         .name = "orange",
1406         .default_trigger = "none",
1407         .gpio = VMX53_LED_ORANGE,
1408         .default_state = LEDS_GPIO_DEFSTATE_ON,
1409        }
1410 };
1411
1412 static struct gpio_led_platform_data vmx_led_data = {
1413        .leds = vmx_leds,
1414        .num_leds = ARRAY_SIZE(vmx_leds),
1415 };
1416
1417 static struct platform_device vmx_led_device = {
1418        .name = "leds-gpio",
1419        .id = -1,
1420        .dev = {
1421                .platform_data = &vmx_led_data,
1422        },
1423 };
1424
1425 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
1426 static struct imxuart_platform_data uart1_pdata = {
1427         .flags = IMXUART_HAVE_RTSCTS,
1428 };
1429
1430 static struct imxuart_platform_data uart2_pdata = {
1431         .flags = IMXUART_HAVE_RTSCTS,
1432 };
1433
1434 static struct imxuart_platform_data uart3_pdata = {
1435         .flags = IMXUART_HAVE_RTSCTS,
1436 };
1437 #endif // CONFIG_SERIAL_IMX
1438
1439 static struct mxc_w1_config mxc_w1_data = {
1440         .search_rom_accelerator = 1,
1441 };
1442 #if 0
1443 static void mxc_register_powerkey(pwrkey_callback pk_cb)
1444 {
1445         pmic_event_callback_t power_key_event;
1446
1447         power_key_event.param = (void *)1;
1448         power_key_event.func = (void *)pk_cb;
1449         pmic_event_subscribe(EVENT_PWRONI, power_key_event);
1450
1451         power_key_event.param = (void *)3;
1452         pmic_event_subscribe(EVENT_PWRON3I, power_key_event);
1453 }
1454
1455 static int mxc_pwrkey_getstatus(int id)
1456 {
1457         int sense;
1458
1459         pmic_read_reg(REG_INT_SENSE1, &sense, 0xffffffff);
1460         if (sense & (1 << 3))
1461                 return 0;
1462
1463         return 1;
1464 }
1465
1466 static struct power_key_platform_data pwrkey_data = {
1467         .key_value = KEY_F4,
1468         .register_pwrkey = mxc_register_powerkey,
1469         .get_key_status = mxc_pwrkey_getstatus,
1470 };
1471 #endif
1472 /*!
1473  * Board specific fixup function. It is called by \b setup_arch() in
1474  * setup.c file very early on during kernel starts. It allows the user to
1475  * statically fill in the proper values for the passed-in parameters. None of
1476  * the parameters is used currently.
1477  *
1478  * @param  desc         pointer to \b struct \b machine_desc
1479  * @param  tags         pointer to \b struct \b tag
1480  * @param  cmdline      pointer to the command line
1481  * @param  mi           pointer to \b struct \b meminfo
1482  */
1483 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
1484                                    char **cmdline, struct meminfo *mi)
1485 {
1486         struct tag *t;
1487         struct tag *mem_tag = 0;
1488         int total_mem = SZ_1G;
1489         int left_mem = 0;
1490         int gpu_mem = SZ_128M;
1491         int fb_mem = SZ_32M;
1492         char *str;
1493
1494         mxc_set_cpu_type(MXC_CPU_MX53);
1495
1496         for_each_tag(mem_tag, tags) {
1497                 if (mem_tag->hdr.tag == ATAG_MEM) {
1498                         total_mem = mem_tag->u.mem.size;
1499                         break;
1500                 }
1501         }
1502
1503         for_each_tag(t, tags) {
1504                 if (t->hdr.tag == ATAG_CMDLINE) {
1505                         str = t->u.cmdline.cmdline;
1506                         str = strstr(str, "mem=");
1507                         if (str != NULL) {
1508                                 str += 4;
1509                                 left_mem = memparse(str, &str);
1510                         }
1511
1512                         str = t->u.cmdline.cmdline;
1513                         str = strstr(str, "gpu_nommu");
1514                         if (str != NULL)
1515                                 gpu_data.enable_mmu = 0;
1516
1517                         str = t->u.cmdline.cmdline;
1518                         str = strstr(str, "gpu_memory=");
1519                         if (str != NULL) {
1520                                 str += 11;
1521                                 gpu_mem = memparse(str, &str);
1522                         }
1523
1524                         break;
1525                 }
1526         }
1527
1528         if (gpu_data.enable_mmu)
1529                 gpu_mem = 0;
1530
1531         if (left_mem == 0 || left_mem > total_mem)
1532                 left_mem = total_mem - gpu_mem - fb_mem;
1533
1534         if (mem_tag) {
1535                 fb_mem = total_mem - left_mem - gpu_mem;
1536                 if (fb_mem < 0) {
1537                         gpu_mem = total_mem - left_mem;
1538                         fb_mem = 0;
1539                 }
1540                 mem_tag->u.mem.size = left_mem;
1541
1542                 /*reserve memory for gpu*/
1543                 if (!gpu_data.enable_mmu) {
1544                         gpu_device.resource[5].start =
1545                                 mem_tag->u.mem.start + left_mem;
1546                         gpu_device.resource[5].end =
1547                                 gpu_device.resource[5].start + gpu_mem - 1;
1548                 }
1549 #if defined(CONFIG_FB_MXC_SYNC_PANEL) || \
1550         defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
1551                 if (fb_mem) {
1552                         mxcfb_resources[0].start =
1553                                 gpu_data.enable_mmu ?
1554                                 mem_tag->u.mem.start + left_mem :
1555                                 gpu_device.resource[5].end + 1;
1556                         mxcfb_resources[0].end =
1557                                 mxcfb_resources[0].start + fb_mem - 1;
1558                 } else {
1559                         mxcfb_resources[0].start = 0;
1560                         mxcfb_resources[0].end = 0;
1561                 }
1562 #endif
1563         }
1564 }
1565
1566 static void __init mx53_loco_io_init(void)
1567 {
1568         mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
1569                                         ARRAY_SIZE(mx53_loco_pads));
1570
1571         // SD/MMC
1572         gpio_request(VMX53_SD1_SEL, "sd1-sel");
1573         gpio_direction_output(VMX53_SD1_SEL, 1);        // 0 = module, 1 = baseboard
1574
1575         gpio_request(VMX53_SD1_CD, "sd1-cd");
1576         gpio_direction_input(VMX53_SD1_CD);
1577
1578         gpio_request(VMX53_SD2_CD, "sd2-cd");
1579         gpio_direction_input(VMX53_SD2_CD);
1580
1581         gpio_request(VMX53_SD2_WP, "sd2-wp");
1582         gpio_direction_input(VMX53_SD2_WP);
1583
1584         // FEC PHY
1585         gpio_request(VMX53_FEC_RST, "fec-rst");
1586         gpio_direction_output(VMX53_FEC_RST, 0);
1587         gpio_set_value(VMX53_FEC_RST, 0);
1588         msleep(1);
1589         gpio_set_value(VMX53_FEC_RST, 1);
1590
1591         // LCD PEN
1592         gpio_request(VMX53_DISP0_PEN, "disp0-power-en");
1593         gpio_direction_output(VMX53_DISP0_PEN, 1);
1594
1595         // I2C_INT
1596         gpio_request(VMX53_I2C_INT, "i2c-int");
1597         gpio_direction_input(VMX53_I2C_INT);
1598
1599         // Touch INT
1600         gpio_request(VMX53_TSC2046_IRQ, "touch-irq");
1601         gpio_direction_input(VMX53_TSC2046_IRQ);
1602
1603         // USB
1604         gpio_request(VMX53_USBH1_OC, "usbh1-oc");
1605         gpio_direction_input(VMX53_USBH1_OC);
1606
1607         gpio_request(VMX53_USBH1_PEN, "usbh1-pwr");
1608         gpio_direction_output(VMX53_USBH1_PEN, 0);
1609
1610         gpio_request(VMX53_USBO_OC, "usbo-oc");
1611         gpio_direction_input(VMX53_USBO_OC);
1612
1613         gpio_request(VMX53_USBO_PEN, "usbo-pwr");
1614         gpio_direction_output(VMX53_USBO_PEN, 0);
1615 }
1616
1617 /*!
1618  * Board specific initialization.
1619  */
1620 static void __init mxc_board_init(void)
1621 {
1622
1623 //      iomux_v3_cfg_t mc34708_int = MX53_PAD_CSI0_DAT12__GPIO5_30;
1624         iomux_v3_cfg_t da9052_csi0_d12;
1625
1626         mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk");
1627         mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk");
1628         mxc_ipu_data.csi_clk[0] = clk_get(NULL, "ssi_ext1_clk");
1629         mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
1630         clk_put(mxc_spdif_data.spdif_core_clk);
1631
1632         mxcsdhc1_device.resource[2].start = gpio_to_irq(VMX53_SD1_CD);
1633         mxcsdhc1_device.resource[2].end = gpio_to_irq(VMX53_SD1_CD);
1634         mxcsdhc2_device.resource[2].start = gpio_to_irq(VMX53_SD2_CD);
1635         mxcsdhc2_device.resource[2].end = gpio_to_irq(VMX53_SD2_CD);
1636
1637         mxc_cpu_common_init();
1638         mx53_loco_io_init();
1639
1640         mxc_register_device(&mxc_dma_device, NULL);
1641         mxc_register_device(&mxc_wdt_device, NULL);
1642 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
1643         mxc_register_device(&mxcuart_devices[0], &uart1_pdata);
1644         mxc_register_device(&mxcuart_devices[1], &uart2_pdata);
1645         mxc_register_device(&mxcuart_devices[2], &uart3_pdata);
1646 #endif // CONFIG_SERIAL_IMX
1647         mxc_register_device(&mxcspi1_device, &vmx53_spi_pdata);
1648         mxc_register_device(&mxci2c_devices[0], &mxci2c_data);
1649 //      mxc_register_device(&mxci2c_devices[1], &mxci2c_data);
1650         mxc_register_device(&mxci2c_devices[2], &mxci2c_data);
1651 #if 0
1652     if (board_is_mx53_loco_mc34708()) {
1653                 /* set pmic INT gpio pin */
1654                 if (board_is_rev(BOARD_REV_2)) {/*Board rev A*/
1655                         mc34708_int = MX53_PAD_CSI0_DAT12__GPIO5_30;
1656                         mx53_loco_mc34708_irq = MX53_LOCO_MC34708_IRQ_REVA;
1657                 } else if (board_is_rev(BOARD_REV_4)) {/*Board rev B*/
1658                         mc34708_int = MX53_PAD_CSI0_DAT5__GPIO5_23;
1659                         mx53_loco_mc34708_irq = MX53_LOCO_MC34708_IRQ_REVB;
1660                 }
1661                 mxc_iomux_v3_setup_pad(mc34708_int);
1662                 gpio_request(mx53_loco_mc34708_irq, "pmic-int");
1663                 gpio_direction_input(mx53_loco_mc34708_irq);
1664                 mx53_loco_init_mc34708(mx53_loco_mc34708_irq);
1665                 dvfs_core_data.reg_id = "SW1A";
1666                 tve_data.dac_reg = "VDAC";
1667                 bus_freq_data.gp_reg_id = "SW1A";
1668                 bus_freq_data.lp_reg_id = "SW2";
1669                 mxc_register_device(&mxc_powerkey_device, &pwrkey_data);
1670         }
1671     else
1672 #endif
1673         {
1674                 da9052_csi0_d12 = MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12;
1675                 mxc_iomux_v3_setup_pad(da9052_csi0_d12);
1676                 mx53_loco_init_da9052();
1677                 dvfs_core_data.reg_id = "DA9052_BUCK_CORE";
1678                 tve_data.dac_reg = "DA9052_LDO7";
1679                 bus_freq_data.gp_reg_id = "DA9052_BUCK_CORE";
1680                 bus_freq_data.lp_reg_id = "DA9052_BUCK_PRO";
1681         }
1682
1683         mxc_register_device(&mxc_rtc_device, NULL);
1684         mxc_register_device(&mxc_w1_master_device, &mxc_w1_data);
1685         mxc_register_device(&mxc_ipu_device, &mxc_ipu_data);
1686         mxc_register_device(&mxc_ldb_device, &ldb_data);
1687         mxc_register_device(&mxc_tve_device, &tve_data);
1688         if (!mxc_fuse_get_vpu_status())
1689                 mxc_register_device(&mxcvpu_device, &mxc_vpu_data);
1690         if (!mxc_fuse_get_gpu_status())
1691                 mxc_register_device(&gpu_device, &gpu_data);
1692         mxc_register_device(&mxcscc_device, NULL);
1693         mxc_register_device(&pm_device, &loco_pm_data);
1694         mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data);
1695         mxc_register_device(&busfreq_device, &bus_freq_data);
1696         mxc_register_device(&mxc_iim_device, &iim_data);
1697         mxc_register_device(&mxc_pwm2_device, NULL);
1698         mxc_register_device(&mxc_pwm1_backlight_device, &mxc_pwm_backlight_data);
1699         mxc_register_device(&mxc_flexcan0_device, &flexcan0_data);
1700         mxc_register_device(&mxc_keypad_device, &keypad_plat_data);
1701         mxc_register_device(&mxcsdhc1_device, &mmc1_data);
1702         mxc_register_device(&mxcsdhc2_device, &mmc2_data);
1703         mxc_register_device(&mxc_ssi1_device, NULL);
1704         mxc_register_device(&mxc_ssi2_device, NULL);
1705         mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data);
1706         mxc_register_device(&mxc_android_pmem_device, &android_pmem_data);
1707         mxc_register_device(&mxc_android_pmem_gpu_device,
1708                                 &android_pmem_gpu_data);
1709         mxc_register_device(&usb_mass_storage_device, &mass_storage_data);
1710         mxc_register_device(&usb_rndis_device, &rndis_data);
1711         mxc_register_device(&android_usb_device, &android_usb_data);
1712         mxc_register_device(&ahci_fsl_device, &sata_data);
1713         mxc_register_device(&mxc_fec_device, &fec_data);
1714         mxc_register_device(&mxc_ptp_device, NULL);
1715         platform_device_register(&vmx_led_device);
1716         /* ASRC is only available for MX53 TO2.0 */
1717         if (mx53_revision() >= IMX_CHIP_REVISION_2_0) {
1718                 mxc_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
1719                 clk_put(mxc_asrc_data.asrc_core_clk);
1720                 mxc_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
1721                 clk_put(mxc_asrc_data.asrc_audio_clk);
1722                 mxc_register_device(&mxc_asrc_device, &mxc_asrc_data);
1723         }
1724
1725 #if defined(CONFIG_MTD_NAND_MXC_V3) || defined(CONFIG_MTD_NAND_MXC_V3_MODULE)        // fsl driver
1726         mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data);
1727 #endif
1728
1729         spi_register_board_info(mxc_ecspi1_board_info,
1730                                 ARRAY_SIZE(mxc_ecspi1_board_info));
1731         i2c_register_board_info(0, mxc_i2c0_board_info,
1732                                 ARRAY_SIZE(mxc_i2c0_board_info));
1733 //      i2c_register_board_info(1, mxc_i2c1_board_info,
1734 //                              ARRAY_SIZE(mxc_i2c1_board_info));
1735         i2c_register_board_info(2, mxc_i2c2_board_info,
1736                                 ARRAY_SIZE(mxc_i2c2_board_info));
1737
1738         sgtl5000_data.ext_ram_clk = clk_get(NULL, "emi_fast_clk");
1739         clk_put(sgtl5000_data.ext_ram_clk);
1740         mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data);
1741
1742         spdif_audio_data.ext_ram_clk = clk_get(NULL, "emi_fast_clk");
1743         clk_put(spdif_audio_data.ext_ram_clk);
1744         mxc_register_device(&mxc_spdif_audio_device, &spdif_audio_data);
1745
1746         mx5_usb_dr_init();
1747         mx5_set_host1_vbus_func(mx53_loco_usbh1_vbus);
1748         mx5_usbh1_init();
1749         mxc_register_device(&mxc_v4l2_device, NULL);
1750         mxc_register_device(&mxc_v4l2out_device, NULL);
1751         loco_add_device_buttons();
1752         pm_power_off = da9053_power_off;
1753         pm_i2c_init(I2C1_BASE_ADDR - MX53_OFFSET);
1754 }
1755
1756 static void __init mx53_loco_timer_init(void)
1757 {
1758         struct clk *uart_clk;
1759
1760         mx53_clocks_init(32768, 24000000, 0, 0);
1761
1762         uart_clk = clk_get_sys("mxcintuart.0", NULL);
1763         early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk);
1764 }
1765
1766 static struct sys_timer mxc_timer = {
1767         .init   = mx53_loco_timer_init,
1768 };
1769
1770 static void __init fixup_android_board(struct machine_desc *desc, struct tag *tags,
1771                                    char **cmdline, struct meminfo *mi)
1772 {
1773         char *str;
1774         struct tag *t;
1775         struct tag *mem_tag = 0, *last_mem_tag = 0;
1776 //      int total_mem = SZ_1G;
1777         unsigned long total_mem = 0;
1778         unsigned long left_mem = 0, avali_mem = 0;
1779         int gpu_mem = SZ_64M;
1780         int pmem_gpu_size = android_pmem_gpu_data.size;
1781         int pmem_adsp_size = android_pmem_data.size;
1782
1783         mxc_set_cpu_type(MXC_CPU_MX53);
1784
1785         /* get mem= and gpu_memory= from cmdline */
1786         for_each_tag(t, tags) {
1787                 if (t->hdr.tag == ATAG_CMDLINE) {
1788                         str = t->u.cmdline.cmdline;
1789                         str = strstr(str, "mem=");
1790                         if (str != NULL) {
1791                                 str += 4;
1792                                 avali_mem = memparse(str, &str);
1793                         }
1794
1795                         str = t->u.cmdline.cmdline;
1796                         str = strstr(str, "gpu_nommu");
1797                         if (str != NULL)
1798                                 gpu_data.enable_mmu = 0;
1799
1800                         str = t->u.cmdline.cmdline;
1801                         str = strstr(str, "gpu_memory=");
1802                         if (str != NULL) {
1803                                 str += 11;
1804                                 gpu_mem = memparse(str, &str);
1805                         }
1806                         break;
1807                 }
1808         }
1809
1810         if (gpu_data.enable_mmu)
1811                 gpu_mem = 0;
1812         /* get total memory from TAGS */
1813         for_each_tag(mem_tag, tags) {
1814                 if (mem_tag->hdr.tag == ATAG_MEM) {
1815 printk("ATAG_MEM: start=%08x, size=%u\n",mem_tag->u.mem.start,mem_tag->u.mem.size);
1816                         last_mem_tag = mem_tag;
1817 //                      break;
1818                 }
1819         }
1820
1821 //printk("total_mem=%u, left_mem=%u, gpu_mem=%d, pmem_gpu_size=%d, pmem_adsp_size=%d\n",
1822 // total_mem, left_mem, gpu_mem, pmem_gpu_size, pmem_adsp_size);
1823
1824 //      if (avali_mem > 0 && avali_mem < left_mem)
1825 //              left_mem = avali_mem;
1826
1827         if (last_mem_tag) {
1828                 mem_tag = last_mem_tag;
1829
1830                 total_mem = mem_tag->u.mem.size;
1831                 left_mem = total_mem - gpu_mem - pmem_gpu_size - pmem_adsp_size;
1832
1833                 android_pmem_data.start = mem_tag->u.mem.start
1834                                 + left_mem + gpu_mem + pmem_gpu_size;
1835                 android_pmem_gpu_data.start = mem_tag->u.mem.start
1836                                 + left_mem + gpu_mem;
1837                 mem_tag->u.mem.size = left_mem;
1838 //printk("android_pmem_data.start=%08lx (%08x+%08x+%08x+%08x)\n",
1839 //      android_pmem_data.start,mem_tag->u.mem.start,left_mem,gpu_mem,pmem_gpu_size);
1840 //printk("android_pmem_gpu_data.start=%08lx (%08x+%08x+%08x)\n",android_pmem_gpu_data.start,
1841 //      mem_tag->u.mem.start,left_mem,gpu_mem);
1842                 /*reserve memory for gpu*/
1843                 if (!gpu_data.enable_mmu) {
1844                         gpu_device.resource[5].start =
1845                                 mem_tag->u.mem.start + left_mem;
1846                         gpu_device.resource[5].end =
1847                                 gpu_device.resource[5].start + gpu_mem - 1;
1848 //printk("gpu_device.resource[5].start=%08x, (%08x+%08x)\n",
1849 //      gpu_device.resource[5].start,mem_tag->u.mem.start,left_mem);
1850 //printk("gpu_device.resource[5].end=%08x\n",gpu_device.resource[5].end);
1851                 }
1852         }
1853 }
1854
1855 /*
1856  * The following uses standard kernel macros define in arch.h in order to
1857  * initialize __mach_desc_MX53_LOCO data structure.
1858  */
1859 //MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
1860 MACHINE_START(VMX53, "Voipac Technologies VMX53 Board")
1861         /* Maintainer: Voipac Technologies */
1862 #ifdef CONFIG_ANDROID_PMEM
1863         .fixup = fixup_android_board,
1864 #else
1865         .fixup = fixup_mxc_board,
1866 #endif
1867         .map_io = mx5_map_io,
1868         .init_irq = mx5_init_irq,
1869         .init_machine = mxc_board_init,
1870         .timer = &mxc_timer,
1871 MACHINE_END