drivers/i2c/busses/i2c-mxs.c

   1 /*
   2  * Freescale MXS I2C bus driver
   3  *
   4  * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
   5  *
   6  * based on a (non-working) driver which was:
   7  *
   8  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/device.h>
  19 #include <linux/module.h>
  20 #include <linux/i2c.h>
  21 #include <linux/err.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/completion.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/io.h>
  27 #include <linux/stmp_device.h>
  28 #include <linux/of.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_i2c.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/dmaengine.h>
  33
  34 #define DRIVER_NAME "mxs-i2c"
  35
  36 #define MXS_I2C_CTRL0           (0x00)
  37 #define MXS_I2C_CTRL0_SET       (0x04)
  38
  39 #define MXS_I2C_CTRL0_SFTRST                    0x80000000
  40 #define MXS_I2C_CTRL0_RUN                       0x20000000
  41 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST          0x02000000
  42 #define MXS_I2C_CTRL0_RETAIN_CLOCK              0x00200000
  43 #define MXS_I2C_CTRL0_POST_SEND_STOP            0x00100000
  44 #define MXS_I2C_CTRL0_PRE_SEND_START            0x00080000
  45 #define MXS_I2C_CTRL0_MASTER_MODE               0x00020000
  46 #define MXS_I2C_CTRL0_DIRECTION                 0x00010000
  47 #define MXS_I2C_CTRL0_XFER_COUNT(v)             ((v) & 0x0000FFFF)
  48
  49 #define MXS_I2C_TIMING0         (0x10)
  50 #define MXS_I2C_TIMING1         (0x20)
  51 #define MXS_I2C_TIMING2         (0x30)
  52
  53 #define MXS_I2C_CTRL1           (0x40)
  54 #define MXS_I2C_CTRL1_SET       (0x44)
  55 #define MXS_I2C_CTRL1_CLR       (0x48)
  56
  57 #define MXS_I2C_CTRL1_CLR_GOT_A_NAK             0x10000000
  58 #define MXS_I2C_CTRL1_BUS_FREE_IRQ              0x80
  59 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ     0x40
  60 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ          0x20
  61 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ    0x10
  62 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ            0x08
  63 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ           0x04
  64 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ            0x02
  65 #define MXS_I2C_CTRL1_SLAVE_IRQ                 0x01
  66
  67 #define MXS_I2C_STAT            (0x50)
  68 #define MXS_I2C_STAT_BUS_BUSY                   0x00000800
  69 #define MXS_I2C_STAT_CLK_GEN_BUSY               0x00000400
  70
  71 #define MXS_I2C_DATA            (0xa0)
  72
  73 #define MXS_I2C_DEBUG0          (0xb0)
  74 #define MXS_I2C_DEBUG0_CLR      (0xb8)
  75
  76 #define MXS_I2C_DEBUG0_DMAREQ   0x80000000
  77
  78 #define MXS_I2C_IRQ_MASK        (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
  79                                  MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
  80                                  MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
  81                                  MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
  82                                  MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
  83                                  MXS_I2C_CTRL1_SLAVE_IRQ)
  84
  85
  86 #define MXS_CMD_I2C_SELECT      (MXS_I2C_CTRL0_RETAIN_CLOCK |   \
  87                                  MXS_I2C_CTRL0_PRE_SEND_START | \
  88                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  89                                  MXS_I2C_CTRL0_DIRECTION |      \
  90                                  MXS_I2C_CTRL0_XFER_COUNT(1))
  91
  92 #define MXS_CMD_I2C_WRITE       (MXS_I2C_CTRL0_PRE_SEND_START | \
  93                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  94                                  MXS_I2C_CTRL0_DIRECTION)
  95
  96 #define MXS_CMD_I2C_READ        (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
  97                                  MXS_I2C_CTRL0_MASTER_MODE)
  98
  99 /**
 100  * struct mxs_i2c_dev - per device, private MXS-I2C data
 101  *
 102  * @dev: driver model device node
 103  * @regs: IO registers pointer
 104  * @cmd_complete: completion object for transaction wait
 105  * @cmd_err: error code for last transaction
 106  * @adapter: i2c subsystem adapter node
 107  */
 108 struct mxs_i2c_dev {
 109         struct device *dev;
 110         void __iomem *regs;
 111         struct completion cmd_complete;
 112         int cmd_err;
 113         struct i2c_adapter adapter;
 114
 115         uint32_t timing0;
 116         uint32_t timing1;
 117
 118         /* DMA support components */
 119         struct dma_chan                 *dmach;
 120         uint32_t                        pio_data[2];
 121         uint32_t                        addr_data;
 122         struct scatterlist              sg_io[2];
 123         bool                            dma_read;
 124 };
 125
 126 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 127 {
 128         stmp_reset_block(i2c->regs);
 129
 130         /*
 131          * Configure timing for the I2C block. The I2C TIMING2 register has to
 132          * be programmed with this particular magic number. The rest is derived
 133          * from the XTAL speed and requested I2C speed.
 134          *
 135          * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
 136          */
 137         writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
 138         writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
 139         writel(0x00300030, i2c->regs + MXS_I2C_TIMING2);
 140
 141         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 142 }
 143
 144 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
 145 {
 146         if (i2c->dma_read) {
 147                 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 148                 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 149         } else {
 150                 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 151         }
 152 }
 153
 154 static void mxs_i2c_dma_irq_callback(void *param)
 155 {
 156         struct mxs_i2c_dev *i2c = param;
 157
 158         complete(&i2c->cmd_complete);
 159         mxs_i2c_dma_finish(i2c);
 160 }
 161
 162 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
 163                         struct i2c_msg *msg, uint32_t flags)
 164 {
 165         struct dma_async_tx_descriptor *desc;
 166         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 167
 168         if (msg->flags & I2C_M_RD) {
 169                 i2c->dma_read = 1;
 170                 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
 171
 172                 /*
 173                  * SELECT command.
 174                  */
 175
 176                 /* Queue the PIO register write transfer. */
 177                 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
 178                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 179                                         (struct scatterlist *)&i2c->pio_data[0],
 180                                         1, DMA_TRANS_NONE, 0);
 181                 if (!desc) {
 182                         dev_err(i2c->dev,
 183                                 "Failed to get PIO reg. write descriptor.\n");
 184                         goto select_init_pio_fail;
 185                 }
 186
 187                 /* Queue the DMA data transfer. */
 188                 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
 189                 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 190                 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
 191                                         DMA_MEM_TO_DEV,
 192                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 193                 if (!desc) {
 194                         dev_err(i2c->dev,
 195                                 "Failed to get DMA data write descriptor.\n");
 196                         goto select_init_dma_fail;
 197                 }
 198
 199                 /*
 200                  * READ command.
 201                  */
 202
 203                 /* Queue the PIO register write transfer. */
 204                 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
 205                                 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
 206                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 207                                         (struct scatterlist *)&i2c->pio_data[1],
 208                                         1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
 209                 if (!desc) {
 210                         dev_err(i2c->dev,
 211                                 "Failed to get PIO reg. write descriptor.\n");
 212                         goto select_init_dma_fail;
 213                 }
 214
 215                 /* Queue the DMA data transfer. */
 216                 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
 217                 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 218                 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
 219                                         DMA_DEV_TO_MEM,
 220                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 221                 if (!desc) {
 222                         dev_err(i2c->dev,
 223                                 "Failed to get DMA data write descriptor.\n");
 224                         goto read_init_dma_fail;
 225                 }
 226         } else {
 227                 i2c->dma_read = 0;
 228                 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
 229
 230                 /*
 231                  * WRITE command.
 232                  */
 233
 234                 /* Queue the PIO register write transfer. */
 235                 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
 236                                 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
 237                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 238                                         (struct scatterlist *)&i2c->pio_data[0],
 239                                         1, DMA_TRANS_NONE, 0);
 240                 if (!desc) {
 241                         dev_err(i2c->dev,
 242                                 "Failed to get PIO reg. write descriptor.\n");
 243                         goto write_init_pio_fail;
 244                 }
 245
 246                 /* Queue the DMA data transfer. */
 247                 sg_init_table(i2c->sg_io, 2);
 248                 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
 249                 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
 250                 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 251                 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
 252                                         DMA_MEM_TO_DEV,
 253                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 254                 if (!desc) {
 255                         dev_err(i2c->dev,
 256                                 "Failed to get DMA data write descriptor.\n");
 257                         goto write_init_dma_fail;
 258                 }
 259         }
 260
 261         /*
 262          * The last descriptor must have this callback,
 263          * to finish the DMA transaction.
 264          */
 265         desc->callback = mxs_i2c_dma_irq_callback;
 266         desc->callback_param = i2c;
 267
 268         /* Start the transfer. */
 269         dmaengine_submit(desc);
 270         dma_async_issue_pending(i2c->dmach);
 271         return 0;
 272
 273 /* Read failpath. */
 274 read_init_dma_fail:
 275         dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 276 select_init_dma_fail:
 277         dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 278 select_init_pio_fail:
 279         dmaengine_terminate_all(i2c->dmach);
 280         return -EINVAL;
 281
 282 /* Write failpath. */
 283 write_init_dma_fail:
 284         dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 285 write_init_pio_fail:
 286         dmaengine_terminate_all(i2c->dmach);
 287         return -EINVAL;
 288 }
 289
 290 static int mxs_i2c_pio_wait_dmareq(struct mxs_i2c_dev *i2c)
 291 {
 292         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 293
 294         while (!(readl(i2c->regs + MXS_I2C_DEBUG0) &
 295                 MXS_I2C_DEBUG0_DMAREQ)) {
 296                 if (time_after(jiffies, timeout))
 297                         return -ETIMEDOUT;
 298                 cond_resched();
 299         }
 300
 301         return 0;
 302 }
 303
 304 static int mxs_i2c_pio_wait_cplt(struct mxs_i2c_dev *i2c, int last)
 305 {
 306         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 307
 308         /*
 309          * We do not use interrupts in the PIO mode. Due to the
 310          * maximum transfer length being 8 bytes in PIO mode, the
 311          * overhead of interrupt would be too large and this would
 312          * neglect the gain from using the PIO mode.
 313          */
 314
 315         while (!(readl(i2c->regs + MXS_I2C_CTRL1) &
 316                 MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)) {
 317                 if (time_after(jiffies, timeout))
 318                         return -ETIMEDOUT;
 319                 cond_resched();
 320         }
 321
 322         writel(MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ,
 323                 i2c->regs + MXS_I2C_CTRL1_CLR);
 324
 325         /*
 326          * When ending a transfer with a stop, we have to wait for the bus to
 327          * go idle before we report the transfer as completed. Otherwise the
 328          * start of the next transfer may race with the end of the current one.
 329          */
 330         while (last && (readl(i2c->regs + MXS_I2C_STAT) &
 331                         (MXS_I2C_STAT_BUS_BUSY | MXS_I2C_STAT_CLK_GEN_BUSY))) {
 332                 if (time_after(jiffies, timeout))
 333                         return -ETIMEDOUT;
 334                 cond_resched();
 335         }
 336
 337         return 0;
 338 }
 339
 340 static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
 341 {
 342         u32 state;
 343
 344         state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
 345
 346         if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 347                 i2c->cmd_err = -ENXIO;
 348         else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
 349                           MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
 350                           MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
 351                           MXS_I2C_CTRL1_SLAVE_IRQ))
 352                 i2c->cmd_err = -EIO;
 353
 354         return i2c->cmd_err;
 355 }
 356
 357 static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
 358 {
 359         u32 reg;
 360
 361         writel(cmd, i2c->regs + MXS_I2C_CTRL0);
 362
 363         /* readback makes sure the write is latched into hardware */
 364         reg = readl(i2c->regs + MXS_I2C_CTRL0);
 365         reg |= MXS_I2C_CTRL0_RUN;
 366         writel(reg, i2c->regs + MXS_I2C_CTRL0);
 367 }
 368
 369 static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
 370                         struct i2c_msg *msg, uint32_t flags)
 371 {
 372         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 373         uint32_t addr_data = msg->addr << 1;
 374         uint32_t data = 0;
 375         int i, shifts_left, ret;
 376
 377         /* Mute IRQs coming from this block. */
 378         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
 379
 380         if (msg->flags & I2C_M_RD) {
 381                 addr_data |= I2C_SMBUS_READ;
 382
 383                 /* SELECT command. */
 384                 mxs_i2c_pio_trigger_cmd(i2c, MXS_CMD_I2C_SELECT);
 385
 386                 ret = mxs_i2c_pio_wait_dmareq(i2c);
 387                 if (ret)
 388                         return ret;
 389
 390                 writel(addr_data, i2c->regs + MXS_I2C_DATA);
 391                 writel(MXS_I2C_DEBUG0_DMAREQ, i2c->regs + MXS_I2C_DEBUG0_CLR);
 392
 393                 ret = mxs_i2c_pio_wait_cplt(i2c, 0);
 394                 if (ret)
 395                         return ret;
 396
 397                 if (mxs_i2c_pio_check_error_state(i2c))
 398                         goto cleanup;
 399
 400                 /* READ command. */
 401                 mxs_i2c_pio_trigger_cmd(i2c,
 402                                         MXS_CMD_I2C_READ | flags |
 403                                         MXS_I2C_CTRL0_XFER_COUNT(msg->len));
 404
 405                 for (i = 0; i < msg->len; i++) {
 406                         if ((i & 3) == 0) {
 407                                 ret = mxs_i2c_pio_wait_dmareq(i2c);
 408                                 if (ret)
 409                                         return ret;
 410                                 data = readl(i2c->regs + MXS_I2C_DATA);
 411                                 writel(MXS_I2C_DEBUG0_DMAREQ,
 412                                        i2c->regs + MXS_I2C_DEBUG0_CLR);
 413                         }
 414                         msg->buf[i] = data & 0xff;
 415                         data >>= 8;
 416                 }
 417         } else {
 418                 addr_data |= I2C_SMBUS_WRITE;
 419
 420                 /* WRITE command. */
 421                 mxs_i2c_pio_trigger_cmd(i2c,
 422                                         MXS_CMD_I2C_WRITE | flags |
 423                                         MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1));
 424
 425                 /*
 426                  * The LSB of data buffer is the first byte blasted across
 427                  * the bus. Higher order bytes follow. Thus the following
 428                  * filling schematic.
 429                  */
 430                 data = addr_data << 24;
 431                 for (i = 0; i < msg->len; i++) {
 432                         data >>= 8;
 433                         data |= (msg->buf[i] << 24);
 434                         if ((i & 3) == 2) {
 435                                 ret = mxs_i2c_pio_wait_dmareq(i2c);
 436                                 if (ret)
 437                                         return ret;
 438                                 writel(data, i2c->regs + MXS_I2C_DATA);
 439                                 writel(MXS_I2C_DEBUG0_DMAREQ,
 440                                        i2c->regs + MXS_I2C_DEBUG0_CLR);
 441                         }
 442                 }
 443
 444                 shifts_left = 24 - (i & 3) * 8;
 445                 if (shifts_left) {
 446                         data >>= shifts_left;
 447                         ret = mxs_i2c_pio_wait_dmareq(i2c);
 448                         if (ret)
 449                                 return ret;
 450                         writel(data, i2c->regs + MXS_I2C_DATA);
 451                         writel(MXS_I2C_DEBUG0_DMAREQ,
 452                                i2c->regs + MXS_I2C_DEBUG0_CLR);
 453                 }
 454         }
 455
 456         ret = mxs_i2c_pio_wait_cplt(i2c, flags & MXS_I2C_CTRL0_POST_SEND_STOP);
 457         if (ret)
 458                 return ret;
 459
 460         /* make sure we capture any occurred error into cmd_err */
 461         mxs_i2c_pio_check_error_state(i2c);
 462
 463 cleanup:
 464         /* Clear any dangling IRQs and re-enable interrupts. */
 465         writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
 466         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 467
 468         return 0;
 469 }
 470
 471 /*
 472  * Low level master read/write transaction.
 473  */
 474 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 475                                 int stop)
 476 {
 477         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 478         int ret;
 479         int flags;
 480
 481         flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
 482
 483         dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 484                 msg->addr, msg->len, msg->flags, stop);
 485
 486         if (msg->len == 0)
 487                 return -EINVAL;
 488
 489         /*
 490          * The current boundary to select between PIO/DMA transfer method
 491          * is set to 8 bytes, transfers shorter than 8 bytes are transfered
 492          * using PIO mode while longer transfers use DMA. The 8 byte border is
 493          * based on this empirical measurement and a lot of previous frobbing.
 494          */
 495         i2c->cmd_err = 0;
 496         if (0) {        /* disable PIO mode until a proper fix is made */
 497                 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
 498                 if (ret)
 499                         mxs_i2c_reset(i2c);
 500         } else {
 501                 INIT_COMPLETION(i2c->cmd_complete);
 502                 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
 503                 if (ret)
 504                         return ret;
 505
 506                 ret = wait_for_completion_timeout(&i2c->cmd_complete,
 507                                                 msecs_to_jiffies(1000));
 508                 if (ret == 0)
 509                         goto timeout;
 510         }
 511
 512         if (i2c->cmd_err == -ENXIO) {
 513                 /*
 514                  * If the transfer fails with a NAK from the slave the
 515                  * controller halts until it gets told to return to idle state.
 516                  */
 517                 writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
 518                        i2c->regs + MXS_I2C_CTRL1_SET);
 519         }
 520
 521         ret = i2c->cmd_err;
 522
 523         dev_dbg(i2c->dev, "Done with err=%d\n", ret);
 524
 525         return ret;
 526
 527 timeout:
 528         dev_dbg(i2c->dev, "Timeout!\n");
 529         mxs_i2c_dma_finish(i2c);
 530         mxs_i2c_reset(i2c);
 531         return -ETIMEDOUT;
 532 }
 533
 534 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 535                         int num)
 536 {
 537         int i;
 538         int err;
 539
 540         for (i = 0; i < num; i++) {
 541                 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
 542                 if (err)
 543                         return err;
 544         }
 545
 546         return num;
 547 }
 548
 549 static u32 mxs_i2c_func(struct i2c_adapter *adap)
 550 {
 551         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 552 }
 553
 554 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
 555 {
 556         struct mxs_i2c_dev *i2c = dev_id;
 557         u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
 558
 559         if (!stat)
 560                 return IRQ_NONE;
 561
 562         if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 563                 i2c->cmd_err = -ENXIO;
 564         else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
 565                     MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
 566                     MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
 567                 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
 568                 i2c->cmd_err = -EIO;
 569
 570         writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
 571
 572         return IRQ_HANDLED;
 573 }
 574
 575 static const struct i2c_algorithm mxs_i2c_algo = {
 576         .master_xfer = mxs_i2c_xfer,
 577         .functionality = mxs_i2c_func,
 578 };
 579
 580 static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, int speed)
 581 {
 582         /* The I2C block clock run at 24MHz */
 583         const uint32_t clk = 24000000;
 584         uint32_t base;
 585         uint16_t high_count, low_count, rcv_count, xmit_count;
 586         struct device *dev = i2c->dev;
 587
 588         if (speed > 540000) {
 589                 dev_warn(dev, "Speed too high (%d Hz), using 540 kHz\n", speed);
 590                 speed = 540000;
 591         } else if (speed < 12000) {
 592                 dev_warn(dev, "Speed too low (%d Hz), using 12 kHz\n", speed);
 593                 speed = 12000;
 594         }
 595
 596         /*
 597          * The timing derivation algorithm. There is no documentation for this
 598          * algorithm available, it was derived by using the scope and fiddling
 599          * with constants until the result observed on the scope was good enough
 600          * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
 601          * possible to assume the algorithm works for other frequencies as well.
 602          *
 603          * Note it was necessary to cap the frequency on both ends as it's not
 604          * possible to configure completely arbitrary frequency for the I2C bus
 605          * clock.
 606          */
 607         base = ((clk / speed) - 38) / 2;
 608         high_count = base + 3;
 609         low_count = base - 3;
 610         rcv_count = (high_count * 3) / 4;
 611         xmit_count = low_count / 4;
 612
 613         i2c->timing0 = (high_count << 16) | rcv_count;
 614         i2c->timing1 = (low_count << 16) | xmit_count;
 615 }
 616
 617 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
 618 {
 619         uint32_t speed;
 620         struct device *dev = i2c->dev;
 621         struct device_node *node = dev->of_node;
 622         int ret;
 623
 624         ret = of_property_read_u32(node, "clock-frequency", &speed);
 625         if (ret) {
 626                 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
 627                 speed = 100000;
 628         }
 629
 630         mxs_i2c_derive_timing(i2c, speed);
 631
 632         return 0;
 633 }
 634
 635 static int mxs_i2c_probe(struct platform_device *pdev)
 636 {
 637         struct device *dev = &pdev->dev;
 638         struct mxs_i2c_dev *i2c;
 639         struct i2c_adapter *adap;
 640         struct resource *res;
 641         resource_size_t res_size;
 642         int err, irq;
 643
 644         i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
 645         if (!i2c)
 646                 return -ENOMEM;
 647
 648         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 649         irq = platform_get_irq(pdev, 0);
 650
 651         if (!res || irq < 0)
 652                 return -ENOENT;
 653
 654         res_size = resource_size(res);
 655         if (!devm_request_mem_region(dev, res->start, res_size, res->name))
 656                 return -EBUSY;
 657
 658         i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
 659         if (!i2c->regs)
 660                 return -EBUSY;
 661
 662         err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
 663         if (err)
 664                 return err;
 665
 666         i2c->dev = dev;
 667
 668         init_completion(&i2c->cmd_complete);
 669
 670         if (dev->of_node) {
 671                 err = mxs_i2c_get_ofdata(i2c);
 672                 if (err)
 673                         return err;
 674         }
 675
 676         /* Setup the DMA */
 677         i2c->dmach = dma_request_slave_channel(dev, "rx-tx");
 678         if (!i2c->dmach) {
 679                 dev_err(dev, "Failed to request dma\n");
 680                 return -ENODEV;
 681         }
 682
 683         platform_set_drvdata(pdev, i2c);
 684
 685         /* Do reset to enforce correct startup after pinmuxing */
 686         mxs_i2c_reset(i2c);
 687
 688         adap = &i2c->adapter;
 689         strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
 690         adap->owner = THIS_MODULE;
 691         adap->algo = &mxs_i2c_algo;
 692         adap->dev.parent = dev;
 693         adap->nr = pdev->id;
 694         adap->dev.of_node = pdev->dev.of_node;
 695         i2c_set_adapdata(adap, i2c);
 696         err = i2c_add_numbered_adapter(adap);
 697         if (err) {
 698                 dev_err(dev, "Failed to add adapter (%d)\n", err);
 699                 writel(MXS_I2C_CTRL0_SFTRST,
 700                                 i2c->regs + MXS_I2C_CTRL0_SET);
 701                 return err;
 702         }
 703
 704         of_i2c_register_devices(adap);
 705
 706         return 0;
 707 }
 708
 709 static int mxs_i2c_remove(struct platform_device *pdev)
 710 {
 711         struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
 712
 713         i2c_del_adapter(&i2c->adapter);
 714
 715         if (i2c->dmach)
 716                 dma_release_channel(i2c->dmach);
 717
 718         writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
 719
 720         return 0;
 721 }
 722
 723 static const struct of_device_id mxs_i2c_dt_ids[] = {
 724         { .compatible = "fsl,imx28-i2c", },
 725         { /* sentinel */ }
 726 };
 727 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
 728
 729 static struct platform_driver mxs_i2c_driver = {
 730         .driver = {
 731                    .name = DRIVER_NAME,
 732                    .owner = THIS_MODULE,
 733                    .of_match_table = mxs_i2c_dt_ids,
 734                    },
 735         .remove = mxs_i2c_remove,
 736 };
 737
 738 static int __init mxs_i2c_init(void)
 739 {
 740         return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
 741 }
 742 subsys_initcall(mxs_i2c_init);
 743
 744 static void __exit mxs_i2c_exit(void)
 745 {
 746         platform_driver_unregister(&mxs_i2c_driver);
 747 }
 748 module_exit(mxs_i2c_exit);
 749
 750 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
 751 MODULE_DESCRIPTION("MXS I2C Bus Driver");
 752 MODULE_LICENSE("GPL");
 753 MODULE_ALIAS("platform:" DRIVER_NAME);