EMS CPC-PCI fix correcting poorly undocumented PITA2 IRQ behavior.

[lincan.git] / lincan / src / ems_cpcpci.c

diff --git a/lincan/src/ems_cpcpci.c b/lincan/src/ems_cpcpci.c
index b0f8b048d81c0b4017e70a8f0147a30dd1563e71..da82fd3de168557769e08dc9c65f32e31e6c8daf 100644 (file)
--- a/lincan/src/ems_cpcpci.c
+++ b/lincan/src/ems_cpcpci.c
@@ -30,8 +30,13 @@
 
 /*PSB4610 PITA-2 bridge control registers*/   
 #define PITA2_ICR  0x00  /* Interrupt Control Register */
-#define   PITA2_ICR_INT0    0x00000002 /* [RC] INT0 Active/Clear */
-#define   PITA2_ICR_INT0_En 0x00020000 /* [RW] Enable INT0 */
+#define   PITA2_ICR_INT0    0x00000002 /* [RC] INT0 Active/Clear */
+#define   PITA2_ICR_GP0_INT 0x00000004 /* [RC] GP0 Interrupt */
+                                       /* GP0_Int_En=1, GP0_Out_En=0 and low detected */
+#define   PITA2_ICR_GP1_INT 0x00000008 /* [RC] GP1 Interrupt */
+#define   PITA2_ICR_GP2_INT 0x00000010 /* [RC] GP2 Interrupt */
+#define   PITA2_ICR_GP3_INT 0x00000020 /* [RC] GP2 Interrupt */
+#define   PITA2_ICR_INT0_En 0x00020000 /* [RW] Enable INT0 */
 
 #define PITA2_MISC 0x1C  /* Miscellaneous Register */
 #define   PITA2_MISC_CONFIG 0x04000000
@@ -186,22 +191,25 @@ can_irqreturn_t ems_cpcpci_irq_handler(int irq, void *dev_id, struct pt_regs *re
        struct candevice_t *candev=chip->hostdevice;
        int i;
        unsigned long icr;
+       int test_irq_again;
 
        icr=readl(candev->dev_base_addr + PITA2_ICR);
-       if(!(icr & PITA2_ICR_INT0)) return IRQ_NONE;
+       if(!(icr & PITA2_ICR_INT0)) return CAN_IRQ_NONE;
        
        /* correct way to handle interrupts from all chips connected to the one PITA-2 */
        do {
                writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->dev_base_addr + PITA2_ICR);
+               test_irq_again=0;
                for(i=0;i<candev->nr_all_chips;i++){
                        chip=candev->chip[i];
                        if(!chip || !(chip->flags&CHIP_CONFIGURED))
                                continue;
-                       sja1000p_irq_handler(irq, dev_id, regs);
+                       if(sja1000p_irq_handler(irq, chip, regs))
+                               test_irq_again=1;
                }
                icr=readl(candev->dev_base_addr + PITA2_ICR);
-       } while(icr & PITA2_ICR_INT0);
-       return IRQ_HANDLED;
+       } while((icr & PITA2_ICR_INT0)||test_irq_again);
+       return CAN_IRQ_HANDLED;
 }
 
 int ems_cpcpci_reset(struct candevice_t *candev)
@@ -295,7 +303,7 @@ int ems_cpcpci_init_hw_data(struct candevice_t *candev)
        
        CANMSG("EMS CPC-PCI check value %04lx, ID %d\n", l, i);
        
-       if((l!=0x55aa01cb)||(i!=0x11)) {
+       if(l!=0x55aa01cb) {
                CANMSG("EMS CPC-PCI unexpected check values\n");
        }